1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/ADT/SmallBitVector.h"
21 #include "llvm/ADT/SmallPtrSet.h"
22 #include "llvm/ADT/SetVector.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/Analysis/AliasAnalysis.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetLowering.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
43 #define DEBUG_TYPE "dagcombine"
45 STATISTIC(NodesCombined , "Number of dag nodes combined");
46 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
47 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
48 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
49 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
50 STATISTIC(SlicedLoads, "Number of load sliced");
54 CombinerAA("combiner-alias-analysis", cl::Hidden,
55 cl::desc("Enable DAG combiner alias-analysis heuristics"));
58 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
59 cl::desc("Enable DAG combiner's use of IR alias analysis"));
62 UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
63 cl::desc("Enable DAG combiner's use of TBAA"));
66 static cl::opt<std::string>
67 CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
68 cl::desc("Only use DAG-combiner alias analysis in this"
72 /// Hidden option to stress test load slicing, i.e., when this option
73 /// is enabled, load slicing bypasses most of its profitability guards.
75 StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
76 cl::desc("Bypass the profitability model of load "
81 MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true),
82 cl::desc("DAG combiner may split indexing from loads"));
84 //------------------------------ DAGCombiner ---------------------------------//
88 const TargetLowering &TLI;
90 CodeGenOpt::Level OptLevel;
95 /// \brief Worklist of all of the nodes that need to be simplified.
97 /// This must behave as a stack -- new nodes to process are pushed onto the
98 /// back and when processing we pop off of the back.
100 /// The worklist will not contain duplicates but may contain null entries
101 /// due to nodes being deleted from the underlying DAG.
102 SmallVector<SDNode *, 64> Worklist;
104 /// \brief Mapping from an SDNode to its position on the worklist.
106 /// This is used to find and remove nodes from the worklist (by nulling
107 /// them) when they are deleted from the underlying DAG. It relies on
108 /// stable indices of nodes within the worklist.
109 DenseMap<SDNode *, unsigned> WorklistMap;
111 /// \brief Set of nodes which have been combined (at least once).
113 /// This is used to allow us to reliably add any operands of a DAG node
114 /// which have not yet been combined to the worklist.
115 SmallPtrSet<SDNode *, 64> CombinedNodes;
117 // AA - Used for DAG load/store alias analysis.
120 /// When an instruction is simplified, add all users of the instruction to
121 /// the work lists because they might get more simplified now.
122 void AddUsersToWorklist(SDNode *N) {
123 for (SDNode *Node : N->uses())
127 /// Call the node-specific routine that folds each particular type of node.
128 SDValue visit(SDNode *N);
131 /// Add to the worklist making sure its instance is at the back (next to be
133 void AddToWorklist(SDNode *N) {
134 // Skip handle nodes as they can't usefully be combined and confuse the
135 // zero-use deletion strategy.
136 if (N->getOpcode() == ISD::HANDLENODE)
139 if (WorklistMap.insert(std::make_pair(N, Worklist.size())).second)
140 Worklist.push_back(N);
143 /// Remove all instances of N from the worklist.
144 void removeFromWorklist(SDNode *N) {
145 CombinedNodes.erase(N);
147 auto It = WorklistMap.find(N);
148 if (It == WorklistMap.end())
149 return; // Not in the worklist.
151 // Null out the entry rather than erasing it to avoid a linear operation.
152 Worklist[It->second] = nullptr;
153 WorklistMap.erase(It);
156 void deleteAndRecombine(SDNode *N);
157 bool recursivelyDeleteUnusedNodes(SDNode *N);
159 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
162 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
163 return CombineTo(N, &Res, 1, AddTo);
166 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
168 SDValue To[] = { Res0, Res1 };
169 return CombineTo(N, To, 2, AddTo);
172 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
176 /// Check the specified integer node value to see if it can be simplified or
177 /// if things it uses can be simplified by bit propagation.
178 /// If so, return true.
179 bool SimplifyDemandedBits(SDValue Op) {
180 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
181 APInt Demanded = APInt::getAllOnesValue(BitWidth);
182 return SimplifyDemandedBits(Op, Demanded);
185 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
187 bool CombineToPreIndexedLoadStore(SDNode *N);
188 bool CombineToPostIndexedLoadStore(SDNode *N);
189 SDValue SplitIndexingFromLoad(LoadSDNode *LD);
190 bool SliceUpLoad(SDNode *N);
192 /// \brief Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
195 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
196 /// \param InVecVT type of the input vector to EVE with bitcasts resolved.
197 /// \param EltNo index of the vector element to load.
198 /// \param OriginalLoad load that EVE came from to be replaced.
199 /// \returns EVE on success SDValue() on failure.
200 SDValue ReplaceExtractVectorEltOfLoadWithNarrowedLoad(
201 SDNode *EVE, EVT InVecVT, SDValue EltNo, LoadSDNode *OriginalLoad);
202 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
203 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
204 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
205 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
206 SDValue PromoteIntBinOp(SDValue Op);
207 SDValue PromoteIntShiftOp(SDValue Op);
208 SDValue PromoteExtend(SDValue Op);
209 bool PromoteLoad(SDValue Op);
211 void ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
212 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
213 ISD::NodeType ExtType);
215 /// Call the node-specific routine that knows how to fold each
216 /// particular type of node. If that doesn't do anything, try the
217 /// target-specific DAG combines.
218 SDValue combine(SDNode *N);
220 // Visitation implementation - Implement dag node combining for different
221 // node types. The semantics are as follows:
223 // SDValue.getNode() == 0 - No change was made
224 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
225 // otherwise - N should be replaced by the returned Operand.
227 SDValue visitTokenFactor(SDNode *N);
228 SDValue visitMERGE_VALUES(SDNode *N);
229 SDValue visitADD(SDNode *N);
230 SDValue visitSUB(SDNode *N);
231 SDValue visitADDC(SDNode *N);
232 SDValue visitSUBC(SDNode *N);
233 SDValue visitADDE(SDNode *N);
234 SDValue visitSUBE(SDNode *N);
235 SDValue visitMUL(SDNode *N);
236 SDValue visitSDIV(SDNode *N);
237 SDValue visitUDIV(SDNode *N);
238 SDValue visitSREM(SDNode *N);
239 SDValue visitUREM(SDNode *N);
240 SDValue visitMULHU(SDNode *N);
241 SDValue visitMULHS(SDNode *N);
242 SDValue visitSMUL_LOHI(SDNode *N);
243 SDValue visitUMUL_LOHI(SDNode *N);
244 SDValue visitSMULO(SDNode *N);
245 SDValue visitUMULO(SDNode *N);
246 SDValue visitSDIVREM(SDNode *N);
247 SDValue visitUDIVREM(SDNode *N);
248 SDValue visitAND(SDNode *N);
249 SDValue visitOR(SDNode *N);
250 SDValue visitXOR(SDNode *N);
251 SDValue SimplifyVBinOp(SDNode *N);
252 SDValue SimplifyVUnaryOp(SDNode *N);
253 SDValue visitSHL(SDNode *N);
254 SDValue visitSRA(SDNode *N);
255 SDValue visitSRL(SDNode *N);
256 SDValue visitRotate(SDNode *N);
257 SDValue visitCTLZ(SDNode *N);
258 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
259 SDValue visitCTTZ(SDNode *N);
260 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
261 SDValue visitCTPOP(SDNode *N);
262 SDValue visitSELECT(SDNode *N);
263 SDValue visitVSELECT(SDNode *N);
264 SDValue visitSELECT_CC(SDNode *N);
265 SDValue visitSETCC(SDNode *N);
266 SDValue visitSIGN_EXTEND(SDNode *N);
267 SDValue visitZERO_EXTEND(SDNode *N);
268 SDValue visitANY_EXTEND(SDNode *N);
269 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
270 SDValue visitTRUNCATE(SDNode *N);
271 SDValue visitBITCAST(SDNode *N);
272 SDValue visitBUILD_PAIR(SDNode *N);
273 SDValue visitFADD(SDNode *N);
274 SDValue visitFSUB(SDNode *N);
275 SDValue visitFMUL(SDNode *N);
276 SDValue visitFMA(SDNode *N);
277 SDValue visitFDIV(SDNode *N);
278 SDValue visitFREM(SDNode *N);
279 SDValue visitFSQRT(SDNode *N);
280 SDValue visitFCOPYSIGN(SDNode *N);
281 SDValue visitSINT_TO_FP(SDNode *N);
282 SDValue visitUINT_TO_FP(SDNode *N);
283 SDValue visitFP_TO_SINT(SDNode *N);
284 SDValue visitFP_TO_UINT(SDNode *N);
285 SDValue visitFP_ROUND(SDNode *N);
286 SDValue visitFP_ROUND_INREG(SDNode *N);
287 SDValue visitFP_EXTEND(SDNode *N);
288 SDValue visitFNEG(SDNode *N);
289 SDValue visitFABS(SDNode *N);
290 SDValue visitFCEIL(SDNode *N);
291 SDValue visitFTRUNC(SDNode *N);
292 SDValue visitFFLOOR(SDNode *N);
293 SDValue visitFMINNUM(SDNode *N);
294 SDValue visitFMAXNUM(SDNode *N);
295 SDValue visitBRCOND(SDNode *N);
296 SDValue visitBR_CC(SDNode *N);
297 SDValue visitLOAD(SDNode *N);
298 SDValue visitSTORE(SDNode *N);
299 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
300 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
301 SDValue visitBUILD_VECTOR(SDNode *N);
302 SDValue visitCONCAT_VECTORS(SDNode *N);
303 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
304 SDValue visitVECTOR_SHUFFLE(SDNode *N);
305 SDValue visitINSERT_SUBVECTOR(SDNode *N);
306 SDValue visitMLOAD(SDNode *N);
307 SDValue visitMSTORE(SDNode *N);
309 SDValue XformToShuffleWithZero(SDNode *N);
310 SDValue ReassociateOps(unsigned Opc, SDLoc DL, SDValue LHS, SDValue RHS);
312 SDValue visitShiftByConstant(SDNode *N, ConstantSDNode *Amt);
314 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
315 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
316 SDValue SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2);
317 SDValue SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2,
318 SDValue N3, ISD::CondCode CC,
319 bool NotExtCompare = false);
320 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
321 SDLoc DL, bool foldBooleans = true);
323 bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
325 bool isOneUseSetCC(SDValue N) const;
327 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
329 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
330 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
331 SDValue BuildSDIV(SDNode *N);
332 SDValue BuildSDIVPow2(SDNode *N);
333 SDValue BuildUDIV(SDNode *N);
334 SDValue BuildReciprocalEstimate(SDValue Op);
335 SDValue BuildRsqrtEstimate(SDValue Op);
336 SDValue BuildRsqrtNROneConst(SDValue Op, SDValue Est, unsigned Iterations);
337 SDValue BuildRsqrtNRTwoConst(SDValue Op, SDValue Est, unsigned Iterations);
338 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
339 bool DemandHighBits = true);
340 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
341 SDNode *MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
342 SDValue InnerPos, SDValue InnerNeg,
343 unsigned PosOpcode, unsigned NegOpcode,
345 SDNode *MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL);
346 SDValue ReduceLoadWidth(SDNode *N);
347 SDValue ReduceLoadOpStoreWidth(SDNode *N);
348 SDValue TransformFPLoadStorePair(SDNode *N);
349 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
350 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N);
352 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
354 /// Walk up chain skipping non-aliasing memory nodes,
355 /// looking for aliasing nodes and adding them to the Aliases vector.
356 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
357 SmallVectorImpl<SDValue> &Aliases);
359 /// Return true if there is any possibility that the two addresses overlap.
360 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const;
362 /// Walk up chain skipping non-aliasing memory nodes, looking for a better
363 /// chain (aliasing node.)
364 SDValue FindBetterChain(SDNode *N, SDValue Chain);
366 /// Merge consecutive store operations into a wide store.
367 /// This optimization uses wide integers or vectors when possible.
368 /// \return True if some memory operations were changed.
369 bool MergeConsecutiveStores(StoreSDNode *N);
371 /// \brief Try to transform a truncation where C is a constant:
372 /// (trunc (and X, C)) -> (and (trunc X), (trunc C))
374 /// \p N needs to be a truncation and its first operand an AND. Other
375 /// requirements are checked by the function (e.g. that trunc is
376 /// single-use) and if missed an empty SDValue is returned.
377 SDValue distributeTruncateThroughAnd(SDNode *N);
380 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
381 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
382 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {
383 AttributeSet FnAttrs =
384 DAG.getMachineFunction().getFunction()->getAttributes();
386 FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
387 Attribute::OptimizeForSize) ||
388 FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize);
391 /// Runs the dag combiner on all nodes in the work list
392 void Run(CombineLevel AtLevel);
394 SelectionDAG &getDAG() const { return DAG; }
396 /// Returns a type large enough to hold any valid shift amount - before type
397 /// legalization these can be huge.
398 EVT getShiftAmountTy(EVT LHSTy) {
399 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
400 if (LHSTy.isVector())
402 return LegalTypes ? TLI.getScalarShiftAmountTy(LHSTy)
403 : TLI.getPointerTy();
406 /// This method returns true if we are running before type legalization or
407 /// if the specified VT is legal.
408 bool isTypeLegal(const EVT &VT) {
409 if (!LegalTypes) return true;
410 return TLI.isTypeLegal(VT);
413 /// Convenience wrapper around TargetLowering::getSetCCResultType
414 EVT getSetCCResultType(EVT VT) const {
415 return TLI.getSetCCResultType(*DAG.getContext(), VT);
422 /// This class is a DAGUpdateListener that removes any deleted
423 /// nodes from the worklist.
424 class WorklistRemover : public SelectionDAG::DAGUpdateListener {
427 explicit WorklistRemover(DAGCombiner &dc)
428 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
430 void NodeDeleted(SDNode *N, SDNode *E) override {
431 DC.removeFromWorklist(N);
436 //===----------------------------------------------------------------------===//
437 // TargetLowering::DAGCombinerInfo implementation
438 //===----------------------------------------------------------------------===//
440 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
441 ((DAGCombiner*)DC)->AddToWorklist(N);
444 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
445 ((DAGCombiner*)DC)->removeFromWorklist(N);
448 SDValue TargetLowering::DAGCombinerInfo::
449 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
450 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
453 SDValue TargetLowering::DAGCombinerInfo::
454 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
455 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
459 SDValue TargetLowering::DAGCombinerInfo::
460 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
461 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
464 void TargetLowering::DAGCombinerInfo::
465 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
466 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
469 //===----------------------------------------------------------------------===//
471 //===----------------------------------------------------------------------===//
473 void DAGCombiner::deleteAndRecombine(SDNode *N) {
474 removeFromWorklist(N);
476 // If the operands of this node are only used by the node, they will now be
477 // dead. Make sure to re-visit them and recursively delete dead nodes.
478 for (const SDValue &Op : N->ops())
479 // For an operand generating multiple values, one of the values may
480 // become dead allowing further simplification (e.g. split index
481 // arithmetic from an indexed load).
482 if (Op->hasOneUse() || Op->getNumValues() > 1)
483 AddToWorklist(Op.getNode());
488 /// Return 1 if we can compute the negated form of the specified expression for
489 /// the same cost as the expression itself, or 2 if we can compute the negated
490 /// form more cheaply than the expression itself.
491 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
492 const TargetLowering &TLI,
493 const TargetOptions *Options,
494 unsigned Depth = 0) {
495 // fneg is removable even if it has multiple uses.
496 if (Op.getOpcode() == ISD::FNEG) return 2;
498 // Don't allow anything with multiple uses.
499 if (!Op.hasOneUse()) return 0;
501 // Don't recurse exponentially.
502 if (Depth > 6) return 0;
504 switch (Op.getOpcode()) {
505 default: return false;
506 case ISD::ConstantFP:
507 // Don't invert constant FP values after legalize. The negated constant
508 // isn't necessarily legal.
509 return LegalOperations ? 0 : 1;
511 // FIXME: determine better conditions for this xform.
512 if (!Options->UnsafeFPMath) return 0;
514 // After operation legalization, it might not be legal to create new FSUBs.
515 if (LegalOperations &&
516 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
519 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
520 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
523 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
524 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
527 // We can't turn -(A-B) into B-A when we honor signed zeros.
528 if (!Options->UnsafeFPMath) return 0;
530 // fold (fneg (fsub A, B)) -> (fsub B, A)
535 if (Options->HonorSignDependentRoundingFPMath()) return 0;
537 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
538 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
542 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
548 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
553 /// If isNegatibleForFree returns true, return the newly negated expression.
554 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
555 bool LegalOperations, unsigned Depth = 0) {
556 const TargetOptions &Options = DAG.getTarget().Options;
557 // fneg is removable even if it has multiple uses.
558 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
560 // Don't allow anything with multiple uses.
561 assert(Op.hasOneUse() && "Unknown reuse!");
563 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
564 switch (Op.getOpcode()) {
565 default: llvm_unreachable("Unknown code");
566 case ISD::ConstantFP: {
567 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
569 return DAG.getConstantFP(V, Op.getValueType());
572 // FIXME: determine better conditions for this xform.
573 assert(Options.UnsafeFPMath);
575 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
576 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
577 DAG.getTargetLoweringInfo(), &Options, Depth+1))
578 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
579 GetNegatedExpression(Op.getOperand(0), DAG,
580 LegalOperations, Depth+1),
582 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
583 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
584 GetNegatedExpression(Op.getOperand(1), DAG,
585 LegalOperations, Depth+1),
588 // We can't turn -(A-B) into B-A when we honor signed zeros.
589 assert(Options.UnsafeFPMath);
591 // fold (fneg (fsub 0, B)) -> B
592 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
593 if (N0CFP->getValueAPF().isZero())
594 return Op.getOperand(1);
596 // fold (fneg (fsub A, B)) -> (fsub B, A)
597 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
598 Op.getOperand(1), Op.getOperand(0));
602 assert(!Options.HonorSignDependentRoundingFPMath());
604 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
605 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
606 DAG.getTargetLoweringInfo(), &Options, Depth+1))
607 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
608 GetNegatedExpression(Op.getOperand(0), DAG,
609 LegalOperations, Depth+1),
612 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
613 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
615 GetNegatedExpression(Op.getOperand(1), DAG,
616 LegalOperations, Depth+1));
620 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
621 GetNegatedExpression(Op.getOperand(0), DAG,
622 LegalOperations, Depth+1));
624 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(),
625 GetNegatedExpression(Op.getOperand(0), DAG,
626 LegalOperations, Depth+1),
631 // Return true if this node is a setcc, or is a select_cc
632 // that selects between the target values used for true and false, making it
633 // equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
634 // the appropriate nodes based on the type of node we are checking. This
635 // simplifies life a bit for the callers.
636 bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
638 if (N.getOpcode() == ISD::SETCC) {
639 LHS = N.getOperand(0);
640 RHS = N.getOperand(1);
641 CC = N.getOperand(2);
645 if (N.getOpcode() != ISD::SELECT_CC ||
646 !TLI.isConstTrueVal(N.getOperand(2).getNode()) ||
647 !TLI.isConstFalseVal(N.getOperand(3).getNode()))
650 if (TLI.getBooleanContents(N.getValueType()) ==
651 TargetLowering::UndefinedBooleanContent)
654 LHS = N.getOperand(0);
655 RHS = N.getOperand(1);
656 CC = N.getOperand(4);
660 /// Return true if this is a SetCC-equivalent operation with only one use.
661 /// If this is true, it allows the users to invert the operation for free when
662 /// it is profitable to do so.
663 bool DAGCombiner::isOneUseSetCC(SDValue N) const {
665 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
670 /// Returns true if N is a BUILD_VECTOR node whose
671 /// elements are all the same constant or undefined.
672 static bool isConstantSplatVector(SDNode *N, APInt& SplatValue) {
673 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(N);
678 unsigned SplatBitSize;
680 EVT EltVT = N->getValueType(0).getVectorElementType();
681 return (C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
683 EltVT.getSizeInBits() >= SplatBitSize);
686 // \brief Returns the SDNode if it is a constant BuildVector or constant.
687 static SDNode *isConstantBuildVectorOrConstantInt(SDValue N) {
688 if (isa<ConstantSDNode>(N))
690 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
691 if (BV && BV->isConstant())
696 // \brief Returns the SDNode if it is a constant splat BuildVector or constant
698 static ConstantSDNode *isConstOrConstSplat(SDValue N) {
699 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N))
702 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
703 BitVector UndefElements;
704 ConstantSDNode *CN = BV->getConstantSplatNode(&UndefElements);
706 // BuildVectors can truncate their operands. Ignore that case here.
707 // FIXME: We blindly ignore splats which include undef which is overly
709 if (CN && UndefElements.none() &&
710 CN->getValueType(0) == N.getValueType().getScalarType())
717 // \brief Returns the SDNode if it is a constant splat BuildVector or constant
719 static ConstantFPSDNode *isConstOrConstSplatFP(SDValue N) {
720 if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
723 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
724 BitVector UndefElements;
725 ConstantFPSDNode *CN = BV->getConstantFPSplatNode(&UndefElements);
727 if (CN && UndefElements.none())
734 SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDLoc DL,
735 SDValue N0, SDValue N1) {
736 EVT VT = N0.getValueType();
737 if (N0.getOpcode() == Opc) {
738 if (SDNode *L = isConstantBuildVectorOrConstantInt(N0.getOperand(1))) {
739 if (SDNode *R = isConstantBuildVectorOrConstantInt(N1)) {
740 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
741 SDValue OpNode = DAG.FoldConstantArithmetic(Opc, VT, L, R);
742 if (!OpNode.getNode())
744 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
746 if (N0.hasOneUse()) {
747 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one
749 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1);
750 if (!OpNode.getNode())
752 AddToWorklist(OpNode.getNode());
753 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
758 if (N1.getOpcode() == Opc) {
759 if (SDNode *R = isConstantBuildVectorOrConstantInt(N1.getOperand(1))) {
760 if (SDNode *L = isConstantBuildVectorOrConstantInt(N0)) {
761 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
762 SDValue OpNode = DAG.FoldConstantArithmetic(Opc, VT, R, L);
763 if (!OpNode.getNode())
765 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
767 if (N1.hasOneUse()) {
768 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one
770 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N1.getOperand(0), N0);
771 if (!OpNode.getNode())
773 AddToWorklist(OpNode.getNode());
774 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
782 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
784 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
786 DEBUG(dbgs() << "\nReplacing.1 ";
788 dbgs() << "\nWith: ";
789 To[0].getNode()->dump(&DAG);
790 dbgs() << " and " << NumTo-1 << " other values\n");
791 for (unsigned i = 0, e = NumTo; i != e; ++i)
792 assert((!To[i].getNode() ||
793 N->getValueType(i) == To[i].getValueType()) &&
794 "Cannot combine value to value of different type!");
796 WorklistRemover DeadNodes(*this);
797 DAG.ReplaceAllUsesWith(N, To);
799 // Push the new nodes and any users onto the worklist
800 for (unsigned i = 0, e = NumTo; i != e; ++i) {
801 if (To[i].getNode()) {
802 AddToWorklist(To[i].getNode());
803 AddUsersToWorklist(To[i].getNode());
808 // Finally, if the node is now dead, remove it from the graph. The node
809 // may not be dead if the replacement process recursively simplified to
810 // something else needing this node.
812 deleteAndRecombine(N);
813 return SDValue(N, 0);
817 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
818 // Replace all uses. If any nodes become isomorphic to other nodes and
819 // are deleted, make sure to remove them from our worklist.
820 WorklistRemover DeadNodes(*this);
821 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
823 // Push the new node and any (possibly new) users onto the worklist.
824 AddToWorklist(TLO.New.getNode());
825 AddUsersToWorklist(TLO.New.getNode());
827 // Finally, if the node is now dead, remove it from the graph. The node
828 // may not be dead if the replacement process recursively simplified to
829 // something else needing this node.
830 if (TLO.Old.getNode()->use_empty())
831 deleteAndRecombine(TLO.Old.getNode());
834 /// Check the specified integer node value to see if it can be simplified or if
835 /// things it uses can be simplified by bit propagation. If so, return true.
836 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
837 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
838 APInt KnownZero, KnownOne;
839 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
843 AddToWorklist(Op.getNode());
845 // Replace the old value with the new one.
847 DEBUG(dbgs() << "\nReplacing.2 ";
848 TLO.Old.getNode()->dump(&DAG);
849 dbgs() << "\nWith: ";
850 TLO.New.getNode()->dump(&DAG);
853 CommitTargetLoweringOpt(TLO);
857 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
859 EVT VT = Load->getValueType(0);
860 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
862 DEBUG(dbgs() << "\nReplacing.9 ";
864 dbgs() << "\nWith: ";
865 Trunc.getNode()->dump(&DAG);
867 WorklistRemover DeadNodes(*this);
868 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
869 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
870 deleteAndRecombine(Load);
871 AddToWorklist(Trunc.getNode());
874 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
877 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
878 EVT MemVT = LD->getMemoryVT();
879 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
880 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD
882 : LD->getExtensionType();
884 return DAG.getExtLoad(ExtType, dl, PVT,
885 LD->getChain(), LD->getBasePtr(),
886 MemVT, LD->getMemOperand());
889 unsigned Opc = Op.getOpcode();
892 case ISD::AssertSext:
893 return DAG.getNode(ISD::AssertSext, dl, PVT,
894 SExtPromoteOperand(Op.getOperand(0), PVT),
896 case ISD::AssertZext:
897 return DAG.getNode(ISD::AssertZext, dl, PVT,
898 ZExtPromoteOperand(Op.getOperand(0), PVT),
900 case ISD::Constant: {
902 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
903 return DAG.getNode(ExtOpc, dl, PVT, Op);
907 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
909 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
912 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
913 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
915 EVT OldVT = Op.getValueType();
917 bool Replace = false;
918 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
919 if (!NewOp.getNode())
921 AddToWorklist(NewOp.getNode());
924 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
925 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
926 DAG.getValueType(OldVT));
929 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
930 EVT OldVT = Op.getValueType();
932 bool Replace = false;
933 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
934 if (!NewOp.getNode())
936 AddToWorklist(NewOp.getNode());
939 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
940 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
943 /// Promote the specified integer binary operation if the target indicates it is
944 /// beneficial. e.g. On x86, it's usually better to promote i16 operations to
945 /// i32 since i16 instructions are longer.
946 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
947 if (!LegalOperations)
950 EVT VT = Op.getValueType();
951 if (VT.isVector() || !VT.isInteger())
954 // If operation type is 'undesirable', e.g. i16 on x86, consider
956 unsigned Opc = Op.getOpcode();
957 if (TLI.isTypeDesirableForOp(Opc, VT))
961 // Consult target whether it is a good idea to promote this operation and
962 // what's the right type to promote it to.
963 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
964 assert(PVT != VT && "Don't know what type to promote to!");
966 bool Replace0 = false;
967 SDValue N0 = Op.getOperand(0);
968 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
972 bool Replace1 = false;
973 SDValue N1 = Op.getOperand(1);
978 NN1 = PromoteOperand(N1, PVT, Replace1);
983 AddToWorklist(NN0.getNode());
985 AddToWorklist(NN1.getNode());
988 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
990 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
992 DEBUG(dbgs() << "\nPromoting ";
993 Op.getNode()->dump(&DAG));
995 return DAG.getNode(ISD::TRUNCATE, dl, VT,
996 DAG.getNode(Opc, dl, PVT, NN0, NN1));
1001 /// Promote the specified integer shift operation if the target indicates it is
1002 /// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1003 /// i32 since i16 instructions are longer.
1004 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
1005 if (!LegalOperations)
1008 EVT VT = Op.getValueType();
1009 if (VT.isVector() || !VT.isInteger())
1012 // If operation type is 'undesirable', e.g. i16 on x86, consider
1014 unsigned Opc = Op.getOpcode();
1015 if (TLI.isTypeDesirableForOp(Opc, VT))
1019 // Consult target whether it is a good idea to promote this operation and
1020 // what's the right type to promote it to.
1021 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1022 assert(PVT != VT && "Don't know what type to promote to!");
1024 bool Replace = false;
1025 SDValue N0 = Op.getOperand(0);
1026 if (Opc == ISD::SRA)
1027 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
1028 else if (Opc == ISD::SRL)
1029 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
1031 N0 = PromoteOperand(N0, PVT, Replace);
1035 AddToWorklist(N0.getNode());
1037 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
1039 DEBUG(dbgs() << "\nPromoting ";
1040 Op.getNode()->dump(&DAG));
1042 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1043 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
1048 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
1049 if (!LegalOperations)
1052 EVT VT = Op.getValueType();
1053 if (VT.isVector() || !VT.isInteger())
1056 // If operation type is 'undesirable', e.g. i16 on x86, consider
1058 unsigned Opc = Op.getOpcode();
1059 if (TLI.isTypeDesirableForOp(Opc, VT))
1063 // Consult target whether it is a good idea to promote this operation and
1064 // what's the right type to promote it to.
1065 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1066 assert(PVT != VT && "Don't know what type to promote to!");
1067 // fold (aext (aext x)) -> (aext x)
1068 // fold (aext (zext x)) -> (zext x)
1069 // fold (aext (sext x)) -> (sext x)
1070 DEBUG(dbgs() << "\nPromoting ";
1071 Op.getNode()->dump(&DAG));
1072 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
1077 bool DAGCombiner::PromoteLoad(SDValue Op) {
1078 if (!LegalOperations)
1081 EVT VT = Op.getValueType();
1082 if (VT.isVector() || !VT.isInteger())
1085 // If operation type is 'undesirable', e.g. i16 on x86, consider
1087 unsigned Opc = Op.getOpcode();
1088 if (TLI.isTypeDesirableForOp(Opc, VT))
1092 // Consult target whether it is a good idea to promote this operation and
1093 // what's the right type to promote it to.
1094 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1095 assert(PVT != VT && "Don't know what type to promote to!");
1098 SDNode *N = Op.getNode();
1099 LoadSDNode *LD = cast<LoadSDNode>(N);
1100 EVT MemVT = LD->getMemoryVT();
1101 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
1102 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD
1104 : LD->getExtensionType();
1105 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
1106 LD->getChain(), LD->getBasePtr(),
1107 MemVT, LD->getMemOperand());
1108 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
1110 DEBUG(dbgs() << "\nPromoting ";
1113 Result.getNode()->dump(&DAG);
1115 WorklistRemover DeadNodes(*this);
1116 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
1117 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
1118 deleteAndRecombine(N);
1119 AddToWorklist(Result.getNode());
1125 /// \brief Recursively delete a node which has no uses and any operands for
1126 /// which it is the only use.
1128 /// Note that this both deletes the nodes and removes them from the worklist.
1129 /// It also adds any nodes who have had a user deleted to the worklist as they
1130 /// may now have only one use and subject to other combines.
1131 bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) {
1132 if (!N->use_empty())
1135 SmallSetVector<SDNode *, 16> Nodes;
1138 N = Nodes.pop_back_val();
1142 if (N->use_empty()) {
1143 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1144 Nodes.insert(N->getOperand(i).getNode());
1146 removeFromWorklist(N);
1151 } while (!Nodes.empty());
1155 //===----------------------------------------------------------------------===//
1156 // Main DAG Combiner implementation
1157 //===----------------------------------------------------------------------===//
1159 void DAGCombiner::Run(CombineLevel AtLevel) {
1160 // set the instance variables, so that the various visit routines may use it.
1162 LegalOperations = Level >= AfterLegalizeVectorOps;
1163 LegalTypes = Level >= AfterLegalizeTypes;
1165 // Early exit if this basic block is in an optnone function.
1166 AttributeSet FnAttrs =
1167 DAG.getMachineFunction().getFunction()->getAttributes();
1168 if (FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
1169 Attribute::OptimizeNone))
1172 // Add all the dag nodes to the worklist.
1173 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
1174 E = DAG.allnodes_end(); I != E; ++I)
1177 // Create a dummy node (which is not added to allnodes), that adds a reference
1178 // to the root node, preventing it from being deleted, and tracking any
1179 // changes of the root.
1180 HandleSDNode Dummy(DAG.getRoot());
1182 // while the worklist isn't empty, find a node and
1183 // try and combine it.
1184 while (!WorklistMap.empty()) {
1186 // The Worklist holds the SDNodes in order, but it may contain null entries.
1188 N = Worklist.pop_back_val();
1191 bool GoodWorklistEntry = WorklistMap.erase(N);
1192 (void)GoodWorklistEntry;
1193 assert(GoodWorklistEntry &&
1194 "Found a worklist entry without a corresponding map entry!");
1196 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1197 // N is deleted from the DAG, since they too may now be dead or may have a
1198 // reduced number of uses, allowing other xforms.
1199 if (recursivelyDeleteUnusedNodes(N))
1202 WorklistRemover DeadNodes(*this);
1204 // If this combine is running after legalizing the DAG, re-legalize any
1205 // nodes pulled off the worklist.
1206 if (Level == AfterLegalizeDAG) {
1207 SmallSetVector<SDNode *, 16> UpdatedNodes;
1208 bool NIsValid = DAG.LegalizeOp(N, UpdatedNodes);
1210 for (SDNode *LN : UpdatedNodes) {
1212 AddUsersToWorklist(LN);
1218 DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG));
1220 // Add any operands of the new node which have not yet been combined to the
1221 // worklist as well. Because the worklist uniques things already, this
1222 // won't repeatedly process the same operand.
1223 CombinedNodes.insert(N);
1224 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1225 if (!CombinedNodes.count(N->getOperand(i).getNode()))
1226 AddToWorklist(N->getOperand(i).getNode());
1228 SDValue RV = combine(N);
1235 // If we get back the same node we passed in, rather than a new node or
1236 // zero, we know that the node must have defined multiple values and
1237 // CombineTo was used. Since CombineTo takes care of the worklist
1238 // mechanics for us, we have no work to do in this case.
1239 if (RV.getNode() == N)
1242 assert(N->getOpcode() != ISD::DELETED_NODE &&
1243 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1244 "Node was deleted but visit returned new node!");
1246 DEBUG(dbgs() << " ... into: ";
1247 RV.getNode()->dump(&DAG));
1249 // Transfer debug value.
1250 DAG.TransferDbgValues(SDValue(N, 0), RV);
1251 if (N->getNumValues() == RV.getNode()->getNumValues())
1252 DAG.ReplaceAllUsesWith(N, RV.getNode());
1254 assert(N->getValueType(0) == RV.getValueType() &&
1255 N->getNumValues() == 1 && "Type mismatch");
1257 DAG.ReplaceAllUsesWith(N, &OpV);
1260 // Push the new node and any users onto the worklist
1261 AddToWorklist(RV.getNode());
1262 AddUsersToWorklist(RV.getNode());
1264 // Finally, if the node is now dead, remove it from the graph. The node
1265 // may not be dead if the replacement process recursively simplified to
1266 // something else needing this node. This will also take care of adding any
1267 // operands which have lost a user to the worklist.
1268 recursivelyDeleteUnusedNodes(N);
1271 // If the root changed (e.g. it was a dead load, update the root).
1272 DAG.setRoot(Dummy.getValue());
1273 DAG.RemoveDeadNodes();
1276 SDValue DAGCombiner::visit(SDNode *N) {
1277 switch (N->getOpcode()) {
1279 case ISD::TokenFactor: return visitTokenFactor(N);
1280 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1281 case ISD::ADD: return visitADD(N);
1282 case ISD::SUB: return visitSUB(N);
1283 case ISD::ADDC: return visitADDC(N);
1284 case ISD::SUBC: return visitSUBC(N);
1285 case ISD::ADDE: return visitADDE(N);
1286 case ISD::SUBE: return visitSUBE(N);
1287 case ISD::MUL: return visitMUL(N);
1288 case ISD::SDIV: return visitSDIV(N);
1289 case ISD::UDIV: return visitUDIV(N);
1290 case ISD::SREM: return visitSREM(N);
1291 case ISD::UREM: return visitUREM(N);
1292 case ISD::MULHU: return visitMULHU(N);
1293 case ISD::MULHS: return visitMULHS(N);
1294 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1295 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1296 case ISD::SMULO: return visitSMULO(N);
1297 case ISD::UMULO: return visitUMULO(N);
1298 case ISD::SDIVREM: return visitSDIVREM(N);
1299 case ISD::UDIVREM: return visitUDIVREM(N);
1300 case ISD::AND: return visitAND(N);
1301 case ISD::OR: return visitOR(N);
1302 case ISD::XOR: return visitXOR(N);
1303 case ISD::SHL: return visitSHL(N);
1304 case ISD::SRA: return visitSRA(N);
1305 case ISD::SRL: return visitSRL(N);
1307 case ISD::ROTL: return visitRotate(N);
1308 case ISD::CTLZ: return visitCTLZ(N);
1309 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1310 case ISD::CTTZ: return visitCTTZ(N);
1311 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1312 case ISD::CTPOP: return visitCTPOP(N);
1313 case ISD::SELECT: return visitSELECT(N);
1314 case ISD::VSELECT: return visitVSELECT(N);
1315 case ISD::SELECT_CC: return visitSELECT_CC(N);
1316 case ISD::SETCC: return visitSETCC(N);
1317 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1318 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1319 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1320 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1321 case ISD::TRUNCATE: return visitTRUNCATE(N);
1322 case ISD::BITCAST: return visitBITCAST(N);
1323 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1324 case ISD::FADD: return visitFADD(N);
1325 case ISD::FSUB: return visitFSUB(N);
1326 case ISD::FMUL: return visitFMUL(N);
1327 case ISD::FMA: return visitFMA(N);
1328 case ISD::FDIV: return visitFDIV(N);
1329 case ISD::FREM: return visitFREM(N);
1330 case ISD::FSQRT: return visitFSQRT(N);
1331 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1332 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1333 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1334 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1335 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1336 case ISD::FP_ROUND: return visitFP_ROUND(N);
1337 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1338 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1339 case ISD::FNEG: return visitFNEG(N);
1340 case ISD::FABS: return visitFABS(N);
1341 case ISD::FFLOOR: return visitFFLOOR(N);
1342 case ISD::FMINNUM: return visitFMINNUM(N);
1343 case ISD::FMAXNUM: return visitFMAXNUM(N);
1344 case ISD::FCEIL: return visitFCEIL(N);
1345 case ISD::FTRUNC: return visitFTRUNC(N);
1346 case ISD::BRCOND: return visitBRCOND(N);
1347 case ISD::BR_CC: return visitBR_CC(N);
1348 case ISD::LOAD: return visitLOAD(N);
1349 case ISD::STORE: return visitSTORE(N);
1350 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1351 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1352 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1353 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1354 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1355 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1356 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
1357 case ISD::MLOAD: return visitMLOAD(N);
1358 case ISD::MSTORE: return visitMSTORE(N);
1363 SDValue DAGCombiner::combine(SDNode *N) {
1364 SDValue RV = visit(N);
1366 // If nothing happened, try a target-specific DAG combine.
1367 if (!RV.getNode()) {
1368 assert(N->getOpcode() != ISD::DELETED_NODE &&
1369 "Node was deleted but visit returned NULL!");
1371 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1372 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1374 // Expose the DAG combiner to the target combiner impls.
1375 TargetLowering::DAGCombinerInfo
1376 DagCombineInfo(DAG, Level, false, this);
1378 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1382 // If nothing happened still, try promoting the operation.
1383 if (!RV.getNode()) {
1384 switch (N->getOpcode()) {
1392 RV = PromoteIntBinOp(SDValue(N, 0));
1397 RV = PromoteIntShiftOp(SDValue(N, 0));
1399 case ISD::SIGN_EXTEND:
1400 case ISD::ZERO_EXTEND:
1401 case ISD::ANY_EXTEND:
1402 RV = PromoteExtend(SDValue(N, 0));
1405 if (PromoteLoad(SDValue(N, 0)))
1411 // If N is a commutative binary node, try commuting it to enable more
1413 if (!RV.getNode() && SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1414 N->getNumValues() == 1) {
1415 SDValue N0 = N->getOperand(0);
1416 SDValue N1 = N->getOperand(1);
1418 // Constant operands are canonicalized to RHS.
1419 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1420 SDValue Ops[] = {N1, N0};
1422 if (const BinaryWithFlagsSDNode *BinNode =
1423 dyn_cast<BinaryWithFlagsSDNode>(N)) {
1424 CSENode = DAG.getNodeIfExists(
1425 N->getOpcode(), N->getVTList(), Ops, BinNode->hasNoUnsignedWrap(),
1426 BinNode->hasNoSignedWrap(), BinNode->isExact());
1428 CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops);
1431 return SDValue(CSENode, 0);
1438 /// Given a node, return its input chain if it has one, otherwise return a null
1440 static SDValue getInputChainForNode(SDNode *N) {
1441 if (unsigned NumOps = N->getNumOperands()) {
1442 if (N->getOperand(0).getValueType() == MVT::Other)
1443 return N->getOperand(0);
1444 if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1445 return N->getOperand(NumOps-1);
1446 for (unsigned i = 1; i < NumOps-1; ++i)
1447 if (N->getOperand(i).getValueType() == MVT::Other)
1448 return N->getOperand(i);
1453 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1454 // If N has two operands, where one has an input chain equal to the other,
1455 // the 'other' chain is redundant.
1456 if (N->getNumOperands() == 2) {
1457 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1458 return N->getOperand(0);
1459 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1460 return N->getOperand(1);
1463 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1464 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1465 SmallPtrSet<SDNode*, 16> SeenOps;
1466 bool Changed = false; // If we should replace this token factor.
1468 // Start out with this token factor.
1471 // Iterate through token factors. The TFs grows when new token factors are
1473 for (unsigned i = 0; i < TFs.size(); ++i) {
1474 SDNode *TF = TFs[i];
1476 // Check each of the operands.
1477 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1478 SDValue Op = TF->getOperand(i);
1480 switch (Op.getOpcode()) {
1481 case ISD::EntryToken:
1482 // Entry tokens don't need to be added to the list. They are
1487 case ISD::TokenFactor:
1488 if (Op.hasOneUse() &&
1489 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1490 // Queue up for processing.
1491 TFs.push_back(Op.getNode());
1492 // Clean up in case the token factor is removed.
1493 AddToWorklist(Op.getNode());
1500 // Only add if it isn't already in the list.
1501 if (SeenOps.insert(Op.getNode()).second)
1512 // If we've change things around then replace token factor.
1515 // The entry token is the only possible outcome.
1516 Result = DAG.getEntryNode();
1518 // New and improved token factor.
1519 Result = DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Ops);
1522 // Don't add users to work list.
1523 return CombineTo(N, Result, false);
1529 /// MERGE_VALUES can always be eliminated.
1530 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1531 WorklistRemover DeadNodes(*this);
1532 // Replacing results may cause a different MERGE_VALUES to suddenly
1533 // be CSE'd with N, and carry its uses with it. Iterate until no
1534 // uses remain, to ensure that the node can be safely deleted.
1535 // First add the users of this node to the work list so that they
1536 // can be tried again once they have new operands.
1537 AddUsersToWorklist(N);
1539 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1540 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1541 } while (!N->use_empty());
1542 deleteAndRecombine(N);
1543 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1546 SDValue DAGCombiner::visitADD(SDNode *N) {
1547 SDValue N0 = N->getOperand(0);
1548 SDValue N1 = N->getOperand(1);
1549 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1550 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1551 EVT VT = N0.getValueType();
1554 if (VT.isVector()) {
1555 SDValue FoldedVOp = SimplifyVBinOp(N);
1556 if (FoldedVOp.getNode()) return FoldedVOp;
1558 // fold (add x, 0) -> x, vector edition
1559 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1561 if (ISD::isBuildVectorAllZeros(N0.getNode()))
1565 // fold (add x, undef) -> undef
1566 if (N0.getOpcode() == ISD::UNDEF)
1568 if (N1.getOpcode() == ISD::UNDEF)
1570 // fold (add c1, c2) -> c1+c2
1572 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1573 // canonicalize constant to RHS
1575 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, N0);
1576 // fold (add x, 0) -> x
1577 if (N1C && N1C->isNullValue())
1579 // fold (add Sym, c) -> Sym+c
1580 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1581 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1582 GA->getOpcode() == ISD::GlobalAddress)
1583 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1585 (uint64_t)N1C->getSExtValue());
1586 // fold ((c1-A)+c2) -> (c1+c2)-A
1587 if (N1C && N0.getOpcode() == ISD::SUB)
1588 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1589 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1590 DAG.getConstant(N1C->getAPIntValue()+
1591 N0C->getAPIntValue(), VT),
1594 SDValue RADD = ReassociateOps(ISD::ADD, SDLoc(N), N0, N1);
1597 // fold ((0-A) + B) -> B-A
1598 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1599 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1600 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, N0.getOperand(1));
1601 // fold (A + (0-B)) -> A-B
1602 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1603 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1604 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1.getOperand(1));
1605 // fold (A+(B-A)) -> B
1606 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1607 return N1.getOperand(0);
1608 // fold ((B-A)+A) -> B
1609 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1610 return N0.getOperand(0);
1611 // fold (A+(B-(A+C))) to (B-C)
1612 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1613 N0 == N1.getOperand(1).getOperand(0))
1614 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1615 N1.getOperand(1).getOperand(1));
1616 // fold (A+(B-(C+A))) to (B-C)
1617 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1618 N0 == N1.getOperand(1).getOperand(1))
1619 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1620 N1.getOperand(1).getOperand(0));
1621 // fold (A+((B-A)+or-C)) to (B+or-C)
1622 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1623 N1.getOperand(0).getOpcode() == ISD::SUB &&
1624 N0 == N1.getOperand(0).getOperand(1))
1625 return DAG.getNode(N1.getOpcode(), SDLoc(N), VT,
1626 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1628 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1629 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1630 SDValue N00 = N0.getOperand(0);
1631 SDValue N01 = N0.getOperand(1);
1632 SDValue N10 = N1.getOperand(0);
1633 SDValue N11 = N1.getOperand(1);
1635 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1636 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1637 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
1638 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
1641 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1642 return SDValue(N, 0);
1644 // fold (a+b) -> (a|b) iff a and b share no bits.
1645 if (VT.isInteger() && !VT.isVector()) {
1646 APInt LHSZero, LHSOne;
1647 APInt RHSZero, RHSOne;
1648 DAG.computeKnownBits(N0, LHSZero, LHSOne);
1650 if (LHSZero.getBoolValue()) {
1651 DAG.computeKnownBits(N1, RHSZero, RHSOne);
1653 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1654 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1655 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero){
1656 if (!LegalOperations || TLI.isOperationLegal(ISD::OR, VT))
1657 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
1662 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1663 if (N1.getOpcode() == ISD::SHL &&
1664 N1.getOperand(0).getOpcode() == ISD::SUB)
1665 if (ConstantSDNode *C =
1666 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1667 if (C->getAPIntValue() == 0)
1668 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0,
1669 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1670 N1.getOperand(0).getOperand(1),
1672 if (N0.getOpcode() == ISD::SHL &&
1673 N0.getOperand(0).getOpcode() == ISD::SUB)
1674 if (ConstantSDNode *C =
1675 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1676 if (C->getAPIntValue() == 0)
1677 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1,
1678 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1679 N0.getOperand(0).getOperand(1),
1682 if (N1.getOpcode() == ISD::AND) {
1683 SDValue AndOp0 = N1.getOperand(0);
1684 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1685 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1686 unsigned DestBits = VT.getScalarType().getSizeInBits();
1688 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1689 // and similar xforms where the inner op is either ~0 or 0.
1690 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1692 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1696 // add (sext i1), X -> sub X, (zext i1)
1697 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1698 N0.getOperand(0).getValueType() == MVT::i1 &&
1699 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1701 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1702 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1705 // add X, (sextinreg Y i1) -> sub X, (and Y 1)
1706 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
1707 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
1708 if (TN->getVT() == MVT::i1) {
1710 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
1711 DAG.getConstant(1, VT));
1712 return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
1719 SDValue DAGCombiner::visitADDC(SDNode *N) {
1720 SDValue N0 = N->getOperand(0);
1721 SDValue N1 = N->getOperand(1);
1722 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1723 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1724 EVT VT = N0.getValueType();
1726 // If the flag result is dead, turn this into an ADD.
1727 if (!N->hasAnyUseOfValue(1))
1728 return CombineTo(N, DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N1),
1729 DAG.getNode(ISD::CARRY_FALSE,
1730 SDLoc(N), MVT::Glue));
1732 // canonicalize constant to RHS.
1734 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0);
1736 // fold (addc x, 0) -> x + no carry out
1737 if (N1C && N1C->isNullValue())
1738 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1739 SDLoc(N), MVT::Glue));
1741 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1742 APInt LHSZero, LHSOne;
1743 APInt RHSZero, RHSOne;
1744 DAG.computeKnownBits(N0, LHSZero, LHSOne);
1746 if (LHSZero.getBoolValue()) {
1747 DAG.computeKnownBits(N1, RHSZero, RHSOne);
1749 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1750 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1751 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1752 return CombineTo(N, DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1),
1753 DAG.getNode(ISD::CARRY_FALSE,
1754 SDLoc(N), MVT::Glue));
1760 SDValue DAGCombiner::visitADDE(SDNode *N) {
1761 SDValue N0 = N->getOperand(0);
1762 SDValue N1 = N->getOperand(1);
1763 SDValue CarryIn = N->getOperand(2);
1764 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1765 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1767 // canonicalize constant to RHS
1769 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
1772 // fold (adde x, y, false) -> (addc x, y)
1773 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1774 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
1779 // Since it may not be valid to emit a fold to zero for vector initializers
1780 // check if we can before folding.
1781 static SDValue tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT,
1783 bool LegalOperations, bool LegalTypes) {
1785 return DAG.getConstant(0, VT);
1786 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
1787 return DAG.getConstant(0, VT);
1791 SDValue DAGCombiner::visitSUB(SDNode *N) {
1792 SDValue N0 = N->getOperand(0);
1793 SDValue N1 = N->getOperand(1);
1794 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1795 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1796 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? nullptr :
1797 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1798 EVT VT = N0.getValueType();
1801 if (VT.isVector()) {
1802 SDValue FoldedVOp = SimplifyVBinOp(N);
1803 if (FoldedVOp.getNode()) return FoldedVOp;
1805 // fold (sub x, 0) -> x, vector edition
1806 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1810 // fold (sub x, x) -> 0
1811 // FIXME: Refactor this and xor and other similar operations together.
1813 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
1814 // fold (sub c1, c2) -> c1-c2
1816 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1817 // fold (sub x, c) -> (add x, -c)
1819 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0,
1820 DAG.getConstant(-N1C->getAPIntValue(), VT));
1821 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1822 if (N0C && N0C->isAllOnesValue())
1823 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
1824 // fold A-(A-B) -> B
1825 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1826 return N1.getOperand(1);
1827 // fold (A+B)-A -> B
1828 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1829 return N0.getOperand(1);
1830 // fold (A+B)-B -> A
1831 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1832 return N0.getOperand(0);
1833 // fold C2-(A+C1) -> (C2-C1)-A
1834 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1835 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(),
1837 return DAG.getNode(ISD::SUB, SDLoc(N), VT, NewC,
1840 // fold ((A+(B+or-C))-B) -> A+or-C
1841 if (N0.getOpcode() == ISD::ADD &&
1842 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1843 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1844 N0.getOperand(1).getOperand(0) == N1)
1845 return DAG.getNode(N0.getOperand(1).getOpcode(), SDLoc(N), VT,
1846 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1847 // fold ((A+(C+B))-B) -> A+C
1848 if (N0.getOpcode() == ISD::ADD &&
1849 N0.getOperand(1).getOpcode() == ISD::ADD &&
1850 N0.getOperand(1).getOperand(1) == N1)
1851 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
1852 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1853 // fold ((A-(B-C))-C) -> A-B
1854 if (N0.getOpcode() == ISD::SUB &&
1855 N0.getOperand(1).getOpcode() == ISD::SUB &&
1856 N0.getOperand(1).getOperand(1) == N1)
1857 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1858 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1860 // If either operand of a sub is undef, the result is undef
1861 if (N0.getOpcode() == ISD::UNDEF)
1863 if (N1.getOpcode() == ISD::UNDEF)
1866 // If the relocation model supports it, consider symbol offsets.
1867 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1868 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1869 // fold (sub Sym, c) -> Sym-c
1870 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1871 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1873 (uint64_t)N1C->getSExtValue());
1874 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1875 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1876 if (GA->getGlobal() == GB->getGlobal())
1877 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1881 // sub X, (sextinreg Y i1) -> add X, (and Y 1)
1882 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
1883 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
1884 if (TN->getVT() == MVT::i1) {
1886 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
1887 DAG.getConstant(1, VT));
1888 return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
1895 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1896 SDValue N0 = N->getOperand(0);
1897 SDValue N1 = N->getOperand(1);
1898 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1899 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1900 EVT VT = N0.getValueType();
1902 // If the flag result is dead, turn this into an SUB.
1903 if (!N->hasAnyUseOfValue(1))
1904 return CombineTo(N, DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1),
1905 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1908 // fold (subc x, x) -> 0 + no borrow
1910 return CombineTo(N, DAG.getConstant(0, VT),
1911 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1914 // fold (subc x, 0) -> x + no borrow
1915 if (N1C && N1C->isNullValue())
1916 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1919 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1920 if (N0C && N0C->isAllOnesValue())
1921 return CombineTo(N, DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0),
1922 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1928 SDValue DAGCombiner::visitSUBE(SDNode *N) {
1929 SDValue N0 = N->getOperand(0);
1930 SDValue N1 = N->getOperand(1);
1931 SDValue CarryIn = N->getOperand(2);
1933 // fold (sube x, y, false) -> (subc x, y)
1934 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1935 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
1940 SDValue DAGCombiner::visitMUL(SDNode *N) {
1941 SDValue N0 = N->getOperand(0);
1942 SDValue N1 = N->getOperand(1);
1943 EVT VT = N0.getValueType();
1945 // fold (mul x, undef) -> 0
1946 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1947 return DAG.getConstant(0, VT);
1949 bool N0IsConst = false;
1950 bool N1IsConst = false;
1951 APInt ConstValue0, ConstValue1;
1953 if (VT.isVector()) {
1954 SDValue FoldedVOp = SimplifyVBinOp(N);
1955 if (FoldedVOp.getNode()) return FoldedVOp;
1957 N0IsConst = isConstantSplatVector(N0.getNode(), ConstValue0);
1958 N1IsConst = isConstantSplatVector(N1.getNode(), ConstValue1);
1960 N0IsConst = dyn_cast<ConstantSDNode>(N0) != nullptr;
1961 ConstValue0 = N0IsConst ? (dyn_cast<ConstantSDNode>(N0))->getAPIntValue()
1963 N1IsConst = dyn_cast<ConstantSDNode>(N1) != nullptr;
1964 ConstValue1 = N1IsConst ? (dyn_cast<ConstantSDNode>(N1))->getAPIntValue()
1968 // fold (mul c1, c2) -> c1*c2
1969 if (N0IsConst && N1IsConst)
1970 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0.getNode(), N1.getNode());
1972 // canonicalize constant to RHS
1973 if (N0IsConst && !N1IsConst)
1974 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
1975 // fold (mul x, 0) -> 0
1976 if (N1IsConst && ConstValue1 == 0)
1978 // We require a splat of the entire scalar bit width for non-contiguous
1981 ConstValue1.getBitWidth() == VT.getScalarType().getSizeInBits();
1982 // fold (mul x, 1) -> x
1983 if (N1IsConst && ConstValue1 == 1 && IsFullSplat)
1985 // fold (mul x, -1) -> 0-x
1986 if (N1IsConst && ConstValue1.isAllOnesValue())
1987 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1988 DAG.getConstant(0, VT), N0);
1989 // fold (mul x, (1 << c)) -> x << c
1990 if (N1IsConst && ConstValue1.isPowerOf2() && IsFullSplat)
1991 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
1992 DAG.getConstant(ConstValue1.logBase2(),
1993 getShiftAmountTy(N0.getValueType())));
1994 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1995 if (N1IsConst && (-ConstValue1).isPowerOf2() && IsFullSplat) {
1996 unsigned Log2Val = (-ConstValue1).logBase2();
1997 // FIXME: If the input is something that is easily negated (e.g. a
1998 // single-use add), we should put the negate there.
1999 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
2000 DAG.getConstant(0, VT),
2001 DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
2002 DAG.getConstant(Log2Val,
2003 getShiftAmountTy(N0.getValueType()))));
2007 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
2008 if (N1IsConst && N0.getOpcode() == ISD::SHL &&
2009 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2010 isa<ConstantSDNode>(N0.getOperand(1)))) {
2011 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT,
2012 N1, N0.getOperand(1));
2013 AddToWorklist(C3.getNode());
2014 return DAG.getNode(ISD::MUL, SDLoc(N), VT,
2015 N0.getOperand(0), C3);
2018 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
2021 SDValue Sh(nullptr,0), Y(nullptr,0);
2022 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
2023 if (N0.getOpcode() == ISD::SHL &&
2024 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2025 isa<ConstantSDNode>(N0.getOperand(1))) &&
2026 N0.getNode()->hasOneUse()) {
2028 } else if (N1.getOpcode() == ISD::SHL &&
2029 isa<ConstantSDNode>(N1.getOperand(1)) &&
2030 N1.getNode()->hasOneUse()) {
2035 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2036 Sh.getOperand(0), Y);
2037 return DAG.getNode(ISD::SHL, SDLoc(N), VT,
2038 Mul, Sh.getOperand(1));
2042 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
2043 if (N1IsConst && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
2044 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2045 isa<ConstantSDNode>(N0.getOperand(1))))
2046 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
2047 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
2048 N0.getOperand(0), N1),
2049 DAG.getNode(ISD::MUL, SDLoc(N1), VT,
2050 N0.getOperand(1), N1));
2053 SDValue RMUL = ReassociateOps(ISD::MUL, SDLoc(N), N0, N1);
2060 SDValue DAGCombiner::visitSDIV(SDNode *N) {
2061 SDValue N0 = N->getOperand(0);
2062 SDValue N1 = N->getOperand(1);
2063 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2064 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2065 EVT VT = N->getValueType(0);
2068 if (VT.isVector()) {
2069 SDValue FoldedVOp = SimplifyVBinOp(N);
2070 if (FoldedVOp.getNode()) return FoldedVOp;
2073 // fold (sdiv c1, c2) -> c1/c2
2074 if (N0C && N1C && !N1C->isNullValue())
2075 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
2076 // fold (sdiv X, 1) -> X
2077 if (N1C && N1C->getAPIntValue() == 1LL)
2079 // fold (sdiv X, -1) -> 0-X
2080 if (N1C && N1C->isAllOnesValue())
2081 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
2082 DAG.getConstant(0, VT), N0);
2083 // If we know the sign bits of both operands are zero, strength reduce to a
2084 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
2085 if (!VT.isVector()) {
2086 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2087 return DAG.getNode(ISD::UDIV, SDLoc(N), N1.getValueType(),
2091 // fold (sdiv X, pow2) -> simple ops after legalize
2092 if (N1C && !N1C->isNullValue() && (N1C->getAPIntValue().isPowerOf2() ||
2093 (-N1C->getAPIntValue()).isPowerOf2())) {
2094 // If dividing by powers of two is cheap, then don't perform the following
2096 if (TLI.isPow2SDivCheap())
2099 // Target-specific implementation of sdiv x, pow2.
2100 SDValue Res = BuildSDIVPow2(N);
2104 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
2106 // Splat the sign bit into the register
2108 DAG.getNode(ISD::SRA, SDLoc(N), VT, N0,
2109 DAG.getConstant(VT.getScalarSizeInBits() - 1,
2110 getShiftAmountTy(N0.getValueType())));
2111 AddToWorklist(SGN.getNode());
2113 // Add (N0 < 0) ? abs2 - 1 : 0;
2115 DAG.getNode(ISD::SRL, SDLoc(N), VT, SGN,
2116 DAG.getConstant(VT.getScalarSizeInBits() - lg2,
2117 getShiftAmountTy(SGN.getValueType())));
2118 SDValue ADD = DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, SRL);
2119 AddToWorklist(SRL.getNode());
2120 AddToWorklist(ADD.getNode()); // Divide by pow2
2121 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), VT, ADD,
2122 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
2124 // If we're dividing by a positive value, we're done. Otherwise, we must
2125 // negate the result.
2126 if (N1C->getAPIntValue().isNonNegative())
2129 AddToWorklist(SRA.getNode());
2130 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), SRA);
2133 // if integer divide is expensive and we satisfy the requirements, emit an
2134 // alternate sequence.
2135 if (N1C && !TLI.isIntDivCheap()) {
2136 SDValue Op = BuildSDIV(N);
2137 if (Op.getNode()) return Op;
2141 if (N0.getOpcode() == ISD::UNDEF)
2142 return DAG.getConstant(0, VT);
2143 // X / undef -> undef
2144 if (N1.getOpcode() == ISD::UNDEF)
2150 SDValue DAGCombiner::visitUDIV(SDNode *N) {
2151 SDValue N0 = N->getOperand(0);
2152 SDValue N1 = N->getOperand(1);
2153 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2154 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2155 EVT VT = N->getValueType(0);
2158 if (VT.isVector()) {
2159 SDValue FoldedVOp = SimplifyVBinOp(N);
2160 if (FoldedVOp.getNode()) return FoldedVOp;
2163 // fold (udiv c1, c2) -> c1/c2
2164 if (N0C && N1C && !N1C->isNullValue())
2165 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
2166 // fold (udiv x, (1 << c)) -> x >>u c
2167 if (N1C && N1C->getAPIntValue().isPowerOf2())
2168 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0,
2169 DAG.getConstant(N1C->getAPIntValue().logBase2(),
2170 getShiftAmountTy(N0.getValueType())));
2171 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
2172 if (N1.getOpcode() == ISD::SHL) {
2173 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2174 if (SHC->getAPIntValue().isPowerOf2()) {
2175 EVT ADDVT = N1.getOperand(1).getValueType();
2176 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N), ADDVT,
2178 DAG.getConstant(SHC->getAPIntValue()
2181 AddToWorklist(Add.getNode());
2182 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, Add);
2186 // fold (udiv x, c) -> alternate
2187 if (N1C && !TLI.isIntDivCheap()) {
2188 SDValue Op = BuildUDIV(N);
2189 if (Op.getNode()) return Op;
2193 if (N0.getOpcode() == ISD::UNDEF)
2194 return DAG.getConstant(0, VT);
2195 // X / undef -> undef
2196 if (N1.getOpcode() == ISD::UNDEF)
2202 SDValue DAGCombiner::visitSREM(SDNode *N) {
2203 SDValue N0 = N->getOperand(0);
2204 SDValue N1 = N->getOperand(1);
2205 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2206 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2207 EVT VT = N->getValueType(0);
2209 // fold (srem c1, c2) -> c1%c2
2210 if (N0C && N1C && !N1C->isNullValue())
2211 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
2212 // If we know the sign bits of both operands are zero, strength reduce to a
2213 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
2214 if (!VT.isVector()) {
2215 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2216 return DAG.getNode(ISD::UREM, SDLoc(N), VT, N0, N1);
2219 // If X/C can be simplified by the division-by-constant logic, lower
2220 // X%C to the equivalent of X-X/C*C.
2221 if (N1C && !N1C->isNullValue()) {
2222 SDValue Div = DAG.getNode(ISD::SDIV, SDLoc(N), VT, N0, N1);
2223 AddToWorklist(Div.getNode());
2224 SDValue OptimizedDiv = combine(Div.getNode());
2225 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2226 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2228 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2229 AddToWorklist(Mul.getNode());
2235 if (N0.getOpcode() == ISD::UNDEF)
2236 return DAG.getConstant(0, VT);
2237 // X % undef -> undef
2238 if (N1.getOpcode() == ISD::UNDEF)
2244 SDValue DAGCombiner::visitUREM(SDNode *N) {
2245 SDValue N0 = N->getOperand(0);
2246 SDValue N1 = N->getOperand(1);
2247 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2248 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2249 EVT VT = N->getValueType(0);
2251 // fold (urem c1, c2) -> c1%c2
2252 if (N0C && N1C && !N1C->isNullValue())
2253 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2254 // fold (urem x, pow2) -> (and x, pow2-1)
2255 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
2256 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0,
2257 DAG.getConstant(N1C->getAPIntValue()-1,VT));
2258 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2259 if (N1.getOpcode() == ISD::SHL) {
2260 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2261 if (SHC->getAPIntValue().isPowerOf2()) {
2263 DAG.getNode(ISD::ADD, SDLoc(N), VT, N1,
2264 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
2266 AddToWorklist(Add.getNode());
2267 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, Add);
2272 // If X/C can be simplified by the division-by-constant logic, lower
2273 // X%C to the equivalent of X-X/C*C.
2274 if (N1C && !N1C->isNullValue()) {
2275 SDValue Div = DAG.getNode(ISD::UDIV, SDLoc(N), VT, N0, N1);
2276 AddToWorklist(Div.getNode());
2277 SDValue OptimizedDiv = combine(Div.getNode());
2278 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2279 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2281 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2282 AddToWorklist(Mul.getNode());
2288 if (N0.getOpcode() == ISD::UNDEF)
2289 return DAG.getConstant(0, VT);
2290 // X % undef -> undef
2291 if (N1.getOpcode() == ISD::UNDEF)
2297 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2298 SDValue N0 = N->getOperand(0);
2299 SDValue N1 = N->getOperand(1);
2300 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2301 EVT VT = N->getValueType(0);
2304 // fold (mulhs x, 0) -> 0
2305 if (N1C && N1C->isNullValue())
2307 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2308 if (N1C && N1C->getAPIntValue() == 1)
2309 return DAG.getNode(ISD::SRA, SDLoc(N), N0.getValueType(), N0,
2310 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2311 getShiftAmountTy(N0.getValueType())));
2312 // fold (mulhs x, undef) -> 0
2313 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2314 return DAG.getConstant(0, VT);
2316 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2318 if (VT.isSimple() && !VT.isVector()) {
2319 MVT Simple = VT.getSimpleVT();
2320 unsigned SimpleSize = Simple.getSizeInBits();
2321 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2322 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2323 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2324 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2325 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2326 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2327 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2328 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2335 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2336 SDValue N0 = N->getOperand(0);
2337 SDValue N1 = N->getOperand(1);
2338 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2339 EVT VT = N->getValueType(0);
2342 // fold (mulhu x, 0) -> 0
2343 if (N1C && N1C->isNullValue())
2345 // fold (mulhu x, 1) -> 0
2346 if (N1C && N1C->getAPIntValue() == 1)
2347 return DAG.getConstant(0, N0.getValueType());
2348 // fold (mulhu x, undef) -> 0
2349 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2350 return DAG.getConstant(0, VT);
2352 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2354 if (VT.isSimple() && !VT.isVector()) {
2355 MVT Simple = VT.getSimpleVT();
2356 unsigned SimpleSize = Simple.getSizeInBits();
2357 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2358 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2359 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2360 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2361 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2362 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2363 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2364 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2371 /// Perform optimizations common to nodes that compute two values. LoOp and HiOp
2372 /// give the opcodes for the two computations that are being performed. Return
2373 /// true if a simplification was made.
2374 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2376 // If the high half is not needed, just compute the low half.
2377 bool HiExists = N->hasAnyUseOfValue(1);
2379 (!LegalOperations ||
2380 TLI.isOperationLegalOrCustom(LoOp, N->getValueType(0)))) {
2381 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
2382 return CombineTo(N, Res, Res);
2385 // If the low half is not needed, just compute the high half.
2386 bool LoExists = N->hasAnyUseOfValue(0);
2388 (!LegalOperations ||
2389 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2390 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
2391 return CombineTo(N, Res, Res);
2394 // If both halves are used, return as it is.
2395 if (LoExists && HiExists)
2398 // If the two computed results can be simplified separately, separate them.
2400 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
2401 AddToWorklist(Lo.getNode());
2402 SDValue LoOpt = combine(Lo.getNode());
2403 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2404 (!LegalOperations ||
2405 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2406 return CombineTo(N, LoOpt, LoOpt);
2410 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
2411 AddToWorklist(Hi.getNode());
2412 SDValue HiOpt = combine(Hi.getNode());
2413 if (HiOpt.getNode() && HiOpt != Hi &&
2414 (!LegalOperations ||
2415 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2416 return CombineTo(N, HiOpt, HiOpt);
2422 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2423 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2424 if (Res.getNode()) return Res;
2426 EVT VT = N->getValueType(0);
2429 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2431 if (VT.isSimple() && !VT.isVector()) {
2432 MVT Simple = VT.getSimpleVT();
2433 unsigned SimpleSize = Simple.getSizeInBits();
2434 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2435 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2436 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2437 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2438 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2439 // Compute the high part as N1.
2440 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2441 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2442 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2443 // Compute the low part as N0.
2444 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2445 return CombineTo(N, Lo, Hi);
2452 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2453 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2454 if (Res.getNode()) return Res;
2456 EVT VT = N->getValueType(0);
2459 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2461 if (VT.isSimple() && !VT.isVector()) {
2462 MVT Simple = VT.getSimpleVT();
2463 unsigned SimpleSize = Simple.getSizeInBits();
2464 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2465 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2466 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2467 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2468 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2469 // Compute the high part as N1.
2470 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2471 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2472 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2473 // Compute the low part as N0.
2474 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2475 return CombineTo(N, Lo, Hi);
2482 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2483 // (smulo x, 2) -> (saddo x, x)
2484 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2485 if (C2->getAPIntValue() == 2)
2486 return DAG.getNode(ISD::SADDO, SDLoc(N), N->getVTList(),
2487 N->getOperand(0), N->getOperand(0));
2492 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2493 // (umulo x, 2) -> (uaddo x, x)
2494 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2495 if (C2->getAPIntValue() == 2)
2496 return DAG.getNode(ISD::UADDO, SDLoc(N), N->getVTList(),
2497 N->getOperand(0), N->getOperand(0));
2502 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2503 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2504 if (Res.getNode()) return Res;
2509 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2510 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2511 if (Res.getNode()) return Res;
2516 /// If this is a binary operator with two operands of the same opcode, try to
2518 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2519 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2520 EVT VT = N0.getValueType();
2521 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2523 // Bail early if none of these transforms apply.
2524 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2526 // For each of OP in AND/OR/XOR:
2527 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2528 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2529 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2530 // fold (OP (bswap x), (bswap y)) -> (bswap (OP x, y))
2531 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2533 // do not sink logical op inside of a vector extend, since it may combine
2535 EVT Op0VT = N0.getOperand(0).getValueType();
2536 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2537 N0.getOpcode() == ISD::SIGN_EXTEND ||
2538 N0.getOpcode() == ISD::BSWAP ||
2539 // Avoid infinite looping with PromoteIntBinOp.
2540 (N0.getOpcode() == ISD::ANY_EXTEND &&
2541 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2542 (N0.getOpcode() == ISD::TRUNCATE &&
2543 (!TLI.isZExtFree(VT, Op0VT) ||
2544 !TLI.isTruncateFree(Op0VT, VT)) &&
2545 TLI.isTypeLegal(Op0VT))) &&
2547 Op0VT == N1.getOperand(0).getValueType() &&
2548 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2549 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2550 N0.getOperand(0).getValueType(),
2551 N0.getOperand(0), N1.getOperand(0));
2552 AddToWorklist(ORNode.getNode());
2553 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, ORNode);
2556 // For each of OP in SHL/SRL/SRA/AND...
2557 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2558 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2559 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2560 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2561 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2562 N0.getOperand(1) == N1.getOperand(1)) {
2563 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2564 N0.getOperand(0).getValueType(),
2565 N0.getOperand(0), N1.getOperand(0));
2566 AddToWorklist(ORNode.getNode());
2567 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
2568 ORNode, N0.getOperand(1));
2571 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
2572 // Only perform this optimization after type legalization and before
2573 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
2574 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
2575 // we don't want to undo this promotion.
2576 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
2578 if ((N0.getOpcode() == ISD::BITCAST ||
2579 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2580 Level == AfterLegalizeTypes) {
2581 SDValue In0 = N0.getOperand(0);
2582 SDValue In1 = N1.getOperand(0);
2583 EVT In0Ty = In0.getValueType();
2584 EVT In1Ty = In1.getValueType();
2586 // If both incoming values are integers, and the original types are the
2588 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
2589 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1);
2590 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
2591 AddToWorklist(Op.getNode());
2596 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
2597 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
2598 // If both shuffles use the same mask, and both shuffle within a single
2599 // vector, then it is worthwhile to move the swizzle after the operation.
2600 // The type-legalizer generates this pattern when loading illegal
2601 // vector types from memory. In many cases this allows additional shuffle
2603 // There are other cases where moving the shuffle after the xor/and/or
2604 // is profitable even if shuffles don't perform a swizzle.
2605 // If both shuffles use the same mask, and both shuffles have the same first
2606 // or second operand, then it might still be profitable to move the shuffle
2607 // after the xor/and/or operation.
2608 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
2609 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2610 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
2612 assert(N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() &&
2613 "Inputs to shuffles are not the same type");
2615 // Check that both shuffles use the same mask. The masks are known to be of
2616 // the same length because the result vector type is the same.
2617 // Check also that shuffles have only one use to avoid introducing extra
2619 if (SVN0->hasOneUse() && SVN1->hasOneUse() &&
2620 SVN0->getMask().equals(SVN1->getMask())) {
2621 SDValue ShOp = N0->getOperand(1);
2623 // Don't try to fold this node if it requires introducing a
2624 // build vector of all zeros that might be illegal at this stage.
2625 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2627 ShOp = DAG.getConstant(0, VT);
2632 // (AND (shuf (A, C), shuf (B, C)) -> shuf (AND (A, B), C)
2633 // (OR (shuf (A, C), shuf (B, C)) -> shuf (OR (A, B), C)
2634 // (XOR (shuf (A, C), shuf (B, C)) -> shuf (XOR (A, B), V_0)
2635 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
2636 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2637 N0->getOperand(0), N1->getOperand(0));
2638 AddToWorklist(NewNode.getNode());
2639 return DAG.getVectorShuffle(VT, SDLoc(N), NewNode, ShOp,
2640 &SVN0->getMask()[0]);
2643 // Don't try to fold this node if it requires introducing a
2644 // build vector of all zeros that might be illegal at this stage.
2645 ShOp = N0->getOperand(0);
2646 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2648 ShOp = DAG.getConstant(0, VT);
2653 // (AND (shuf (C, A), shuf (C, B)) -> shuf (C, AND (A, B))
2654 // (OR (shuf (C, A), shuf (C, B)) -> shuf (C, OR (A, B))
2655 // (XOR (shuf (C, A), shuf (C, B)) -> shuf (V_0, XOR (A, B))
2656 if (N0->getOperand(0) == N1->getOperand(0) && ShOp.getNode()) {
2657 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2658 N0->getOperand(1), N1->getOperand(1));
2659 AddToWorklist(NewNode.getNode());
2660 return DAG.getVectorShuffle(VT, SDLoc(N), ShOp, NewNode,
2661 &SVN0->getMask()[0]);
2669 SDValue DAGCombiner::visitAND(SDNode *N) {
2670 SDValue N0 = N->getOperand(0);
2671 SDValue N1 = N->getOperand(1);
2672 SDValue LL, LR, RL, RR, CC0, CC1;
2673 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2674 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2675 EVT VT = N1.getValueType();
2676 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2679 if (VT.isVector()) {
2680 SDValue FoldedVOp = SimplifyVBinOp(N);
2681 if (FoldedVOp.getNode()) return FoldedVOp;
2683 // fold (and x, 0) -> 0, vector edition
2684 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2685 // do not return N0, because undef node may exist in N0
2686 return DAG.getConstant(
2687 APInt::getNullValue(
2688 N0.getValueType().getScalarType().getSizeInBits()),
2690 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2691 // do not return N1, because undef node may exist in N1
2692 return DAG.getConstant(
2693 APInt::getNullValue(
2694 N1.getValueType().getScalarType().getSizeInBits()),
2697 // fold (and x, -1) -> x, vector edition
2698 if (ISD::isBuildVectorAllOnes(N0.getNode()))
2700 if (ISD::isBuildVectorAllOnes(N1.getNode()))
2704 // fold (and x, undef) -> 0
2705 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2706 return DAG.getConstant(0, VT);
2707 // fold (and c1, c2) -> c1&c2
2709 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2710 // canonicalize constant to RHS
2712 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
2713 // fold (and x, -1) -> x
2714 if (N1C && N1C->isAllOnesValue())
2716 // if (and x, c) is known to be zero, return 0
2717 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2718 APInt::getAllOnesValue(BitWidth)))
2719 return DAG.getConstant(0, VT);
2721 SDValue RAND = ReassociateOps(ISD::AND, SDLoc(N), N0, N1);
2724 // fold (and (or x, C), D) -> D if (C & D) == D
2725 if (N1C && N0.getOpcode() == ISD::OR)
2726 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2727 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2729 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2730 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2731 SDValue N0Op0 = N0.getOperand(0);
2732 APInt Mask = ~N1C->getAPIntValue();
2733 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2734 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2735 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
2736 N0.getValueType(), N0Op0);
2738 // Replace uses of the AND with uses of the Zero extend node.
2741 // We actually want to replace all uses of the any_extend with the
2742 // zero_extend, to avoid duplicating things. This will later cause this
2743 // AND to be folded.
2744 CombineTo(N0.getNode(), Zext);
2745 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2748 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2749 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2750 // already be zero by virtue of the width of the base type of the load.
2752 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2754 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2755 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2756 N0.getOpcode() == ISD::LOAD) {
2757 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2758 N0 : N0.getOperand(0) );
2760 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2761 // This can be a pure constant or a vector splat, in which case we treat the
2762 // vector as a scalar and use the splat value.
2763 APInt Constant = APInt::getNullValue(1);
2764 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2765 Constant = C->getAPIntValue();
2766 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2767 APInt SplatValue, SplatUndef;
2768 unsigned SplatBitSize;
2770 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2771 SplatBitSize, HasAnyUndefs);
2773 // Undef bits can contribute to a possible optimisation if set, so
2775 SplatValue |= SplatUndef;
2777 // The splat value may be something like "0x00FFFFFF", which means 0 for
2778 // the first vector value and FF for the rest, repeating. We need a mask
2779 // that will apply equally to all members of the vector, so AND all the
2780 // lanes of the constant together.
2781 EVT VT = Vector->getValueType(0);
2782 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2784 // If the splat value has been compressed to a bitlength lower
2785 // than the size of the vector lane, we need to re-expand it to
2787 if (BitWidth > SplatBitSize)
2788 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
2789 SplatBitSize < BitWidth;
2790 SplatBitSize = SplatBitSize * 2)
2791 SplatValue |= SplatValue.shl(SplatBitSize);
2793 Constant = APInt::getAllOnesValue(BitWidth);
2794 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
2795 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
2799 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
2800 // actually legal and isn't going to get expanded, else this is a false
2802 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2803 Load->getValueType(0),
2804 Load->getMemoryVT());
2806 // Resize the constant to the same size as the original memory access before
2807 // extension. If it is still the AllOnesValue then this AND is completely
2810 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
2813 switch (Load->getExtensionType()) {
2814 default: B = false; break;
2815 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2817 case ISD::NON_EXTLOAD: B = true; break;
2820 if (B && Constant.isAllOnesValue()) {
2821 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
2822 // preserve semantics once we get rid of the AND.
2823 SDValue NewLoad(Load, 0);
2824 if (Load->getExtensionType() == ISD::EXTLOAD) {
2825 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2826 Load->getValueType(0), SDLoc(Load),
2827 Load->getChain(), Load->getBasePtr(),
2828 Load->getOffset(), Load->getMemoryVT(),
2829 Load->getMemOperand());
2830 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
2831 if (Load->getNumValues() == 3) {
2832 // PRE/POST_INC loads have 3 values.
2833 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
2834 NewLoad.getValue(2) };
2835 CombineTo(Load, To, 3, true);
2837 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
2841 // Fold the AND away, taking care not to fold to the old load node if we
2843 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
2845 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2848 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2849 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2850 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2851 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2853 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2854 LL.getValueType().isInteger()) {
2855 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2856 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2857 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2858 LR.getValueType(), LL, RL);
2859 AddToWorklist(ORNode.getNode());
2860 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
2862 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2863 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2864 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(N0),
2865 LR.getValueType(), LL, RL);
2866 AddToWorklist(ANDNode.getNode());
2867 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1);
2869 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2870 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2871 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2872 LR.getValueType(), LL, RL);
2873 AddToWorklist(ORNode.getNode());
2874 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
2877 // Simplify (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)
2878 if (LL == RL && isa<ConstantSDNode>(LR) && isa<ConstantSDNode>(RR) &&
2879 Op0 == Op1 && LL.getValueType().isInteger() &&
2880 Op0 == ISD::SETNE && ((cast<ConstantSDNode>(LR)->isNullValue() &&
2881 cast<ConstantSDNode>(RR)->isAllOnesValue()) ||
2882 (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2883 cast<ConstantSDNode>(RR)->isNullValue()))) {
2884 SDValue ADDNode = DAG.getNode(ISD::ADD, SDLoc(N0), LL.getValueType(),
2885 LL, DAG.getConstant(1, LL.getValueType()));
2886 AddToWorklist(ADDNode.getNode());
2887 return DAG.getSetCC(SDLoc(N), VT, ADDNode,
2888 DAG.getConstant(2, LL.getValueType()), ISD::SETUGE);
2890 // canonicalize equivalent to ll == rl
2891 if (LL == RR && LR == RL) {
2892 Op1 = ISD::getSetCCSwappedOperands(Op1);
2895 if (LL == RL && LR == RR) {
2896 bool isInteger = LL.getValueType().isInteger();
2897 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2898 if (Result != ISD::SETCC_INVALID &&
2899 (!LegalOperations ||
2900 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
2901 TLI.isOperationLegal(ISD::SETCC,
2902 getSetCCResultType(N0.getSimpleValueType())))))
2903 return DAG.getSetCC(SDLoc(N), N0.getValueType(),
2908 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2909 if (N0.getOpcode() == N1.getOpcode()) {
2910 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2911 if (Tmp.getNode()) return Tmp;
2914 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2915 // fold (and (sra)) -> (and (srl)) when possible.
2916 if (!VT.isVector() &&
2917 SimplifyDemandedBits(SDValue(N, 0)))
2918 return SDValue(N, 0);
2920 // fold (zext_inreg (extload x)) -> (zextload x)
2921 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2922 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2923 EVT MemVT = LN0->getMemoryVT();
2924 // If we zero all the possible extended bits, then we can turn this into
2925 // a zextload if we are running before legalize or the operation is legal.
2926 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2927 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2928 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2929 ((!LegalOperations && !LN0->isVolatile()) ||
2930 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
2931 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2932 LN0->getChain(), LN0->getBasePtr(),
2933 MemVT, LN0->getMemOperand());
2935 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2936 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2939 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2940 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2942 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2943 EVT MemVT = LN0->getMemoryVT();
2944 // If we zero all the possible extended bits, then we can turn this into
2945 // a zextload if we are running before legalize or the operation is legal.
2946 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2947 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2948 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2949 ((!LegalOperations && !LN0->isVolatile()) ||
2950 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
2951 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2952 LN0->getChain(), LN0->getBasePtr(),
2953 MemVT, LN0->getMemOperand());
2955 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2956 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2960 // fold (and (load x), 255) -> (zextload x, i8)
2961 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2962 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2963 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2964 (N0.getOpcode() == ISD::ANY_EXTEND &&
2965 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2966 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2967 LoadSDNode *LN0 = HasAnyExt
2968 ? cast<LoadSDNode>(N0.getOperand(0))
2969 : cast<LoadSDNode>(N0);
2970 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2971 LN0->isUnindexed() && N0.hasOneUse() && SDValue(LN0, 0).hasOneUse()) {
2972 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2973 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2974 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2975 EVT LoadedVT = LN0->getMemoryVT();
2976 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2978 if (ExtVT == LoadedVT &&
2979 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy,
2983 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
2984 LN0->getChain(), LN0->getBasePtr(), ExtVT,
2985 LN0->getMemOperand());
2987 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2988 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2991 // Do not change the width of a volatile load.
2992 // Do not generate loads of non-round integer types since these can
2993 // be expensive (and would be wrong if the type is not byte sized).
2994 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2995 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy,
2997 EVT PtrType = LN0->getOperand(1).getValueType();
2999 unsigned Alignment = LN0->getAlignment();
3000 SDValue NewPtr = LN0->getBasePtr();
3002 // For big endian targets, we need to add an offset to the pointer
3003 // to load the correct bytes. For little endian systems, we merely
3004 // need to read fewer bytes from the same pointer.
3005 if (TLI.isBigEndian()) {
3006 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
3007 unsigned EVTStoreBytes = ExtVT.getStoreSize();
3008 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
3009 NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0), PtrType,
3010 NewPtr, DAG.getConstant(PtrOff, PtrType));
3011 Alignment = MinAlign(Alignment, PtrOff);
3014 AddToWorklist(NewPtr.getNode());
3017 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
3018 LN0->getChain(), NewPtr,
3019 LN0->getPointerInfo(),
3020 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
3021 LN0->isInvariant(), Alignment, LN0->getAAInfo());
3023 CombineTo(LN0, Load, Load.getValue(1));
3024 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3030 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
3031 VT.getSizeInBits() <= 64) {
3032 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3033 APInt ADDC = ADDI->getAPIntValue();
3034 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
3035 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
3036 // immediate for an add, but it is legal if its top c2 bits are set,
3037 // transform the ADD so the immediate doesn't need to be materialized
3039 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
3040 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3041 SRLI->getZExtValue());
3042 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
3044 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
3046 DAG.getNode(ISD::ADD, SDLoc(N0), VT,
3047 N0.getOperand(0), DAG.getConstant(ADDC, VT));
3048 CombineTo(N0.getNode(), NewAdd);
3049 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3057 // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
3058 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
3059 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
3060 N0.getOperand(1), false);
3061 if (BSwap.getNode())
3068 /// Match (a >> 8) | (a << 8) as (bswap a) >> 16.
3069 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
3070 bool DemandHighBits) {
3071 if (!LegalOperations)
3074 EVT VT = N->getValueType(0);
3075 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
3077 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3080 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
3081 bool LookPassAnd0 = false;
3082 bool LookPassAnd1 = false;
3083 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
3085 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
3087 if (N0.getOpcode() == ISD::AND) {
3088 if (!N0.getNode()->hasOneUse())
3090 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3091 if (!N01C || N01C->getZExtValue() != 0xFF00)
3093 N0 = N0.getOperand(0);
3094 LookPassAnd0 = true;
3097 if (N1.getOpcode() == ISD::AND) {
3098 if (!N1.getNode()->hasOneUse())
3100 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
3101 if (!N11C || N11C->getZExtValue() != 0xFF)
3103 N1 = N1.getOperand(0);
3104 LookPassAnd1 = true;
3107 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
3109 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
3111 if (!N0.getNode()->hasOneUse() ||
3112 !N1.getNode()->hasOneUse())
3115 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3116 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
3119 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
3122 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
3123 SDValue N00 = N0->getOperand(0);
3124 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
3125 if (!N00.getNode()->hasOneUse())
3127 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
3128 if (!N001C || N001C->getZExtValue() != 0xFF)
3130 N00 = N00.getOperand(0);
3131 LookPassAnd0 = true;
3134 SDValue N10 = N1->getOperand(0);
3135 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
3136 if (!N10.getNode()->hasOneUse())
3138 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
3139 if (!N101C || N101C->getZExtValue() != 0xFF00)
3141 N10 = N10.getOperand(0);
3142 LookPassAnd1 = true;
3148 // Make sure everything beyond the low halfword gets set to zero since the SRL
3149 // 16 will clear the top bits.
3150 unsigned OpSizeInBits = VT.getSizeInBits();
3151 if (DemandHighBits && OpSizeInBits > 16) {
3152 // If the left-shift isn't masked out then the only way this is a bswap is
3153 // if all bits beyond the low 8 are 0. In that case the entire pattern
3154 // reduces to a left shift anyway: leave it for other parts of the combiner.
3158 // However, if the right shift isn't masked out then it might be because
3159 // it's not needed. See if we can spot that too.
3160 if (!LookPassAnd1 &&
3161 !DAG.MaskedValueIsZero(
3162 N10, APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - 16)))
3166 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
3167 if (OpSizeInBits > 16)
3168 Res = DAG.getNode(ISD::SRL, SDLoc(N), VT, Res,
3169 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
3173 /// Return true if the specified node is an element that makes up a 32-bit
3174 /// packed halfword byteswap.
3175 /// ((x & 0x000000ff) << 8) |
3176 /// ((x & 0x0000ff00) >> 8) |
3177 /// ((x & 0x00ff0000) << 8) |
3178 /// ((x & 0xff000000) >> 8)
3179 static bool isBSwapHWordElement(SDValue N, MutableArrayRef<SDNode *> Parts) {
3180 if (!N.getNode()->hasOneUse())
3183 unsigned Opc = N.getOpcode();
3184 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
3187 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3192 switch (N1C->getZExtValue()) {
3195 case 0xFF: Num = 0; break;
3196 case 0xFF00: Num = 1; break;
3197 case 0xFF0000: Num = 2; break;
3198 case 0xFF000000: Num = 3; break;
3201 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
3202 SDValue N0 = N.getOperand(0);
3203 if (Opc == ISD::AND) {
3204 if (Num == 0 || Num == 2) {
3206 // (x >> 8) & 0xff0000
3207 if (N0.getOpcode() != ISD::SRL)
3209 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3210 if (!C || C->getZExtValue() != 8)
3213 // (x << 8) & 0xff00
3214 // (x << 8) & 0xff000000
3215 if (N0.getOpcode() != ISD::SHL)
3217 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3218 if (!C || C->getZExtValue() != 8)
3221 } else if (Opc == ISD::SHL) {
3223 // (x & 0xff0000) << 8
3224 if (Num != 0 && Num != 2)
3226 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3227 if (!C || C->getZExtValue() != 8)
3229 } else { // Opc == ISD::SRL
3230 // (x & 0xff00) >> 8
3231 // (x & 0xff000000) >> 8
3232 if (Num != 1 && Num != 3)
3234 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3235 if (!C || C->getZExtValue() != 8)
3242 Parts[Num] = N0.getOperand(0).getNode();
3246 /// Match a 32-bit packed halfword bswap. That is
3247 /// ((x & 0x000000ff) << 8) |
3248 /// ((x & 0x0000ff00) >> 8) |
3249 /// ((x & 0x00ff0000) << 8) |
3250 /// ((x & 0xff000000) >> 8)
3251 /// => (rotl (bswap x), 16)
3252 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
3253 if (!LegalOperations)
3256 EVT VT = N->getValueType(0);
3259 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3263 // (or (or (and), (and)), (or (and), (and)))
3264 // (or (or (or (and), (and)), (and)), (and))
3265 if (N0.getOpcode() != ISD::OR)
3267 SDValue N00 = N0.getOperand(0);
3268 SDValue N01 = N0.getOperand(1);
3269 SDNode *Parts[4] = {};
3271 if (N1.getOpcode() == ISD::OR &&
3272 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) {
3273 // (or (or (and), (and)), (or (and), (and)))
3274 SDValue N000 = N00.getOperand(0);
3275 if (!isBSwapHWordElement(N000, Parts))
3278 SDValue N001 = N00.getOperand(1);
3279 if (!isBSwapHWordElement(N001, Parts))
3281 SDValue N010 = N01.getOperand(0);
3282 if (!isBSwapHWordElement(N010, Parts))
3284 SDValue N011 = N01.getOperand(1);
3285 if (!isBSwapHWordElement(N011, Parts))
3288 // (or (or (or (and), (and)), (and)), (and))
3289 if (!isBSwapHWordElement(N1, Parts))
3291 if (!isBSwapHWordElement(N01, Parts))
3293 if (N00.getOpcode() != ISD::OR)
3295 SDValue N000 = N00.getOperand(0);
3296 if (!isBSwapHWordElement(N000, Parts))
3298 SDValue N001 = N00.getOperand(1);
3299 if (!isBSwapHWordElement(N001, Parts))
3303 // Make sure the parts are all coming from the same node.
3304 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
3307 SDValue BSwap = DAG.getNode(ISD::BSWAP, SDLoc(N), VT,
3308 SDValue(Parts[0],0));
3310 // Result of the bswap should be rotated by 16. If it's not legal, then
3311 // do (x << 16) | (x >> 16).
3312 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
3313 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
3314 return DAG.getNode(ISD::ROTL, SDLoc(N), VT, BSwap, ShAmt);
3315 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
3316 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, BSwap, ShAmt);
3317 return DAG.getNode(ISD::OR, SDLoc(N), VT,
3318 DAG.getNode(ISD::SHL, SDLoc(N), VT, BSwap, ShAmt),
3319 DAG.getNode(ISD::SRL, SDLoc(N), VT, BSwap, ShAmt));
3322 SDValue DAGCombiner::visitOR(SDNode *N) {
3323 SDValue N0 = N->getOperand(0);
3324 SDValue N1 = N->getOperand(1);
3325 SDValue LL, LR, RL, RR, CC0, CC1;
3326 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3327 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3328 EVT VT = N1.getValueType();
3331 if (VT.isVector()) {
3332 SDValue FoldedVOp = SimplifyVBinOp(N);
3333 if (FoldedVOp.getNode()) return FoldedVOp;
3335 // fold (or x, 0) -> x, vector edition
3336 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3338 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3341 // fold (or x, -1) -> -1, vector edition
3342 if (ISD::isBuildVectorAllOnes(N0.getNode()))
3343 // do not return N0, because undef node may exist in N0
3344 return DAG.getConstant(
3345 APInt::getAllOnesValue(
3346 N0.getValueType().getScalarType().getSizeInBits()),
3348 if (ISD::isBuildVectorAllOnes(N1.getNode()))
3349 // do not return N1, because undef node may exist in N1
3350 return DAG.getConstant(
3351 APInt::getAllOnesValue(
3352 N1.getValueType().getScalarType().getSizeInBits()),
3355 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
3356 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
3357 // Do this only if the resulting shuffle is legal.
3358 if (isa<ShuffleVectorSDNode>(N0) &&
3359 isa<ShuffleVectorSDNode>(N1) &&
3360 // Avoid folding a node with illegal type.
3361 TLI.isTypeLegal(VT) &&
3362 N0->getOperand(1) == N1->getOperand(1) &&
3363 ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode())) {
3364 bool CanFold = true;
3365 unsigned NumElts = VT.getVectorNumElements();
3366 const ShuffleVectorSDNode *SV0 = cast<ShuffleVectorSDNode>(N0);
3367 const ShuffleVectorSDNode *SV1 = cast<ShuffleVectorSDNode>(N1);
3368 // We construct two shuffle masks:
3369 // - Mask1 is a shuffle mask for a shuffle with N0 as the first operand
3370 // and N1 as the second operand.
3371 // - Mask2 is a shuffle mask for a shuffle with N1 as the first operand
3372 // and N0 as the second operand.
3373 // We do this because OR is commutable and therefore there might be
3374 // two ways to fold this node into a shuffle.
3375 SmallVector<int,4> Mask1;
3376 SmallVector<int,4> Mask2;
3378 for (unsigned i = 0; i != NumElts && CanFold; ++i) {
3379 int M0 = SV0->getMaskElt(i);
3380 int M1 = SV1->getMaskElt(i);
3382 // Both shuffle indexes are undef. Propagate Undef.
3383 if (M0 < 0 && M1 < 0) {
3384 Mask1.push_back(M0);
3385 Mask2.push_back(M0);
3389 if (M0 < 0 || M1 < 0 ||
3390 (M0 < (int)NumElts && M1 < (int)NumElts) ||
3391 (M0 >= (int)NumElts && M1 >= (int)NumElts)) {
3396 Mask1.push_back(M0 < (int)NumElts ? M0 : M1 + NumElts);
3397 Mask2.push_back(M1 < (int)NumElts ? M1 : M0 + NumElts);
3401 // Fold this sequence only if the resulting shuffle is 'legal'.
3402 if (TLI.isShuffleMaskLegal(Mask1, VT))
3403 return DAG.getVectorShuffle(VT, SDLoc(N), N0->getOperand(0),
3404 N1->getOperand(0), &Mask1[0]);
3405 if (TLI.isShuffleMaskLegal(Mask2, VT))
3406 return DAG.getVectorShuffle(VT, SDLoc(N), N1->getOperand(0),
3407 N0->getOperand(0), &Mask2[0]);
3412 // fold (or x, undef) -> -1
3413 if (!LegalOperations &&
3414 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3415 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
3416 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
3418 // fold (or c1, c2) -> c1|c2
3420 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
3421 // canonicalize constant to RHS
3423 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
3424 // fold (or x, 0) -> x
3425 if (N1C && N1C->isNullValue())
3427 // fold (or x, -1) -> -1
3428 if (N1C && N1C->isAllOnesValue())
3430 // fold (or x, c) -> c iff (x & ~c) == 0
3431 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3434 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
3435 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
3436 if (BSwap.getNode())
3438 BSwap = MatchBSwapHWordLow(N, N0, N1);
3439 if (BSwap.getNode())
3443 SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1);
3446 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
3447 // iff (c1 & c2) == 0.
3448 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3449 isa<ConstantSDNode>(N0.getOperand(1))) {
3450 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3451 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) {
3452 SDValue COR = DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1);
3455 return DAG.getNode(ISD::AND, SDLoc(N), VT,
3456 DAG.getNode(ISD::OR, SDLoc(N0), VT,
3457 N0.getOperand(0), N1), COR);
3460 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3461 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3462 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3463 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3465 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
3466 LL.getValueType().isInteger()) {
3467 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
3468 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
3469 if (cast<ConstantSDNode>(LR)->isNullValue() &&
3470 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3471 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(LR),
3472 LR.getValueType(), LL, RL);
3473 AddToWorklist(ORNode.getNode());
3474 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
3476 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
3477 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
3478 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
3479 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3480 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(LR),
3481 LR.getValueType(), LL, RL);
3482 AddToWorklist(ANDNode.getNode());
3483 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1);
3486 // canonicalize equivalent to ll == rl
3487 if (LL == RR && LR == RL) {
3488 Op1 = ISD::getSetCCSwappedOperands(Op1);
3491 if (LL == RL && LR == RR) {
3492 bool isInteger = LL.getValueType().isInteger();
3493 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3494 if (Result != ISD::SETCC_INVALID &&
3495 (!LegalOperations ||
3496 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
3497 TLI.isOperationLegal(ISD::SETCC,
3498 getSetCCResultType(N0.getValueType())))))
3499 return DAG.getSetCC(SDLoc(N), N0.getValueType(),
3504 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
3505 if (N0.getOpcode() == N1.getOpcode()) {
3506 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3507 if (Tmp.getNode()) return Tmp;
3510 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3511 if (N0.getOpcode() == ISD::AND &&
3512 N1.getOpcode() == ISD::AND &&
3513 N0.getOperand(1).getOpcode() == ISD::Constant &&
3514 N1.getOperand(1).getOpcode() == ISD::Constant &&
3515 // Don't increase # computations.
3516 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3517 // We can only do this xform if we know that bits from X that are set in C2
3518 // but not in C1 are already zero. Likewise for Y.
3519 const APInt &LHSMask =
3520 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3521 const APInt &RHSMask =
3522 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
3524 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3525 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3526 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
3527 N0.getOperand(0), N1.getOperand(0));
3528 return DAG.getNode(ISD::AND, SDLoc(N), VT, X,
3529 DAG.getConstant(LHSMask | RHSMask, VT));
3533 // See if this is some rotate idiom.
3534 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N)))
3535 return SDValue(Rot, 0);
3537 // Simplify the operands using demanded-bits information.
3538 if (!VT.isVector() &&
3539 SimplifyDemandedBits(SDValue(N, 0)))
3540 return SDValue(N, 0);
3545 /// Match "(X shl/srl V1) & V2" where V2 may not be present.
3546 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3547 if (Op.getOpcode() == ISD::AND) {
3548 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3549 Mask = Op.getOperand(1);
3550 Op = Op.getOperand(0);
3556 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3564 // Return true if we can prove that, whenever Neg and Pos are both in the
3565 // range [0, OpSize), Neg == (Pos == 0 ? 0 : OpSize - Pos). This means that
3566 // for two opposing shifts shift1 and shift2 and a value X with OpBits bits:
3568 // (or (shift1 X, Neg), (shift2 X, Pos))
3570 // reduces to a rotate in direction shift2 by Pos or (equivalently) a rotate
3571 // in direction shift1 by Neg. The range [0, OpSize) means that we only need
3572 // to consider shift amounts with defined behavior.
3573 static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned OpSize) {
3574 // If OpSize is a power of 2 then:
3576 // (a) (Pos == 0 ? 0 : OpSize - Pos) == (OpSize - Pos) & (OpSize - 1)
3577 // (b) Neg == Neg & (OpSize - 1) whenever Neg is in [0, OpSize).
3579 // So if OpSize is a power of 2 and Neg is (and Neg', OpSize-1), we check
3580 // for the stronger condition:
3582 // Neg & (OpSize - 1) == (OpSize - Pos) & (OpSize - 1) [A]
3584 // for all Neg and Pos. Since Neg & (OpSize - 1) == Neg' & (OpSize - 1)
3585 // we can just replace Neg with Neg' for the rest of the function.
3587 // In other cases we check for the even stronger condition:
3589 // Neg == OpSize - Pos [B]
3591 // for all Neg and Pos. Note that the (or ...) then invokes undefined
3592 // behavior if Pos == 0 (and consequently Neg == OpSize).
3594 // We could actually use [A] whenever OpSize is a power of 2, but the
3595 // only extra cases that it would match are those uninteresting ones
3596 // where Neg and Pos are never in range at the same time. E.g. for
3597 // OpSize == 32, using [A] would allow a Neg of the form (sub 64, Pos)
3598 // as well as (sub 32, Pos), but:
3600 // (or (shift1 X, (sub 64, Pos)), (shift2 X, Pos))
3602 // always invokes undefined behavior for 32-bit X.
3604 // Below, Mask == OpSize - 1 when using [A] and is all-ones otherwise.
3605 unsigned MaskLoBits = 0;
3606 if (Neg.getOpcode() == ISD::AND &&
3607 isPowerOf2_64(OpSize) &&
3608 Neg.getOperand(1).getOpcode() == ISD::Constant &&
3609 cast<ConstantSDNode>(Neg.getOperand(1))->getAPIntValue() == OpSize - 1) {
3610 Neg = Neg.getOperand(0);
3611 MaskLoBits = Log2_64(OpSize);
3614 // Check whether Neg has the form (sub NegC, NegOp1) for some NegC and NegOp1.
3615 if (Neg.getOpcode() != ISD::SUB)
3617 ConstantSDNode *NegC = dyn_cast<ConstantSDNode>(Neg.getOperand(0));
3620 SDValue NegOp1 = Neg.getOperand(1);
3622 // On the RHS of [A], if Pos is Pos' & (OpSize - 1), just replace Pos with
3623 // Pos'. The truncation is redundant for the purpose of the equality.
3625 Pos.getOpcode() == ISD::AND &&
3626 Pos.getOperand(1).getOpcode() == ISD::Constant &&
3627 cast<ConstantSDNode>(Pos.getOperand(1))->getAPIntValue() == OpSize - 1)
3628 Pos = Pos.getOperand(0);
3630 // The condition we need is now:
3632 // (NegC - NegOp1) & Mask == (OpSize - Pos) & Mask
3634 // If NegOp1 == Pos then we need:
3636 // OpSize & Mask == NegC & Mask
3638 // (because "x & Mask" is a truncation and distributes through subtraction).
3641 Width = NegC->getAPIntValue();
3642 // Check for cases where Pos has the form (add NegOp1, PosC) for some PosC.
3643 // Then the condition we want to prove becomes:
3645 // (NegC - NegOp1) & Mask == (OpSize - (NegOp1 + PosC)) & Mask
3647 // which, again because "x & Mask" is a truncation, becomes:
3649 // NegC & Mask == (OpSize - PosC) & Mask
3650 // OpSize & Mask == (NegC + PosC) & Mask
3651 else if (Pos.getOpcode() == ISD::ADD &&
3652 Pos.getOperand(0) == NegOp1 &&
3653 Pos.getOperand(1).getOpcode() == ISD::Constant)
3654 Width = (cast<ConstantSDNode>(Pos.getOperand(1))->getAPIntValue() +
3655 NegC->getAPIntValue());
3659 // Now we just need to check that OpSize & Mask == Width & Mask.
3661 // Opsize & Mask is 0 since Mask is Opsize - 1.
3662 return Width.getLoBits(MaskLoBits) == 0;
3663 return Width == OpSize;
3666 // A subroutine of MatchRotate used once we have found an OR of two opposite
3667 // shifts of Shifted. If Neg == <operand size> - Pos then the OR reduces
3668 // to both (PosOpcode Shifted, Pos) and (NegOpcode Shifted, Neg), with the
3669 // former being preferred if supported. InnerPos and InnerNeg are Pos and
3670 // Neg with outer conversions stripped away.
3671 SDNode *DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos,
3672 SDValue Neg, SDValue InnerPos,
3673 SDValue InnerNeg, unsigned PosOpcode,
3674 unsigned NegOpcode, SDLoc DL) {
3675 // fold (or (shl x, (*ext y)),
3676 // (srl x, (*ext (sub 32, y)))) ->
3677 // (rotl x, y) or (rotr x, (sub 32, y))
3679 // fold (or (shl x, (*ext (sub 32, y))),
3680 // (srl x, (*ext y))) ->
3681 // (rotr x, y) or (rotl x, (sub 32, y))
3682 EVT VT = Shifted.getValueType();
3683 if (matchRotateSub(InnerPos, InnerNeg, VT.getSizeInBits())) {
3684 bool HasPos = TLI.isOperationLegalOrCustom(PosOpcode, VT);
3685 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted,
3686 HasPos ? Pos : Neg).getNode();
3692 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3693 // idioms for rotate, and if the target supports rotation instructions, generate
3695 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL) {
3696 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3697 EVT VT = LHS.getValueType();
3698 if (!TLI.isTypeLegal(VT)) return nullptr;
3700 // The target must have at least one rotate flavor.
3701 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3702 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3703 if (!HasROTL && !HasROTR) return nullptr;
3705 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3706 SDValue LHSShift; // The shift.
3707 SDValue LHSMask; // AND value if any.
3708 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3709 return nullptr; // Not part of a rotate.
3711 SDValue RHSShift; // The shift.
3712 SDValue RHSMask; // AND value if any.
3713 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3714 return nullptr; // Not part of a rotate.
3716 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3717 return nullptr; // Not shifting the same value.
3719 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3720 return nullptr; // Shifts must disagree.
3722 // Canonicalize shl to left side in a shl/srl pair.
3723 if (RHSShift.getOpcode() == ISD::SHL) {
3724 std::swap(LHS, RHS);
3725 std::swap(LHSShift, RHSShift);
3726 std::swap(LHSMask , RHSMask );
3729 unsigned OpSizeInBits = VT.getSizeInBits();
3730 SDValue LHSShiftArg = LHSShift.getOperand(0);
3731 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3732 SDValue RHSShiftArg = RHSShift.getOperand(0);
3733 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3735 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3736 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3737 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3738 RHSShiftAmt.getOpcode() == ISD::Constant) {
3739 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3740 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3741 if ((LShVal + RShVal) != OpSizeInBits)
3744 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3745 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt);
3747 // If there is an AND of either shifted operand, apply it to the result.
3748 if (LHSMask.getNode() || RHSMask.getNode()) {
3749 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3751 if (LHSMask.getNode()) {
3752 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3753 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3755 if (RHSMask.getNode()) {
3756 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3757 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3760 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3763 return Rot.getNode();
3766 // If there is a mask here, and we have a variable shift, we can't be sure
3767 // that we're masking out the right stuff.
3768 if (LHSMask.getNode() || RHSMask.getNode())
3771 // If the shift amount is sign/zext/any-extended just peel it off.
3772 SDValue LExtOp0 = LHSShiftAmt;
3773 SDValue RExtOp0 = RHSShiftAmt;
3774 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3775 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3776 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3777 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3778 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3779 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3780 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3781 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3782 LExtOp0 = LHSShiftAmt.getOperand(0);
3783 RExtOp0 = RHSShiftAmt.getOperand(0);
3786 SDNode *TryL = MatchRotatePosNeg(LHSShiftArg, LHSShiftAmt, RHSShiftAmt,
3787 LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL);
3791 SDNode *TryR = MatchRotatePosNeg(RHSShiftArg, RHSShiftAmt, LHSShiftAmt,
3792 RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL);
3799 SDValue DAGCombiner::visitXOR(SDNode *N) {
3800 SDValue N0 = N->getOperand(0);
3801 SDValue N1 = N->getOperand(1);
3802 SDValue LHS, RHS, CC;
3803 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3804 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3805 EVT VT = N0.getValueType();
3808 if (VT.isVector()) {
3809 SDValue FoldedVOp = SimplifyVBinOp(N);
3810 if (FoldedVOp.getNode()) return FoldedVOp;
3812 // fold (xor x, 0) -> x, vector edition
3813 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3815 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3819 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3820 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3821 return DAG.getConstant(0, VT);
3822 // fold (xor x, undef) -> undef
3823 if (N0.getOpcode() == ISD::UNDEF)
3825 if (N1.getOpcode() == ISD::UNDEF)
3827 // fold (xor c1, c2) -> c1^c2
3829 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3830 // canonicalize constant to RHS
3832 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
3833 // fold (xor x, 0) -> x
3834 if (N1C && N1C->isNullValue())
3837 SDValue RXOR = ReassociateOps(ISD::XOR, SDLoc(N), N0, N1);
3841 // fold !(x cc y) -> (x !cc y)
3842 if (TLI.isConstTrueVal(N1.getNode()) && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3843 bool isInt = LHS.getValueType().isInteger();
3844 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3847 if (!LegalOperations ||
3848 TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) {
3849 switch (N0.getOpcode()) {
3851 llvm_unreachable("Unhandled SetCC Equivalent!");
3853 return DAG.getSetCC(SDLoc(N), VT, LHS, RHS, NotCC);
3854 case ISD::SELECT_CC:
3855 return DAG.getSelectCC(SDLoc(N), LHS, RHS, N0.getOperand(2),
3856 N0.getOperand(3), NotCC);
3861 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3862 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3863 N0.getNode()->hasOneUse() &&
3864 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3865 SDValue V = N0.getOperand(0);
3866 V = DAG.getNode(ISD::XOR, SDLoc(N0), V.getValueType(), V,
3867 DAG.getConstant(1, V.getValueType()));
3868 AddToWorklist(V.getNode());
3869 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, V);
3872 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3873 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3874 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3875 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3876 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3877 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3878 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
3879 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
3880 AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
3881 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
3884 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3885 if (N1C && N1C->isAllOnesValue() &&
3886 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3887 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3888 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3889 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3890 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
3891 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
3892 AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
3893 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
3896 // fold (xor (and x, y), y) -> (and (not x), y)
3897 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3898 N0->getOperand(1) == N1) {
3899 SDValue X = N0->getOperand(0);
3900 SDValue NotX = DAG.getNOT(SDLoc(X), X, VT);
3901 AddToWorklist(NotX.getNode());
3902 return DAG.getNode(ISD::AND, SDLoc(N), VT, NotX, N1);
3904 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3905 if (N1C && N0.getOpcode() == ISD::XOR) {
3906 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3907 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3909 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(1),
3910 DAG.getConstant(N1C->getAPIntValue() ^
3911 N00C->getAPIntValue(), VT));
3913 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(0),
3914 DAG.getConstant(N1C->getAPIntValue() ^
3915 N01C->getAPIntValue(), VT));
3917 // fold (xor x, x) -> 0
3919 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
3921 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3922 if (N0.getOpcode() == N1.getOpcode()) {
3923 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3924 if (Tmp.getNode()) return Tmp;
3927 // Simplify the expression using non-local knowledge.
3928 if (!VT.isVector() &&
3929 SimplifyDemandedBits(SDValue(N, 0)))
3930 return SDValue(N, 0);
3935 /// Handle transforms common to the three shifts, when the shift amount is a
3937 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, ConstantSDNode *Amt) {
3938 // We can't and shouldn't fold opaque constants.
3939 if (Amt->isOpaque())
3942 SDNode *LHS = N->getOperand(0).getNode();
3943 if (!LHS->hasOneUse()) return SDValue();
3945 // We want to pull some binops through shifts, so that we have (and (shift))
3946 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3947 // thing happens with address calculations, so it's important to canonicalize
3949 bool HighBitSet = false; // Can we transform this if the high bit is set?
3951 switch (LHS->getOpcode()) {
3952 default: return SDValue();
3955 HighBitSet = false; // We can only transform sra if the high bit is clear.
3958 HighBitSet = true; // We can only transform sra if the high bit is set.
3961 if (N->getOpcode() != ISD::SHL)
3962 return SDValue(); // only shl(add) not sr[al](add).
3963 HighBitSet = false; // We can only transform sra if the high bit is clear.
3967 // We require the RHS of the binop to be a constant and not opaque as well.
3968 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3969 if (!BinOpCst || BinOpCst->isOpaque()) return SDValue();
3971 // FIXME: disable this unless the input to the binop is a shift by a constant.
3972 // If it is not a shift, it pessimizes some common cases like:
3974 // void foo(int *X, int i) { X[i & 1235] = 1; }
3975 // int bar(int *X, int i) { return X[i & 255]; }
3976 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3977 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3978 BinOpLHSVal->getOpcode() != ISD::SRA &&
3979 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3980 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3983 EVT VT = N->getValueType(0);
3985 // If this is a signed shift right, and the high bit is modified by the
3986 // logical operation, do not perform the transformation. The highBitSet
3987 // boolean indicates the value of the high bit of the constant which would
3988 // cause it to be modified for this operation.
3989 if (N->getOpcode() == ISD::SRA) {
3990 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3991 if (BinOpRHSSignSet != HighBitSet)
3995 if (!TLI.isDesirableToCommuteWithShift(LHS))
3998 // Fold the constants, shifting the binop RHS by the shift amount.
3999 SDValue NewRHS = DAG.getNode(N->getOpcode(), SDLoc(LHS->getOperand(1)),
4001 LHS->getOperand(1), N->getOperand(1));
4002 assert(isa<ConstantSDNode>(NewRHS) && "Folding was not successful!");
4004 // Create the new shift.
4005 SDValue NewShift = DAG.getNode(N->getOpcode(),
4006 SDLoc(LHS->getOperand(0)),
4007 VT, LHS->getOperand(0), N->getOperand(1));
4009 // Create the new binop.
4010 return DAG.getNode(LHS->getOpcode(), SDLoc(N), VT, NewShift, NewRHS);
4013 SDValue DAGCombiner::distributeTruncateThroughAnd(SDNode *N) {
4014 assert(N->getOpcode() == ISD::TRUNCATE);
4015 assert(N->getOperand(0).getOpcode() == ISD::AND);
4017 // (truncate:TruncVT (and N00, N01C)) -> (and (truncate:TruncVT N00), TruncC)
4018 if (N->hasOneUse() && N->getOperand(0).hasOneUse()) {
4019 SDValue N01 = N->getOperand(0).getOperand(1);
4021 if (ConstantSDNode *N01C = isConstOrConstSplat(N01)) {
4022 EVT TruncVT = N->getValueType(0);
4023 SDValue N00 = N->getOperand(0).getOperand(0);
4024 APInt TruncC = N01C->getAPIntValue();
4025 TruncC = TruncC.trunc(TruncVT.getScalarSizeInBits());
4027 return DAG.getNode(ISD::AND, SDLoc(N), TruncVT,
4028 DAG.getNode(ISD::TRUNCATE, SDLoc(N), TruncVT, N00),
4029 DAG.getConstant(TruncC, TruncVT));
4036 SDValue DAGCombiner::visitRotate(SDNode *N) {
4037 // fold (rot* x, (trunc (and y, c))) -> (rot* x, (and (trunc y), (trunc c))).
4038 if (N->getOperand(1).getOpcode() == ISD::TRUNCATE &&
4039 N->getOperand(1).getOperand(0).getOpcode() == ISD::AND) {
4040 SDValue NewOp1 = distributeTruncateThroughAnd(N->getOperand(1).getNode());
4041 if (NewOp1.getNode())
4042 return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
4043 N->getOperand(0), NewOp1);
4048 SDValue DAGCombiner::visitSHL(SDNode *N) {
4049 SDValue N0 = N->getOperand(0);
4050 SDValue N1 = N->getOperand(1);
4051 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4052 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4053 EVT VT = N0.getValueType();
4054 unsigned OpSizeInBits = VT.getScalarSizeInBits();
4057 if (VT.isVector()) {
4058 SDValue FoldedVOp = SimplifyVBinOp(N);
4059 if (FoldedVOp.getNode()) return FoldedVOp;
4061 BuildVectorSDNode *N1CV = dyn_cast<BuildVectorSDNode>(N1);
4062 // If setcc produces all-one true value then:
4063 // (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<<N1CV)
4064 if (N1CV && N1CV->isConstant()) {
4065 if (N0.getOpcode() == ISD::AND) {
4066 SDValue N00 = N0->getOperand(0);
4067 SDValue N01 = N0->getOperand(1);
4068 BuildVectorSDNode *N01CV = dyn_cast<BuildVectorSDNode>(N01);
4070 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC &&
4071 TLI.getBooleanContents(N00.getOperand(0).getValueType()) ==
4072 TargetLowering::ZeroOrNegativeOneBooleanContent) {
4073 SDValue C = DAG.FoldConstantArithmetic(ISD::SHL, VT, N01CV, N1CV);
4075 return DAG.getNode(ISD::AND, SDLoc(N), VT, N00, C);
4078 N1C = isConstOrConstSplat(N1);
4083 // fold (shl c1, c2) -> c1<<c2
4085 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
4086 // fold (shl 0, x) -> 0
4087 if (N0C && N0C->isNullValue())
4089 // fold (shl x, c >= size(x)) -> undef
4090 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4091 return DAG.getUNDEF(VT);
4092 // fold (shl x, 0) -> x
4093 if (N1C && N1C->isNullValue())
4095 // fold (shl undef, x) -> 0
4096 if (N0.getOpcode() == ISD::UNDEF)
4097 return DAG.getConstant(0, VT);
4098 // if (shl x, c) is known to be zero, return 0
4099 if (DAG.MaskedValueIsZero(SDValue(N, 0),
4100 APInt::getAllOnesValue(OpSizeInBits)))
4101 return DAG.getConstant(0, VT);
4102 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
4103 if (N1.getOpcode() == ISD::TRUNCATE &&
4104 N1.getOperand(0).getOpcode() == ISD::AND) {
4105 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4106 if (NewOp1.getNode())
4107 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, NewOp1);
4110 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4111 return SDValue(N, 0);
4113 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
4114 if (N1C && N0.getOpcode() == ISD::SHL) {
4115 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4116 uint64_t c1 = N0C1->getZExtValue();
4117 uint64_t c2 = N1C->getZExtValue();
4118 if (c1 + c2 >= OpSizeInBits)
4119 return DAG.getConstant(0, VT);
4120 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
4121 DAG.getConstant(c1 + c2, N1.getValueType()));
4125 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
4126 // For this to be valid, the second form must not preserve any of the bits
4127 // that are shifted out by the inner shift in the first form. This means
4128 // the outer shift size must be >= the number of bits added by the ext.
4129 // As a corollary, we don't care what kind of ext it is.
4130 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
4131 N0.getOpcode() == ISD::ANY_EXTEND ||
4132 N0.getOpcode() == ISD::SIGN_EXTEND) &&
4133 N0.getOperand(0).getOpcode() == ISD::SHL) {
4134 SDValue N0Op0 = N0.getOperand(0);
4135 if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
4136 uint64_t c1 = N0Op0C1->getZExtValue();
4137 uint64_t c2 = N1C->getZExtValue();
4138 EVT InnerShiftVT = N0Op0.getValueType();
4139 uint64_t InnerShiftSize = InnerShiftVT.getScalarSizeInBits();
4140 if (c2 >= OpSizeInBits - InnerShiftSize) {
4141 if (c1 + c2 >= OpSizeInBits)
4142 return DAG.getConstant(0, VT);
4143 return DAG.getNode(ISD::SHL, SDLoc(N0), VT,
4144 DAG.getNode(N0.getOpcode(), SDLoc(N0), VT,
4145 N0Op0->getOperand(0)),
4146 DAG.getConstant(c1 + c2, N1.getValueType()));
4151 // fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C))
4152 // Only fold this if the inner zext has no other uses to avoid increasing
4153 // the total number of instructions.
4154 if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
4155 N0.getOperand(0).getOpcode() == ISD::SRL) {
4156 SDValue N0Op0 = N0.getOperand(0);
4157 if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
4158 uint64_t c1 = N0Op0C1->getZExtValue();
4159 if (c1 < VT.getScalarSizeInBits()) {
4160 uint64_t c2 = N1C->getZExtValue();
4162 SDValue NewOp0 = N0.getOperand(0);
4163 EVT CountVT = NewOp0.getOperand(1).getValueType();
4164 SDValue NewSHL = DAG.getNode(ISD::SHL, SDLoc(N), NewOp0.getValueType(),
4165 NewOp0, DAG.getConstant(c2, CountVT));
4166 AddToWorklist(NewSHL.getNode());
4167 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
4173 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
4174 // (and (srl x, (sub c1, c2), MASK)
4175 // Only fold this if the inner shift has no other uses -- if it does, folding
4176 // this will increase the total number of instructions.
4177 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4178 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4179 uint64_t c1 = N0C1->getZExtValue();
4180 if (c1 < OpSizeInBits) {
4181 uint64_t c2 = N1C->getZExtValue();
4182 APInt Mask = APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - c1);
4185 Mask = Mask.shl(c2 - c1);
4186 Shift = DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
4187 DAG.getConstant(c2 - c1, N1.getValueType()));
4189 Mask = Mask.lshr(c1 - c2);
4190 Shift = DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
4191 DAG.getConstant(c1 - c2, N1.getValueType()));
4193 return DAG.getNode(ISD::AND, SDLoc(N0), VT, Shift,
4194 DAG.getConstant(Mask, VT));
4198 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
4199 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
4200 unsigned BitSize = VT.getScalarSizeInBits();
4201 SDValue HiBitsMask =
4202 DAG.getConstant(APInt::getHighBitsSet(BitSize,
4203 BitSize - N1C->getZExtValue()), VT);
4204 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
4208 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2)
4209 // Variant of version done on multiply, except mul by a power of 2 is turned
4212 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
4213 (isa<ConstantSDNode>(N0.getOperand(1)) ||
4214 isConstantSplatVector(N0.getOperand(1).getNode(), Val))) {
4215 SDValue Shl0 = DAG.getNode(ISD::SHL, SDLoc(N0), VT, N0.getOperand(0), N1);
4216 SDValue Shl1 = DAG.getNode(ISD::SHL, SDLoc(N1), VT, N0.getOperand(1), N1);
4217 return DAG.getNode(ISD::ADD, SDLoc(N), VT, Shl0, Shl1);
4221 SDValue NewSHL = visitShiftByConstant(N, N1C);
4222 if (NewSHL.getNode())
4229 SDValue DAGCombiner::visitSRA(SDNode *N) {
4230 SDValue N0 = N->getOperand(0);
4231 SDValue N1 = N->getOperand(1);
4232 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4233 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4234 EVT VT = N0.getValueType();
4235 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
4238 if (VT.isVector()) {
4239 SDValue FoldedVOp = SimplifyVBinOp(N);
4240 if (FoldedVOp.getNode()) return FoldedVOp;
4242 N1C = isConstOrConstSplat(N1);
4245 // fold (sra c1, c2) -> (sra c1, c2)
4247 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
4248 // fold (sra 0, x) -> 0
4249 if (N0C && N0C->isNullValue())
4251 // fold (sra -1, x) -> -1
4252 if (N0C && N0C->isAllOnesValue())
4254 // fold (sra x, (setge c, size(x))) -> undef
4255 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4256 return DAG.getUNDEF(VT);
4257 // fold (sra x, 0) -> x
4258 if (N1C && N1C->isNullValue())
4260 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
4262 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
4263 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
4264 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
4266 ExtVT = EVT::getVectorVT(*DAG.getContext(),
4267 ExtVT, VT.getVectorNumElements());
4268 if ((!LegalOperations ||
4269 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
4270 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
4271 N0.getOperand(0), DAG.getValueType(ExtVT));
4274 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
4275 if (N1C && N0.getOpcode() == ISD::SRA) {
4276 if (ConstantSDNode *C1 = isConstOrConstSplat(N0.getOperand(1))) {
4277 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
4278 if (Sum >= OpSizeInBits)
4279 Sum = OpSizeInBits - 1;
4280 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0),
4281 DAG.getConstant(Sum, N1.getValueType()));
4285 // fold (sra (shl X, m), (sub result_size, n))
4286 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
4287 // result_size - n != m.
4288 // If truncate is free for the target sext(shl) is likely to result in better
4290 if (N0.getOpcode() == ISD::SHL && N1C) {
4291 // Get the two constanst of the shifts, CN0 = m, CN = n.
4292 const ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1));
4294 LLVMContext &Ctx = *DAG.getContext();
4295 // Determine what the truncate's result bitsize and type would be.
4296 EVT TruncVT = EVT::getIntegerVT(Ctx, OpSizeInBits - N1C->getZExtValue());
4299 TruncVT = EVT::getVectorVT(Ctx, TruncVT, VT.getVectorNumElements());
4301 // Determine the residual right-shift amount.
4302 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
4304 // If the shift is not a no-op (in which case this should be just a sign
4305 // extend already), the truncated to type is legal, sign_extend is legal
4306 // on that type, and the truncate to that type is both legal and free,
4307 // perform the transform.
4308 if ((ShiftAmt > 0) &&
4309 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
4310 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
4311 TLI.isTruncateFree(VT, TruncVT)) {
4313 SDValue Amt = DAG.getConstant(ShiftAmt,
4314 getShiftAmountTy(N0.getOperand(0).getValueType()));
4315 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), VT,
4316 N0.getOperand(0), Amt);
4317 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), TruncVT,
4319 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N),
4320 N->getValueType(0), Trunc);
4325 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
4326 if (N1.getOpcode() == ISD::TRUNCATE &&
4327 N1.getOperand(0).getOpcode() == ISD::AND) {
4328 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4329 if (NewOp1.getNode())
4330 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, NewOp1);
4333 // fold (sra (trunc (srl x, c1)), c2) -> (trunc (sra x, c1 + c2))
4334 // if c1 is equal to the number of bits the trunc removes
4335 if (N0.getOpcode() == ISD::TRUNCATE &&
4336 (N0.getOperand(0).getOpcode() == ISD::SRL ||
4337 N0.getOperand(0).getOpcode() == ISD::SRA) &&
4338 N0.getOperand(0).hasOneUse() &&
4339 N0.getOperand(0).getOperand(1).hasOneUse() &&
4341 SDValue N0Op0 = N0.getOperand(0);
4342 if (ConstantSDNode *LargeShift = isConstOrConstSplat(N0Op0.getOperand(1))) {
4343 unsigned LargeShiftVal = LargeShift->getZExtValue();
4344 EVT LargeVT = N0Op0.getValueType();
4346 if (LargeVT.getScalarSizeInBits() - OpSizeInBits == LargeShiftVal) {
4348 DAG.getConstant(LargeShiftVal + N1C->getZExtValue(),
4349 getShiftAmountTy(N0Op0.getOperand(0).getValueType()));
4350 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), LargeVT,
4351 N0Op0.getOperand(0), Amt);
4352 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, SRA);
4357 // Simplify, based on bits shifted out of the LHS.
4358 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4359 return SDValue(N, 0);
4362 // If the sign bit is known to be zero, switch this to a SRL.
4363 if (DAG.SignBitIsZero(N0))
4364 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1);
4367 SDValue NewSRA = visitShiftByConstant(N, N1C);
4368 if (NewSRA.getNode())
4375 SDValue DAGCombiner::visitSRL(SDNode *N) {
4376 SDValue N0 = N->getOperand(0);
4377 SDValue N1 = N->getOperand(1);
4378 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4379 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4380 EVT VT = N0.getValueType();
4381 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
4384 if (VT.isVector()) {
4385 SDValue FoldedVOp = SimplifyVBinOp(N);
4386 if (FoldedVOp.getNode()) return FoldedVOp;
4388 N1C = isConstOrConstSplat(N1);
4391 // fold (srl c1, c2) -> c1 >>u c2
4393 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
4394 // fold (srl 0, x) -> 0
4395 if (N0C && N0C->isNullValue())
4397 // fold (srl x, c >= size(x)) -> undef
4398 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4399 return DAG.getUNDEF(VT);
4400 // fold (srl x, 0) -> x
4401 if (N1C && N1C->isNullValue())
4403 // if (srl x, c) is known to be zero, return 0
4404 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
4405 APInt::getAllOnesValue(OpSizeInBits)))
4406 return DAG.getConstant(0, VT);
4408 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
4409 if (N1C && N0.getOpcode() == ISD::SRL) {
4410 if (ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1))) {
4411 uint64_t c1 = N01C->getZExtValue();
4412 uint64_t c2 = N1C->getZExtValue();
4413 if (c1 + c2 >= OpSizeInBits)
4414 return DAG.getConstant(0, VT);
4415 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
4416 DAG.getConstant(c1 + c2, N1.getValueType()));
4420 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
4421 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
4422 N0.getOperand(0).getOpcode() == ISD::SRL &&
4423 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
4425 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
4426 uint64_t c2 = N1C->getZExtValue();
4427 EVT InnerShiftVT = N0.getOperand(0).getValueType();
4428 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
4429 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
4430 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
4431 if (c1 + OpSizeInBits == InnerShiftSize) {
4432 if (c1 + c2 >= InnerShiftSize)
4433 return DAG.getConstant(0, VT);
4434 return DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT,
4435 DAG.getNode(ISD::SRL, SDLoc(N0), InnerShiftVT,
4436 N0.getOperand(0)->getOperand(0),
4437 DAG.getConstant(c1 + c2, ShiftCountVT)));
4441 // fold (srl (shl x, c), c) -> (and x, cst2)
4442 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1) {
4443 unsigned BitSize = N0.getScalarValueSizeInBits();
4444 if (BitSize <= 64) {
4445 uint64_t ShAmt = N1C->getZExtValue() + 64 - BitSize;
4446 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
4447 DAG.getConstant(~0ULL >> ShAmt, VT));
4451 // fold (srl (anyextend x), c) -> (and (anyextend (srl x, c)), mask)
4452 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
4453 // Shifting in all undef bits?
4454 EVT SmallVT = N0.getOperand(0).getValueType();
4455 unsigned BitSize = SmallVT.getScalarSizeInBits();
4456 if (N1C->getZExtValue() >= BitSize)
4457 return DAG.getUNDEF(VT);
4459 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
4460 uint64_t ShiftAmt = N1C->getZExtValue();
4461 SDValue SmallShift = DAG.getNode(ISD::SRL, SDLoc(N0), SmallVT,
4463 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
4464 AddToWorklist(SmallShift.getNode());
4465 APInt Mask = APInt::getAllOnesValue(OpSizeInBits).lshr(ShiftAmt);
4466 return DAG.getNode(ISD::AND, SDLoc(N), VT,
4467 DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, SmallShift),
4468 DAG.getConstant(Mask, VT));
4472 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
4473 // bit, which is unmodified by sra.
4474 if (N1C && N1C->getZExtValue() + 1 == OpSizeInBits) {
4475 if (N0.getOpcode() == ISD::SRA)
4476 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
4479 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
4480 if (N1C && N0.getOpcode() == ISD::CTLZ &&
4481 N1C->getAPIntValue() == Log2_32(OpSizeInBits)) {
4482 APInt KnownZero, KnownOne;
4483 DAG.computeKnownBits(N0.getOperand(0), KnownZero, KnownOne);
4485 // If any of the input bits are KnownOne, then the input couldn't be all
4486 // zeros, thus the result of the srl will always be zero.
4487 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
4489 // If all of the bits input the to ctlz node are known to be zero, then
4490 // the result of the ctlz is "32" and the result of the shift is one.
4491 APInt UnknownBits = ~KnownZero;
4492 if (UnknownBits == 0) return DAG.getConstant(1, VT);
4494 // Otherwise, check to see if there is exactly one bit input to the ctlz.
4495 if ((UnknownBits & (UnknownBits - 1)) == 0) {
4496 // Okay, we know that only that the single bit specified by UnknownBits
4497 // could be set on input to the CTLZ node. If this bit is set, the SRL
4498 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
4499 // to an SRL/XOR pair, which is likely to simplify more.
4500 unsigned ShAmt = UnknownBits.countTrailingZeros();
4501 SDValue Op = N0.getOperand(0);
4504 Op = DAG.getNode(ISD::SRL, SDLoc(N0), VT, Op,
4505 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
4506 AddToWorklist(Op.getNode());
4509 return DAG.getNode(ISD::XOR, SDLoc(N), VT,
4510 Op, DAG.getConstant(1, VT));
4514 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
4515 if (N1.getOpcode() == ISD::TRUNCATE &&
4516 N1.getOperand(0).getOpcode() == ISD::AND) {
4517 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4518 if (NewOp1.getNode())
4519 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1);
4522 // fold operands of srl based on knowledge that the low bits are not
4524 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4525 return SDValue(N, 0);
4528 SDValue NewSRL = visitShiftByConstant(N, N1C);
4529 if (NewSRL.getNode())
4533 // Attempt to convert a srl of a load into a narrower zero-extending load.
4534 SDValue NarrowLoad = ReduceLoadWidth(N);
4535 if (NarrowLoad.getNode())
4538 // Here is a common situation. We want to optimize:
4541 // %b = and i32 %a, 2
4542 // %c = srl i32 %b, 1
4543 // brcond i32 %c ...
4549 // %c = setcc eq %b, 0
4552 // However when after the source operand of SRL is optimized into AND, the SRL
4553 // itself may not be optimized further. Look for it and add the BRCOND into
4555 if (N->hasOneUse()) {
4556 SDNode *Use = *N->use_begin();
4557 if (Use->getOpcode() == ISD::BRCOND)
4559 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
4560 // Also look pass the truncate.
4561 Use = *Use->use_begin();
4562 if (Use->getOpcode() == ISD::BRCOND)
4570 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
4571 SDValue N0 = N->getOperand(0);
4572 EVT VT = N->getValueType(0);
4574 // fold (ctlz c1) -> c2
4575 if (isa<ConstantSDNode>(N0))
4576 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0);
4580 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
4581 SDValue N0 = N->getOperand(0);
4582 EVT VT = N->getValueType(0);
4584 // fold (ctlz_zero_undef c1) -> c2
4585 if (isa<ConstantSDNode>(N0))
4586 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4590 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
4591 SDValue N0 = N->getOperand(0);
4592 EVT VT = N->getValueType(0);
4594 // fold (cttz c1) -> c2
4595 if (isa<ConstantSDNode>(N0))
4596 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0);
4600 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
4601 SDValue N0 = N->getOperand(0);
4602 EVT VT = N->getValueType(0);
4604 // fold (cttz_zero_undef c1) -> c2
4605 if (isa<ConstantSDNode>(N0))
4606 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4610 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
4611 SDValue N0 = N->getOperand(0);
4612 EVT VT = N->getValueType(0);
4614 // fold (ctpop c1) -> c2
4615 if (isa<ConstantSDNode>(N0))
4616 return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0);
4621 /// \brief Generate Min/Max node
4622 static SDValue combineMinNumMaxNum(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS,
4623 SDValue True, SDValue False,
4624 ISD::CondCode CC, const TargetLowering &TLI,
4625 SelectionDAG &DAG) {
4626 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
4636 unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
4637 if (TLI.isOperationLegal(Opcode, VT))
4638 return DAG.getNode(Opcode, DL, VT, LHS, RHS);
4647 unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
4648 if (TLI.isOperationLegal(Opcode, VT))
4649 return DAG.getNode(Opcode, DL, VT, LHS, RHS);
4657 SDValue DAGCombiner::visitSELECT(SDNode *N) {
4658 SDValue N0 = N->getOperand(0);
4659 SDValue N1 = N->getOperand(1);
4660 SDValue N2 = N->getOperand(2);
4661 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4662 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4663 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
4664 EVT VT = N->getValueType(0);
4665 EVT VT0 = N0.getValueType();
4667 // fold (select C, X, X) -> X
4670 // fold (select true, X, Y) -> X
4671 if (N0C && !N0C->isNullValue())
4673 // fold (select false, X, Y) -> Y
4674 if (N0C && N0C->isNullValue())
4676 // fold (select C, 1, X) -> (or C, X)
4677 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
4678 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4679 // fold (select C, 0, 1) -> (xor C, 1)
4680 // We can't do this reliably if integer based booleans have different contents
4681 // to floating point based booleans. This is because we can't tell whether we
4682 // have an integer-based boolean or a floating-point-based boolean unless we
4683 // can find the SETCC that produced it and inspect its operands. This is
4684 // fairly easy if C is the SETCC node, but it can potentially be
4685 // undiscoverable (or not reasonably discoverable). For example, it could be
4686 // in another basic block or it could require searching a complicated
4688 if (VT.isInteger() &&
4689 (VT0 == MVT::i1 || (VT0.isInteger() &&
4690 TLI.getBooleanContents(false, false) ==
4691 TLI.getBooleanContents(false, true) &&
4692 TLI.getBooleanContents(false, false) ==
4693 TargetLowering::ZeroOrOneBooleanContent)) &&
4694 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
4697 return DAG.getNode(ISD::XOR, SDLoc(N), VT0,
4698 N0, DAG.getConstant(1, VT0));
4699 XORNode = DAG.getNode(ISD::XOR, SDLoc(N0), VT0,
4700 N0, DAG.getConstant(1, VT0));
4701 AddToWorklist(XORNode.getNode());
4703 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, XORNode);
4704 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, XORNode);
4706 // fold (select C, 0, X) -> (and (not C), X)
4707 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
4708 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4709 AddToWorklist(NOTNode.getNode());
4710 return DAG.getNode(ISD::AND, SDLoc(N), VT, NOTNode, N2);
4712 // fold (select C, X, 1) -> (or (not C), X)
4713 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
4714 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4715 AddToWorklist(NOTNode.getNode());
4716 return DAG.getNode(ISD::OR, SDLoc(N), VT, NOTNode, N1);
4718 // fold (select C, X, 0) -> (and C, X)
4719 if (VT == MVT::i1 && N2C && N2C->isNullValue())
4720 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4721 // fold (select X, X, Y) -> (or X, Y)
4722 // fold (select X, 1, Y) -> (or X, Y)
4723 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
4724 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4725 // fold (select X, Y, X) -> (and X, Y)
4726 // fold (select X, Y, 0) -> (and X, Y)
4727 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
4728 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4730 // If we can fold this based on the true/false value, do so.
4731 if (SimplifySelectOps(N, N1, N2))
4732 return SDValue(N, 0); // Don't revisit N.
4734 // fold selects based on a setcc into other things, such as min/max/abs
4735 if (N0.getOpcode() == ISD::SETCC) {
4736 // select x, y (fcmp lt x, y) -> fminnum x, y
4737 // select x, y (fcmp gt x, y) -> fmaxnum x, y
4739 // This is OK if we don't care about what happens if either operand is a
4743 // FIXME: Instead of testing for UnsafeFPMath, this should be checking for
4744 // no signed zeros as well as no nans.
4745 const TargetOptions &Options = DAG.getTarget().Options;
4746 if (Options.UnsafeFPMath &&
4747 VT.isFloatingPoint() && N0.hasOneUse() &&
4748 DAG.isKnownNeverNaN(N1) && DAG.isKnownNeverNaN(N2)) {
4749 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
4752 combineMinNumMaxNum(SDLoc(N), VT, N0.getOperand(0), N0.getOperand(1),
4753 N1, N2, CC, TLI, DAG);
4758 if ((!LegalOperations &&
4759 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) ||
4760 TLI.isOperationLegal(ISD::SELECT_CC, VT))
4761 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT,
4762 N0.getOperand(0), N0.getOperand(1),
4763 N1, N2, N0.getOperand(2));
4764 return SimplifySelect(SDLoc(N), N0, N1, N2);
4771 std::pair<SDValue, SDValue> SplitVSETCC(const SDNode *N, SelectionDAG &DAG) {
4774 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
4776 // Split the inputs.
4777 SDValue Lo, Hi, LL, LH, RL, RH;
4778 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
4779 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
4781 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
4782 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
4784 return std::make_pair(Lo, Hi);
4787 // This function assumes all the vselect's arguments are CONCAT_VECTOR
4788 // nodes and that the condition is a BV of ConstantSDNodes (or undefs).
4789 static SDValue ConvertSelectToConcatVector(SDNode *N, SelectionDAG &DAG) {
4791 SDValue Cond = N->getOperand(0);
4792 SDValue LHS = N->getOperand(1);
4793 SDValue RHS = N->getOperand(2);
4794 EVT VT = N->getValueType(0);
4795 int NumElems = VT.getVectorNumElements();
4796 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS &&
4797 RHS.getOpcode() == ISD::CONCAT_VECTORS &&
4798 Cond.getOpcode() == ISD::BUILD_VECTOR);
4800 // CONCAT_VECTOR can take an arbitrary number of arguments. We only care about
4801 // binary ones here.
4802 if (LHS->getNumOperands() != 2 || RHS->getNumOperands() != 2)
4805 // We're sure we have an even number of elements due to the
4806 // concat_vectors we have as arguments to vselect.
4807 // Skip BV elements until we find one that's not an UNDEF
4808 // After we find an UNDEF element, keep looping until we get to half the
4809 // length of the BV and see if all the non-undef nodes are the same.
4810 ConstantSDNode *BottomHalf = nullptr;
4811 for (int i = 0; i < NumElems / 2; ++i) {
4812 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
4815 if (BottomHalf == nullptr)
4816 BottomHalf = cast<ConstantSDNode>(Cond.getOperand(i));
4817 else if (Cond->getOperand(i).getNode() != BottomHalf)
4821 // Do the same for the second half of the BuildVector
4822 ConstantSDNode *TopHalf = nullptr;
4823 for (int i = NumElems / 2; i < NumElems; ++i) {
4824 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
4827 if (TopHalf == nullptr)
4828 TopHalf = cast<ConstantSDNode>(Cond.getOperand(i));
4829 else if (Cond->getOperand(i).getNode() != TopHalf)
4833 assert(TopHalf && BottomHalf &&
4834 "One half of the selector was all UNDEFs and the other was all the "
4835 "same value. This should have been addressed before this function.");
4837 ISD::CONCAT_VECTORS, dl, VT,
4838 BottomHalf->isNullValue() ? RHS->getOperand(0) : LHS->getOperand(0),
4839 TopHalf->isNullValue() ? RHS->getOperand(1) : LHS->getOperand(1));
4842 SDValue DAGCombiner::visitMSTORE(SDNode *N) {
4844 if (Level >= AfterLegalizeTypes)
4847 MaskedStoreSDNode *MST = dyn_cast<MaskedStoreSDNode>(N);
4848 SDValue Mask = MST->getMask();
4849 SDValue Data = MST->getData();
4852 // If the MSTORE data type requires splitting and the mask is provided by a
4853 // SETCC, then split both nodes and its operands before legalization. This
4854 // prevents the type legalizer from unrolling SETCC into scalar comparisons
4855 // and enables future optimizations (e.g. min/max pattern matching on X86).
4856 if (Mask.getOpcode() == ISD::SETCC) {
4858 // Check if any splitting is required.
4859 if (TLI.getTypeAction(*DAG.getContext(), Data.getValueType()) !=
4860 TargetLowering::TypeSplitVector)
4863 SDValue MaskLo, MaskHi, Lo, Hi;
4864 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
4867 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MST->getValueType(0));
4869 SDValue Chain = MST->getChain();
4870 SDValue Ptr = MST->getBasePtr();
4872 EVT MemoryVT = MST->getMemoryVT();
4873 unsigned Alignment = MST->getOriginalAlignment();
4875 // if Alignment is equal to the vector size,
4876 // take the half of it for the second part
4877 unsigned SecondHalfAlignment =
4878 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
4879 Alignment/2 : Alignment;
4881 EVT LoMemVT, HiMemVT;
4882 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
4884 SDValue DataLo, DataHi;
4885 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
4887 MachineMemOperand *MMO = DAG.getMachineFunction().
4888 getMachineMemOperand(MST->getPointerInfo(),
4889 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
4890 Alignment, MST->getAAInfo(), MST->getRanges());
4892 Lo = DAG.getMaskedStore(Chain, DL, DataLo, Ptr, MaskLo, MMO);
4894 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
4895 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4896 DAG.getConstant(IncrementSize, Ptr.getValueType()));
4898 MMO = DAG.getMachineFunction().
4899 getMachineMemOperand(MST->getPointerInfo(),
4900 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
4901 SecondHalfAlignment, MST->getAAInfo(),
4904 Hi = DAG.getMaskedStore(Chain, DL, DataHi, Ptr, MaskHi, MMO);
4906 AddToWorklist(Lo.getNode());
4907 AddToWorklist(Hi.getNode());
4909 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
4914 SDValue DAGCombiner::visitMLOAD(SDNode *N) {
4916 if (Level >= AfterLegalizeTypes)
4919 MaskedLoadSDNode *MLD = dyn_cast<MaskedLoadSDNode>(N);
4920 SDValue Mask = MLD->getMask();
4923 // If the MLOAD result requires splitting and the mask is provided by a
4924 // SETCC, then split both nodes and its operands before legalization. This
4925 // prevents the type legalizer from unrolling SETCC into scalar comparisons
4926 // and enables future optimizations (e.g. min/max pattern matching on X86).
4928 if (Mask.getOpcode() == ISD::SETCC) {
4929 EVT VT = N->getValueType(0);
4931 // Check if any splitting is required.
4932 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
4933 TargetLowering::TypeSplitVector)
4936 SDValue MaskLo, MaskHi, Lo, Hi;
4937 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
4939 SDValue Src0 = MLD->getSrc0();
4940 SDValue Src0Lo, Src0Hi;
4941 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, DL);
4944 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
4946 SDValue Chain = MLD->getChain();
4947 SDValue Ptr = MLD->getBasePtr();
4948 EVT MemoryVT = MLD->getMemoryVT();
4949 unsigned Alignment = MLD->getOriginalAlignment();
4951 // if Alignment is equal to the vector size,
4952 // take the half of it for the second part
4953 unsigned SecondHalfAlignment =
4954 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
4955 Alignment/2 : Alignment;
4957 EVT LoMemVT, HiMemVT;
4958 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
4960 MachineMemOperand *MMO = DAG.getMachineFunction().
4961 getMachineMemOperand(MLD->getPointerInfo(),
4962 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
4963 Alignment, MLD->getAAInfo(), MLD->getRanges());
4965 Lo = DAG.getMaskedLoad(LoVT, DL, Chain, Ptr, MaskLo, Src0Lo, MMO);
4967 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
4968 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4969 DAG.getConstant(IncrementSize, Ptr.getValueType()));
4971 MMO = DAG.getMachineFunction().
4972 getMachineMemOperand(MLD->getPointerInfo(),
4973 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
4974 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
4976 Hi = DAG.getMaskedLoad(HiVT, DL, Chain, Ptr, MaskHi, Src0Hi, MMO);
4978 AddToWorklist(Lo.getNode());
4979 AddToWorklist(Hi.getNode());
4981 // Build a factor node to remember that this load is independent of the
4983 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo.getValue(1),
4986 // Legalized the chain result - switch anything that used the old chain to
4988 DAG.ReplaceAllUsesOfValueWith(SDValue(MLD, 1), Chain);
4990 SDValue LoadRes = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
4992 SDValue RetOps[] = { LoadRes, Chain };
4993 return DAG.getMergeValues(RetOps, DL);
4998 SDValue DAGCombiner::visitVSELECT(SDNode *N) {
4999 SDValue N0 = N->getOperand(0);
5000 SDValue N1 = N->getOperand(1);
5001 SDValue N2 = N->getOperand(2);
5004 // Canonicalize integer abs.
5005 // vselect (setg[te] X, 0), X, -X ->
5006 // vselect (setgt X, -1), X, -X ->
5007 // vselect (setl[te] X, 0), -X, X ->
5008 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5009 if (N0.getOpcode() == ISD::SETCC) {
5010 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
5011 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
5013 bool RHSIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
5015 if (((RHSIsAllZeros && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
5016 (ISD::isBuildVectorAllOnes(RHS.getNode()) && CC == ISD::SETGT)) &&
5017 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1))
5018 isAbs = ISD::isBuildVectorAllZeros(N2.getOperand(0).getNode());
5019 else if ((RHSIsAllZeros && (CC == ISD::SETLT || CC == ISD::SETLE)) &&
5020 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1))
5021 isAbs = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode());
5024 EVT VT = LHS.getValueType();
5025 SDValue Shift = DAG.getNode(
5026 ISD::SRA, DL, VT, LHS,
5027 DAG.getConstant(VT.getScalarType().getSizeInBits() - 1, VT));
5028 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, LHS, Shift);
5029 AddToWorklist(Shift.getNode());
5030 AddToWorklist(Add.getNode());
5031 return DAG.getNode(ISD::XOR, DL, VT, Add, Shift);
5035 // If the VSELECT result requires splitting and the mask is provided by a
5036 // SETCC, then split both nodes and its operands before legalization. This
5037 // prevents the type legalizer from unrolling SETCC into scalar comparisons
5038 // and enables future optimizations (e.g. min/max pattern matching on X86).
5039 if (N0.getOpcode() == ISD::SETCC) {
5040 EVT VT = N->getValueType(0);
5042 // Check if any splitting is required.
5043 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
5044 TargetLowering::TypeSplitVector)
5047 SDValue Lo, Hi, CCLo, CCHi, LL, LH, RL, RH;
5048 std::tie(CCLo, CCHi) = SplitVSETCC(N0.getNode(), DAG);
5049 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 1);
5050 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 2);
5052 Lo = DAG.getNode(N->getOpcode(), DL, LL.getValueType(), CCLo, LL, RL);
5053 Hi = DAG.getNode(N->getOpcode(), DL, LH.getValueType(), CCHi, LH, RH);
5055 // Add the new VSELECT nodes to the work list in case they need to be split
5057 AddToWorklist(Lo.getNode());
5058 AddToWorklist(Hi.getNode());
5060 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
5063 // Fold (vselect (build_vector all_ones), N1, N2) -> N1
5064 if (ISD::isBuildVectorAllOnes(N0.getNode()))
5066 // Fold (vselect (build_vector all_zeros), N1, N2) -> N2
5067 if (ISD::isBuildVectorAllZeros(N0.getNode()))
5070 // The ConvertSelectToConcatVector function is assuming both the above
5071 // checks for (vselect (build_vector all{ones,zeros) ...) have been made
5073 if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
5074 N2.getOpcode() == ISD::CONCAT_VECTORS &&
5075 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
5076 SDValue CV = ConvertSelectToConcatVector(N, DAG);
5084 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
5085 SDValue N0 = N->getOperand(0);
5086 SDValue N1 = N->getOperand(1);
5087 SDValue N2 = N->getOperand(2);
5088 SDValue N3 = N->getOperand(3);
5089 SDValue N4 = N->getOperand(4);
5090 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
5092 // fold select_cc lhs, rhs, x, x, cc -> x
5096 // Determine if the condition we're dealing with is constant
5097 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
5098 N0, N1, CC, SDLoc(N), false);
5099 if (SCC.getNode()) {
5100 AddToWorklist(SCC.getNode());
5102 if (ConstantSDNode *SCCC = dyn_cast<ConstantSDNode>(SCC.getNode())) {
5103 if (!SCCC->isNullValue())
5104 return N2; // cond always true -> true val
5106 return N3; // cond always false -> false val
5109 // Fold to a simpler select_cc
5110 if (SCC.getOpcode() == ISD::SETCC)
5111 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N2.getValueType(),
5112 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
5116 // If we can fold this based on the true/false value, do so.
5117 if (SimplifySelectOps(N, N2, N3))
5118 return SDValue(N, 0); // Don't revisit N.
5120 // fold select_cc into other things, such as min/max/abs
5121 return SimplifySelectCC(SDLoc(N), N0, N1, N2, N3, CC);
5124 SDValue DAGCombiner::visitSETCC(SDNode *N) {
5125 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
5126 cast<CondCodeSDNode>(N->getOperand(2))->get(),
5130 // tryToFoldExtendOfConstant - Try to fold a sext/zext/aext
5131 // dag node into a ConstantSDNode or a build_vector of constants.
5132 // This function is called by the DAGCombiner when visiting sext/zext/aext
5133 // dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).
5134 // Vector extends are not folded if operations are legal; this is to
5135 // avoid introducing illegal build_vector dag nodes.
5136 static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
5137 SelectionDAG &DAG, bool LegalTypes,
5138 bool LegalOperations) {
5139 unsigned Opcode = N->getOpcode();
5140 SDValue N0 = N->getOperand(0);
5141 EVT VT = N->getValueType(0);
5143 assert((Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND ||
5144 Opcode == ISD::ANY_EXTEND) && "Expected EXTEND dag node in input!");
5146 // fold (sext c1) -> c1
5147 // fold (zext c1) -> c1
5148 // fold (aext c1) -> c1
5149 if (isa<ConstantSDNode>(N0))
5150 return DAG.getNode(Opcode, SDLoc(N), VT, N0).getNode();
5152 // fold (sext (build_vector AllConstants) -> (build_vector AllConstants)
5153 // fold (zext (build_vector AllConstants) -> (build_vector AllConstants)
5154 // fold (aext (build_vector AllConstants) -> (build_vector AllConstants)
5155 EVT SVT = VT.getScalarType();
5156 if (!(VT.isVector() &&
5157 (!LegalTypes || (!LegalOperations && TLI.isTypeLegal(SVT))) &&
5158 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())))
5161 // We can fold this node into a build_vector.
5162 unsigned VTBits = SVT.getSizeInBits();
5163 unsigned EVTBits = N0->getValueType(0).getScalarType().getSizeInBits();
5164 unsigned ShAmt = VTBits - EVTBits;
5165 SmallVector<SDValue, 8> Elts;
5166 unsigned NumElts = N0->getNumOperands();
5169 for (unsigned i=0; i != NumElts; ++i) {
5170 SDValue Op = N0->getOperand(i);
5171 if (Op->getOpcode() == ISD::UNDEF) {
5172 Elts.push_back(DAG.getUNDEF(SVT));
5176 ConstantSDNode *CurrentND = cast<ConstantSDNode>(Op);
5177 const APInt &C = APInt(VTBits, CurrentND->getAPIntValue().getZExtValue());
5178 if (Opcode == ISD::SIGN_EXTEND)
5179 Elts.push_back(DAG.getConstant(C.shl(ShAmt).ashr(ShAmt).getZExtValue(),
5182 Elts.push_back(DAG.getConstant(C.shl(ShAmt).lshr(ShAmt).getZExtValue(),
5186 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Elts).getNode();
5189 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
5190 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
5191 // transformation. Returns true if extension are possible and the above
5192 // mentioned transformation is profitable.
5193 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
5195 SmallVectorImpl<SDNode *> &ExtendNodes,
5196 const TargetLowering &TLI) {
5197 bool HasCopyToRegUses = false;
5198 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
5199 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
5200 UE = N0.getNode()->use_end();
5205 if (UI.getUse().getResNo() != N0.getResNo())
5207 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
5208 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
5209 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
5210 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
5211 // Sign bits will be lost after a zext.
5214 for (unsigned i = 0; i != 2; ++i) {
5215 SDValue UseOp = User->getOperand(i);
5218 if (!isa<ConstantSDNode>(UseOp))
5223 ExtendNodes.push_back(User);
5226 // If truncates aren't free and there are users we can't
5227 // extend, it isn't worthwhile.
5230 // Remember if this value is live-out.
5231 if (User->getOpcode() == ISD::CopyToReg)
5232 HasCopyToRegUses = true;
5235 if (HasCopyToRegUses) {
5236 bool BothLiveOut = false;
5237 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
5239 SDUse &Use = UI.getUse();
5240 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
5246 // Both unextended and extended values are live out. There had better be
5247 // a good reason for the transformation.
5248 return ExtendNodes.size();
5253 void DAGCombiner::ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
5254 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
5255 ISD::NodeType ExtType) {
5256 // Extend SetCC uses if necessary.
5257 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
5258 SDNode *SetCC = SetCCs[i];
5259 SmallVector<SDValue, 4> Ops;
5261 for (unsigned j = 0; j != 2; ++j) {
5262 SDValue SOp = SetCC->getOperand(j);
5264 Ops.push_back(ExtLoad);
5266 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
5269 Ops.push_back(SetCC->getOperand(2));
5270 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops));
5274 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
5275 SDValue N0 = N->getOperand(0);
5276 EVT VT = N->getValueType(0);
5278 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
5280 return SDValue(Res, 0);
5282 // fold (sext (sext x)) -> (sext x)
5283 // fold (sext (aext x)) -> (sext x)
5284 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
5285 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT,
5288 if (N0.getOpcode() == ISD::TRUNCATE) {
5289 // fold (sext (truncate (load x))) -> (sext (smaller load x))
5290 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
5291 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5292 if (NarrowLoad.getNode()) {
5293 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5294 if (NarrowLoad.getNode() != N0.getNode()) {
5295 CombineTo(N0.getNode(), NarrowLoad);
5296 // CombineTo deleted the truncate, if needed, but not what's under it.
5299 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5302 // See if the value being truncated is already sign extended. If so, just
5303 // eliminate the trunc/sext pair.
5304 SDValue Op = N0.getOperand(0);
5305 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
5306 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
5307 unsigned DestBits = VT.getScalarType().getSizeInBits();
5308 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
5310 if (OpBits == DestBits) {
5311 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
5312 // bits, it is already ready.
5313 if (NumSignBits > DestBits-MidBits)
5315 } else if (OpBits < DestBits) {
5316 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
5317 // bits, just sext from i32.
5318 if (NumSignBits > OpBits-MidBits)
5319 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, Op);
5321 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
5322 // bits, just truncate to i32.
5323 if (NumSignBits > OpBits-MidBits)
5324 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
5327 // fold (sext (truncate x)) -> (sextinreg x).
5328 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
5329 N0.getValueType())) {
5330 if (OpBits < DestBits)
5331 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op);
5332 else if (OpBits > DestBits)
5333 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op);
5334 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, Op,
5335 DAG.getValueType(N0.getValueType()));
5339 // fold (sext (load x)) -> (sext (truncate (sextload x)))
5340 // None of the supported targets knows how to perform load and sign extend
5341 // on vectors in one instruction. We only perform this transformation on
5343 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
5344 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5345 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5346 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, N0.getValueType()))) {
5347 bool DoXform = true;
5348 SmallVector<SDNode*, 4> SetCCs;
5349 if (!N0.hasOneUse())
5350 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
5352 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5353 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5355 LN0->getBasePtr(), N0.getValueType(),
5356 LN0->getMemOperand());
5357 CombineTo(N, ExtLoad);
5358 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5359 N0.getValueType(), ExtLoad);
5360 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5361 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5363 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5367 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
5368 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
5369 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
5370 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
5371 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5372 EVT MemVT = LN0->getMemoryVT();
5373 if ((!LegalOperations && !LN0->isVolatile()) ||
5374 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, MemVT)) {
5375 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5377 LN0->getBasePtr(), MemVT,
5378 LN0->getMemOperand());
5379 CombineTo(N, ExtLoad);
5380 CombineTo(N0.getNode(),
5381 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5382 N0.getValueType(), ExtLoad),
5383 ExtLoad.getValue(1));
5384 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5388 // fold (sext (and/or/xor (load x), cst)) ->
5389 // (and/or/xor (sextload x), (sext cst))
5390 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
5391 N0.getOpcode() == ISD::XOR) &&
5392 isa<LoadSDNode>(N0.getOperand(0)) &&
5393 N0.getOperand(1).getOpcode() == ISD::Constant &&
5394 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, N0.getValueType()) &&
5395 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
5396 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
5397 if (LN0->getExtensionType() != ISD::ZEXTLOAD && LN0->isUnindexed()) {
5398 bool DoXform = true;
5399 SmallVector<SDNode*, 4> SetCCs;
5400 if (!N0.hasOneUse())
5401 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
5404 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(LN0), VT,
5405 LN0->getChain(), LN0->getBasePtr(),
5407 LN0->getMemOperand());
5408 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5409 Mask = Mask.sext(VT.getSizeInBits());
5410 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
5411 ExtLoad, DAG.getConstant(Mask, VT));
5412 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
5413 SDLoc(N0.getOperand(0)),
5414 N0.getOperand(0).getValueType(), ExtLoad);
5416 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
5417 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5419 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5424 if (N0.getOpcode() == ISD::SETCC) {
5425 EVT N0VT = N0.getOperand(0).getValueType();
5426 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
5427 // Only do this before legalize for now.
5428 if (VT.isVector() && !LegalOperations &&
5429 TLI.getBooleanContents(N0VT) ==
5430 TargetLowering::ZeroOrNegativeOneBooleanContent) {
5431 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
5432 // of the same size as the compared operands. Only optimize sext(setcc())
5433 // if this is the case.
5434 EVT SVT = getSetCCResultType(N0VT);
5436 // We know that the # elements of the results is the same as the
5437 // # elements of the compare (and the # elements of the compare result
5438 // for that matter). Check to see that they are the same size. If so,
5439 // we know that the element size of the sext'd result matches the
5440 // element size of the compare operands.
5441 if (VT.getSizeInBits() == SVT.getSizeInBits())
5442 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5444 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5446 // If the desired elements are smaller or larger than the source
5447 // elements we can use a matching integer vector type and then
5448 // truncate/sign extend
5449 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger();
5450 if (SVT == MatchingVectorType) {
5451 SDValue VsetCC = DAG.getSetCC(SDLoc(N), MatchingVectorType,
5452 N0.getOperand(0), N0.getOperand(1),
5453 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5454 return DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT);
5458 // sext(setcc x, y, cc) -> (select (setcc x, y, cc), -1, 0)
5459 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
5461 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
5463 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5464 NegOne, DAG.getConstant(0, VT),
5465 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5466 if (SCC.getNode()) return SCC;
5468 if (!VT.isVector()) {
5469 EVT SetCCVT = getSetCCResultType(N0.getOperand(0).getValueType());
5470 if (!LegalOperations || TLI.isOperationLegal(ISD::SETCC, SetCCVT)) {
5472 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
5473 SDValue SetCC = DAG.getSetCC(DL, SetCCVT,
5474 N0.getOperand(0), N0.getOperand(1), CC);
5475 return DAG.getSelect(DL, VT, SetCC,
5476 NegOne, DAG.getConstant(0, VT));
5481 // fold (sext x) -> (zext x) if the sign bit is known zero.
5482 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
5483 DAG.SignBitIsZero(N0))
5484 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0);
5489 // isTruncateOf - If N is a truncate of some other value, return true, record
5490 // the value being truncated in Op and which of Op's bits are zero in KnownZero.
5491 // This function computes KnownZero to avoid a duplicated call to
5492 // computeKnownBits in the caller.
5493 static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
5496 if (N->getOpcode() == ISD::TRUNCATE) {
5497 Op = N->getOperand(0);
5498 DAG.computeKnownBits(Op, KnownZero, KnownOne);
5502 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
5503 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
5506 SDValue Op0 = N->getOperand(0);
5507 SDValue Op1 = N->getOperand(1);
5508 assert(Op0.getValueType() == Op1.getValueType());
5510 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0);
5511 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1);
5512 if (COp0 && COp0->isNullValue())
5514 else if (COp1 && COp1->isNullValue())
5519 DAG.computeKnownBits(Op, KnownZero, KnownOne);
5521 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
5527 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
5528 SDValue N0 = N->getOperand(0);
5529 EVT VT = N->getValueType(0);
5531 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
5533 return SDValue(Res, 0);
5535 // fold (zext (zext x)) -> (zext x)
5536 // fold (zext (aext x)) -> (zext x)
5537 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
5538 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT,
5541 // fold (zext (truncate x)) -> (zext x) or
5542 // (zext (truncate x)) -> (truncate x)
5543 // This is valid when the truncated bits of x are already zero.
5544 // FIXME: We should extend this to work for vectors too.
5547 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
5548 APInt TruncatedBits =
5549 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
5550 APInt(Op.getValueSizeInBits(), 0) :
5551 APInt::getBitsSet(Op.getValueSizeInBits(),
5552 N0.getValueSizeInBits(),
5553 std::min(Op.getValueSizeInBits(),
5554 VT.getSizeInBits()));
5555 if (TruncatedBits == (KnownZero & TruncatedBits)) {
5556 if (VT.bitsGT(Op.getValueType()))
5557 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, Op);
5558 if (VT.bitsLT(Op.getValueType()))
5559 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
5565 // fold (zext (truncate (load x))) -> (zext (smaller load x))
5566 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
5567 if (N0.getOpcode() == ISD::TRUNCATE) {
5568 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5569 if (NarrowLoad.getNode()) {
5570 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5571 if (NarrowLoad.getNode() != N0.getNode()) {
5572 CombineTo(N0.getNode(), NarrowLoad);
5573 // CombineTo deleted the truncate, if needed, but not what's under it.
5576 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5580 // fold (zext (truncate x)) -> (and x, mask)
5581 if (N0.getOpcode() == ISD::TRUNCATE &&
5582 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
5584 // fold (zext (truncate (load x))) -> (zext (smaller load x))
5585 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
5586 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5587 if (NarrowLoad.getNode()) {
5588 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5589 if (NarrowLoad.getNode() != N0.getNode()) {
5590 CombineTo(N0.getNode(), NarrowLoad);
5591 // CombineTo deleted the truncate, if needed, but not what's under it.
5594 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5597 SDValue Op = N0.getOperand(0);
5598 if (Op.getValueType().bitsLT(VT)) {
5599 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Op);
5600 AddToWorklist(Op.getNode());
5601 } else if (Op.getValueType().bitsGT(VT)) {
5602 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
5603 AddToWorklist(Op.getNode());
5605 return DAG.getZeroExtendInReg(Op, SDLoc(N),
5606 N0.getValueType().getScalarType());
5609 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
5610 // if either of the casts is not free.
5611 if (N0.getOpcode() == ISD::AND &&
5612 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
5613 N0.getOperand(1).getOpcode() == ISD::Constant &&
5614 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
5615 N0.getValueType()) ||
5616 !TLI.isZExtFree(N0.getValueType(), VT))) {
5617 SDValue X = N0.getOperand(0).getOperand(0);
5618 if (X.getValueType().bitsLT(VT)) {
5619 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(X), VT, X);
5620 } else if (X.getValueType().bitsGT(VT)) {
5621 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
5623 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5624 Mask = Mask.zext(VT.getSizeInBits());
5625 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5626 X, DAG.getConstant(Mask, VT));
5629 // fold (zext (load x)) -> (zext (truncate (zextload x)))
5630 // None of the supported targets knows how to perform load and vector_zext
5631 // on vectors in one instruction. We only perform this transformation on
5633 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
5634 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5635 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5636 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, N0.getValueType()))) {
5637 bool DoXform = true;
5638 SmallVector<SDNode*, 4> SetCCs;
5639 if (!N0.hasOneUse())
5640 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
5642 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5643 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
5645 LN0->getBasePtr(), N0.getValueType(),
5646 LN0->getMemOperand());
5647 CombineTo(N, ExtLoad);
5648 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5649 N0.getValueType(), ExtLoad);
5650 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5652 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5654 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5658 // fold (zext (and/or/xor (load x), cst)) ->
5659 // (and/or/xor (zextload x), (zext cst))
5660 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
5661 N0.getOpcode() == ISD::XOR) &&
5662 isa<LoadSDNode>(N0.getOperand(0)) &&
5663 N0.getOperand(1).getOpcode() == ISD::Constant &&
5664 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, N0.getValueType()) &&
5665 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
5666 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
5667 if (LN0->getExtensionType() != ISD::SEXTLOAD && LN0->isUnindexed()) {
5668 bool DoXform = true;
5669 SmallVector<SDNode*, 4> SetCCs;
5670 if (!N0.hasOneUse())
5671 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
5674 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), VT,
5675 LN0->getChain(), LN0->getBasePtr(),
5677 LN0->getMemOperand());
5678 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5679 Mask = Mask.zext(VT.getSizeInBits());
5680 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
5681 ExtLoad, DAG.getConstant(Mask, VT));
5682 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
5683 SDLoc(N0.getOperand(0)),
5684 N0.getOperand(0).getValueType(), ExtLoad);
5686 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
5687 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5689 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5694 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
5695 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
5696 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
5697 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
5698 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5699 EVT MemVT = LN0->getMemoryVT();
5700 if ((!LegalOperations && !LN0->isVolatile()) ||
5701 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT)) {
5702 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
5704 LN0->getBasePtr(), MemVT,
5705 LN0->getMemOperand());
5706 CombineTo(N, ExtLoad);
5707 CombineTo(N0.getNode(),
5708 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(),
5710 ExtLoad.getValue(1));
5711 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5715 if (N0.getOpcode() == ISD::SETCC) {
5716 if (!LegalOperations && VT.isVector() &&
5717 N0.getValueType().getVectorElementType() == MVT::i1) {
5718 EVT N0VT = N0.getOperand(0).getValueType();
5719 if (getSetCCResultType(N0VT) == N0.getValueType())
5722 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
5723 // Only do this before legalize for now.
5724 EVT EltVT = VT.getVectorElementType();
5725 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
5726 DAG.getConstant(1, EltVT));
5727 if (VT.getSizeInBits() == N0VT.getSizeInBits())
5728 // We know that the # elements of the results is the same as the
5729 // # elements of the compare (and the # elements of the compare result
5730 // for that matter). Check to see that they are the same size. If so,
5731 // we know that the element size of the sext'd result matches the
5732 // element size of the compare operands.
5733 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5734 DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5736 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
5737 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT,
5740 // If the desired elements are smaller or larger than the source
5741 // elements we can use a matching integer vector type and then
5742 // truncate/sign extend
5743 EVT MatchingElementType =
5744 EVT::getIntegerVT(*DAG.getContext(),
5745 N0VT.getScalarType().getSizeInBits());
5746 EVT MatchingVectorType =
5747 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
5748 N0VT.getVectorNumElements());
5750 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
5752 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5753 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5754 DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT),
5755 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, OneOps));
5758 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
5760 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5761 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
5762 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5763 if (SCC.getNode()) return SCC;
5766 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
5767 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
5768 isa<ConstantSDNode>(N0.getOperand(1)) &&
5769 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
5771 SDValue ShAmt = N0.getOperand(1);
5772 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
5773 if (N0.getOpcode() == ISD::SHL) {
5774 SDValue InnerZExt = N0.getOperand(0);
5775 // If the original shl may be shifting out bits, do not perform this
5777 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
5778 InnerZExt.getOperand(0).getValueType().getSizeInBits();
5779 if (ShAmtVal > KnownZeroBits)
5785 // Ensure that the shift amount is wide enough for the shifted value.
5786 if (VT.getSizeInBits() >= 256)
5787 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
5789 return DAG.getNode(N0.getOpcode(), DL, VT,
5790 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
5797 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
5798 SDValue N0 = N->getOperand(0);
5799 EVT VT = N->getValueType(0);
5801 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
5803 return SDValue(Res, 0);
5805 // fold (aext (aext x)) -> (aext x)
5806 // fold (aext (zext x)) -> (zext x)
5807 // fold (aext (sext x)) -> (sext x)
5808 if (N0.getOpcode() == ISD::ANY_EXTEND ||
5809 N0.getOpcode() == ISD::ZERO_EXTEND ||
5810 N0.getOpcode() == ISD::SIGN_EXTEND)
5811 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0));
5813 // fold (aext (truncate (load x))) -> (aext (smaller load x))
5814 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
5815 if (N0.getOpcode() == ISD::TRUNCATE) {
5816 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5817 if (NarrowLoad.getNode()) {
5818 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5819 if (NarrowLoad.getNode() != N0.getNode()) {
5820 CombineTo(N0.getNode(), NarrowLoad);
5821 // CombineTo deleted the truncate, if needed, but not what's under it.
5824 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5828 // fold (aext (truncate x))
5829 if (N0.getOpcode() == ISD::TRUNCATE) {
5830 SDValue TruncOp = N0.getOperand(0);
5831 if (TruncOp.getValueType() == VT)
5832 return TruncOp; // x iff x size == zext size.
5833 if (TruncOp.getValueType().bitsGT(VT))
5834 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, TruncOp);
5835 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, TruncOp);
5838 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
5839 // if the trunc is not free.
5840 if (N0.getOpcode() == ISD::AND &&
5841 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
5842 N0.getOperand(1).getOpcode() == ISD::Constant &&
5843 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
5844 N0.getValueType())) {
5845 SDValue X = N0.getOperand(0).getOperand(0);
5846 if (X.getValueType().bitsLT(VT)) {
5847 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, X);
5848 } else if (X.getValueType().bitsGT(VT)) {
5849 X = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, X);
5851 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5852 Mask = Mask.zext(VT.getSizeInBits());
5853 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5854 X, DAG.getConstant(Mask, VT));
5857 // fold (aext (load x)) -> (aext (truncate (extload x)))
5858 // None of the supported targets knows how to perform load and any_ext
5859 // on vectors in one instruction. We only perform this transformation on
5861 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
5862 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5863 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) {
5864 bool DoXform = true;
5865 SmallVector<SDNode*, 4> SetCCs;
5866 if (!N0.hasOneUse())
5867 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
5869 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5870 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
5872 LN0->getBasePtr(), N0.getValueType(),
5873 LN0->getMemOperand());
5874 CombineTo(N, ExtLoad);
5875 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5876 N0.getValueType(), ExtLoad);
5877 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5878 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5880 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5884 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
5885 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
5886 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
5887 if (N0.getOpcode() == ISD::LOAD &&
5888 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5890 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5891 ISD::LoadExtType ExtType = LN0->getExtensionType();
5892 EVT MemVT = LN0->getMemoryVT();
5893 if (!LegalOperations || TLI.isLoadExtLegal(ExtType, VT, MemVT)) {
5894 SDValue ExtLoad = DAG.getExtLoad(ExtType, SDLoc(N),
5895 VT, LN0->getChain(), LN0->getBasePtr(),
5896 MemVT, LN0->getMemOperand());
5897 CombineTo(N, ExtLoad);
5898 CombineTo(N0.getNode(),
5899 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5900 N0.getValueType(), ExtLoad),
5901 ExtLoad.getValue(1));
5902 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5906 if (N0.getOpcode() == ISD::SETCC) {
5908 // aext(setcc) -> vsetcc
5909 // aext(setcc) -> truncate(vsetcc)
5910 // aext(setcc) -> aext(vsetcc)
5911 // Only do this before legalize for now.
5912 if (VT.isVector() && !LegalOperations) {
5913 EVT N0VT = N0.getOperand(0).getValueType();
5914 // We know that the # elements of the results is the same as the
5915 // # elements of the compare (and the # elements of the compare result
5916 // for that matter). Check to see that they are the same size. If so,
5917 // we know that the element size of the sext'd result matches the
5918 // element size of the compare operands.
5919 if (VT.getSizeInBits() == N0VT.getSizeInBits())
5920 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5922 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5923 // If the desired elements are smaller or larger than the source
5924 // elements we can use a matching integer vector type and then
5925 // truncate/any extend
5927 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger();
5929 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
5931 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5932 return DAG.getAnyExtOrTrunc(VsetCC, SDLoc(N), VT);
5936 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
5938 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5939 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
5940 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5948 /// See if the specified operand can be simplified with the knowledge that only
5949 /// the bits specified by Mask are used. If so, return the simpler operand,
5950 /// otherwise return a null SDValue.
5951 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
5952 switch (V.getOpcode()) {
5954 case ISD::Constant: {
5955 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
5956 assert(CV && "Const value should be ConstSDNode.");
5957 const APInt &CVal = CV->getAPIntValue();
5958 APInt NewVal = CVal & Mask;
5960 return DAG.getConstant(NewVal, V.getValueType());
5965 // If the LHS or RHS don't contribute bits to the or, drop them.
5966 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
5967 return V.getOperand(1);
5968 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
5969 return V.getOperand(0);
5972 // Only look at single-use SRLs.
5973 if (!V.getNode()->hasOneUse())
5975 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
5976 // See if we can recursively simplify the LHS.
5977 unsigned Amt = RHSC->getZExtValue();
5979 // Watch out for shift count overflow though.
5980 if (Amt >= Mask.getBitWidth()) break;
5981 APInt NewMask = Mask << Amt;
5982 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
5983 if (SimplifyLHS.getNode())
5984 return DAG.getNode(ISD::SRL, SDLoc(V), V.getValueType(),
5985 SimplifyLHS, V.getOperand(1));
5991 /// If the result of a wider load is shifted to right of N bits and then
5992 /// truncated to a narrower type and where N is a multiple of number of bits of
5993 /// the narrower type, transform it to a narrower load from address + N / num of
5994 /// bits of new type. If the result is to be extended, also fold the extension
5995 /// to form a extending load.
5996 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
5997 unsigned Opc = N->getOpcode();
5999 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
6000 SDValue N0 = N->getOperand(0);
6001 EVT VT = N->getValueType(0);
6004 // This transformation isn't valid for vector loads.
6008 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
6010 if (Opc == ISD::SIGN_EXTEND_INREG) {
6011 ExtType = ISD::SEXTLOAD;
6012 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
6013 } else if (Opc == ISD::SRL) {
6014 // Another special-case: SRL is basically zero-extending a narrower value.
6015 ExtType = ISD::ZEXTLOAD;
6017 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
6018 if (!N01) return SDValue();
6019 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
6020 VT.getSizeInBits() - N01->getZExtValue());
6022 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, VT, ExtVT))
6025 unsigned EVTBits = ExtVT.getSizeInBits();
6027 // Do not generate loads of non-round integer types since these can
6028 // be expensive (and would be wrong if the type is not byte sized).
6029 if (!ExtVT.isRound())
6033 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
6034 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
6035 ShAmt = N01->getZExtValue();
6036 // Is the shift amount a multiple of size of VT?
6037 if ((ShAmt & (EVTBits-1)) == 0) {
6038 N0 = N0.getOperand(0);
6039 // Is the load width a multiple of size of VT?
6040 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
6044 // At this point, we must have a load or else we can't do the transform.
6045 if (!isa<LoadSDNode>(N0)) return SDValue();
6047 // Because a SRL must be assumed to *need* to zero-extend the high bits
6048 // (as opposed to anyext the high bits), we can't combine the zextload
6049 // lowering of SRL and an sextload.
6050 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD)
6053 // If the shift amount is larger than the input type then we're not
6054 // accessing any of the loaded bytes. If the load was a zextload/extload
6055 // then the result of the shift+trunc is zero/undef (handled elsewhere).
6056 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
6061 // If the load is shifted left (and the result isn't shifted back right),
6062 // we can fold the truncate through the shift.
6063 unsigned ShLeftAmt = 0;
6064 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
6065 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
6066 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
6067 ShLeftAmt = N01->getZExtValue();
6068 N0 = N0.getOperand(0);
6072 // If we haven't found a load, we can't narrow it. Don't transform one with
6073 // multiple uses, this would require adding a new load.
6074 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse())
6077 // Don't change the width of a volatile load.
6078 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6079 if (LN0->isVolatile())
6082 // Verify that we are actually reducing a load width here.
6083 if (LN0->getMemoryVT().getSizeInBits() < EVTBits)
6086 // For the transform to be legal, the load must produce only two values
6087 // (the value loaded and the chain). Don't transform a pre-increment
6088 // load, for example, which produces an extra value. Otherwise the
6089 // transformation is not equivalent, and the downstream logic to replace
6090 // uses gets things wrong.
6091 if (LN0->getNumValues() > 2)
6094 // If the load that we're shrinking is an extload and we're not just
6095 // discarding the extension we can't simply shrink the load. Bail.
6096 // TODO: It would be possible to merge the extensions in some cases.
6097 if (LN0->getExtensionType() != ISD::NON_EXTLOAD &&
6098 LN0->getMemoryVT().getSizeInBits() < ExtVT.getSizeInBits() + ShAmt)
6101 if (!TLI.shouldReduceLoadWidth(LN0, ExtType, ExtVT))
6104 EVT PtrType = N0.getOperand(1).getValueType();
6106 if (PtrType == MVT::Untyped || PtrType.isExtended())
6107 // It's not possible to generate a constant of extended or untyped type.
6110 // For big endian targets, we need to adjust the offset to the pointer to
6111 // load the correct bytes.
6112 if (TLI.isBigEndian()) {
6113 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
6114 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
6115 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
6118 uint64_t PtrOff = ShAmt / 8;
6119 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
6120 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0),
6121 PtrType, LN0->getBasePtr(),
6122 DAG.getConstant(PtrOff, PtrType));
6123 AddToWorklist(NewPtr.getNode());
6126 if (ExtType == ISD::NON_EXTLOAD)
6127 Load = DAG.getLoad(VT, SDLoc(N0), LN0->getChain(), NewPtr,
6128 LN0->getPointerInfo().getWithOffset(PtrOff),
6129 LN0->isVolatile(), LN0->isNonTemporal(),
6130 LN0->isInvariant(), NewAlign, LN0->getAAInfo());
6132 Load = DAG.getExtLoad(ExtType, SDLoc(N0), VT, LN0->getChain(),NewPtr,
6133 LN0->getPointerInfo().getWithOffset(PtrOff),
6134 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
6135 LN0->isInvariant(), NewAlign, LN0->getAAInfo());
6137 // Replace the old load's chain with the new load's chain.
6138 WorklistRemover DeadNodes(*this);
6139 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
6141 // Shift the result left, if we've swallowed a left shift.
6142 SDValue Result = Load;
6143 if (ShLeftAmt != 0) {
6144 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
6145 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
6147 // If the shift amount is as large as the result size (but, presumably,
6148 // no larger than the source) then the useful bits of the result are
6149 // zero; we can't simply return the shortened shift, because the result
6150 // of that operation is undefined.
6151 if (ShLeftAmt >= VT.getSizeInBits())
6152 Result = DAG.getConstant(0, VT);
6154 Result = DAG.getNode(ISD::SHL, SDLoc(N0), VT,
6155 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
6158 // Return the new loaded value.
6162 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
6163 SDValue N0 = N->getOperand(0);
6164 SDValue N1 = N->getOperand(1);
6165 EVT VT = N->getValueType(0);
6166 EVT EVT = cast<VTSDNode>(N1)->getVT();
6167 unsigned VTBits = VT.getScalarType().getSizeInBits();
6168 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
6170 // fold (sext_in_reg c1) -> c1
6171 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
6172 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1);
6174 // If the input is already sign extended, just drop the extension.
6175 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
6178 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
6179 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
6180 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT()))
6181 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
6182 N0.getOperand(0), N1);
6184 // fold (sext_in_reg (sext x)) -> (sext x)
6185 // fold (sext_in_reg (aext x)) -> (sext x)
6186 // if x is small enough.
6187 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
6188 SDValue N00 = N0.getOperand(0);
6189 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
6190 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
6191 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00, N1);
6194 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
6195 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
6196 return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT);
6198 // fold operands of sext_in_reg based on knowledge that the top bits are not
6200 if (SimplifyDemandedBits(SDValue(N, 0)))
6201 return SDValue(N, 0);
6203 // fold (sext_in_reg (load x)) -> (smaller sextload x)
6204 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
6205 SDValue NarrowLoad = ReduceLoadWidth(N);
6206 if (NarrowLoad.getNode())
6209 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
6210 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
6211 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
6212 if (N0.getOpcode() == ISD::SRL) {
6213 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
6214 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
6215 // We can turn this into an SRA iff the input to the SRL is already sign
6217 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
6218 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
6219 return DAG.getNode(ISD::SRA, SDLoc(N), VT,
6220 N0.getOperand(0), N0.getOperand(1));
6224 // fold (sext_inreg (extload x)) -> (sextload x)
6225 if (ISD::isEXTLoad(N0.getNode()) &&
6226 ISD::isUNINDEXEDLoad(N0.getNode()) &&
6227 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
6228 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6229 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, EVT))) {
6230 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6231 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
6233 LN0->getBasePtr(), EVT,
6234 LN0->getMemOperand());
6235 CombineTo(N, ExtLoad);
6236 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
6237 AddToWorklist(ExtLoad.getNode());
6238 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6240 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
6241 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
6243 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
6244 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6245 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, EVT))) {
6246 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6247 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
6249 LN0->getBasePtr(), EVT,
6250 LN0->getMemOperand());
6251 CombineTo(N, ExtLoad);
6252 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
6253 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6256 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
6257 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
6258 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
6259 N0.getOperand(1), false);
6260 if (BSwap.getNode())
6261 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
6265 // Fold a sext_inreg of a build_vector of ConstantSDNodes or undefs
6266 // into a build_vector.
6267 if (ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
6268 SmallVector<SDValue, 8> Elts;
6269 unsigned NumElts = N0->getNumOperands();
6270 unsigned ShAmt = VTBits - EVTBits;
6272 for (unsigned i = 0; i != NumElts; ++i) {
6273 SDValue Op = N0->getOperand(i);
6274 if (Op->getOpcode() == ISD::UNDEF) {
6279 ConstantSDNode *CurrentND = cast<ConstantSDNode>(Op);
6280 const APInt &C = APInt(VTBits, CurrentND->getAPIntValue().getZExtValue());
6281 Elts.push_back(DAG.getConstant(C.shl(ShAmt).ashr(ShAmt).getZExtValue(),
6282 Op.getValueType()));
6285 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Elts);
6291 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
6292 SDValue N0 = N->getOperand(0);
6293 EVT VT = N->getValueType(0);
6294 bool isLE = TLI.isLittleEndian();
6297 if (N0.getValueType() == N->getValueType(0))
6299 // fold (truncate c1) -> c1
6300 if (isa<ConstantSDNode>(N0))
6301 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0);
6302 // fold (truncate (truncate x)) -> (truncate x)
6303 if (N0.getOpcode() == ISD::TRUNCATE)
6304 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
6305 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
6306 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
6307 N0.getOpcode() == ISD::SIGN_EXTEND ||
6308 N0.getOpcode() == ISD::ANY_EXTEND) {
6309 if (N0.getOperand(0).getValueType().bitsLT(VT))
6310 // if the source is smaller than the dest, we still need an extend
6311 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
6313 if (N0.getOperand(0).getValueType().bitsGT(VT))
6314 // if the source is larger than the dest, than we just need the truncate
6315 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
6316 // if the source and dest are the same type, we can drop both the extend
6317 // and the truncate.
6318 return N0.getOperand(0);
6321 // Fold extract-and-trunc into a narrow extract. For example:
6322 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
6323 // i32 y = TRUNCATE(i64 x)
6325 // v16i8 b = BITCAST (v2i64 val)
6326 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
6328 // Note: We only run this optimization after type legalization (which often
6329 // creates this pattern) and before operation legalization after which
6330 // we need to be more careful about the vector instructions that we generate.
6331 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6332 LegalTypes && !LegalOperations && N0->hasOneUse() && VT != MVT::i1) {
6334 EVT VecTy = N0.getOperand(0).getValueType();
6335 EVT ExTy = N0.getValueType();
6336 EVT TrTy = N->getValueType(0);
6338 unsigned NumElem = VecTy.getVectorNumElements();
6339 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
6341 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
6342 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
6344 SDValue EltNo = N0->getOperand(1);
6345 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
6346 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6347 EVT IndexTy = TLI.getVectorIdxTy();
6348 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
6350 SDValue V = DAG.getNode(ISD::BITCAST, SDLoc(N),
6351 NVT, N0.getOperand(0));
6353 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
6355 DAG.getConstant(Index, IndexTy));
6359 // trunc (select c, a, b) -> select c, (trunc a), (trunc b)
6360 if (N0.getOpcode() == ISD::SELECT) {
6361 EVT SrcVT = N0.getValueType();
6362 if ((!LegalOperations || TLI.isOperationLegal(ISD::SELECT, SrcVT)) &&
6363 TLI.isTruncateFree(SrcVT, VT)) {
6365 SDValue Cond = N0.getOperand(0);
6366 SDValue TruncOp0 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));
6367 SDValue TruncOp1 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(2));
6368 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, Cond, TruncOp0, TruncOp1);
6372 // Fold a series of buildvector, bitcast, and truncate if possible.
6374 // (2xi32 trunc (bitcast ((4xi32)buildvector x, x, y, y) 2xi64)) to
6375 // (2xi32 (buildvector x, y)).
6376 if (Level == AfterLegalizeVectorOps && VT.isVector() &&
6377 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
6378 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
6379 N0.getOperand(0).hasOneUse()) {
6381 SDValue BuildVect = N0.getOperand(0);
6382 EVT BuildVectEltTy = BuildVect.getValueType().getVectorElementType();
6383 EVT TruncVecEltTy = VT.getVectorElementType();
6385 // Check that the element types match.
6386 if (BuildVectEltTy == TruncVecEltTy) {
6387 // Now we only need to compute the offset of the truncated elements.
6388 unsigned BuildVecNumElts = BuildVect.getNumOperands();
6389 unsigned TruncVecNumElts = VT.getVectorNumElements();
6390 unsigned TruncEltOffset = BuildVecNumElts / TruncVecNumElts;
6392 assert((BuildVecNumElts % TruncVecNumElts) == 0 &&
6393 "Invalid number of elements");
6395 SmallVector<SDValue, 8> Opnds;
6396 for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset)
6397 Opnds.push_back(BuildVect.getOperand(i));
6399 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
6403 // See if we can simplify the input to this truncate through knowledge that
6404 // only the low bits are being used.
6405 // For example "trunc (or (shl x, 8), y)" // -> trunc y
6406 // Currently we only perform this optimization on scalars because vectors
6407 // may have different active low bits.
6408 if (!VT.isVector()) {
6410 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
6411 VT.getSizeInBits()));
6412 if (Shorter.getNode())
6413 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Shorter);
6415 // fold (truncate (load x)) -> (smaller load x)
6416 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
6417 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
6418 SDValue Reduced = ReduceLoadWidth(N);
6419 if (Reduced.getNode())
6421 // Handle the case where the load remains an extending load even
6422 // after truncation.
6423 if (N0.hasOneUse() && ISD::isUNINDEXEDLoad(N0.getNode())) {
6424 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6425 if (!LN0->isVolatile() &&
6426 LN0->getMemoryVT().getStoreSizeInBits() < VT.getSizeInBits()) {
6427 SDValue NewLoad = DAG.getExtLoad(LN0->getExtensionType(), SDLoc(LN0),
6428 VT, LN0->getChain(), LN0->getBasePtr(),
6430 LN0->getMemOperand());
6431 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLoad.getValue(1));
6436 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)),
6437 // where ... are all 'undef'.
6438 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
6439 SmallVector<EVT, 8> VTs;
6442 unsigned NumDefs = 0;
6444 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
6445 SDValue X = N0.getOperand(i);
6446 if (X.getOpcode() != ISD::UNDEF) {
6451 // Stop if more than one members are non-undef.
6454 VTs.push_back(EVT::getVectorVT(*DAG.getContext(),
6455 VT.getVectorElementType(),
6456 X.getValueType().getVectorNumElements()));
6460 return DAG.getUNDEF(VT);
6463 assert(V.getNode() && "The single defined operand is empty!");
6464 SmallVector<SDValue, 8> Opnds;
6465 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
6467 Opnds.push_back(DAG.getUNDEF(VTs[i]));
6470 SDValue NV = DAG.getNode(ISD::TRUNCATE, SDLoc(V), VTs[i], V);
6471 AddToWorklist(NV.getNode());
6472 Opnds.push_back(NV);
6474 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Opnds);
6478 // Simplify the operands using demanded-bits information.
6479 if (!VT.isVector() &&
6480 SimplifyDemandedBits(SDValue(N, 0)))
6481 return SDValue(N, 0);
6486 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
6487 SDValue Elt = N->getOperand(i);
6488 if (Elt.getOpcode() != ISD::MERGE_VALUES)
6489 return Elt.getNode();
6490 return Elt.getOperand(Elt.getResNo()).getNode();
6493 /// build_pair (load, load) -> load
6494 /// if load locations are consecutive.
6495 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
6496 assert(N->getOpcode() == ISD::BUILD_PAIR);
6498 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
6499 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
6500 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
6501 LD1->getAddressSpace() != LD2->getAddressSpace())
6503 EVT LD1VT = LD1->getValueType(0);
6505 if (ISD::isNON_EXTLoad(LD2) &&
6507 // If both are volatile this would reduce the number of volatile loads.
6508 // If one is volatile it might be ok, but play conservative and bail out.
6509 !LD1->isVolatile() &&
6510 !LD2->isVolatile() &&
6511 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
6512 unsigned Align = LD1->getAlignment();
6513 unsigned NewAlign = TLI.getDataLayout()->
6514 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
6516 if (NewAlign <= Align &&
6517 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
6518 return DAG.getLoad(VT, SDLoc(N), LD1->getChain(),
6519 LD1->getBasePtr(), LD1->getPointerInfo(),
6520 false, false, false, Align);
6526 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
6527 SDValue N0 = N->getOperand(0);
6528 EVT VT = N->getValueType(0);
6530 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
6531 // Only do this before legalize, since afterward the target may be depending
6532 // on the bitconvert.
6533 // First check to see if this is all constant.
6535 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
6537 bool isSimple = cast<BuildVectorSDNode>(N0)->isConstant();
6539 EVT DestEltVT = N->getValueType(0).getVectorElementType();
6540 assert(!DestEltVT.isVector() &&
6541 "Element type of vector ValueType must not be vector!");
6543 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
6546 // If the input is a constant, let getNode fold it.
6547 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
6548 SDValue Res = DAG.getNode(ISD::BITCAST, SDLoc(N), VT, N0);
6549 if (Res.getNode() != N) {
6550 if (!LegalOperations ||
6551 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
6554 // Folding it resulted in an illegal node, and it's too late to
6555 // do that. Clean up the old node and forego the transformation.
6556 // Ideally this won't happen very often, because instcombine
6557 // and the earlier dagcombine runs (where illegal nodes are
6558 // permitted) should have folded most of them already.
6559 deleteAndRecombine(Res.getNode());
6563 // (conv (conv x, t1), t2) -> (conv x, t2)
6564 if (N0.getOpcode() == ISD::BITCAST)
6565 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT,
6568 // fold (conv (load x)) -> (load (conv*)x)
6569 // If the resultant load doesn't need a higher alignment than the original!
6570 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6571 // Do not change the width of a volatile load.
6572 !cast<LoadSDNode>(N0)->isVolatile() &&
6573 // Do not remove the cast if the types differ in endian layout.
6574 TLI.hasBigEndianPartOrdering(N0.getValueType()) ==
6575 TLI.hasBigEndianPartOrdering(VT) &&
6576 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)) &&
6577 TLI.isLoadBitCastBeneficial(N0.getValueType(), VT)) {
6578 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6579 unsigned Align = TLI.getDataLayout()->
6580 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
6581 unsigned OrigAlign = LN0->getAlignment();
6583 if (Align <= OrigAlign) {
6584 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(),
6585 LN0->getBasePtr(), LN0->getPointerInfo(),
6586 LN0->isVolatile(), LN0->isNonTemporal(),
6587 LN0->isInvariant(), OrigAlign,
6589 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
6594 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
6595 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
6596 // This often reduces constant pool loads.
6597 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
6598 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
6599 N0.getNode()->hasOneUse() && VT.isInteger() &&
6600 !VT.isVector() && !N0.getValueType().isVector()) {
6601 SDValue NewConv = DAG.getNode(ISD::BITCAST, SDLoc(N0), VT,
6603 AddToWorklist(NewConv.getNode());
6605 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
6606 if (N0.getOpcode() == ISD::FNEG)
6607 return DAG.getNode(ISD::XOR, SDLoc(N), VT,
6608 NewConv, DAG.getConstant(SignBit, VT));
6609 assert(N0.getOpcode() == ISD::FABS);
6610 return DAG.getNode(ISD::AND, SDLoc(N), VT,
6611 NewConv, DAG.getConstant(~SignBit, VT));
6614 // fold (bitconvert (fcopysign cst, x)) ->
6615 // (or (and (bitconvert x), sign), (and cst, (not sign)))
6616 // Note that we don't handle (copysign x, cst) because this can always be
6617 // folded to an fneg or fabs.
6618 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
6619 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
6620 VT.isInteger() && !VT.isVector()) {
6621 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
6622 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
6623 if (isTypeLegal(IntXVT)) {
6624 SDValue X = DAG.getNode(ISD::BITCAST, SDLoc(N0),
6625 IntXVT, N0.getOperand(1));
6626 AddToWorklist(X.getNode());
6628 // If X has a different width than the result/lhs, sext it or truncate it.
6629 unsigned VTWidth = VT.getSizeInBits();
6630 if (OrigXWidth < VTWidth) {
6631 X = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, X);
6632 AddToWorklist(X.getNode());
6633 } else if (OrigXWidth > VTWidth) {
6634 // To get the sign bit in the right place, we have to shift it right
6635 // before truncating.
6636 X = DAG.getNode(ISD::SRL, SDLoc(X),
6637 X.getValueType(), X,
6638 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
6639 AddToWorklist(X.getNode());
6640 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
6641 AddToWorklist(X.getNode());
6644 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
6645 X = DAG.getNode(ISD::AND, SDLoc(X), VT,
6646 X, DAG.getConstant(SignBit, VT));
6647 AddToWorklist(X.getNode());
6649 SDValue Cst = DAG.getNode(ISD::BITCAST, SDLoc(N0),
6650 VT, N0.getOperand(0));
6651 Cst = DAG.getNode(ISD::AND, SDLoc(Cst), VT,
6652 Cst, DAG.getConstant(~SignBit, VT));
6653 AddToWorklist(Cst.getNode());
6655 return DAG.getNode(ISD::OR, SDLoc(N), VT, X, Cst);
6659 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
6660 if (N0.getOpcode() == ISD::BUILD_PAIR) {
6661 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
6662 if (CombineLD.getNode())
6669 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
6670 EVT VT = N->getValueType(0);
6671 return CombineConsecutiveLoads(N, VT);
6674 /// We know that BV is a build_vector node with Constant, ConstantFP or Undef
6675 /// operands. DstEltVT indicates the destination element value type.
6676 SDValue DAGCombiner::
6677 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
6678 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
6680 // If this is already the right type, we're done.
6681 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
6683 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
6684 unsigned DstBitSize = DstEltVT.getSizeInBits();
6686 // If this is a conversion of N elements of one type to N elements of another
6687 // type, convert each element. This handles FP<->INT cases.
6688 if (SrcBitSize == DstBitSize) {
6689 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
6690 BV->getValueType(0).getVectorNumElements());
6692 // Due to the FP element handling below calling this routine recursively,
6693 // we can end up with a scalar-to-vector node here.
6694 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
6695 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT,
6696 DAG.getNode(ISD::BITCAST, SDLoc(BV),
6697 DstEltVT, BV->getOperand(0)));
6699 SmallVector<SDValue, 8> Ops;
6700 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
6701 SDValue Op = BV->getOperand(i);
6702 // If the vector element type is not legal, the BUILD_VECTOR operands
6703 // are promoted and implicitly truncated. Make that explicit here.
6704 if (Op.getValueType() != SrcEltVT)
6705 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(BV), SrcEltVT, Op);
6706 Ops.push_back(DAG.getNode(ISD::BITCAST, SDLoc(BV),
6708 AddToWorklist(Ops.back().getNode());
6710 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
6713 // Otherwise, we're growing or shrinking the elements. To avoid having to
6714 // handle annoying details of growing/shrinking FP values, we convert them to
6716 if (SrcEltVT.isFloatingPoint()) {
6717 // Convert the input float vector to a int vector where the elements are the
6719 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
6720 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
6724 // Now we know the input is an integer vector. If the output is a FP type,
6725 // convert to integer first, then to FP of the right size.
6726 if (DstEltVT.isFloatingPoint()) {
6727 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
6728 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
6730 // Next, convert to FP elements of the same size.
6731 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
6734 // Okay, we know the src/dst types are both integers of differing types.
6735 // Handling growing first.
6736 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
6737 if (SrcBitSize < DstBitSize) {
6738 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
6740 SmallVector<SDValue, 8> Ops;
6741 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
6742 i += NumInputsPerOutput) {
6743 bool isLE = TLI.isLittleEndian();
6744 APInt NewBits = APInt(DstBitSize, 0);
6745 bool EltIsUndef = true;
6746 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
6747 // Shift the previously computed bits over.
6748 NewBits <<= SrcBitSize;
6749 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
6750 if (Op.getOpcode() == ISD::UNDEF) continue;
6753 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
6754 zextOrTrunc(SrcBitSize).zext(DstBitSize);
6758 Ops.push_back(DAG.getUNDEF(DstEltVT));
6760 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
6763 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
6764 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
6767 // Finally, this must be the case where we are shrinking elements: each input
6768 // turns into multiple outputs.
6769 bool isS2V = ISD::isScalarToVector(BV);
6770 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
6771 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
6772 NumOutputsPerInput*BV->getNumOperands());
6773 SmallVector<SDValue, 8> Ops;
6775 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
6776 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
6777 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
6778 Ops.push_back(DAG.getUNDEF(DstEltVT));
6782 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
6783 getAPIntValue().zextOrTrunc(SrcBitSize);
6785 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
6786 APInt ThisVal = OpVal.trunc(DstBitSize);
6787 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
6788 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
6789 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
6790 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT,
6792 OpVal = OpVal.lshr(DstBitSize);
6795 // For big endian targets, swap the order of the pieces of each element.
6796 if (TLI.isBigEndian())
6797 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
6800 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
6803 SDValue DAGCombiner::visitFADD(SDNode *N) {
6804 SDValue N0 = N->getOperand(0);
6805 SDValue N1 = N->getOperand(1);
6806 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6807 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6808 EVT VT = N->getValueType(0);
6809 const TargetOptions &Options = DAG.getTarget().Options;
6812 if (VT.isVector()) {
6813 SDValue FoldedVOp = SimplifyVBinOp(N);
6814 if (FoldedVOp.getNode()) return FoldedVOp;
6817 // fold (fadd c1, c2) -> c1 + c2
6819 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N1);
6821 // canonicalize constant to RHS
6822 if (N0CFP && !N1CFP)
6823 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N0);
6825 // fold (fadd A, (fneg B)) -> (fsub A, B)
6826 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
6827 isNegatibleForFree(N1, LegalOperations, TLI, &Options) == 2)
6828 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0,
6829 GetNegatedExpression(N1, DAG, LegalOperations));
6831 // fold (fadd (fneg A), B) -> (fsub B, A)
6832 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
6833 isNegatibleForFree(N0, LegalOperations, TLI, &Options) == 2)
6834 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N1,
6835 GetNegatedExpression(N0, DAG, LegalOperations));
6837 // If 'unsafe math' is enabled, fold lots of things.
6838 if (Options.UnsafeFPMath) {
6839 // No FP constant should be created after legalization as Instruction
6840 // Selection pass has a hard time dealing with FP constants.
6841 bool AllowNewConst = (Level < AfterLegalizeDAG);
6843 // fold (fadd A, 0) -> A
6844 if (N1CFP && N1CFP->getValueAPF().isZero())
6847 // fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
6848 if (N1CFP && N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
6849 isa<ConstantFPSDNode>(N0.getOperand(1)))
6850 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0.getOperand(0),
6851 DAG.getNode(ISD::FADD, SDLoc(N), VT,
6852 N0.getOperand(1), N1));
6854 // If allowed, fold (fadd (fneg x), x) -> 0.0
6855 if (AllowNewConst && N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
6856 return DAG.getConstantFP(0.0, VT);
6858 // If allowed, fold (fadd x, (fneg x)) -> 0.0
6859 if (AllowNewConst && N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
6860 return DAG.getConstantFP(0.0, VT);
6862 // We can fold chains of FADD's of the same value into multiplications.
6863 // This transform is not safe in general because we are reducing the number
6864 // of rounding steps.
6865 if (TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && !N0CFP && !N1CFP) {
6866 if (N0.getOpcode() == ISD::FMUL) {
6867 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
6868 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
6870 // (fadd (fmul x, c), x) -> (fmul x, c+1)
6871 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
6872 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6874 DAG.getConstantFP(1.0, VT));
6875 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1, NewCFP);
6878 // (fadd (fmul x, c), (fadd x, x)) -> (fmul x, c+2)
6879 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
6880 N1.getOperand(0) == N1.getOperand(1) &&
6881 N0.getOperand(0) == N1.getOperand(0)) {
6882 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6884 DAG.getConstantFP(2.0, VT));
6885 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6886 N0.getOperand(0), NewCFP);
6890 if (N1.getOpcode() == ISD::FMUL) {
6891 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
6892 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1));
6894 // (fadd x, (fmul x, c)) -> (fmul x, c+1)
6895 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
6896 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6898 DAG.getConstantFP(1.0, VT));
6899 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, NewCFP);
6902 // (fadd (fadd x, x), (fmul x, c)) -> (fmul x, c+2)
6903 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
6904 N0.getOperand(0) == N0.getOperand(1) &&
6905 N1.getOperand(0) == N0.getOperand(0)) {
6906 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6908 DAG.getConstantFP(2.0, VT));
6909 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1.getOperand(0), NewCFP);
6913 if (N0.getOpcode() == ISD::FADD && AllowNewConst) {
6914 ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
6915 // (fadd (fadd x, x), x) -> (fmul x, 3.0)
6916 if (!CFP && N0.getOperand(0) == N0.getOperand(1) &&
6917 (N0.getOperand(0) == N1))
6918 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6919 N1, DAG.getConstantFP(3.0, VT));
6922 if (N1.getOpcode() == ISD::FADD && AllowNewConst) {
6923 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
6924 // (fadd x, (fadd x, x)) -> (fmul x, 3.0)
6925 if (!CFP10 && N1.getOperand(0) == N1.getOperand(1) &&
6926 N1.getOperand(0) == N0)
6927 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6928 N0, DAG.getConstantFP(3.0, VT));
6931 // (fadd (fadd x, x), (fadd x, x)) -> (fmul x, 4.0)
6932 if (AllowNewConst &&
6933 N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
6934 N0.getOperand(0) == N0.getOperand(1) &&
6935 N1.getOperand(0) == N1.getOperand(1) &&
6936 N0.getOperand(0) == N1.getOperand(0))
6937 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6938 N0.getOperand(0), DAG.getConstantFP(4.0, VT));
6940 } // enable-unsafe-fp-math
6942 // FADD -> FMA combines:
6943 if ((Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath) &&
6944 TLI.isFMAFasterThanFMulAndFAdd(VT) &&
6945 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT))) {
6947 // fold (fadd (fmul x, y), z) -> (fma x, y, z)
6948 if (N0.getOpcode() == ISD::FMUL &&
6949 (N0->hasOneUse() || TLI.enableAggressiveFMAFusion(VT)))
6950 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6951 N0.getOperand(0), N0.getOperand(1), N1);
6953 // fold (fadd x, (fmul y, z)) -> (fma y, z, x)
6954 // Note: Commutes FADD operands.
6955 if (N1.getOpcode() == ISD::FMUL &&
6956 (N1->hasOneUse() || TLI.enableAggressiveFMAFusion(VT)))
6957 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6958 N1.getOperand(0), N1.getOperand(1), N0);
6960 // When FP_EXTEND nodes are free on the target, and there is an opportunity
6961 // to combine into FMA, arrange such nodes accordingly.
6962 if (TLI.isFPExtFree(VT)) {
6964 // fold (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z)
6965 if (N0.getOpcode() == ISD::FP_EXTEND) {
6966 SDValue N00 = N0.getOperand(0);
6967 if (N00.getOpcode() == ISD::FMUL)
6968 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6969 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
6971 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
6972 N00.getOperand(1)), N1);
6975 // fold (fadd x, (fpext (fmul y, z)), z) -> (fma (fpext y), (fpext z), x)
6976 // Note: Commutes FADD operands.
6977 if (N1.getOpcode() == ISD::FP_EXTEND) {
6978 SDValue N10 = N1.getOperand(0);
6979 if (N10.getOpcode() == ISD::FMUL)
6980 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6981 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
6983 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
6984 N10.getOperand(1)), N0);
6988 // More folding opportunities when target permits.
6989 if (TLI.enableAggressiveFMAFusion(VT)) {
6991 // fold (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, z))
6992 if (N0.getOpcode() == ISD::FMA &&
6993 N0.getOperand(2).getOpcode() == ISD::FMUL)
6994 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6995 N0.getOperand(0), N0.getOperand(1),
6996 DAG.getNode(ISD::FMA, SDLoc(N), VT,
6997 N0.getOperand(2).getOperand(0),
6998 N0.getOperand(2).getOperand(1),
7001 // fold (fadd x, (fma y, z, (fmul u, v)) -> (fma y, z (fma u, v, x))
7002 if (N1->getOpcode() == ISD::FMA &&
7003 N1.getOperand(2).getOpcode() == ISD::FMUL)
7004 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
7005 N1.getOperand(0), N1.getOperand(1),
7006 DAG.getNode(ISD::FMA, SDLoc(N), VT,
7007 N1.getOperand(2).getOperand(0),
7008 N1.getOperand(2).getOperand(1),
7016 SDValue DAGCombiner::visitFSUB(SDNode *N) {
7017 SDValue N0 = N->getOperand(0);
7018 SDValue N1 = N->getOperand(1);
7019 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
7020 ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
7021 EVT VT = N->getValueType(0);
7023 const TargetOptions &Options = DAG.getTarget().Options;
7026 if (VT.isVector()) {
7027 SDValue FoldedVOp = SimplifyVBinOp(N);
7028 if (FoldedVOp.getNode()) return FoldedVOp;
7031 // fold (fsub c1, c2) -> c1-c2
7033 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0, N1);
7035 // fold (fsub A, (fneg B)) -> (fadd A, B)
7036 if (isNegatibleForFree(N1, LegalOperations, TLI, &Options))
7037 return DAG.getNode(ISD::FADD, dl, VT, N0,
7038 GetNegatedExpression(N1, DAG, LegalOperations));
7040 // If 'unsafe math' is enabled, fold lots of things.
7041 if (Options.UnsafeFPMath) {
7043 if (N1CFP && N1CFP->getValueAPF().isZero())
7046 // (fsub 0, B) -> -B
7047 if (N0CFP && N0CFP->getValueAPF().isZero()) {
7048 if (isNegatibleForFree(N1, LegalOperations, TLI, &Options))
7049 return GetNegatedExpression(N1, DAG, LegalOperations);
7050 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
7051 return DAG.getNode(ISD::FNEG, dl, VT, N1);
7054 // (fsub x, x) -> 0.0
7056 return DAG.getConstantFP(0.0f, VT);
7058 // (fsub x, (fadd x, y)) -> (fneg y)
7059 // (fsub x, (fadd y, x)) -> (fneg y)
7060 if (N1.getOpcode() == ISD::FADD) {
7061 SDValue N10 = N1->getOperand(0);
7062 SDValue N11 = N1->getOperand(1);
7064 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, &Options))
7065 return GetNegatedExpression(N11, DAG, LegalOperations);
7067 if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, &Options))
7068 return GetNegatedExpression(N10, DAG, LegalOperations);
7072 // FSUB -> FMA combines:
7073 if ((Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath) &&
7074 TLI.isFMAFasterThanFMulAndFAdd(VT) &&
7075 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT))) {
7077 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
7078 if (N0.getOpcode() == ISD::FMUL &&
7079 (N0->hasOneUse() || TLI.enableAggressiveFMAFusion(VT)))
7080 return DAG.getNode(ISD::FMA, dl, VT,
7081 N0.getOperand(0), N0.getOperand(1),
7082 DAG.getNode(ISD::FNEG, dl, VT, N1));
7084 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
7085 // Note: Commutes FSUB operands.
7086 if (N1.getOpcode() == ISD::FMUL &&
7087 (N1->hasOneUse() || TLI.enableAggressiveFMAFusion(VT)))
7088 return DAG.getNode(ISD::FMA, dl, VT,
7089 DAG.getNode(ISD::FNEG, dl, VT,
7091 N1.getOperand(1), N0);
7093 // fold (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
7094 if (N0.getOpcode() == ISD::FNEG &&
7095 N0.getOperand(0).getOpcode() == ISD::FMUL &&
7096 ((N0->hasOneUse() && N0.getOperand(0).hasOneUse()) ||
7097 TLI.enableAggressiveFMAFusion(VT))) {
7098 SDValue N00 = N0.getOperand(0).getOperand(0);
7099 SDValue N01 = N0.getOperand(0).getOperand(1);
7100 return DAG.getNode(ISD::FMA, dl, VT,
7101 DAG.getNode(ISD::FNEG, dl, VT, N00), N01,
7102 DAG.getNode(ISD::FNEG, dl, VT, N1));
7105 // When FP_EXTEND nodes are free on the target, and there is an opportunity
7106 // to combine into FMA, arrange such nodes accordingly.
7107 if (TLI.isFPExtFree(VT)) {
7109 // fold (fsub (fpext (fmul x, y)), z)
7110 // -> (fma (fpext x), (fpext y), (fneg z))
7111 if (N0.getOpcode() == ISD::FP_EXTEND) {
7112 SDValue N00 = N0.getOperand(0);
7113 if (N00.getOpcode() == ISD::FMUL)
7114 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
7115 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
7117 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
7119 DAG.getNode(ISD::FNEG, SDLoc(N), VT, N1));
7122 // fold (fsub x, (fpext (fmul y, z)))
7123 // -> (fma (fneg (fpext y)), (fpext z), x)
7124 // Note: Commutes FSUB operands.
7125 if (N1.getOpcode() == ISD::FP_EXTEND) {
7126 SDValue N10 = N1.getOperand(0);
7127 if (N10.getOpcode() == ISD::FMUL)
7128 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
7129 DAG.getNode(ISD::FNEG, SDLoc(N), VT,
7130 DAG.getNode(ISD::FP_EXTEND, SDLoc(N),
7131 VT, N10.getOperand(0))),
7132 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
7137 // fold (fsub (fpext (fneg (fmul, x, y))), z)
7138 // -> (fma (fneg (fpext x)), (fpext y), (fneg z))
7139 if (N0.getOpcode() == ISD::FP_EXTEND) {
7140 SDValue N00 = N0.getOperand(0);
7141 if (N00.getOpcode() == ISD::FNEG) {
7142 SDValue N000 = N00.getOperand(0);
7143 if (N000.getOpcode() == ISD::FMUL) {
7144 return DAG.getNode(ISD::FMA, dl, VT,
7145 DAG.getNode(ISD::FNEG, dl, VT,
7146 DAG.getNode(ISD::FP_EXTEND, SDLoc(N),
7147 VT, N000.getOperand(0))),
7148 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
7149 N000.getOperand(1)),
7150 DAG.getNode(ISD::FNEG, dl, VT, N1));
7155 // fold (fsub (fneg (fpext (fmul, x, y))), z)
7156 // -> (fma (fneg (fpext x)), (fpext y), (fneg z))
7157 if (N0.getOpcode() == ISD::FNEG) {
7158 SDValue N00 = N0.getOperand(0);
7159 if (N00.getOpcode() == ISD::FP_EXTEND) {
7160 SDValue N000 = N00.getOperand(0);
7161 if (N000.getOpcode() == ISD::FMUL) {
7162 return DAG.getNode(ISD::FMA, dl, VT,
7163 DAG.getNode(ISD::FNEG, dl, VT,
7164 DAG.getNode(ISD::FP_EXTEND, SDLoc(N),
7165 VT, N000.getOperand(0))),
7166 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
7167 N000.getOperand(1)),
7168 DAG.getNode(ISD::FNEG, dl, VT, N1));
7174 // More folding opportunities when target permits.
7175 if (TLI.enableAggressiveFMAFusion(VT)) {
7177 // fold (fsub (fma x, y, (fmul u, v)), z)
7178 // -> (fma x, y (fma u, v, (fneg z)))
7179 if (N0.getOpcode() == ISD::FMA &&
7180 N0.getOperand(2).getOpcode() == ISD::FMUL)
7181 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
7182 N0.getOperand(0), N0.getOperand(1),
7183 DAG.getNode(ISD::FMA, SDLoc(N), VT,
7184 N0.getOperand(2).getOperand(0),
7185 N0.getOperand(2).getOperand(1),
7186 DAG.getNode(ISD::FNEG, SDLoc(N), VT,
7189 // fold (fsub x, (fma y, z, (fmul u, v)))
7190 // -> (fma (fneg y), z, (fma (fneg u), v, x))
7191 if (N1.getOpcode() == ISD::FMA &&
7192 N1.getOperand(2).getOpcode() == ISD::FMUL) {
7193 SDValue N20 = N1.getOperand(2).getOperand(0);
7194 SDValue N21 = N1.getOperand(2).getOperand(1);
7195 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
7196 DAG.getNode(ISD::FNEG, SDLoc(N), VT,
7199 DAG.getNode(ISD::FMA, SDLoc(N), VT,
7200 DAG.getNode(ISD::FNEG, SDLoc(N), VT,
7210 SDValue DAGCombiner::visitFMUL(SDNode *N) {
7211 SDValue N0 = N->getOperand(0);
7212 SDValue N1 = N->getOperand(1);
7213 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
7214 ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
7215 EVT VT = N->getValueType(0);
7216 const TargetOptions &Options = DAG.getTarget().Options;
7219 if (VT.isVector()) {
7220 // This just handles C1 * C2 for vectors. Other vector folds are below.
7221 SDValue FoldedVOp = SimplifyVBinOp(N);
7222 if (FoldedVOp.getNode())
7224 // Canonicalize vector constant to RHS.
7225 if (N0.getOpcode() == ISD::BUILD_VECTOR &&
7226 N1.getOpcode() != ISD::BUILD_VECTOR)
7227 if (auto *BV0 = dyn_cast<BuildVectorSDNode>(N0))
7228 if (BV0->isConstant())
7229 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
7232 // fold (fmul c1, c2) -> c1*c2
7234 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, N1);
7236 // canonicalize constant to RHS
7237 if (N0CFP && !N1CFP)
7238 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1, N0);
7240 // fold (fmul A, 1.0) -> A
7241 if (N1CFP && N1CFP->isExactlyValue(1.0))
7244 if (Options.UnsafeFPMath) {
7245 // fold (fmul A, 0) -> 0
7246 if (N1CFP && N1CFP->getValueAPF().isZero())
7249 // fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
7250 if (N0.getOpcode() == ISD::FMUL) {
7251 // Fold scalars or any vector constants (not just splats).
7252 // This fold is done in general by InstCombine, but extra fmul insts
7253 // may have been generated during lowering.
7254 SDValue N01 = N0.getOperand(1);
7255 auto *BV1 = dyn_cast<BuildVectorSDNode>(N1);
7256 auto *BV01 = dyn_cast<BuildVectorSDNode>(N01);
7257 if ((N1CFP && isConstOrConstSplatFP(N01)) ||
7258 (BV1 && BV01 && BV1->isConstant() && BV01->isConstant())) {
7260 SDValue MulConsts = DAG.getNode(ISD::FMUL, SL, VT, N01, N1);
7261 return DAG.getNode(ISD::FMUL, SL, VT, N0.getOperand(0), MulConsts);
7265 // fold (fmul (fadd x, x), c) -> (fmul x, (fmul 2.0, c))
7266 // Undo the fmul 2.0, x -> fadd x, x transformation, since if it occurs
7267 // during an early run of DAGCombiner can prevent folding with fmuls
7268 // inserted during lowering.
7269 if (N0.getOpcode() == ISD::FADD && N0.getOperand(0) == N0.getOperand(1)) {
7271 const SDValue Two = DAG.getConstantFP(2.0, VT);
7272 SDValue MulConsts = DAG.getNode(ISD::FMUL, SL, VT, Two, N1);
7273 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0.getOperand(0), MulConsts);
7277 // fold (fmul X, 2.0) -> (fadd X, X)
7278 if (N1CFP && N1CFP->isExactlyValue(+2.0))
7279 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N0);
7281 // fold (fmul X, -1.0) -> (fneg X)
7282 if (N1CFP && N1CFP->isExactlyValue(-1.0))
7283 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
7284 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0);
7286 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
7287 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, &Options)) {
7288 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, &Options)) {
7289 // Both can be negated for free, check to see if at least one is cheaper
7291 if (LHSNeg == 2 || RHSNeg == 2)
7292 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
7293 GetNegatedExpression(N0, DAG, LegalOperations),
7294 GetNegatedExpression(N1, DAG, LegalOperations));
7301 SDValue DAGCombiner::visitFMA(SDNode *N) {
7302 SDValue N0 = N->getOperand(0);
7303 SDValue N1 = N->getOperand(1);
7304 SDValue N2 = N->getOperand(2);
7305 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7306 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7307 EVT VT = N->getValueType(0);
7309 const TargetOptions &Options = DAG.getTarget().Options;
7311 // Constant fold FMA.
7312 if (isa<ConstantFPSDNode>(N0) &&
7313 isa<ConstantFPSDNode>(N1) &&
7314 isa<ConstantFPSDNode>(N2)) {
7315 return DAG.getNode(ISD::FMA, dl, VT, N0, N1, N2);
7318 if (Options.UnsafeFPMath) {
7319 if (N0CFP && N0CFP->isZero())
7321 if (N1CFP && N1CFP->isZero())
7324 if (N0CFP && N0CFP->isExactlyValue(1.0))
7325 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N2);
7326 if (N1CFP && N1CFP->isExactlyValue(1.0))
7327 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N2);
7329 // Canonicalize (fma c, x, y) -> (fma x, c, y)
7330 if (N0CFP && !N1CFP)
7331 return DAG.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2);
7333 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)
7334 if (Options.UnsafeFPMath && N1CFP &&
7335 N2.getOpcode() == ISD::FMUL &&
7336 N0 == N2.getOperand(0) &&
7337 N2.getOperand(1).getOpcode() == ISD::ConstantFP) {
7338 return DAG.getNode(ISD::FMUL, dl, VT, N0,
7339 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1)));
7343 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y)
7344 if (Options.UnsafeFPMath &&
7345 N0.getOpcode() == ISD::FMUL && N1CFP &&
7346 N0.getOperand(1).getOpcode() == ISD::ConstantFP) {
7347 return DAG.getNode(ISD::FMA, dl, VT,
7349 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)),
7353 // (fma x, 1, y) -> (fadd x, y)
7354 // (fma x, -1, y) -> (fadd (fneg x), y)
7356 if (N1CFP->isExactlyValue(1.0))
7357 return DAG.getNode(ISD::FADD, dl, VT, N0, N2);
7359 if (N1CFP->isExactlyValue(-1.0) &&
7360 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {
7361 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0);
7362 AddToWorklist(RHSNeg.getNode());
7363 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg);
7367 // (fma x, c, x) -> (fmul x, (c+1))
7368 if (Options.UnsafeFPMath && N1CFP && N0 == N2)
7369 return DAG.getNode(ISD::FMUL, dl, VT, N0,
7370 DAG.getNode(ISD::FADD, dl, VT,
7371 N1, DAG.getConstantFP(1.0, VT)));
7373 // (fma x, c, (fneg x)) -> (fmul x, (c-1))
7374 if (Options.UnsafeFPMath && N1CFP &&
7375 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0)
7376 return DAG.getNode(ISD::FMUL, dl, VT, N0,
7377 DAG.getNode(ISD::FADD, dl, VT,
7378 N1, DAG.getConstantFP(-1.0, VT)));
7384 SDValue DAGCombiner::visitFDIV(SDNode *N) {
7385 SDValue N0 = N->getOperand(0);
7386 SDValue N1 = N->getOperand(1);
7387 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7388 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7389 EVT VT = N->getValueType(0);
7391 const TargetOptions &Options = DAG.getTarget().Options;
7394 if (VT.isVector()) {
7395 SDValue FoldedVOp = SimplifyVBinOp(N);
7396 if (FoldedVOp.getNode()) return FoldedVOp;
7399 // fold (fdiv c1, c2) -> c1/c2
7401 return DAG.getNode(ISD::FDIV, SDLoc(N), VT, N0, N1);
7403 if (Options.UnsafeFPMath) {
7404 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
7406 // Compute the reciprocal 1.0 / c2.
7407 APFloat N1APF = N1CFP->getValueAPF();
7408 APFloat Recip(N1APF.getSemantics(), 1); // 1.0
7409 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven);
7410 // Only do the transform if the reciprocal is a legal fp immediate that
7411 // isn't too nasty (eg NaN, denormal, ...).
7412 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty
7413 (!LegalOperations ||
7414 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
7415 // backend)... we should handle this gracefully after Legalize.
7416 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
7417 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
7418 TLI.isFPImmLegal(Recip, VT)))
7419 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0,
7420 DAG.getConstantFP(Recip, VT));
7423 // If this FDIV is part of a reciprocal square root, it may be folded
7424 // into a target-specific square root estimate instruction.
7425 if (N1.getOpcode() == ISD::FSQRT) {
7426 if (SDValue RV = BuildRsqrtEstimate(N1.getOperand(0))) {
7427 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7429 } else if (N1.getOpcode() == ISD::FP_EXTEND &&
7430 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
7431 if (SDValue RV = BuildRsqrtEstimate(N1.getOperand(0).getOperand(0))) {
7432 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N1), VT, RV);
7433 AddToWorklist(RV.getNode());
7434 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7436 } else if (N1.getOpcode() == ISD::FP_ROUND &&
7437 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
7438 if (SDValue RV = BuildRsqrtEstimate(N1.getOperand(0).getOperand(0))) {
7439 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N1), VT, RV, N1.getOperand(1));
7440 AddToWorklist(RV.getNode());
7441 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7443 } else if (N1.getOpcode() == ISD::FMUL) {
7444 // Look through an FMUL. Even though this won't remove the FDIV directly,
7445 // it's still worthwhile to get rid of the FSQRT if possible.
7448 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) {
7449 SqrtOp = N1.getOperand(0);
7450 OtherOp = N1.getOperand(1);
7451 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) {
7452 SqrtOp = N1.getOperand(1);
7453 OtherOp = N1.getOperand(0);
7455 if (SqrtOp.getNode()) {
7456 // We found a FSQRT, so try to make this fold:
7457 // x / (y * sqrt(z)) -> x * (rsqrt(z) / y)
7458 if (SDValue RV = BuildRsqrtEstimate(SqrtOp.getOperand(0))) {
7459 RV = DAG.getNode(ISD::FDIV, SDLoc(N1), VT, RV, OtherOp);
7460 AddToWorklist(RV.getNode());
7461 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7466 // Fold into a reciprocal estimate and multiply instead of a real divide.
7467 if (SDValue RV = BuildReciprocalEstimate(N1)) {
7468 AddToWorklist(RV.getNode());
7469 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
7473 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
7474 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, &Options)) {
7475 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, &Options)) {
7476 // Both can be negated for free, check to see if at least one is cheaper
7478 if (LHSNeg == 2 || RHSNeg == 2)
7479 return DAG.getNode(ISD::FDIV, SDLoc(N), VT,
7480 GetNegatedExpression(N0, DAG, LegalOperations),
7481 GetNegatedExpression(N1, DAG, LegalOperations));
7485 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
7487 // E.g., (a / D; b / D;) -> (recip = 1.0 / D; a * recip; b * recip)
7488 // Notice that this is not always beneficial. One reason is different target
7489 // may have different costs for FDIV and FMUL, so sometimes the cost of two
7490 // FDIVs may be lower than the cost of one FDIV and two FMULs. Another reason
7491 // is the critical path is increased from "one FDIV" to "one FDIV + one FMUL".
7492 if (Options.UnsafeFPMath) {
7493 // Skip if current node is a reciprocal.
7494 if (N0CFP && N0CFP->isExactlyValue(1.0))
7497 SmallVector<SDNode *, 4> Users;
7498 // Find all FDIV users of the same divisor.
7499 for (SDNode::use_iterator UI = N1.getNode()->use_begin(),
7500 UE = N1.getNode()->use_end();
7502 SDNode *User = UI.getUse().getUser();
7503 if (User->getOpcode() == ISD::FDIV && User->getOperand(1) == N1)
7504 Users.push_back(User);
7507 if (TLI.combineRepeatedFPDivisors(Users.size())) {
7508 SDValue FPOne = DAG.getConstantFP(1.0, VT); // floating point 1.0
7509 SDValue Reciprocal = DAG.getNode(ISD::FDIV, SDLoc(N), VT, FPOne, N1);
7511 // Dividend / Divisor -> Dividend * Reciprocal
7512 for (auto I = Users.begin(), E = Users.end(); I != E; ++I) {
7513 if ((*I)->getOperand(0) != FPOne) {
7514 SDValue NewNode = DAG.getNode(ISD::FMUL, SDLoc(*I), VT,
7515 (*I)->getOperand(0), Reciprocal);
7516 DAG.ReplaceAllUsesWith(*I, NewNode.getNode());
7526 SDValue DAGCombiner::visitFREM(SDNode *N) {
7527 SDValue N0 = N->getOperand(0);
7528 SDValue N1 = N->getOperand(1);
7529 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7530 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7531 EVT VT = N->getValueType(0);
7533 // fold (frem c1, c2) -> fmod(c1,c2)
7535 return DAG.getNode(ISD::FREM, SDLoc(N), VT, N0, N1);
7540 SDValue DAGCombiner::visitFSQRT(SDNode *N) {
7541 if (DAG.getTarget().Options.UnsafeFPMath &&
7542 !TLI.isFsqrtCheap()) {
7543 // Compute this as X * (1/sqrt(X)) = X * (X ** -0.5)
7544 if (SDValue RV = BuildRsqrtEstimate(N->getOperand(0))) {
7545 EVT VT = RV.getValueType();
7546 RV = DAG.getNode(ISD::FMUL, SDLoc(N), VT, N->getOperand(0), RV);
7547 AddToWorklist(RV.getNode());
7549 // Unfortunately, RV is now NaN if the input was exactly 0.
7550 // Select out this case and force the answer to 0.
7551 SDValue Zero = DAG.getConstantFP(0.0, VT);
7553 DAG.getSetCC(SDLoc(N), TLI.getSetCCResultType(*DAG.getContext(), VT),
7554 N->getOperand(0), Zero, ISD::SETEQ);
7555 AddToWorklist(ZeroCmp.getNode());
7556 AddToWorklist(RV.getNode());
7558 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT,
7559 SDLoc(N), VT, ZeroCmp, Zero, RV);
7566 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
7567 SDValue N0 = N->getOperand(0);
7568 SDValue N1 = N->getOperand(1);
7569 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7570 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7571 EVT VT = N->getValueType(0);
7573 if (N0CFP && N1CFP) // Constant fold
7574 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1);
7577 const APFloat& V = N1CFP->getValueAPF();
7578 // copysign(x, c1) -> fabs(x) iff ispos(c1)
7579 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
7580 if (!V.isNegative()) {
7581 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
7582 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
7584 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
7585 return DAG.getNode(ISD::FNEG, SDLoc(N), VT,
7586 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0));
7590 // copysign(fabs(x), y) -> copysign(x, y)
7591 // copysign(fneg(x), y) -> copysign(x, y)
7592 // copysign(copysign(x,z), y) -> copysign(x, y)
7593 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
7594 N0.getOpcode() == ISD::FCOPYSIGN)
7595 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7596 N0.getOperand(0), N1);
7598 // copysign(x, abs(y)) -> abs(x)
7599 if (N1.getOpcode() == ISD::FABS)
7600 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
7602 // copysign(x, copysign(y,z)) -> copysign(x, z)
7603 if (N1.getOpcode() == ISD::FCOPYSIGN)
7604 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7605 N0, N1.getOperand(1));
7607 // copysign(x, fp_extend(y)) -> copysign(x, y)
7608 // copysign(x, fp_round(y)) -> copysign(x, y)
7609 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
7610 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7611 N0, N1.getOperand(0));
7616 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
7617 SDValue N0 = N->getOperand(0);
7618 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
7619 EVT VT = N->getValueType(0);
7620 EVT OpVT = N0.getValueType();
7622 // fold (sint_to_fp c1) -> c1fp
7624 // ...but only if the target supports immediate floating-point values
7625 (!LegalOperations ||
7626 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
7627 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
7629 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
7630 // but UINT_TO_FP is legal on this target, try to convert.
7631 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
7632 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
7633 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
7634 if (DAG.SignBitIsZero(N0))
7635 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
7638 // The next optimizations are desirable only if SELECT_CC can be lowered.
7639 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
7640 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
7641 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
7643 (!LegalOperations ||
7644 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
7646 { N0.getOperand(0), N0.getOperand(1),
7647 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT),
7649 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
7652 // fold (sint_to_fp (zext (setcc x, y, cc))) ->
7653 // (select_cc x, y, 1.0, 0.0,, cc)
7654 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
7655 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
7656 (!LegalOperations ||
7657 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
7659 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
7660 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT),
7661 N0.getOperand(0).getOperand(2) };
7662 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
7669 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
7670 SDValue N0 = N->getOperand(0);
7671 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
7672 EVT VT = N->getValueType(0);
7673 EVT OpVT = N0.getValueType();
7675 // fold (uint_to_fp c1) -> c1fp
7677 // ...but only if the target supports immediate floating-point values
7678 (!LegalOperations ||
7679 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
7680 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
7682 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
7683 // but SINT_TO_FP is legal on this target, try to convert.
7684 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
7685 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
7686 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
7687 if (DAG.SignBitIsZero(N0))
7688 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
7691 // The next optimizations are desirable only if SELECT_CC can be lowered.
7692 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
7693 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
7695 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
7696 (!LegalOperations ||
7697 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
7699 { N0.getOperand(0), N0.getOperand(1),
7700 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT),
7702 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
7709 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
7710 SDValue N0 = N->getOperand(0);
7711 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7712 EVT VT = N->getValueType(0);
7714 // fold (fp_to_sint c1fp) -> c1
7716 return DAG.getNode(ISD::FP_TO_SINT, SDLoc(N), VT, N0);
7721 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
7722 SDValue N0 = N->getOperand(0);
7723 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7724 EVT VT = N->getValueType(0);
7726 // fold (fp_to_uint c1fp) -> c1
7728 return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), VT, N0);
7733 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
7734 SDValue N0 = N->getOperand(0);
7735 SDValue N1 = N->getOperand(1);
7736 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7737 EVT VT = N->getValueType(0);
7739 // fold (fp_round c1fp) -> c1fp
7741 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1);
7743 // fold (fp_round (fp_extend x)) -> x
7744 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
7745 return N0.getOperand(0);
7747 // fold (fp_round (fp_round x)) -> (fp_round x)
7748 if (N0.getOpcode() == ISD::FP_ROUND) {
7749 // This is a value preserving truncation if both round's are.
7750 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
7751 N0.getNode()->getConstantOperandVal(1) == 1;
7752 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0.getOperand(0),
7753 DAG.getIntPtrConstant(IsTrunc));
7756 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
7757 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
7758 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT,
7759 N0.getOperand(0), N1);
7760 AddToWorklist(Tmp.getNode());
7761 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7762 Tmp, N0.getOperand(1));
7768 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
7769 SDValue N0 = N->getOperand(0);
7770 EVT VT = N->getValueType(0);
7771 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
7772 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7774 // fold (fp_round_inreg c1fp) -> c1fp
7775 if (N0CFP && isTypeLegal(EVT)) {
7776 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
7777 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Round);
7783 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
7784 SDValue N0 = N->getOperand(0);
7785 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7786 EVT VT = N->getValueType(0);
7788 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
7789 if (N->hasOneUse() &&
7790 N->use_begin()->getOpcode() == ISD::FP_ROUND)
7793 // fold (fp_extend c1fp) -> c1fp
7795 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0);
7797 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
7799 if (N0.getOpcode() == ISD::FP_ROUND
7800 && N0.getNode()->getConstantOperandVal(1) == 1) {
7801 SDValue In = N0.getOperand(0);
7802 if (In.getValueType() == VT) return In;
7803 if (VT.bitsLT(In.getValueType()))
7804 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT,
7805 In, N0.getOperand(1));
7806 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, In);
7809 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
7810 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7811 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) {
7812 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7813 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
7815 LN0->getBasePtr(), N0.getValueType(),
7816 LN0->getMemOperand());
7817 CombineTo(N, ExtLoad);
7818 CombineTo(N0.getNode(),
7819 DAG.getNode(ISD::FP_ROUND, SDLoc(N0),
7820 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
7821 ExtLoad.getValue(1));
7822 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7828 SDValue DAGCombiner::visitFCEIL(SDNode *N) {
7829 SDValue N0 = N->getOperand(0);
7830 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7831 EVT VT = N->getValueType(0);
7833 // fold (fceil c1) -> fceil(c1)
7835 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0);
7840 SDValue DAGCombiner::visitFTRUNC(SDNode *N) {
7841 SDValue N0 = N->getOperand(0);
7842 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7843 EVT VT = N->getValueType(0);
7845 // fold (ftrunc c1) -> ftrunc(c1)
7847 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0);
7852 SDValue DAGCombiner::visitFFLOOR(SDNode *N) {
7853 SDValue N0 = N->getOperand(0);
7854 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7855 EVT VT = N->getValueType(0);
7857 // fold (ffloor c1) -> ffloor(c1)
7859 return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0);
7864 // FIXME: FNEG and FABS have a lot in common; refactor.
7865 SDValue DAGCombiner::visitFNEG(SDNode *N) {
7866 SDValue N0 = N->getOperand(0);
7867 EVT VT = N->getValueType(0);
7869 if (VT.isVector()) {
7870 SDValue FoldedVOp = SimplifyVUnaryOp(N);
7871 if (FoldedVOp.getNode()) return FoldedVOp;
7874 // Constant fold FNEG.
7875 if (isa<ConstantFPSDNode>(N0))
7876 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N->getOperand(0));
7878 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
7879 &DAG.getTarget().Options))
7880 return GetNegatedExpression(N0, DAG, LegalOperations);
7882 // Transform fneg(bitconvert(x)) -> bitconvert(x ^ sign) to avoid loading
7883 // constant pool values.
7884 if (!TLI.isFNegFree(VT) &&
7885 N0.getOpcode() == ISD::BITCAST &&
7886 N0.getNode()->hasOneUse()) {
7887 SDValue Int = N0.getOperand(0);
7888 EVT IntVT = Int.getValueType();
7889 if (IntVT.isInteger() && !IntVT.isVector()) {
7891 if (N0.getValueType().isVector()) {
7892 // For a vector, get a mask such as 0x80... per scalar element
7894 SignMask = APInt::getSignBit(N0.getValueType().getScalarSizeInBits());
7895 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
7897 // For a scalar, just generate 0x80...
7898 SignMask = APInt::getSignBit(IntVT.getSizeInBits());
7900 Int = DAG.getNode(ISD::XOR, SDLoc(N0), IntVT, Int,
7901 DAG.getConstant(SignMask, IntVT));
7902 AddToWorklist(Int.getNode());
7903 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Int);
7907 // (fneg (fmul c, x)) -> (fmul -c, x)
7908 if (N0.getOpcode() == ISD::FMUL) {
7909 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
7911 APFloat CVal = CFP1->getValueAPF();
7913 if (Level >= AfterLegalizeDAG &&
7914 (TLI.isFPImmLegal(CVal, N->getValueType(0)) ||
7915 TLI.isOperationLegal(ISD::ConstantFP, N->getValueType(0))))
7917 ISD::FMUL, SDLoc(N), VT, N0.getOperand(0),
7918 DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0.getOperand(1)));
7925 SDValue DAGCombiner::visitFMINNUM(SDNode *N) {
7926 SDValue N0 = N->getOperand(0);
7927 SDValue N1 = N->getOperand(1);
7928 const ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7929 const ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7931 if (N0CFP && N1CFP) {
7932 const APFloat &C0 = N0CFP->getValueAPF();
7933 const APFloat &C1 = N1CFP->getValueAPF();
7934 return DAG.getConstantFP(minnum(C0, C1), N->getValueType(0));
7938 EVT VT = N->getValueType(0);
7939 // Canonicalize to constant on RHS.
7940 return DAG.getNode(ISD::FMINNUM, SDLoc(N), VT, N1, N0);
7946 SDValue DAGCombiner::visitFMAXNUM(SDNode *N) {
7947 SDValue N0 = N->getOperand(0);
7948 SDValue N1 = N->getOperand(1);
7949 const ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7950 const ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7952 if (N0CFP && N1CFP) {
7953 const APFloat &C0 = N0CFP->getValueAPF();
7954 const APFloat &C1 = N1CFP->getValueAPF();
7955 return DAG.getConstantFP(maxnum(C0, C1), N->getValueType(0));
7959 EVT VT = N->getValueType(0);
7960 // Canonicalize to constant on RHS.
7961 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), VT, N1, N0);
7967 SDValue DAGCombiner::visitFABS(SDNode *N) {
7968 SDValue N0 = N->getOperand(0);
7969 EVT VT = N->getValueType(0);
7971 if (VT.isVector()) {
7972 SDValue FoldedVOp = SimplifyVUnaryOp(N);
7973 if (FoldedVOp.getNode()) return FoldedVOp;
7976 // fold (fabs c1) -> fabs(c1)
7977 if (isa<ConstantFPSDNode>(N0))
7978 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
7980 // fold (fabs (fabs x)) -> (fabs x)
7981 if (N0.getOpcode() == ISD::FABS)
7982 return N->getOperand(0);
7984 // fold (fabs (fneg x)) -> (fabs x)
7985 // fold (fabs (fcopysign x, y)) -> (fabs x)
7986 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
7987 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0));
7989 // Transform fabs(bitconvert(x)) -> bitconvert(x & ~sign) to avoid loading
7990 // constant pool values.
7991 if (!TLI.isFAbsFree(VT) &&
7992 N0.getOpcode() == ISD::BITCAST &&
7993 N0.getNode()->hasOneUse()) {
7994 SDValue Int = N0.getOperand(0);
7995 EVT IntVT = Int.getValueType();
7996 if (IntVT.isInteger() && !IntVT.isVector()) {
7998 if (N0.getValueType().isVector()) {
7999 // For a vector, get a mask such as 0x7f... per scalar element
8001 SignMask = ~APInt::getSignBit(N0.getValueType().getScalarSizeInBits());
8002 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
8004 // For a scalar, just generate 0x7f...
8005 SignMask = ~APInt::getSignBit(IntVT.getSizeInBits());
8007 Int = DAG.getNode(ISD::AND, SDLoc(N0), IntVT, Int,
8008 DAG.getConstant(SignMask, IntVT));
8009 AddToWorklist(Int.getNode());
8010 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Int);
8017 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
8018 SDValue Chain = N->getOperand(0);
8019 SDValue N1 = N->getOperand(1);
8020 SDValue N2 = N->getOperand(2);
8022 // If N is a constant we could fold this into a fallthrough or unconditional
8023 // branch. However that doesn't happen very often in normal code, because
8024 // Instcombine/SimplifyCFG should have handled the available opportunities.
8025 // If we did this folding here, it would be necessary to update the
8026 // MachineBasicBlock CFG, which is awkward.
8028 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
8030 if (N1.getOpcode() == ISD::SETCC &&
8031 TLI.isOperationLegalOrCustom(ISD::BR_CC,
8032 N1.getOperand(0).getValueType())) {
8033 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
8034 Chain, N1.getOperand(2),
8035 N1.getOperand(0), N1.getOperand(1), N2);
8038 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
8039 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
8040 (N1.getOperand(0).hasOneUse() &&
8041 N1.getOperand(0).getOpcode() == ISD::SRL))) {
8042 SDNode *Trunc = nullptr;
8043 if (N1.getOpcode() == ISD::TRUNCATE) {
8044 // Look pass the truncate.
8045 Trunc = N1.getNode();
8046 N1 = N1.getOperand(0);
8049 // Match this pattern so that we can generate simpler code:
8052 // %b = and i32 %a, 2
8053 // %c = srl i32 %b, 1
8054 // brcond i32 %c ...
8059 // %b = and i32 %a, 2
8060 // %c = setcc eq %b, 0
8063 // This applies only when the AND constant value has one bit set and the
8064 // SRL constant is equal to the log2 of the AND constant. The back-end is
8065 // smart enough to convert the result into a TEST/JMP sequence.
8066 SDValue Op0 = N1.getOperand(0);
8067 SDValue Op1 = N1.getOperand(1);
8069 if (Op0.getOpcode() == ISD::AND &&
8070 Op1.getOpcode() == ISD::Constant) {
8071 SDValue AndOp1 = Op0.getOperand(1);
8073 if (AndOp1.getOpcode() == ISD::Constant) {
8074 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
8076 if (AndConst.isPowerOf2() &&
8077 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
8079 DAG.getSetCC(SDLoc(N),
8080 getSetCCResultType(Op0.getValueType()),
8081 Op0, DAG.getConstant(0, Op0.getValueType()),
8084 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, SDLoc(N),
8085 MVT::Other, Chain, SetCC, N2);
8086 // Don't add the new BRCond into the worklist or else SimplifySelectCC
8087 // will convert it back to (X & C1) >> C2.
8088 CombineTo(N, NewBRCond, false);
8089 // Truncate is dead.
8091 deleteAndRecombine(Trunc);
8092 // Replace the uses of SRL with SETCC
8093 WorklistRemover DeadNodes(*this);
8094 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
8095 deleteAndRecombine(N1.getNode());
8096 return SDValue(N, 0); // Return N so it doesn't get rechecked!
8102 // Restore N1 if the above transformation doesn't match.
8103 N1 = N->getOperand(1);
8106 // Transform br(xor(x, y)) -> br(x != y)
8107 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
8108 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
8109 SDNode *TheXor = N1.getNode();
8110 SDValue Op0 = TheXor->getOperand(0);
8111 SDValue Op1 = TheXor->getOperand(1);
8112 if (Op0.getOpcode() == Op1.getOpcode()) {
8113 // Avoid missing important xor optimizations.
8114 SDValue Tmp = visitXOR(TheXor);
8115 if (Tmp.getNode()) {
8116 if (Tmp.getNode() != TheXor) {
8117 DEBUG(dbgs() << "\nReplacing.8 ";
8119 dbgs() << "\nWith: ";
8120 Tmp.getNode()->dump(&DAG);
8122 WorklistRemover DeadNodes(*this);
8123 DAG.ReplaceAllUsesOfValueWith(N1, Tmp);
8124 deleteAndRecombine(TheXor);
8125 return DAG.getNode(ISD::BRCOND, SDLoc(N),
8126 MVT::Other, Chain, Tmp, N2);
8129 // visitXOR has changed XOR's operands or replaced the XOR completely,
8131 return SDValue(N, 0);
8135 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
8137 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
8138 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
8139 Op0.getOpcode() == ISD::XOR) {
8140 TheXor = Op0.getNode();
8144 EVT SetCCVT = N1.getValueType();
8146 SetCCVT = getSetCCResultType(SetCCVT);
8147 SDValue SetCC = DAG.getSetCC(SDLoc(TheXor),
8150 Equal ? ISD::SETEQ : ISD::SETNE);
8151 // Replace the uses of XOR with SETCC
8152 WorklistRemover DeadNodes(*this);
8153 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
8154 deleteAndRecombine(N1.getNode());
8155 return DAG.getNode(ISD::BRCOND, SDLoc(N),
8156 MVT::Other, Chain, SetCC, N2);
8163 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
8165 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
8166 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
8167 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
8169 // If N is a constant we could fold this into a fallthrough or unconditional
8170 // branch. However that doesn't happen very often in normal code, because
8171 // Instcombine/SimplifyCFG should have handled the available opportunities.
8172 // If we did this folding here, it would be necessary to update the
8173 // MachineBasicBlock CFG, which is awkward.
8175 // Use SimplifySetCC to simplify SETCC's.
8176 SDValue Simp = SimplifySetCC(getSetCCResultType(CondLHS.getValueType()),
8177 CondLHS, CondRHS, CC->get(), SDLoc(N),
8179 if (Simp.getNode()) AddToWorklist(Simp.getNode());
8181 // fold to a simpler setcc
8182 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
8183 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
8184 N->getOperand(0), Simp.getOperand(2),
8185 Simp.getOperand(0), Simp.getOperand(1),
8191 /// Return true if 'Use' is a load or a store that uses N as its base pointer
8192 /// and that N may be folded in the load / store addressing mode.
8193 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
8195 const TargetLowering &TLI) {
8197 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
8198 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
8200 VT = Use->getValueType(0);
8201 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
8202 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
8204 VT = ST->getValue().getValueType();
8208 TargetLowering::AddrMode AM;
8209 if (N->getOpcode() == ISD::ADD) {
8210 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
8213 AM.BaseOffs = Offset->getSExtValue();
8217 } else if (N->getOpcode() == ISD::SUB) {
8218 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
8221 AM.BaseOffs = -Offset->getSExtValue();
8228 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
8231 /// Try turning a load/store into a pre-indexed load/store when the base
8232 /// pointer is an add or subtract and it has other uses besides the load/store.
8233 /// After the transformation, the new indexed load/store has effectively folded
8234 /// the add/subtract in and all of its other uses are redirected to the
8236 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
8237 if (Level < AfterLegalizeDAG)
8243 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8244 if (LD->isIndexed())
8246 VT = LD->getMemoryVT();
8247 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
8248 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
8250 Ptr = LD->getBasePtr();
8251 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8252 if (ST->isIndexed())
8254 VT = ST->getMemoryVT();
8255 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
8256 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
8258 Ptr = ST->getBasePtr();
8264 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
8265 // out. There is no reason to make this a preinc/predec.
8266 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
8267 Ptr.getNode()->hasOneUse())
8270 // Ask the target to do addressing mode selection.
8273 ISD::MemIndexedMode AM = ISD::UNINDEXED;
8274 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
8277 // Backends without true r+i pre-indexed forms may need to pass a
8278 // constant base with a variable offset so that constant coercion
8279 // will work with the patterns in canonical form.
8280 bool Swapped = false;
8281 if (isa<ConstantSDNode>(BasePtr)) {
8282 std::swap(BasePtr, Offset);
8286 // Don't create a indexed load / store with zero offset.
8287 if (isa<ConstantSDNode>(Offset) &&
8288 cast<ConstantSDNode>(Offset)->isNullValue())
8291 // Try turning it into a pre-indexed load / store except when:
8292 // 1) The new base ptr is a frame index.
8293 // 2) If N is a store and the new base ptr is either the same as or is a
8294 // predecessor of the value being stored.
8295 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
8296 // that would create a cycle.
8297 // 4) All uses are load / store ops that use it as old base ptr.
8299 // Check #1. Preinc'ing a frame index would require copying the stack pointer
8300 // (plus the implicit offset) to a register to preinc anyway.
8301 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
8306 SDValue Val = cast<StoreSDNode>(N)->getValue();
8307 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
8311 // If the offset is a constant, there may be other adds of constants that
8312 // can be folded with this one. We should do this to avoid having to keep
8313 // a copy of the original base pointer.
8314 SmallVector<SDNode *, 16> OtherUses;
8315 if (isa<ConstantSDNode>(Offset))
8316 for (SDNode *Use : BasePtr.getNode()->uses()) {
8317 if (Use == Ptr.getNode())
8320 if (Use->isPredecessorOf(N))
8323 if (Use->getOpcode() != ISD::ADD && Use->getOpcode() != ISD::SUB) {
8328 SDValue Op0 = Use->getOperand(0), Op1 = Use->getOperand(1);
8329 if (Op1.getNode() == BasePtr.getNode())
8330 std::swap(Op0, Op1);
8331 assert(Op0.getNode() == BasePtr.getNode() &&
8332 "Use of ADD/SUB but not an operand");
8334 if (!isa<ConstantSDNode>(Op1)) {
8339 // FIXME: In some cases, we can be smarter about this.
8340 if (Op1.getValueType() != Offset.getValueType()) {
8345 OtherUses.push_back(Use);
8349 std::swap(BasePtr, Offset);
8351 // Now check for #3 and #4.
8352 bool RealUse = false;
8354 // Caches for hasPredecessorHelper
8355 SmallPtrSet<const SDNode *, 32> Visited;
8356 SmallVector<const SDNode *, 16> Worklist;
8358 for (SDNode *Use : Ptr.getNode()->uses()) {
8361 if (N->hasPredecessorHelper(Use, Visited, Worklist))
8364 // If Ptr may be folded in addressing mode of other use, then it's
8365 // not profitable to do this transformation.
8366 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
8375 Result = DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
8376 BasePtr, Offset, AM);
8378 Result = DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
8379 BasePtr, Offset, AM);
8382 DEBUG(dbgs() << "\nReplacing.4 ";
8384 dbgs() << "\nWith: ";
8385 Result.getNode()->dump(&DAG);
8387 WorklistRemover DeadNodes(*this);
8389 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
8390 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
8392 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
8395 // Finally, since the node is now dead, remove it from the graph.
8396 deleteAndRecombine(N);
8399 std::swap(BasePtr, Offset);
8401 // Replace other uses of BasePtr that can be updated to use Ptr
8402 for (unsigned i = 0, e = OtherUses.size(); i != e; ++i) {
8403 unsigned OffsetIdx = 1;
8404 if (OtherUses[i]->getOperand(OffsetIdx).getNode() == BasePtr.getNode())
8406 assert(OtherUses[i]->getOperand(!OffsetIdx).getNode() ==
8407 BasePtr.getNode() && "Expected BasePtr operand");
8409 // We need to replace ptr0 in the following expression:
8410 // x0 * offset0 + y0 * ptr0 = t0
8412 // x1 * offset1 + y1 * ptr0 = t1 (the indexed load/store)
8414 // where x0, x1, y0 and y1 in {-1, 1} are given by the types of the
8415 // indexed load/store and the expresion that needs to be re-written.
8417 // Therefore, we have:
8418 // t0 = (x0 * offset0 - x1 * y0 * y1 *offset1) + (y0 * y1) * t1
8420 ConstantSDNode *CN =
8421 cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx));
8423 APInt Offset0 = CN->getAPIntValue();
8424 APInt Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue();
8426 X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1;
8427 Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1;
8428 X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1;
8429 Y1 = (AM == ISD::PRE_DEC && Swapped) ? -1 : 1;
8431 unsigned Opcode = (Y0 * Y1 < 0) ? ISD::SUB : ISD::ADD;
8433 APInt CNV = Offset0;
8434 if (X0 < 0) CNV = -CNV;
8435 if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1;
8436 else CNV = CNV - Offset1;
8438 // We can now generate the new expression.
8439 SDValue NewOp1 = DAG.getConstant(CNV, CN->getValueType(0));
8440 SDValue NewOp2 = Result.getValue(isLoad ? 1 : 0);
8442 SDValue NewUse = DAG.getNode(Opcode,
8443 SDLoc(OtherUses[i]),
8444 OtherUses[i]->getValueType(0), NewOp1, NewOp2);
8445 DAG.ReplaceAllUsesOfValueWith(SDValue(OtherUses[i], 0), NewUse);
8446 deleteAndRecombine(OtherUses[i]);
8449 // Replace the uses of Ptr with uses of the updated base value.
8450 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0));
8451 deleteAndRecombine(Ptr.getNode());
8456 /// Try to combine a load/store with a add/sub of the base pointer node into a
8457 /// post-indexed load/store. The transformation folded the add/subtract into the
8458 /// new indexed load/store effectively and all of its uses are redirected to the
8460 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
8461 if (Level < AfterLegalizeDAG)
8467 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8468 if (LD->isIndexed())
8470 VT = LD->getMemoryVT();
8471 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
8472 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
8474 Ptr = LD->getBasePtr();
8475 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8476 if (ST->isIndexed())
8478 VT = ST->getMemoryVT();
8479 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
8480 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
8482 Ptr = ST->getBasePtr();
8488 if (Ptr.getNode()->hasOneUse())
8491 for (SDNode *Op : Ptr.getNode()->uses()) {
8493 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
8498 ISD::MemIndexedMode AM = ISD::UNINDEXED;
8499 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
8500 // Don't create a indexed load / store with zero offset.
8501 if (isa<ConstantSDNode>(Offset) &&
8502 cast<ConstantSDNode>(Offset)->isNullValue())
8505 // Try turning it into a post-indexed load / store except when
8506 // 1) All uses are load / store ops that use it as base ptr (and
8507 // it may be folded as addressing mmode).
8508 // 2) Op must be independent of N, i.e. Op is neither a predecessor
8509 // nor a successor of N. Otherwise, if Op is folded that would
8512 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
8516 bool TryNext = false;
8517 for (SDNode *Use : BasePtr.getNode()->uses()) {
8518 if (Use == Ptr.getNode())
8521 // If all the uses are load / store addresses, then don't do the
8523 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
8524 bool RealUse = false;
8525 for (SDNode *UseUse : Use->uses()) {
8526 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
8541 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
8542 SDValue Result = isLoad
8543 ? DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
8544 BasePtr, Offset, AM)
8545 : DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
8546 BasePtr, Offset, AM);
8549 DEBUG(dbgs() << "\nReplacing.5 ";
8551 dbgs() << "\nWith: ";
8552 Result.getNode()->dump(&DAG);
8554 WorklistRemover DeadNodes(*this);
8556 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
8557 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
8559 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
8562 // Finally, since the node is now dead, remove it from the graph.
8563 deleteAndRecombine(N);
8565 // Replace the uses of Use with uses of the updated base value.
8566 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
8567 Result.getValue(isLoad ? 1 : 0));
8568 deleteAndRecombine(Op);
8577 /// \brief Return the base-pointer arithmetic from an indexed \p LD.
8578 SDValue DAGCombiner::SplitIndexingFromLoad(LoadSDNode *LD) {
8579 ISD::MemIndexedMode AM = LD->getAddressingMode();
8580 assert(AM != ISD::UNINDEXED);
8581 SDValue BP = LD->getOperand(1);
8582 SDValue Inc = LD->getOperand(2);
8584 // Some backends use TargetConstants for load offsets, but don't expect
8585 // TargetConstants in general ADD nodes. We can convert these constants into
8586 // regular Constants (if the constant is not opaque).
8587 assert((Inc.getOpcode() != ISD::TargetConstant ||
8588 !cast<ConstantSDNode>(Inc)->isOpaque()) &&
8589 "Cannot split out indexing using opaque target constants");
8590 if (Inc.getOpcode() == ISD::TargetConstant) {
8591 ConstantSDNode *ConstInc = cast<ConstantSDNode>(Inc);
8592 Inc = DAG.getConstant(*ConstInc->getConstantIntValue(),
8593 ConstInc->getValueType(0));
8597 (AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB);
8598 return DAG.getNode(Opc, SDLoc(LD), BP.getSimpleValueType(), BP, Inc);
8601 SDValue DAGCombiner::visitLOAD(SDNode *N) {
8602 LoadSDNode *LD = cast<LoadSDNode>(N);
8603 SDValue Chain = LD->getChain();
8604 SDValue Ptr = LD->getBasePtr();
8606 // If load is not volatile and there are no uses of the loaded value (and
8607 // the updated indexed value in case of indexed loads), change uses of the
8608 // chain value into uses of the chain input (i.e. delete the dead load).
8609 if (!LD->isVolatile()) {
8610 if (N->getValueType(1) == MVT::Other) {
8612 if (!N->hasAnyUseOfValue(0)) {
8613 // It's not safe to use the two value CombineTo variant here. e.g.
8614 // v1, chain2 = load chain1, loc
8615 // v2, chain3 = load chain2, loc
8617 // Now we replace use of chain2 with chain1. This makes the second load
8618 // isomorphic to the one we are deleting, and thus makes this load live.
8619 DEBUG(dbgs() << "\nReplacing.6 ";
8621 dbgs() << "\nWith chain: ";
8622 Chain.getNode()->dump(&DAG);
8624 WorklistRemover DeadNodes(*this);
8625 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
8628 deleteAndRecombine(N);
8630 return SDValue(N, 0); // Return N so it doesn't get rechecked!
8634 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
8636 // If this load has an opaque TargetConstant offset, then we cannot split
8637 // the indexing into an add/sub directly (that TargetConstant may not be
8638 // valid for a different type of node, and we cannot convert an opaque
8639 // target constant into a regular constant).
8640 bool HasOTCInc = LD->getOperand(2).getOpcode() == ISD::TargetConstant &&
8641 cast<ConstantSDNode>(LD->getOperand(2))->isOpaque();
8643 if (!N->hasAnyUseOfValue(0) &&
8644 ((MaySplitLoadIndex && !HasOTCInc) || !N->hasAnyUseOfValue(1))) {
8645 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
8647 if (N->hasAnyUseOfValue(1) && MaySplitLoadIndex && !HasOTCInc) {
8648 Index = SplitIndexingFromLoad(LD);
8649 // Try to fold the base pointer arithmetic into subsequent loads and
8651 AddUsersToWorklist(N);
8653 Index = DAG.getUNDEF(N->getValueType(1));
8654 DEBUG(dbgs() << "\nReplacing.7 ";
8656 dbgs() << "\nWith: ";
8657 Undef.getNode()->dump(&DAG);
8658 dbgs() << " and 2 other values\n");
8659 WorklistRemover DeadNodes(*this);
8660 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef);
8661 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Index);
8662 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain);
8663 deleteAndRecombine(N);
8664 return SDValue(N, 0); // Return N so it doesn't get rechecked!
8669 // If this load is directly stored, replace the load value with the stored
8671 // TODO: Handle store large -> read small portion.
8672 // TODO: Handle TRUNCSTORE/LOADEXT
8673 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
8674 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
8675 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
8676 if (PrevST->getBasePtr() == Ptr &&
8677 PrevST->getValue().getValueType() == N->getValueType(0))
8678 return CombineTo(N, Chain.getOperand(1), Chain);
8682 // Try to infer better alignment information than the load already has.
8683 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
8684 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
8685 if (Align > LD->getMemOperand()->getBaseAlignment()) {
8687 DAG.getExtLoad(LD->getExtensionType(), SDLoc(N),
8688 LD->getValueType(0),
8689 Chain, Ptr, LD->getPointerInfo(),
8691 LD->isVolatile(), LD->isNonTemporal(),
8692 LD->isInvariant(), Align, LD->getAAInfo());
8693 return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true);
8698 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
8699 : DAG.getSubtarget().useAA();
8701 if (CombinerAAOnlyFunc.getNumOccurrences() &&
8702 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
8705 if (UseAA && LD->isUnindexed()) {
8706 // Walk up chain skipping non-aliasing memory nodes.
8707 SDValue BetterChain = FindBetterChain(N, Chain);
8709 // If there is a better chain.
8710 if (Chain != BetterChain) {
8713 // Replace the chain to void dependency.
8714 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
8715 ReplLoad = DAG.getLoad(N->getValueType(0), SDLoc(LD),
8716 BetterChain, Ptr, LD->getMemOperand());
8718 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD),
8719 LD->getValueType(0),
8720 BetterChain, Ptr, LD->getMemoryVT(),
8721 LD->getMemOperand());
8724 // Create token factor to keep old chain connected.
8725 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
8726 MVT::Other, Chain, ReplLoad.getValue(1));
8728 // Make sure the new and old chains are cleaned up.
8729 AddToWorklist(Token.getNode());
8731 // Replace uses with load result and token factor. Don't add users
8733 return CombineTo(N, ReplLoad.getValue(0), Token, false);
8737 // Try transforming N to an indexed load.
8738 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
8739 return SDValue(N, 0);
8741 // Try to slice up N to more direct loads if the slices are mapped to
8742 // different register banks or pairing can take place.
8744 return SDValue(N, 0);
8750 /// \brief Helper structure used to slice a load in smaller loads.
8751 /// Basically a slice is obtained from the following sequence:
8752 /// Origin = load Ty1, Base
8753 /// Shift = srl Ty1 Origin, CstTy Amount
8754 /// Inst = trunc Shift to Ty2
8756 /// Then, it will be rewriten into:
8757 /// Slice = load SliceTy, Base + SliceOffset
8758 /// [Inst = zext Slice to Ty2], only if SliceTy <> Ty2
8760 /// SliceTy is deduced from the number of bits that are actually used to
8762 struct LoadedSlice {
8763 /// \brief Helper structure used to compute the cost of a slice.
8765 /// Are we optimizing for code size.
8770 unsigned CrossRegisterBanksCopies;
8774 Cost(bool ForCodeSize = false)
8775 : ForCodeSize(ForCodeSize), Loads(0), Truncates(0),
8776 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {}
8778 /// \brief Get the cost of one isolated slice.
8779 Cost(const LoadedSlice &LS, bool ForCodeSize = false)
8780 : ForCodeSize(ForCodeSize), Loads(1), Truncates(0),
8781 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {
8782 EVT TruncType = LS.Inst->getValueType(0);
8783 EVT LoadedType = LS.getLoadedType();
8784 if (TruncType != LoadedType &&
8785 !LS.DAG->getTargetLoweringInfo().isZExtFree(LoadedType, TruncType))
8789 /// \brief Account for slicing gain in the current cost.
8790 /// Slicing provide a few gains like removing a shift or a
8791 /// truncate. This method allows to grow the cost of the original
8792 /// load with the gain from this slice.
8793 void addSliceGain(const LoadedSlice &LS) {
8794 // Each slice saves a truncate.
8795 const TargetLowering &TLI = LS.DAG->getTargetLoweringInfo();
8796 if (!TLI.isTruncateFree(LS.Inst->getValueType(0),
8797 LS.Inst->getOperand(0).getValueType()))
8799 // If there is a shift amount, this slice gets rid of it.
8802 // If this slice can merge a cross register bank copy, account for it.
8803 if (LS.canMergeExpensiveCrossRegisterBankCopy())
8804 ++CrossRegisterBanksCopies;
8807 Cost &operator+=(const Cost &RHS) {
8809 Truncates += RHS.Truncates;
8810 CrossRegisterBanksCopies += RHS.CrossRegisterBanksCopies;
8816 bool operator==(const Cost &RHS) const {
8817 return Loads == RHS.Loads && Truncates == RHS.Truncates &&
8818 CrossRegisterBanksCopies == RHS.CrossRegisterBanksCopies &&
8819 ZExts == RHS.ZExts && Shift == RHS.Shift;
8822 bool operator!=(const Cost &RHS) const { return !(*this == RHS); }
8824 bool operator<(const Cost &RHS) const {
8825 // Assume cross register banks copies are as expensive as loads.
8826 // FIXME: Do we want some more target hooks?
8827 unsigned ExpensiveOpsLHS = Loads + CrossRegisterBanksCopies;
8828 unsigned ExpensiveOpsRHS = RHS.Loads + RHS.CrossRegisterBanksCopies;
8829 // Unless we are optimizing for code size, consider the
8830 // expensive operation first.
8831 if (!ForCodeSize && ExpensiveOpsLHS != ExpensiveOpsRHS)
8832 return ExpensiveOpsLHS < ExpensiveOpsRHS;
8833 return (Truncates + ZExts + Shift + ExpensiveOpsLHS) <
8834 (RHS.Truncates + RHS.ZExts + RHS.Shift + ExpensiveOpsRHS);
8837 bool operator>(const Cost &RHS) const { return RHS < *this; }
8839 bool operator<=(const Cost &RHS) const { return !(RHS < *this); }
8841 bool operator>=(const Cost &RHS) const { return !(*this < RHS); }
8843 // The last instruction that represent the slice. This should be a
8844 // truncate instruction.
8846 // The original load instruction.
8848 // The right shift amount in bits from the original load.
8850 // The DAG from which Origin came from.
8851 // This is used to get some contextual information about legal types, etc.
8854 LoadedSlice(SDNode *Inst = nullptr, LoadSDNode *Origin = nullptr,
8855 unsigned Shift = 0, SelectionDAG *DAG = nullptr)
8856 : Inst(Inst), Origin(Origin), Shift(Shift), DAG(DAG) {}
8858 LoadedSlice(const LoadedSlice &LS)
8859 : Inst(LS.Inst), Origin(LS.Origin), Shift(LS.Shift), DAG(LS.DAG) {}
8861 /// \brief Get the bits used in a chunk of bits \p BitWidth large.
8862 /// \return Result is \p BitWidth and has used bits set to 1 and
8863 /// not used bits set to 0.
8864 APInt getUsedBits() const {
8865 // Reproduce the trunc(lshr) sequence:
8866 // - Start from the truncated value.
8867 // - Zero extend to the desired bit width.
8869 assert(Origin && "No original load to compare against.");
8870 unsigned BitWidth = Origin->getValueSizeInBits(0);
8871 assert(Inst && "This slice is not bound to an instruction");
8872 assert(Inst->getValueSizeInBits(0) <= BitWidth &&
8873 "Extracted slice is bigger than the whole type!");
8874 APInt UsedBits(Inst->getValueSizeInBits(0), 0);
8875 UsedBits.setAllBits();
8876 UsedBits = UsedBits.zext(BitWidth);
8881 /// \brief Get the size of the slice to be loaded in bytes.
8882 unsigned getLoadedSize() const {
8883 unsigned SliceSize = getUsedBits().countPopulation();
8884 assert(!(SliceSize & 0x7) && "Size is not a multiple of a byte.");
8885 return SliceSize / 8;
8888 /// \brief Get the type that will be loaded for this slice.
8889 /// Note: This may not be the final type for the slice.
8890 EVT getLoadedType() const {
8891 assert(DAG && "Missing context");
8892 LLVMContext &Ctxt = *DAG->getContext();
8893 return EVT::getIntegerVT(Ctxt, getLoadedSize() * 8);
8896 /// \brief Get the alignment of the load used for this slice.
8897 unsigned getAlignment() const {
8898 unsigned Alignment = Origin->getAlignment();
8899 unsigned Offset = getOffsetFromBase();
8901 Alignment = MinAlign(Alignment, Alignment + Offset);
8905 /// \brief Check if this slice can be rewritten with legal operations.
8906 bool isLegal() const {
8907 // An invalid slice is not legal.
8908 if (!Origin || !Inst || !DAG)
8911 // Offsets are for indexed load only, we do not handle that.
8912 if (Origin->getOffset().getOpcode() != ISD::UNDEF)
8915 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
8917 // Check that the type is legal.
8918 EVT SliceType = getLoadedType();
8919 if (!TLI.isTypeLegal(SliceType))
8922 // Check that the load is legal for this type.
8923 if (!TLI.isOperationLegal(ISD::LOAD, SliceType))
8926 // Check that the offset can be computed.
8927 // 1. Check its type.
8928 EVT PtrType = Origin->getBasePtr().getValueType();
8929 if (PtrType == MVT::Untyped || PtrType.isExtended())
8932 // 2. Check that it fits in the immediate.
8933 if (!TLI.isLegalAddImmediate(getOffsetFromBase()))
8936 // 3. Check that the computation is legal.
8937 if (!TLI.isOperationLegal(ISD::ADD, PtrType))
8940 // Check that the zext is legal if it needs one.
8941 EVT TruncateType = Inst->getValueType(0);
8942 if (TruncateType != SliceType &&
8943 !TLI.isOperationLegal(ISD::ZERO_EXTEND, TruncateType))
8949 /// \brief Get the offset in bytes of this slice in the original chunk of
8951 /// \pre DAG != nullptr.
8952 uint64_t getOffsetFromBase() const {
8953 assert(DAG && "Missing context.");
8955 DAG->getTargetLoweringInfo().getDataLayout()->isBigEndian();
8956 assert(!(Shift & 0x7) && "Shifts not aligned on Bytes are not supported.");
8957 uint64_t Offset = Shift / 8;
8958 unsigned TySizeInBytes = Origin->getValueSizeInBits(0) / 8;
8959 assert(!(Origin->getValueSizeInBits(0) & 0x7) &&
8960 "The size of the original loaded type is not a multiple of a"
8962 // If Offset is bigger than TySizeInBytes, it means we are loading all
8963 // zeros. This should have been optimized before in the process.
8964 assert(TySizeInBytes > Offset &&
8965 "Invalid shift amount for given loaded size");
8967 Offset = TySizeInBytes - Offset - getLoadedSize();
8971 /// \brief Generate the sequence of instructions to load the slice
8972 /// represented by this object and redirect the uses of this slice to
8973 /// this new sequence of instructions.
8974 /// \pre this->Inst && this->Origin are valid Instructions and this
8975 /// object passed the legal check: LoadedSlice::isLegal returned true.
8976 /// \return The last instruction of the sequence used to load the slice.
8977 SDValue loadSlice() const {
8978 assert(Inst && Origin && "Unable to replace a non-existing slice.");
8979 const SDValue &OldBaseAddr = Origin->getBasePtr();
8980 SDValue BaseAddr = OldBaseAddr;
8981 // Get the offset in that chunk of bytes w.r.t. the endianess.
8982 int64_t Offset = static_cast<int64_t>(getOffsetFromBase());
8983 assert(Offset >= 0 && "Offset too big to fit in int64_t!");
8985 // BaseAddr = BaseAddr + Offset.
8986 EVT ArithType = BaseAddr.getValueType();
8987 BaseAddr = DAG->getNode(ISD::ADD, SDLoc(Origin), ArithType, BaseAddr,
8988 DAG->getConstant(Offset, ArithType));
8991 // Create the type of the loaded slice according to its size.
8992 EVT SliceType = getLoadedType();
8994 // Create the load for the slice.
8995 SDValue LastInst = DAG->getLoad(
8996 SliceType, SDLoc(Origin), Origin->getChain(), BaseAddr,
8997 Origin->getPointerInfo().getWithOffset(Offset), Origin->isVolatile(),
8998 Origin->isNonTemporal(), Origin->isInvariant(), getAlignment());
8999 // If the final type is not the same as the loaded type, this means that
9000 // we have to pad with zero. Create a zero extend for that.
9001 EVT FinalType = Inst->getValueType(0);
9002 if (SliceType != FinalType)
9004 DAG->getNode(ISD::ZERO_EXTEND, SDLoc(LastInst), FinalType, LastInst);
9008 /// \brief Check if this slice can be merged with an expensive cross register
9009 /// bank copy. E.g.,
9011 /// f = bitcast i32 i to float
9012 bool canMergeExpensiveCrossRegisterBankCopy() const {
9013 if (!Inst || !Inst->hasOneUse())
9015 SDNode *Use = *Inst->use_begin();
9016 if (Use->getOpcode() != ISD::BITCAST)
9018 assert(DAG && "Missing context");
9019 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
9020 EVT ResVT = Use->getValueType(0);
9021 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT());
9022 const TargetRegisterClass *ArgRC =
9023 TLI.getRegClassFor(Use->getOperand(0).getValueType().getSimpleVT());
9024 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT))
9027 // At this point, we know that we perform a cross-register-bank copy.
9028 // Check if it is expensive.
9029 const TargetRegisterInfo *TRI = DAG->getSubtarget().getRegisterInfo();
9030 // Assume bitcasts are cheap, unless both register classes do not
9031 // explicitly share a common sub class.
9032 if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC))
9035 // Check if it will be merged with the load.
9036 // 1. Check the alignment constraint.
9037 unsigned RequiredAlignment = TLI.getDataLayout()->getABITypeAlignment(
9038 ResVT.getTypeForEVT(*DAG->getContext()));
9040 if (RequiredAlignment > getAlignment())
9043 // 2. Check that the load is a legal operation for that type.
9044 if (!TLI.isOperationLegal(ISD::LOAD, ResVT))
9047 // 3. Check that we do not have a zext in the way.
9048 if (Inst->getValueType(0) != getLoadedType())
9056 /// \brief Check that all bits set in \p UsedBits form a dense region, i.e.,
9057 /// \p UsedBits looks like 0..0 1..1 0..0.
9058 static bool areUsedBitsDense(const APInt &UsedBits) {
9059 // If all the bits are one, this is dense!
9060 if (UsedBits.isAllOnesValue())
9063 // Get rid of the unused bits on the right.
9064 APInt NarrowedUsedBits = UsedBits.lshr(UsedBits.countTrailingZeros());
9065 // Get rid of the unused bits on the left.
9066 if (NarrowedUsedBits.countLeadingZeros())
9067 NarrowedUsedBits = NarrowedUsedBits.trunc(NarrowedUsedBits.getActiveBits());
9068 // Check that the chunk of bits is completely used.
9069 return NarrowedUsedBits.isAllOnesValue();
9072 /// \brief Check whether or not \p First and \p Second are next to each other
9073 /// in memory. This means that there is no hole between the bits loaded
9074 /// by \p First and the bits loaded by \p Second.
9075 static bool areSlicesNextToEachOther(const LoadedSlice &First,
9076 const LoadedSlice &Second) {
9077 assert(First.Origin == Second.Origin && First.Origin &&
9078 "Unable to match different memory origins.");
9079 APInt UsedBits = First.getUsedBits();
9080 assert((UsedBits & Second.getUsedBits()) == 0 &&
9081 "Slices are not supposed to overlap.");
9082 UsedBits |= Second.getUsedBits();
9083 return areUsedBitsDense(UsedBits);
9086 /// \brief Adjust the \p GlobalLSCost according to the target
9087 /// paring capabilities and the layout of the slices.
9088 /// \pre \p GlobalLSCost should account for at least as many loads as
9089 /// there is in the slices in \p LoadedSlices.
9090 static void adjustCostForPairing(SmallVectorImpl<LoadedSlice> &LoadedSlices,
9091 LoadedSlice::Cost &GlobalLSCost) {
9092 unsigned NumberOfSlices = LoadedSlices.size();
9093 // If there is less than 2 elements, no pairing is possible.
9094 if (NumberOfSlices < 2)
9097 // Sort the slices so that elements that are likely to be next to each
9098 // other in memory are next to each other in the list.
9099 std::sort(LoadedSlices.begin(), LoadedSlices.end(),
9100 [](const LoadedSlice &LHS, const LoadedSlice &RHS) {
9101 assert(LHS.Origin == RHS.Origin && "Different bases not implemented.");
9102 return LHS.getOffsetFromBase() < RHS.getOffsetFromBase();
9104 const TargetLowering &TLI = LoadedSlices[0].DAG->getTargetLoweringInfo();
9105 // First (resp. Second) is the first (resp. Second) potentially candidate
9106 // to be placed in a paired load.
9107 const LoadedSlice *First = nullptr;
9108 const LoadedSlice *Second = nullptr;
9109 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice,
9110 // Set the beginning of the pair.
9113 Second = &LoadedSlices[CurrSlice];
9115 // If First is NULL, it means we start a new pair.
9116 // Get to the next slice.
9120 EVT LoadedType = First->getLoadedType();
9122 // If the types of the slices are different, we cannot pair them.
9123 if (LoadedType != Second->getLoadedType())
9126 // Check if the target supplies paired loads for this type.
9127 unsigned RequiredAlignment = 0;
9128 if (!TLI.hasPairedLoad(LoadedType, RequiredAlignment)) {
9129 // move to the next pair, this type is hopeless.
9133 // Check if we meet the alignment requirement.
9134 if (RequiredAlignment > First->getAlignment())
9137 // Check that both loads are next to each other in memory.
9138 if (!areSlicesNextToEachOther(*First, *Second))
9141 assert(GlobalLSCost.Loads > 0 && "We save more loads than we created!");
9142 --GlobalLSCost.Loads;
9143 // Move to the next pair.
9148 /// \brief Check the profitability of all involved LoadedSlice.
9149 /// Currently, it is considered profitable if there is exactly two
9150 /// involved slices (1) which are (2) next to each other in memory, and
9151 /// whose cost (\see LoadedSlice::Cost) is smaller than the original load (3).
9153 /// Note: The order of the elements in \p LoadedSlices may be modified, but not
9154 /// the elements themselves.
9156 /// FIXME: When the cost model will be mature enough, we can relax
9157 /// constraints (1) and (2).
9158 static bool isSlicingProfitable(SmallVectorImpl<LoadedSlice> &LoadedSlices,
9159 const APInt &UsedBits, bool ForCodeSize) {
9160 unsigned NumberOfSlices = LoadedSlices.size();
9161 if (StressLoadSlicing)
9162 return NumberOfSlices > 1;
9165 if (NumberOfSlices != 2)
9169 if (!areUsedBitsDense(UsedBits))
9173 LoadedSlice::Cost OrigCost(ForCodeSize), GlobalSlicingCost(ForCodeSize);
9174 // The original code has one big load.
9176 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice) {
9177 const LoadedSlice &LS = LoadedSlices[CurrSlice];
9178 // Accumulate the cost of all the slices.
9179 LoadedSlice::Cost SliceCost(LS, ForCodeSize);
9180 GlobalSlicingCost += SliceCost;
9182 // Account as cost in the original configuration the gain obtained
9183 // with the current slices.
9184 OrigCost.addSliceGain(LS);
9187 // If the target supports paired load, adjust the cost accordingly.
9188 adjustCostForPairing(LoadedSlices, GlobalSlicingCost);
9189 return OrigCost > GlobalSlicingCost;
9192 /// \brief If the given load, \p LI, is used only by trunc or trunc(lshr)
9193 /// operations, split it in the various pieces being extracted.
9195 /// This sort of thing is introduced by SROA.
9196 /// This slicing takes care not to insert overlapping loads.
9197 /// \pre LI is a simple load (i.e., not an atomic or volatile load).
9198 bool DAGCombiner::SliceUpLoad(SDNode *N) {
9199 if (Level < AfterLegalizeDAG)
9202 LoadSDNode *LD = cast<LoadSDNode>(N);
9203 if (LD->isVolatile() || !ISD::isNormalLoad(LD) ||
9204 !LD->getValueType(0).isInteger())
9207 // Keep track of already used bits to detect overlapping values.
9208 // In that case, we will just abort the transformation.
9209 APInt UsedBits(LD->getValueSizeInBits(0), 0);
9211 SmallVector<LoadedSlice, 4> LoadedSlices;
9213 // Check if this load is used as several smaller chunks of bits.
9214 // Basically, look for uses in trunc or trunc(lshr) and record a new chain
9215 // of computation for each trunc.
9216 for (SDNode::use_iterator UI = LD->use_begin(), UIEnd = LD->use_end();
9217 UI != UIEnd; ++UI) {
9218 // Skip the uses of the chain.
9219 if (UI.getUse().getResNo() != 0)
9225 // Check if this is a trunc(lshr).
9226 if (User->getOpcode() == ISD::SRL && User->hasOneUse() &&
9227 isa<ConstantSDNode>(User->getOperand(1))) {
9228 Shift = cast<ConstantSDNode>(User->getOperand(1))->getZExtValue();
9229 User = *User->use_begin();
9232 // At this point, User is a Truncate, iff we encountered, trunc or
9234 if (User->getOpcode() != ISD::TRUNCATE)
9237 // The width of the type must be a power of 2 and greater than 8-bits.
9238 // Otherwise the load cannot be represented in LLVM IR.
9239 // Moreover, if we shifted with a non-8-bits multiple, the slice
9240 // will be across several bytes. We do not support that.
9241 unsigned Width = User->getValueSizeInBits(0);
9242 if (Width < 8 || !isPowerOf2_32(Width) || (Shift & 0x7))
9245 // Build the slice for this chain of computations.
9246 LoadedSlice LS(User, LD, Shift, &DAG);
9247 APInt CurrentUsedBits = LS.getUsedBits();
9249 // Check if this slice overlaps with another.
9250 if ((CurrentUsedBits & UsedBits) != 0)
9252 // Update the bits used globally.
9253 UsedBits |= CurrentUsedBits;
9255 // Check if the new slice would be legal.
9259 // Record the slice.
9260 LoadedSlices.push_back(LS);
9263 // Abort slicing if it does not seem to be profitable.
9264 if (!isSlicingProfitable(LoadedSlices, UsedBits, ForCodeSize))
9269 // Rewrite each chain to use an independent load.
9270 // By construction, each chain can be represented by a unique load.
9272 // Prepare the argument for the new token factor for all the slices.
9273 SmallVector<SDValue, 8> ArgChains;
9274 for (SmallVectorImpl<LoadedSlice>::const_iterator
9275 LSIt = LoadedSlices.begin(),
9276 LSItEnd = LoadedSlices.end();
9277 LSIt != LSItEnd; ++LSIt) {
9278 SDValue SliceInst = LSIt->loadSlice();
9279 CombineTo(LSIt->Inst, SliceInst, true);
9280 if (SliceInst.getNode()->getOpcode() != ISD::LOAD)
9281 SliceInst = SliceInst.getOperand(0);
9282 assert(SliceInst->getOpcode() == ISD::LOAD &&
9283 "It takes more than a zext to get to the loaded slice!!");
9284 ArgChains.push_back(SliceInst.getValue(1));
9287 SDValue Chain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other,
9289 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
9293 /// Check to see if V is (and load (ptr), imm), where the load is having
9294 /// specific bytes cleared out. If so, return the byte size being masked out
9295 /// and the shift amount.
9296 static std::pair<unsigned, unsigned>
9297 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
9298 std::pair<unsigned, unsigned> Result(0, 0);
9300 // Check for the structure we're looking for.
9301 if (V->getOpcode() != ISD::AND ||
9302 !isa<ConstantSDNode>(V->getOperand(1)) ||
9303 !ISD::isNormalLoad(V->getOperand(0).getNode()))
9306 // Check the chain and pointer.
9307 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
9308 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
9310 // The store should be chained directly to the load or be an operand of a
9312 if (LD == Chain.getNode())
9314 else if (Chain->getOpcode() != ISD::TokenFactor)
9315 return Result; // Fail.
9318 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
9319 if (Chain->getOperand(i).getNode() == LD) {
9323 if (!isOk) return Result;
9326 // This only handles simple types.
9327 if (V.getValueType() != MVT::i16 &&
9328 V.getValueType() != MVT::i32 &&
9329 V.getValueType() != MVT::i64)
9332 // Check the constant mask. Invert it so that the bits being masked out are
9333 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
9334 // follow the sign bit for uniformity.
9335 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
9336 unsigned NotMaskLZ = countLeadingZeros(NotMask);
9337 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
9338 unsigned NotMaskTZ = countTrailingZeros(NotMask);
9339 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
9340 if (NotMaskLZ == 64) return Result; // All zero mask.
9342 // See if we have a continuous run of bits. If so, we have 0*1+0*
9343 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
9346 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
9347 if (V.getValueType() != MVT::i64 && NotMaskLZ)
9348 NotMaskLZ -= 64-V.getValueSizeInBits();
9350 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
9351 switch (MaskedBytes) {
9355 default: return Result; // All one mask, or 5-byte mask.
9358 // Verify that the first bit starts at a multiple of mask so that the access
9359 // is aligned the same as the access width.
9360 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
9362 Result.first = MaskedBytes;
9363 Result.second = NotMaskTZ/8;
9368 /// Check to see if IVal is something that provides a value as specified by
9369 /// MaskInfo. If so, replace the specified store with a narrower store of
9372 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
9373 SDValue IVal, StoreSDNode *St,
9375 unsigned NumBytes = MaskInfo.first;
9376 unsigned ByteShift = MaskInfo.second;
9377 SelectionDAG &DAG = DC->getDAG();
9379 // Check to see if IVal is all zeros in the part being masked in by the 'or'
9380 // that uses this. If not, this is not a replacement.
9381 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
9382 ByteShift*8, (ByteShift+NumBytes)*8);
9383 if (!DAG.MaskedValueIsZero(IVal, Mask)) return nullptr;
9385 // Check that it is legal on the target to do this. It is legal if the new
9386 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
9388 MVT VT = MVT::getIntegerVT(NumBytes*8);
9389 if (!DC->isTypeLegal(VT))
9392 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
9393 // shifted by ByteShift and truncated down to NumBytes.
9395 IVal = DAG.getNode(ISD::SRL, SDLoc(IVal), IVal.getValueType(), IVal,
9396 DAG.getConstant(ByteShift*8,
9397 DC->getShiftAmountTy(IVal.getValueType())));
9399 // Figure out the offset for the store and the alignment of the access.
9401 unsigned NewAlign = St->getAlignment();
9403 if (DAG.getTargetLoweringInfo().isLittleEndian())
9404 StOffset = ByteShift;
9406 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
9408 SDValue Ptr = St->getBasePtr();
9410 Ptr = DAG.getNode(ISD::ADD, SDLoc(IVal), Ptr.getValueType(),
9411 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
9412 NewAlign = MinAlign(NewAlign, StOffset);
9415 // Truncate down to the new size.
9416 IVal = DAG.getNode(ISD::TRUNCATE, SDLoc(IVal), VT, IVal);
9419 return DAG.getStore(St->getChain(), SDLoc(St), IVal, Ptr,
9420 St->getPointerInfo().getWithOffset(StOffset),
9421 false, false, NewAlign).getNode();
9425 /// Look for sequence of load / op / store where op is one of 'or', 'xor', and
9426 /// 'and' of immediates. If 'op' is only touching some of the loaded bits, try
9427 /// narrowing the load and store if it would end up being a win for performance
9429 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
9430 StoreSDNode *ST = cast<StoreSDNode>(N);
9431 if (ST->isVolatile())
9434 SDValue Chain = ST->getChain();
9435 SDValue Value = ST->getValue();
9436 SDValue Ptr = ST->getBasePtr();
9437 EVT VT = Value.getValueType();
9439 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
9442 unsigned Opc = Value.getOpcode();
9444 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
9445 // is a byte mask indicating a consecutive number of bytes, check to see if
9446 // Y is known to provide just those bytes. If so, we try to replace the
9447 // load + replace + store sequence with a single (narrower) store, which makes
9449 if (Opc == ISD::OR) {
9450 std::pair<unsigned, unsigned> MaskedLoad;
9451 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
9452 if (MaskedLoad.first)
9453 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
9454 Value.getOperand(1), ST,this))
9455 return SDValue(NewST, 0);
9457 // Or is commutative, so try swapping X and Y.
9458 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
9459 if (MaskedLoad.first)
9460 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
9461 Value.getOperand(0), ST,this))
9462 return SDValue(NewST, 0);
9465 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
9466 Value.getOperand(1).getOpcode() != ISD::Constant)
9469 SDValue N0 = Value.getOperand(0);
9470 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
9471 Chain == SDValue(N0.getNode(), 1)) {
9472 LoadSDNode *LD = cast<LoadSDNode>(N0);
9473 if (LD->getBasePtr() != Ptr ||
9474 LD->getPointerInfo().getAddrSpace() !=
9475 ST->getPointerInfo().getAddrSpace())
9478 // Find the type to narrow it the load / op / store to.
9479 SDValue N1 = Value.getOperand(1);
9480 unsigned BitWidth = N1.getValueSizeInBits();
9481 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
9482 if (Opc == ISD::AND)
9483 Imm ^= APInt::getAllOnesValue(BitWidth);
9484 if (Imm == 0 || Imm.isAllOnesValue())
9486 unsigned ShAmt = Imm.countTrailingZeros();
9487 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
9488 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
9489 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
9490 while (NewBW < BitWidth &&
9491 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
9492 TLI.isNarrowingProfitable(VT, NewVT))) {
9493 NewBW = NextPowerOf2(NewBW);
9494 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
9496 if (NewBW >= BitWidth)
9499 // If the lsb changed does not start at the type bitwidth boundary,
9500 // start at the previous one.
9502 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
9503 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt,
9504 std::min(BitWidth, ShAmt + NewBW));
9505 if ((Imm & Mask) == Imm) {
9506 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
9507 if (Opc == ISD::AND)
9508 NewImm ^= APInt::getAllOnesValue(NewBW);
9509 uint64_t PtrOff = ShAmt / 8;
9510 // For big endian targets, we need to adjust the offset to the pointer to
9511 // load the correct bytes.
9512 if (TLI.isBigEndian())
9513 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
9515 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
9516 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
9517 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy))
9520 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LD),
9521 Ptr.getValueType(), Ptr,
9522 DAG.getConstant(PtrOff, Ptr.getValueType()));
9523 SDValue NewLD = DAG.getLoad(NewVT, SDLoc(N0),
9524 LD->getChain(), NewPtr,
9525 LD->getPointerInfo().getWithOffset(PtrOff),
9526 LD->isVolatile(), LD->isNonTemporal(),
9527 LD->isInvariant(), NewAlign,
9529 SDValue NewVal = DAG.getNode(Opc, SDLoc(Value), NewVT, NewLD,
9530 DAG.getConstant(NewImm, NewVT));
9531 SDValue NewST = DAG.getStore(Chain, SDLoc(N),
9533 ST->getPointerInfo().getWithOffset(PtrOff),
9534 false, false, NewAlign);
9536 AddToWorklist(NewPtr.getNode());
9537 AddToWorklist(NewLD.getNode());
9538 AddToWorklist(NewVal.getNode());
9539 WorklistRemover DeadNodes(*this);
9540 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
9549 /// For a given floating point load / store pair, if the load value isn't used
9550 /// by any other operations, then consider transforming the pair to integer
9551 /// load / store operations if the target deems the transformation profitable.
9552 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
9553 StoreSDNode *ST = cast<StoreSDNode>(N);
9554 SDValue Chain = ST->getChain();
9555 SDValue Value = ST->getValue();
9556 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
9557 Value.hasOneUse() &&
9558 Chain == SDValue(Value.getNode(), 1)) {
9559 LoadSDNode *LD = cast<LoadSDNode>(Value);
9560 EVT VT = LD->getMemoryVT();
9561 if (!VT.isFloatingPoint() ||
9562 VT != ST->getMemoryVT() ||
9563 LD->isNonTemporal() ||
9564 ST->isNonTemporal() ||
9565 LD->getPointerInfo().getAddrSpace() != 0 ||
9566 ST->getPointerInfo().getAddrSpace() != 0)
9569 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
9570 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
9571 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
9572 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
9573 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
9576 unsigned LDAlign = LD->getAlignment();
9577 unsigned STAlign = ST->getAlignment();
9578 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
9579 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy);
9580 if (LDAlign < ABIAlign || STAlign < ABIAlign)
9583 SDValue NewLD = DAG.getLoad(IntVT, SDLoc(Value),
9584 LD->getChain(), LD->getBasePtr(),
9585 LD->getPointerInfo(),
9586 false, false, false, LDAlign);
9588 SDValue NewST = DAG.getStore(NewLD.getValue(1), SDLoc(N),
9589 NewLD, ST->getBasePtr(),
9590 ST->getPointerInfo(),
9591 false, false, STAlign);
9593 AddToWorklist(NewLD.getNode());
9594 AddToWorklist(NewST.getNode());
9595 WorklistRemover DeadNodes(*this);
9596 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1));
9604 /// Helper struct to parse and store a memory address as base + index + offset.
9605 /// We ignore sign extensions when it is safe to do so.
9606 /// The following two expressions are not equivalent. To differentiate we need
9607 /// to store whether there was a sign extension involved in the index
9609 /// (load (i64 add (i64 copyfromreg %c)
9610 /// (i64 signextend (add (i8 load %index)
9614 /// (load (i64 add (i64 copyfromreg %c)
9615 /// (i64 signextend (i32 add (i32 signextend (i8 load %index))
9617 struct BaseIndexOffset {
9621 bool IsIndexSignExt;
9623 BaseIndexOffset() : Offset(0), IsIndexSignExt(false) {}
9625 BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset,
9626 bool IsIndexSignExt) :
9627 Base(Base), Index(Index), Offset(Offset), IsIndexSignExt(IsIndexSignExt) {}
9629 bool equalBaseIndex(const BaseIndexOffset &Other) {
9630 return Other.Base == Base && Other.Index == Index &&
9631 Other.IsIndexSignExt == IsIndexSignExt;
9634 /// Parses tree in Ptr for base, index, offset addresses.
9635 static BaseIndexOffset match(SDValue Ptr) {
9636 bool IsIndexSignExt = false;
9638 // We only can pattern match BASE + INDEX + OFFSET. If Ptr is not an ADD
9639 // instruction, then it could be just the BASE or everything else we don't
9640 // know how to handle. Just use Ptr as BASE and give up.
9641 if (Ptr->getOpcode() != ISD::ADD)
9642 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
9644 // We know that we have at least an ADD instruction. Try to pattern match
9645 // the simple case of BASE + OFFSET.
9646 if (isa<ConstantSDNode>(Ptr->getOperand(1))) {
9647 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
9648 return BaseIndexOffset(Ptr->getOperand(0), SDValue(), Offset,
9652 // Inside a loop the current BASE pointer is calculated using an ADD and a
9653 // MUL instruction. In this case Ptr is the actual BASE pointer.
9654 // (i64 add (i64 %array_ptr)
9655 // (i64 mul (i64 %induction_var)
9656 // (i64 %element_size)))
9657 if (Ptr->getOperand(1)->getOpcode() == ISD::MUL)
9658 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
9660 // Look at Base + Index + Offset cases.
9661 SDValue Base = Ptr->getOperand(0);
9662 SDValue IndexOffset = Ptr->getOperand(1);
9664 // Skip signextends.
9665 if (IndexOffset->getOpcode() == ISD::SIGN_EXTEND) {
9666 IndexOffset = IndexOffset->getOperand(0);
9667 IsIndexSignExt = true;
9670 // Either the case of Base + Index (no offset) or something else.
9671 if (IndexOffset->getOpcode() != ISD::ADD)
9672 return BaseIndexOffset(Base, IndexOffset, 0, IsIndexSignExt);
9674 // Now we have the case of Base + Index + offset.
9675 SDValue Index = IndexOffset->getOperand(0);
9676 SDValue Offset = IndexOffset->getOperand(1);
9678 if (!isa<ConstantSDNode>(Offset))
9679 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
9681 // Ignore signextends.
9682 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
9683 Index = Index->getOperand(0);
9684 IsIndexSignExt = true;
9685 } else IsIndexSignExt = false;
9687 int64_t Off = cast<ConstantSDNode>(Offset)->getSExtValue();
9688 return BaseIndexOffset(Base, Index, Off, IsIndexSignExt);
9692 /// Holds a pointer to an LSBaseSDNode as well as information on where it
9693 /// is located in a sequence of memory operations connected by a chain.
9695 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq):
9696 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { }
9697 // Ptr to the mem node.
9698 LSBaseSDNode *MemNode;
9699 // Offset from the base ptr.
9700 int64_t OffsetFromBase;
9701 // What is the sequence number of this mem node.
9702 // Lowest mem operand in the DAG starts at zero.
9703 unsigned SequenceNum;
9706 bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
9707 EVT MemVT = St->getMemoryVT();
9708 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8;
9709 bool NoVectors = DAG.getMachineFunction().getFunction()->getAttributes().
9710 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
9712 // Don't merge vectors into wider inputs.
9713 if (MemVT.isVector() || !MemVT.isSimple())
9716 // Perform an early exit check. Do not bother looking at stored values that
9717 // are not constants or loads.
9718 SDValue StoredVal = St->getValue();
9719 bool IsLoadSrc = isa<LoadSDNode>(StoredVal);
9720 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) &&
9724 // Only look at ends of store sequences.
9725 SDValue Chain = SDValue(St, 0);
9726 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE)
9729 // This holds the base pointer, index, and the offset in bytes from the base
9731 BaseIndexOffset BasePtr = BaseIndexOffset::match(St->getBasePtr());
9733 // We must have a base and an offset.
9734 if (!BasePtr.Base.getNode())
9737 // Do not handle stores to undef base pointers.
9738 if (BasePtr.Base.getOpcode() == ISD::UNDEF)
9741 // Save the LoadSDNodes that we find in the chain.
9742 // We need to make sure that these nodes do not interfere with
9743 // any of the store nodes.
9744 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes;
9746 // Save the StoreSDNodes that we find in the chain.
9747 SmallVector<MemOpLink, 8> StoreNodes;
9749 // Walk up the chain and look for nodes with offsets from the same
9750 // base pointer. Stop when reaching an instruction with a different kind
9751 // or instruction which has a different base pointer.
9753 StoreSDNode *Index = St;
9755 // If the chain has more than one use, then we can't reorder the mem ops.
9756 if (Index != St && !SDValue(Index, 0)->hasOneUse())
9759 // Find the base pointer and offset for this memory node.
9760 BaseIndexOffset Ptr = BaseIndexOffset::match(Index->getBasePtr());
9762 // Check that the base pointer is the same as the original one.
9763 if (!Ptr.equalBaseIndex(BasePtr))
9766 // Check that the alignment is the same.
9767 if (Index->getAlignment() != St->getAlignment())
9770 // The memory operands must not be volatile.
9771 if (Index->isVolatile() || Index->isIndexed())
9775 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index))
9776 if (St->isTruncatingStore())
9779 // The stored memory type must be the same.
9780 if (Index->getMemoryVT() != MemVT)
9783 // We do not allow unaligned stores because we want to prevent overriding
9785 if (Index->getAlignment()*8 != MemVT.getSizeInBits())
9788 // We found a potential memory operand to merge.
9789 StoreNodes.push_back(MemOpLink(Index, Ptr.Offset, Seq++));
9791 // Find the next memory operand in the chain. If the next operand in the
9792 // chain is a store then move up and continue the scan with the next
9793 // memory operand. If the next operand is a load save it and use alias
9794 // information to check if it interferes with anything.
9795 SDNode *NextInChain = Index->getChain().getNode();
9797 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) {
9798 // We found a store node. Use it for the next iteration.
9801 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) {
9802 if (Ldn->isVolatile()) {
9807 // Save the load node for later. Continue the scan.
9808 AliasLoadNodes.push_back(Ldn);
9809 NextInChain = Ldn->getChain().getNode();
9818 // Check if there is anything to merge.
9819 if (StoreNodes.size() < 2)
9822 // Sort the memory operands according to their distance from the base pointer.
9823 std::sort(StoreNodes.begin(), StoreNodes.end(),
9824 [](MemOpLink LHS, MemOpLink RHS) {
9825 return LHS.OffsetFromBase < RHS.OffsetFromBase ||
9826 (LHS.OffsetFromBase == RHS.OffsetFromBase &&
9827 LHS.SequenceNum > RHS.SequenceNum);
9830 // Scan the memory operations on the chain and find the first non-consecutive
9831 // store memory address.
9832 unsigned LastConsecutiveStore = 0;
9833 int64_t StartAddress = StoreNodes[0].OffsetFromBase;
9834 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) {
9836 // Check that the addresses are consecutive starting from the second
9837 // element in the list of stores.
9839 int64_t CurrAddress = StoreNodes[i].OffsetFromBase;
9840 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
9845 // Check if this store interferes with any of the loads that we found.
9846 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld)
9847 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) {
9851 // We found a load that alias with this store. Stop the sequence.
9855 // Mark this node as useful.
9856 LastConsecutiveStore = i;
9859 // The node with the lowest store address.
9860 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;
9862 // Store the constants into memory as one consecutive store.
9864 unsigned LastLegalType = 0;
9865 unsigned LastLegalVectorType = 0;
9866 bool NonZero = false;
9867 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
9868 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
9869 SDValue StoredVal = St->getValue();
9871 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) {
9872 NonZero |= !C->isNullValue();
9873 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) {
9874 NonZero |= !C->getConstantFPValue()->isNullValue();
9880 // Find a legal type for the constant store.
9881 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
9882 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
9883 if (TLI.isTypeLegal(StoreTy))
9884 LastLegalType = i+1;
9885 // Or check whether a truncstore is legal.
9886 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) ==
9887 TargetLowering::TypePromoteInteger) {
9888 EVT LegalizedStoredValueTy =
9889 TLI.getTypeToTransformTo(*DAG.getContext(), StoredVal.getValueType());
9890 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy))
9891 LastLegalType = i+1;
9894 // Find a legal type for the vector store.
9895 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
9896 if (TLI.isTypeLegal(Ty))
9897 LastLegalVectorType = i + 1;
9900 // We only use vectors if the constant is known to be zero and the
9901 // function is not marked with the noimplicitfloat attribute.
9902 if (NonZero || NoVectors)
9903 LastLegalVectorType = 0;
9905 // Check if we found a legal integer type to store.
9906 if (LastLegalType == 0 && LastLegalVectorType == 0)
9909 bool UseVector = (LastLegalVectorType > LastLegalType) && !NoVectors;
9910 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType;
9912 // Make sure we have something to merge.
9916 unsigned EarliestNodeUsed = 0;
9917 for (unsigned i=0; i < NumElem; ++i) {
9918 // Find a chain for the new wide-store operand. Notice that some
9919 // of the store nodes that we found may not be selected for inclusion
9920 // in the wide store. The chain we use needs to be the chain of the
9921 // earliest store node which is *used* and replaced by the wide store.
9922 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
9923 EarliestNodeUsed = i;
9926 // The earliest Node in the DAG.
9927 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
9928 SDLoc DL(StoreNodes[0].MemNode);
9932 // Find a legal type for the vector store.
9933 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
9934 assert(TLI.isTypeLegal(Ty) && "Illegal vector store");
9935 StoredVal = DAG.getConstant(0, Ty);
9937 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
9938 APInt StoreInt(StoreBW, 0);
9940 // Construct a single integer constant which is made of the smaller
9942 bool IsLE = TLI.isLittleEndian();
9943 for (unsigned i = 0; i < NumElem ; ++i) {
9944 unsigned Idx = IsLE ?(NumElem - 1 - i) : i;
9945 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode);
9946 SDValue Val = St->getValue();
9947 StoreInt<<=ElementSizeBytes*8;
9948 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) {
9949 StoreInt|=C->getAPIntValue().zext(StoreBW);
9950 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) {
9951 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW);
9953 llvm_unreachable("Invalid constant element type");
9957 // Create the new Load and Store operations.
9958 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
9959 StoredVal = DAG.getConstant(StoreInt, StoreTy);
9962 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal,
9963 FirstInChain->getBasePtr(),
9964 FirstInChain->getPointerInfo(),
9966 FirstInChain->getAlignment());
9968 // Replace the first store with the new store
9969 CombineTo(EarliestOp, NewStore);
9970 // Erase all other stores.
9971 for (unsigned i = 0; i < NumElem ; ++i) {
9972 if (StoreNodes[i].MemNode == EarliestOp)
9974 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
9975 // ReplaceAllUsesWith will replace all uses that existed when it was
9976 // called, but graph optimizations may cause new ones to appear. For
9977 // example, the case in pr14333 looks like
9979 // St's chain -> St -> another store -> X
9981 // And the only difference from St to the other store is the chain.
9982 // When we change it's chain to be St's chain they become identical,
9983 // get CSEed and the net result is that X is now a use of St.
9984 // Since we know that St is redundant, just iterate.
9985 while (!St->use_empty())
9986 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain());
9987 deleteAndRecombine(St);
9993 // Below we handle the case of multiple consecutive stores that
9994 // come from multiple consecutive loads. We merge them into a single
9995 // wide load and a single wide store.
9997 // Look for load nodes which are used by the stored values.
9998 SmallVector<MemOpLink, 8> LoadNodes;
10000 // Find acceptable loads. Loads need to have the same chain (token factor),
10001 // must not be zext, volatile, indexed, and they must be consecutive.
10002 BaseIndexOffset LdBasePtr;
10003 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
10004 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
10005 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue());
10008 // Loads must only have one use.
10009 if (!Ld->hasNUsesOfValue(1, 0))
10012 // Check that the alignment is the same as the stores.
10013 if (Ld->getAlignment() != St->getAlignment())
10016 // The memory operands must not be volatile.
10017 if (Ld->isVolatile() || Ld->isIndexed())
10020 // We do not accept ext loads.
10021 if (Ld->getExtensionType() != ISD::NON_EXTLOAD)
10024 // The stored memory type must be the same.
10025 if (Ld->getMemoryVT() != MemVT)
10028 BaseIndexOffset LdPtr = BaseIndexOffset::match(Ld->getBasePtr());
10029 // If this is not the first ptr that we check.
10030 if (LdBasePtr.Base.getNode()) {
10031 // The base ptr must be the same.
10032 if (!LdPtr.equalBaseIndex(LdBasePtr))
10035 // Check that all other base pointers are the same as this one.
10039 // We found a potential memory operand to merge.
10040 LoadNodes.push_back(MemOpLink(Ld, LdPtr.Offset, 0));
10043 if (LoadNodes.size() < 2)
10046 // If we have load/store pair instructions and we only have two values,
10048 unsigned RequiredAlignment;
10049 if (LoadNodes.size() == 2 && TLI.hasPairedLoad(MemVT, RequiredAlignment) &&
10050 St->getAlignment() >= RequiredAlignment)
10053 // Scan the memory operations on the chain and find the first non-consecutive
10054 // load memory address. These variables hold the index in the store node
10056 unsigned LastConsecutiveLoad = 0;
10057 // This variable refers to the size and not index in the array.
10058 unsigned LastLegalVectorType = 0;
10059 unsigned LastLegalIntegerType = 0;
10060 StartAddress = LoadNodes[0].OffsetFromBase;
10061 SDValue FirstChain = LoadNodes[0].MemNode->getChain();
10062 for (unsigned i = 1; i < LoadNodes.size(); ++i) {
10063 // All loads much share the same chain.
10064 if (LoadNodes[i].MemNode->getChain() != FirstChain)
10067 int64_t CurrAddress = LoadNodes[i].OffsetFromBase;
10068 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
10070 LastConsecutiveLoad = i;
10072 // Find a legal type for the vector store.
10073 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
10074 if (TLI.isTypeLegal(StoreTy))
10075 LastLegalVectorType = i + 1;
10077 // Find a legal type for the integer store.
10078 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
10079 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
10080 if (TLI.isTypeLegal(StoreTy))
10081 LastLegalIntegerType = i + 1;
10082 // Or check whether a truncstore and extload is legal.
10083 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) ==
10084 TargetLowering::TypePromoteInteger) {
10085 EVT LegalizedStoredValueTy =
10086 TLI.getTypeToTransformTo(*DAG.getContext(), StoreTy);
10087 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) &&
10088 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LegalizedStoredValueTy, StoreTy) &&
10089 TLI.isLoadExtLegal(ISD::SEXTLOAD, LegalizedStoredValueTy, StoreTy) &&
10090 TLI.isLoadExtLegal(ISD::EXTLOAD, LegalizedStoredValueTy, StoreTy))
10091 LastLegalIntegerType = i+1;
10095 // Only use vector types if the vector type is larger than the integer type.
10096 // If they are the same, use integers.
10097 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType && !NoVectors;
10098 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType);
10100 // We add +1 here because the LastXXX variables refer to location while
10101 // the NumElem refers to array/index size.
10102 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1;
10103 NumElem = std::min(LastLegalType, NumElem);
10108 // The earliest Node in the DAG.
10109 unsigned EarliestNodeUsed = 0;
10110 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
10111 for (unsigned i=1; i<NumElem; ++i) {
10112 // Find a chain for the new wide-store operand. Notice that some
10113 // of the store nodes that we found may not be selected for inclusion
10114 // in the wide store. The chain we use needs to be the chain of the
10115 // earliest store node which is *used* and replaced by the wide store.
10116 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
10117 EarliestNodeUsed = i;
10120 // Find if it is better to use vectors or integers to load and store
10124 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
10126 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
10127 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
10130 SDLoc LoadDL(LoadNodes[0].MemNode);
10131 SDLoc StoreDL(StoreNodes[0].MemNode);
10133 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode);
10134 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL,
10135 FirstLoad->getChain(),
10136 FirstLoad->getBasePtr(),
10137 FirstLoad->getPointerInfo(),
10138 false, false, false,
10139 FirstLoad->getAlignment());
10141 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad,
10142 FirstInChain->getBasePtr(),
10143 FirstInChain->getPointerInfo(), false, false,
10144 FirstInChain->getAlignment());
10146 // Replace one of the loads with the new load.
10147 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode);
10148 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1),
10149 SDValue(NewLoad.getNode(), 1));
10151 // Remove the rest of the load chains.
10152 for (unsigned i = 1; i < NumElem ; ++i) {
10153 // Replace all chain users of the old load nodes with the chain of the new
10155 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode);
10156 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain());
10159 // Replace the first store with the new store.
10160 CombineTo(EarliestOp, NewStore);
10161 // Erase all other stores.
10162 for (unsigned i = 0; i < NumElem ; ++i) {
10163 // Remove all Store nodes.
10164 if (StoreNodes[i].MemNode == EarliestOp)
10166 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
10167 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain());
10168 deleteAndRecombine(St);
10174 SDValue DAGCombiner::visitSTORE(SDNode *N) {
10175 StoreSDNode *ST = cast<StoreSDNode>(N);
10176 SDValue Chain = ST->getChain();
10177 SDValue Value = ST->getValue();
10178 SDValue Ptr = ST->getBasePtr();
10180 // If this is a store of a bit convert, store the input value if the
10181 // resultant store does not need a higher alignment than the original.
10182 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
10183 ST->isUnindexed()) {
10184 unsigned OrigAlign = ST->getAlignment();
10185 EVT SVT = Value.getOperand(0).getValueType();
10186 unsigned Align = TLI.getDataLayout()->
10187 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
10188 if (Align <= OrigAlign &&
10189 ((!LegalOperations && !ST->isVolatile()) ||
10190 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
10191 return DAG.getStore(Chain, SDLoc(N), Value.getOperand(0),
10192 Ptr, ST->getPointerInfo(), ST->isVolatile(),
10193 ST->isNonTemporal(), OrigAlign,
10197 // Turn 'store undef, Ptr' -> nothing.
10198 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
10201 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
10202 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
10203 // NOTE: If the original store is volatile, this transform must not increase
10204 // the number of stores. For example, on x86-32 an f64 can be stored in one
10205 // processor operation but an i64 (which is not legal) requires two. So the
10206 // transform should not be done in this case.
10207 if (Value.getOpcode() != ISD::TargetConstantFP) {
10209 switch (CFP->getSimpleValueType(0).SimpleTy) {
10210 default: llvm_unreachable("Unknown FP type");
10211 case MVT::f16: // We don't do this for these yet.
10217 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
10218 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
10219 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
10220 bitcastToAPInt().getZExtValue(), MVT::i32);
10221 return DAG.getStore(Chain, SDLoc(N), Tmp,
10222 Ptr, ST->getMemOperand());
10226 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
10227 !ST->isVolatile()) ||
10228 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
10229 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
10230 getZExtValue(), MVT::i64);
10231 return DAG.getStore(Chain, SDLoc(N), Tmp,
10232 Ptr, ST->getMemOperand());
10235 if (!ST->isVolatile() &&
10236 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
10237 // Many FP stores are not made apparent until after legalize, e.g. for
10238 // argument passing. Since this is so common, custom legalize the
10239 // 64-bit integer store into two 32-bit stores.
10240 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
10241 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
10242 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
10243 if (TLI.isBigEndian()) std::swap(Lo, Hi);
10245 unsigned Alignment = ST->getAlignment();
10246 bool isVolatile = ST->isVolatile();
10247 bool isNonTemporal = ST->isNonTemporal();
10248 AAMDNodes AAInfo = ST->getAAInfo();
10250 SDValue St0 = DAG.getStore(Chain, SDLoc(ST), Lo,
10251 Ptr, ST->getPointerInfo(),
10252 isVolatile, isNonTemporal,
10253 ST->getAlignment(), AAInfo);
10254 Ptr = DAG.getNode(ISD::ADD, SDLoc(N), Ptr.getValueType(), Ptr,
10255 DAG.getConstant(4, Ptr.getValueType()));
10256 Alignment = MinAlign(Alignment, 4U);
10257 SDValue St1 = DAG.getStore(Chain, SDLoc(ST), Hi,
10258 Ptr, ST->getPointerInfo().getWithOffset(4),
10259 isVolatile, isNonTemporal,
10260 Alignment, AAInfo);
10261 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other,
10270 // Try to infer better alignment information than the store already has.
10271 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
10272 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
10273 if (Align > ST->getAlignment())
10274 return DAG.getTruncStore(Chain, SDLoc(N), Value,
10275 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
10276 ST->isVolatile(), ST->isNonTemporal(), Align,
10281 // Try transforming a pair floating point load / store ops to integer
10282 // load / store ops.
10283 SDValue NewST = TransformFPLoadStorePair(N);
10284 if (NewST.getNode())
10287 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
10288 : DAG.getSubtarget().useAA();
10290 if (CombinerAAOnlyFunc.getNumOccurrences() &&
10291 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
10294 if (UseAA && ST->isUnindexed()) {
10295 // Walk up chain skipping non-aliasing memory nodes.
10296 SDValue BetterChain = FindBetterChain(N, Chain);
10298 // If there is a better chain.
10299 if (Chain != BetterChain) {
10302 // Replace the chain to avoid dependency.
10303 if (ST->isTruncatingStore()) {
10304 ReplStore = DAG.getTruncStore(BetterChain, SDLoc(N), Value, Ptr,
10305 ST->getMemoryVT(), ST->getMemOperand());
10307 ReplStore = DAG.getStore(BetterChain, SDLoc(N), Value, Ptr,
10308 ST->getMemOperand());
10311 // Create token to keep both nodes around.
10312 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
10313 MVT::Other, Chain, ReplStore);
10315 // Make sure the new and old chains are cleaned up.
10316 AddToWorklist(Token.getNode());
10318 // Don't add users to work list.
10319 return CombineTo(N, Token, false);
10323 // Try transforming N to an indexed store.
10324 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
10325 return SDValue(N, 0);
10327 // FIXME: is there such a thing as a truncating indexed store?
10328 if (ST->isTruncatingStore() && ST->isUnindexed() &&
10329 Value.getValueType().isInteger()) {
10330 // See if we can simplify the input to this truncstore with knowledge that
10331 // only the low bits are being used. For example:
10332 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
10334 GetDemandedBits(Value,
10335 APInt::getLowBitsSet(
10336 Value.getValueType().getScalarType().getSizeInBits(),
10337 ST->getMemoryVT().getScalarType().getSizeInBits()));
10338 AddToWorklist(Value.getNode());
10339 if (Shorter.getNode())
10340 return DAG.getTruncStore(Chain, SDLoc(N), Shorter,
10341 Ptr, ST->getMemoryVT(), ST->getMemOperand());
10343 // Otherwise, see if we can simplify the operation with
10344 // SimplifyDemandedBits, which only works if the value has a single use.
10345 if (SimplifyDemandedBits(Value,
10346 APInt::getLowBitsSet(
10347 Value.getValueType().getScalarType().getSizeInBits(),
10348 ST->getMemoryVT().getScalarType().getSizeInBits())))
10349 return SDValue(N, 0);
10352 // If this is a load followed by a store to the same location, then the store
10354 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
10355 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
10356 ST->isUnindexed() && !ST->isVolatile() &&
10357 // There can't be any side effects between the load and store, such as
10358 // a call or store.
10359 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
10360 // The store is dead, remove it.
10365 // If this is a store followed by a store with the same value to the same
10366 // location, then the store is dead/noop.
10367 if (StoreSDNode *ST1 = dyn_cast<StoreSDNode>(Chain)) {
10368 if (ST1->getBasePtr() == Ptr && ST->getMemoryVT() == ST1->getMemoryVT() &&
10369 ST1->getValue() == Value && ST->isUnindexed() && !ST->isVolatile() &&
10370 ST1->isUnindexed() && !ST1->isVolatile()) {
10371 // The store is dead, remove it.
10376 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
10377 // truncating store. We can do this even if this is already a truncstore.
10378 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
10379 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
10380 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
10381 ST->getMemoryVT())) {
10382 return DAG.getTruncStore(Chain, SDLoc(N), Value.getOperand(0),
10383 Ptr, ST->getMemoryVT(), ST->getMemOperand());
10386 // Only perform this optimization before the types are legal, because we
10387 // don't want to perform this optimization on every DAGCombine invocation.
10389 bool EverChanged = false;
10392 // There can be multiple store sequences on the same chain.
10393 // Keep trying to merge store sequences until we are unable to do so
10394 // or until we merge the last store on the chain.
10395 bool Changed = MergeConsecutiveStores(ST);
10396 EverChanged |= Changed;
10397 if (!Changed) break;
10398 } while (ST->getOpcode() != ISD::DELETED_NODE);
10401 return SDValue(N, 0);
10404 return ReduceLoadOpStoreWidth(N);
10407 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
10408 SDValue InVec = N->getOperand(0);
10409 SDValue InVal = N->getOperand(1);
10410 SDValue EltNo = N->getOperand(2);
10413 // If the inserted element is an UNDEF, just use the input vector.
10414 if (InVal.getOpcode() == ISD::UNDEF)
10417 EVT VT = InVec.getValueType();
10419 // If we can't generate a legal BUILD_VECTOR, exit
10420 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
10423 // Check that we know which element is being inserted
10424 if (!isa<ConstantSDNode>(EltNo))
10426 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
10428 // Canonicalize insert_vector_elt dag nodes.
10430 // (insert_vector_elt (insert_vector_elt A, Idx0), Idx1)
10431 // -> (insert_vector_elt (insert_vector_elt A, Idx1), Idx0)
10433 // Do this only if the child insert_vector node has one use; also
10434 // do this only if indices are both constants and Idx1 < Idx0.
10435 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse()
10436 && isa<ConstantSDNode>(InVec.getOperand(2))) {
10437 unsigned OtherElt =
10438 cast<ConstantSDNode>(InVec.getOperand(2))->getZExtValue();
10439 if (Elt < OtherElt) {
10441 SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VT,
10442 InVec.getOperand(0), InVal, EltNo);
10443 AddToWorklist(NewOp.getNode());
10444 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()),
10445 VT, NewOp, InVec.getOperand(1), InVec.getOperand(2));
10449 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
10450 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
10451 // vector elements.
10452 SmallVector<SDValue, 8> Ops;
10453 // Do not combine these two vectors if the output vector will not replace
10454 // the input vector.
10455 if (InVec.getOpcode() == ISD::BUILD_VECTOR && InVec.hasOneUse()) {
10456 Ops.append(InVec.getNode()->op_begin(),
10457 InVec.getNode()->op_end());
10458 } else if (InVec.getOpcode() == ISD::UNDEF) {
10459 unsigned NElts = VT.getVectorNumElements();
10460 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
10465 // Insert the element
10466 if (Elt < Ops.size()) {
10467 // All the operands of BUILD_VECTOR must have the same type;
10468 // we enforce that here.
10469 EVT OpVT = Ops[0].getValueType();
10470 if (InVal.getValueType() != OpVT)
10471 InVal = OpVT.bitsGT(InVal.getValueType()) ?
10472 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
10473 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
10477 // Return the new vector
10478 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
10481 SDValue DAGCombiner::ReplaceExtractVectorEltOfLoadWithNarrowedLoad(
10482 SDNode *EVE, EVT InVecVT, SDValue EltNo, LoadSDNode *OriginalLoad) {
10483 EVT ResultVT = EVE->getValueType(0);
10484 EVT VecEltVT = InVecVT.getVectorElementType();
10485 unsigned Align = OriginalLoad->getAlignment();
10486 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
10487 VecEltVT.getTypeForEVT(*DAG.getContext()));
10489 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VecEltVT))
10494 SDValue NewPtr = OriginalLoad->getBasePtr();
10496 EVT PtrType = NewPtr.getValueType();
10497 MachinePointerInfo MPI;
10498 if (auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo)) {
10499 int Elt = ConstEltNo->getZExtValue();
10500 unsigned PtrOff = VecEltVT.getSizeInBits() * Elt / 8;
10501 if (TLI.isBigEndian())
10502 PtrOff = InVecVT.getSizeInBits() / 8 - PtrOff;
10503 Offset = DAG.getConstant(PtrOff, PtrType);
10504 MPI = OriginalLoad->getPointerInfo().getWithOffset(PtrOff);
10506 Offset = DAG.getNode(
10507 ISD::MUL, SDLoc(EVE), EltNo.getValueType(), EltNo,
10508 DAG.getConstant(VecEltVT.getStoreSize(), EltNo.getValueType()));
10509 if (TLI.isBigEndian())
10510 Offset = DAG.getNode(
10511 ISD::SUB, SDLoc(EVE), EltNo.getValueType(),
10512 DAG.getConstant(InVecVT.getStoreSize(), EltNo.getValueType()), Offset);
10513 MPI = OriginalLoad->getPointerInfo();
10515 NewPtr = DAG.getNode(ISD::ADD, SDLoc(EVE), PtrType, NewPtr, Offset);
10517 // The replacement we need to do here is a little tricky: we need to
10518 // replace an extractelement of a load with a load.
10519 // Use ReplaceAllUsesOfValuesWith to do the replacement.
10520 // Note that this replacement assumes that the extractvalue is the only
10521 // use of the load; that's okay because we don't want to perform this
10522 // transformation in other cases anyway.
10525 if (ResultVT.bitsGT(VecEltVT)) {
10526 // If the result type of vextract is wider than the load, then issue an
10527 // extending load instead.
10528 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, ResultVT,
10532 Load = DAG.getExtLoad(
10533 ExtType, SDLoc(EVE), ResultVT, OriginalLoad->getChain(), NewPtr, MPI,
10534 VecEltVT, OriginalLoad->isVolatile(), OriginalLoad->isNonTemporal(),
10535 OriginalLoad->isInvariant(), Align, OriginalLoad->getAAInfo());
10536 Chain = Load.getValue(1);
10538 Load = DAG.getLoad(
10539 VecEltVT, SDLoc(EVE), OriginalLoad->getChain(), NewPtr, MPI,
10540 OriginalLoad->isVolatile(), OriginalLoad->isNonTemporal(),
10541 OriginalLoad->isInvariant(), Align, OriginalLoad->getAAInfo());
10542 Chain = Load.getValue(1);
10543 if (ResultVT.bitsLT(VecEltVT))
10544 Load = DAG.getNode(ISD::TRUNCATE, SDLoc(EVE), ResultVT, Load);
10546 Load = DAG.getNode(ISD::BITCAST, SDLoc(EVE), ResultVT, Load);
10548 WorklistRemover DeadNodes(*this);
10549 SDValue From[] = { SDValue(EVE, 0), SDValue(OriginalLoad, 1) };
10550 SDValue To[] = { Load, Chain };
10551 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
10552 // Since we're explicitly calling ReplaceAllUses, add the new node to the
10553 // worklist explicitly as well.
10554 AddToWorklist(Load.getNode());
10555 AddUsersToWorklist(Load.getNode()); // Add users too
10556 // Make sure to revisit this node to clean it up; it will usually be dead.
10557 AddToWorklist(EVE);
10559 return SDValue(EVE, 0);
10562 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
10563 // (vextract (scalar_to_vector val, 0) -> val
10564 SDValue InVec = N->getOperand(0);
10565 EVT VT = InVec.getValueType();
10566 EVT NVT = N->getValueType(0);
10568 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
10569 // Check if the result type doesn't match the inserted element type. A
10570 // SCALAR_TO_VECTOR may truncate the inserted element and the
10571 // EXTRACT_VECTOR_ELT may widen the extracted vector.
10572 SDValue InOp = InVec.getOperand(0);
10573 if (InOp.getValueType() != NVT) {
10574 assert(InOp.getValueType().isInteger() && NVT.isInteger());
10575 return DAG.getSExtOrTrunc(InOp, SDLoc(InVec), NVT);
10580 SDValue EltNo = N->getOperand(1);
10581 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
10583 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
10584 // We only perform this optimization before the op legalization phase because
10585 // we may introduce new vector instructions which are not backed by TD
10586 // patterns. For example on AVX, extracting elements from a wide vector
10587 // without using extract_subvector. However, if we can find an underlying
10588 // scalar value, then we can always use that.
10589 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
10591 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
10592 int NumElem = VT.getVectorNumElements();
10593 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
10594 // Find the new index to extract from.
10595 int OrigElt = SVOp->getMaskElt(Elt);
10597 // Extracting an undef index is undef.
10599 return DAG.getUNDEF(NVT);
10601 // Select the right vector half to extract from.
10603 if (OrigElt < NumElem) {
10604 SVInVec = InVec->getOperand(0);
10606 SVInVec = InVec->getOperand(1);
10607 OrigElt -= NumElem;
10610 if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) {
10611 SDValue InOp = SVInVec.getOperand(OrigElt);
10612 if (InOp.getValueType() != NVT) {
10613 assert(InOp.getValueType().isInteger() && NVT.isInteger());
10614 InOp = DAG.getSExtOrTrunc(InOp, SDLoc(SVInVec), NVT);
10620 // FIXME: We should handle recursing on other vector shuffles and
10621 // scalar_to_vector here as well.
10623 if (!LegalOperations) {
10624 EVT IndexTy = TLI.getVectorIdxTy();
10625 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), NVT,
10626 SVInVec, DAG.getConstant(OrigElt, IndexTy));
10630 bool BCNumEltsChanged = false;
10631 EVT ExtVT = VT.getVectorElementType();
10634 // If the result of load has to be truncated, then it's not necessarily
10636 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT))
10639 if (InVec.getOpcode() == ISD::BITCAST) {
10640 // Don't duplicate a load with other uses.
10641 if (!InVec.hasOneUse())
10644 EVT BCVT = InVec.getOperand(0).getValueType();
10645 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
10647 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
10648 BCNumEltsChanged = true;
10649 InVec = InVec.getOperand(0);
10650 ExtVT = BCVT.getVectorElementType();
10653 // (vextract (vN[if]M load $addr), i) -> ([if]M load $addr + i * size)
10654 if (!LegalOperations && !ConstEltNo && InVec.hasOneUse() &&
10655 ISD::isNormalLoad(InVec.getNode()) &&
10656 !N->getOperand(1)->hasPredecessor(InVec.getNode())) {
10657 SDValue Index = N->getOperand(1);
10658 if (LoadSDNode *OrigLoad = dyn_cast<LoadSDNode>(InVec))
10659 return ReplaceExtractVectorEltOfLoadWithNarrowedLoad(N, VT, Index,
10663 // Perform only after legalization to ensure build_vector / vector_shuffle
10664 // optimizations have already been done.
10665 if (!LegalOperations) return SDValue();
10667 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
10668 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
10669 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
10672 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
10674 LoadSDNode *LN0 = nullptr;
10675 const ShuffleVectorSDNode *SVN = nullptr;
10676 if (ISD::isNormalLoad(InVec.getNode())) {
10677 LN0 = cast<LoadSDNode>(InVec);
10678 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10679 InVec.getOperand(0).getValueType() == ExtVT &&
10680 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
10681 // Don't duplicate a load with other uses.
10682 if (!InVec.hasOneUse())
10685 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
10686 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
10687 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
10689 // (load $addr+1*size)
10691 // Don't duplicate a load with other uses.
10692 if (!InVec.hasOneUse())
10695 // If the bit convert changed the number of elements, it is unsafe
10696 // to examine the mask.
10697 if (BCNumEltsChanged)
10700 // Select the input vector, guarding against out of range extract vector.
10701 unsigned NumElems = VT.getVectorNumElements();
10702 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
10703 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
10705 if (InVec.getOpcode() == ISD::BITCAST) {
10706 // Don't duplicate a load with other uses.
10707 if (!InVec.hasOneUse())
10710 InVec = InVec.getOperand(0);
10712 if (ISD::isNormalLoad(InVec.getNode())) {
10713 LN0 = cast<LoadSDNode>(InVec);
10714 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
10715 EltNo = DAG.getConstant(Elt, EltNo.getValueType());
10719 // Make sure we found a non-volatile load and the extractelement is
10721 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
10724 // If Idx was -1 above, Elt is going to be -1, so just return undef.
10726 return DAG.getUNDEF(LVT);
10728 return ReplaceExtractVectorEltOfLoadWithNarrowedLoad(N, VT, EltNo, LN0);
10734 // Simplify (build_vec (ext )) to (bitcast (build_vec ))
10735 SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) {
10736 // We perform this optimization post type-legalization because
10737 // the type-legalizer often scalarizes integer-promoted vectors.
10738 // Performing this optimization before may create bit-casts which
10739 // will be type-legalized to complex code sequences.
10740 // We perform this optimization only before the operation legalizer because we
10741 // may introduce illegal operations.
10742 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes)
10745 unsigned NumInScalars = N->getNumOperands();
10747 EVT VT = N->getValueType(0);
10749 // Check to see if this is a BUILD_VECTOR of a bunch of values
10750 // which come from any_extend or zero_extend nodes. If so, we can create
10751 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
10752 // optimizations. We do not handle sign-extend because we can't fill the sign
10754 EVT SourceType = MVT::Other;
10755 bool AllAnyExt = true;
10757 for (unsigned i = 0; i != NumInScalars; ++i) {
10758 SDValue In = N->getOperand(i);
10759 // Ignore undef inputs.
10760 if (In.getOpcode() == ISD::UNDEF) continue;
10762 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
10763 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
10765 // Abort if the element is not an extension.
10766 if (!ZeroExt && !AnyExt) {
10767 SourceType = MVT::Other;
10771 // The input is a ZeroExt or AnyExt. Check the original type.
10772 EVT InTy = In.getOperand(0).getValueType();
10774 // Check that all of the widened source types are the same.
10775 if (SourceType == MVT::Other)
10778 else if (InTy != SourceType) {
10779 // Multiple income types. Abort.
10780 SourceType = MVT::Other;
10784 // Check if all of the extends are ANY_EXTENDs.
10785 AllAnyExt &= AnyExt;
10788 // In order to have valid types, all of the inputs must be extended from the
10789 // same source type and all of the inputs must be any or zero extend.
10790 // Scalar sizes must be a power of two.
10791 EVT OutScalarTy = VT.getScalarType();
10792 bool ValidTypes = SourceType != MVT::Other &&
10793 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
10794 isPowerOf2_32(SourceType.getSizeInBits());
10796 // Create a new simpler BUILD_VECTOR sequence which other optimizations can
10797 // turn into a single shuffle instruction.
10801 bool isLE = TLI.isLittleEndian();
10802 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
10803 assert(ElemRatio > 1 && "Invalid element size ratio");
10804 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
10805 DAG.getConstant(0, SourceType);
10807 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements();
10808 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
10810 // Populate the new build_vector
10811 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
10812 SDValue Cast = N->getOperand(i);
10813 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
10814 Cast.getOpcode() == ISD::ZERO_EXTEND ||
10815 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
10817 if (Cast.getOpcode() == ISD::UNDEF)
10818 In = DAG.getUNDEF(SourceType);
10820 In = Cast->getOperand(0);
10821 unsigned Index = isLE ? (i * ElemRatio) :
10822 (i * ElemRatio + (ElemRatio - 1));
10824 assert(Index < Ops.size() && "Invalid index");
10828 // The type of the new BUILD_VECTOR node.
10829 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
10830 assert(VecVT.getSizeInBits() == VT.getSizeInBits() &&
10831 "Invalid vector size");
10832 // Check if the new vector type is legal.
10833 if (!isTypeLegal(VecVT)) return SDValue();
10835 // Make the new BUILD_VECTOR.
10836 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
10838 // The new BUILD_VECTOR node has the potential to be further optimized.
10839 AddToWorklist(BV.getNode());
10840 // Bitcast to the desired type.
10841 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
10844 SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) {
10845 EVT VT = N->getValueType(0);
10847 unsigned NumInScalars = N->getNumOperands();
10850 EVT SrcVT = MVT::Other;
10851 unsigned Opcode = ISD::DELETED_NODE;
10852 unsigned NumDefs = 0;
10854 for (unsigned i = 0; i != NumInScalars; ++i) {
10855 SDValue In = N->getOperand(i);
10856 unsigned Opc = In.getOpcode();
10858 if (Opc == ISD::UNDEF)
10861 // If all scalar values are floats and converted from integers.
10862 if (Opcode == ISD::DELETED_NODE &&
10863 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) {
10870 EVT InVT = In.getOperand(0).getValueType();
10872 // If all scalar values are typed differently, bail out. It's chosen to
10873 // simplify BUILD_VECTOR of integer types.
10874 if (SrcVT == MVT::Other)
10881 // If the vector has just one element defined, it's not worth to fold it into
10882 // a vectorized one.
10886 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP)
10887 && "Should only handle conversion from integer to float.");
10888 assert(SrcVT != MVT::Other && "Cannot determine source type!");
10890 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars);
10892 if (!TLI.isOperationLegalOrCustom(Opcode, NVT))
10895 SmallVector<SDValue, 8> Opnds;
10896 for (unsigned i = 0; i != NumInScalars; ++i) {
10897 SDValue In = N->getOperand(i);
10899 if (In.getOpcode() == ISD::UNDEF)
10900 Opnds.push_back(DAG.getUNDEF(SrcVT));
10902 Opnds.push_back(In.getOperand(0));
10904 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Opnds);
10905 AddToWorklist(BV.getNode());
10907 return DAG.getNode(Opcode, dl, VT, BV);
10910 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
10911 unsigned NumInScalars = N->getNumOperands();
10913 EVT VT = N->getValueType(0);
10915 // A vector built entirely of undefs is undef.
10916 if (ISD::allOperandsUndef(N))
10917 return DAG.getUNDEF(VT);
10919 SDValue V = reduceBuildVecExtToExtBuildVec(N);
10923 V = reduceBuildVecConvertToConvertBuildVec(N);
10927 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
10928 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
10929 // at most two distinct vectors, turn this into a shuffle node.
10931 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
10932 if (!isTypeLegal(VT))
10935 // May only combine to shuffle after legalize if shuffle is legal.
10936 if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, VT))
10939 SDValue VecIn1, VecIn2;
10940 bool UsesZeroVector = false;
10941 for (unsigned i = 0; i != NumInScalars; ++i) {
10942 SDValue Op = N->getOperand(i);
10943 // Ignore undef inputs.
10944 if (Op.getOpcode() == ISD::UNDEF) continue;
10946 // See if we can combine this build_vector into a blend with a zero vector.
10947 if (!VecIn2.getNode() && ((Op.getOpcode() == ISD::Constant &&
10948 cast<ConstantSDNode>(Op.getNode())->isNullValue()) ||
10949 (Op.getOpcode() == ISD::ConstantFP &&
10950 cast<ConstantFPSDNode>(Op.getNode())->getValueAPF().isZero()))) {
10951 UsesZeroVector = true;
10955 // If this input is something other than a EXTRACT_VECTOR_ELT with a
10956 // constant index, bail out.
10957 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
10958 !isa<ConstantSDNode>(Op.getOperand(1))) {
10959 VecIn1 = VecIn2 = SDValue(nullptr, 0);
10963 // We allow up to two distinct input vectors.
10964 SDValue ExtractedFromVec = Op.getOperand(0);
10965 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
10968 if (!VecIn1.getNode()) {
10969 VecIn1 = ExtractedFromVec;
10970 } else if (!VecIn2.getNode() && !UsesZeroVector) {
10971 VecIn2 = ExtractedFromVec;
10973 // Too many inputs.
10974 VecIn1 = VecIn2 = SDValue(nullptr, 0);
10979 // If everything is good, we can make a shuffle operation.
10980 if (VecIn1.getNode()) {
10981 unsigned InNumElements = VecIn1.getValueType().getVectorNumElements();
10982 SmallVector<int, 8> Mask;
10983 for (unsigned i = 0; i != NumInScalars; ++i) {
10984 unsigned Opcode = N->getOperand(i).getOpcode();
10985 if (Opcode == ISD::UNDEF) {
10986 Mask.push_back(-1);
10990 // Operands can also be zero.
10991 if (Opcode != ISD::EXTRACT_VECTOR_ELT) {
10992 assert(UsesZeroVector &&
10993 (Opcode == ISD::Constant || Opcode == ISD::ConstantFP) &&
10994 "Unexpected node found!");
10995 Mask.push_back(NumInScalars+i);
10999 // If extracting from the first vector, just use the index directly.
11000 SDValue Extract = N->getOperand(i);
11001 SDValue ExtVal = Extract.getOperand(1);
11002 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
11003 if (Extract.getOperand(0) == VecIn1) {
11004 Mask.push_back(ExtIndex);
11008 // Otherwise, use InIdx + InputVecSize
11009 Mask.push_back(InNumElements + ExtIndex);
11012 // Avoid introducing illegal shuffles with zero.
11013 if (UsesZeroVector && !TLI.isVectorClearMaskLegal(Mask, VT))
11016 // We can't generate a shuffle node with mismatched input and output types.
11017 // Attempt to transform a single input vector to the correct type.
11018 if ((VT != VecIn1.getValueType())) {
11019 // If the input vector type has a different base type to the output
11020 // vector type, bail out.
11021 EVT VTElemType = VT.getVectorElementType();
11022 if ((VecIn1.getValueType().getVectorElementType() != VTElemType) ||
11023 (VecIn2.getNode() &&
11024 (VecIn2.getValueType().getVectorElementType() != VTElemType)))
11027 // If the input vector is too small, widen it.
11028 // We only support widening of vectors which are half the size of the
11029 // output registers. For example XMM->YMM widening on X86 with AVX.
11030 EVT VecInT = VecIn1.getValueType();
11031 if (VecInT.getSizeInBits() * 2 == VT.getSizeInBits()) {
11032 // If we only have one small input, widen it by adding undef values.
11033 if (!VecIn2.getNode())
11034 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, VecIn1,
11035 DAG.getUNDEF(VecIn1.getValueType()));
11036 else if (VecIn1.getValueType() == VecIn2.getValueType()) {
11037 // If we have two small inputs of the same type, try to concat them.
11038 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, VecIn1, VecIn2);
11039 VecIn2 = SDValue(nullptr, 0);
11042 } else if (VecInT.getSizeInBits() == VT.getSizeInBits() * 2) {
11043 // If the input vector is too large, try to split it.
11044 // We don't support having two input vectors that are too large.
11045 if (VecIn2.getNode())
11048 if (!TLI.isExtractSubvectorCheap(VT, VT.getVectorNumElements()))
11051 // Try to replace VecIn1 with two extract_subvectors
11052 // No need to update the masks, they should still be correct.
11053 VecIn2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, VecIn1,
11054 DAG.getConstant(VT.getVectorNumElements(), TLI.getVectorIdxTy()));
11055 VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, VecIn1,
11056 DAG.getConstant(0, TLI.getVectorIdxTy()));
11057 UsesZeroVector = false;
11062 if (UsesZeroVector)
11063 VecIn2 = VT.isInteger() ? DAG.getConstant(0, VT) :
11064 DAG.getConstantFP(0.0, VT);
11066 // If VecIn2 is unused then change it to undef.
11067 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
11069 // Check that we were able to transform all incoming values to the same
11071 if (VecIn2.getValueType() != VecIn1.getValueType() ||
11072 VecIn1.getValueType() != VT)
11075 // Return the new VECTOR_SHUFFLE node.
11079 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]);
11085 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
11086 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
11087 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
11088 // inputs come from at most two distinct vectors, turn this into a shuffle
11091 // If we only have one input vector, we don't need to do any concatenation.
11092 if (N->getNumOperands() == 1)
11093 return N->getOperand(0);
11095 // Check if all of the operands are undefs.
11096 EVT VT = N->getValueType(0);
11097 if (ISD::allOperandsUndef(N))
11098 return DAG.getUNDEF(VT);
11100 // Optimize concat_vectors where one of the vectors is undef.
11101 if (N->getNumOperands() == 2 &&
11102 N->getOperand(1)->getOpcode() == ISD::UNDEF) {
11103 SDValue In = N->getOperand(0);
11104 assert(In.getValueType().isVector() && "Must concat vectors");
11106 // Transform: concat_vectors(scalar, undef) -> scalar_to_vector(sclr).
11107 if (In->getOpcode() == ISD::BITCAST &&
11108 !In->getOperand(0)->getValueType(0).isVector()) {
11109 SDValue Scalar = In->getOperand(0);
11110 EVT SclTy = Scalar->getValueType(0);
11112 if (!SclTy.isFloatingPoint() && !SclTy.isInteger())
11115 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SclTy,
11116 VT.getSizeInBits() / SclTy.getSizeInBits());
11117 if (!TLI.isTypeLegal(NVT) || !TLI.isTypeLegal(Scalar.getValueType()))
11120 SDLoc dl = SDLoc(N);
11121 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NVT, Scalar);
11122 return DAG.getNode(ISD::BITCAST, dl, VT, Res);
11126 // fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
11127 // -> (BUILD_VECTOR A, B, ..., C, D, ...)
11128 if (N->getNumOperands() == 2 &&
11129 N->getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
11130 N->getOperand(1).getOpcode() == ISD::BUILD_VECTOR) {
11131 EVT VT = N->getValueType(0);
11132 SDValue N0 = N->getOperand(0);
11133 SDValue N1 = N->getOperand(1);
11134 SmallVector<SDValue, 8> Opnds;
11135 unsigned BuildVecNumElts = N0.getNumOperands();
11137 EVT SclTy0 = N0.getOperand(0)->getValueType(0);
11138 EVT SclTy1 = N1.getOperand(0)->getValueType(0);
11139 if (SclTy0.isFloatingPoint()) {
11140 for (unsigned i = 0; i != BuildVecNumElts; ++i)
11141 Opnds.push_back(N0.getOperand(i));
11142 for (unsigned i = 0; i != BuildVecNumElts; ++i)
11143 Opnds.push_back(N1.getOperand(i));
11145 // If BUILD_VECTOR are from built from integer, they may have different
11146 // operand types. Get the smaller type and truncate all operands to it.
11147 EVT MinTy = SclTy0.bitsLE(SclTy1) ? SclTy0 : SclTy1;
11148 for (unsigned i = 0; i != BuildVecNumElts; ++i)
11149 Opnds.push_back(DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinTy,
11150 N0.getOperand(i)));
11151 for (unsigned i = 0; i != BuildVecNumElts; ++i)
11152 Opnds.push_back(DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinTy,
11153 N1.getOperand(i)));
11156 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
11159 // Type legalization of vectors and DAG canonicalization of SHUFFLE_VECTOR
11160 // nodes often generate nop CONCAT_VECTOR nodes.
11161 // Scan the CONCAT_VECTOR operands and look for a CONCAT operations that
11162 // place the incoming vectors at the exact same location.
11163 SDValue SingleSource = SDValue();
11164 unsigned PartNumElem = N->getOperand(0).getValueType().getVectorNumElements();
11166 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
11167 SDValue Op = N->getOperand(i);
11169 if (Op.getOpcode() == ISD::UNDEF)
11172 // Check if this is the identity extract:
11173 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR)
11176 // Find the single incoming vector for the extract_subvector.
11177 if (SingleSource.getNode()) {
11178 if (Op.getOperand(0) != SingleSource)
11181 SingleSource = Op.getOperand(0);
11183 // Check the source type is the same as the type of the result.
11184 // If not, this concat may extend the vector, so we can not
11185 // optimize it away.
11186 if (SingleSource.getValueType() != N->getValueType(0))
11190 unsigned IdentityIndex = i * PartNumElem;
11191 ConstantSDNode *CS = dyn_cast<ConstantSDNode>(Op.getOperand(1));
11192 // The extract index must be constant.
11196 // Check that we are reading from the identity index.
11197 if (CS->getZExtValue() != IdentityIndex)
11201 if (SingleSource.getNode())
11202 return SingleSource;
11207 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
11208 EVT NVT = N->getValueType(0);
11209 SDValue V = N->getOperand(0);
11211 if (V->getOpcode() == ISD::CONCAT_VECTORS) {
11213 // (extract_subvec (concat V1, V2, ...), i)
11216 // Only operand 0 is checked as 'concat' assumes all inputs of the same
11218 if (V->getOperand(0).getValueType() != NVT)
11220 unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
11221 unsigned NumElems = NVT.getVectorNumElements();
11222 assert((Idx % NumElems) == 0 &&
11223 "IDX in concat is not a multiple of the result vector length.");
11224 return V->getOperand(Idx / NumElems);
11228 if (V->getOpcode() == ISD::BITCAST)
11229 V = V.getOperand(0);
11231 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
11233 // Handle only simple case where vector being inserted and vector
11234 // being extracted are of same type, and are half size of larger vectors.
11235 EVT BigVT = V->getOperand(0).getValueType();
11236 EVT SmallVT = V->getOperand(1).getValueType();
11237 if (!NVT.bitsEq(SmallVT) || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
11240 // Only handle cases where both indexes are constants with the same type.
11241 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
11242 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
11244 if (InsIdx && ExtIdx &&
11245 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
11246 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
11248 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
11250 // indices are equal or bit offsets are equal => V1
11251 // otherwise => (extract_subvec V1, ExtIdx)
11252 if (InsIdx->getZExtValue() * SmallVT.getScalarType().getSizeInBits() ==
11253 ExtIdx->getZExtValue() * NVT.getScalarType().getSizeInBits())
11254 return DAG.getNode(ISD::BITCAST, dl, NVT, V->getOperand(1));
11255 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT,
11256 DAG.getNode(ISD::BITCAST, dl,
11257 N->getOperand(0).getValueType(),
11258 V->getOperand(0)), N->getOperand(1));
11265 static SDValue simplifyShuffleOperandRecursively(SmallBitVector &UsedElements,
11266 SDValue V, SelectionDAG &DAG) {
11268 EVT VT = V.getValueType();
11270 switch (V.getOpcode()) {
11274 case ISD::CONCAT_VECTORS: {
11275 EVT OpVT = V->getOperand(0).getValueType();
11276 int OpSize = OpVT.getVectorNumElements();
11277 SmallBitVector OpUsedElements(OpSize, false);
11278 bool FoundSimplification = false;
11279 SmallVector<SDValue, 4> NewOps;
11280 NewOps.reserve(V->getNumOperands());
11281 for (int i = 0, NumOps = V->getNumOperands(); i < NumOps; ++i) {
11282 SDValue Op = V->getOperand(i);
11283 bool OpUsed = false;
11284 for (int j = 0; j < OpSize; ++j)
11285 if (UsedElements[i * OpSize + j]) {
11286 OpUsedElements[j] = true;
11290 OpUsed ? simplifyShuffleOperandRecursively(OpUsedElements, Op, DAG)
11291 : DAG.getUNDEF(OpVT));
11292 FoundSimplification |= Op == NewOps.back();
11293 OpUsedElements.reset();
11295 if (FoundSimplification)
11296 V = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, NewOps);
11300 case ISD::INSERT_SUBVECTOR: {
11301 SDValue BaseV = V->getOperand(0);
11302 SDValue SubV = V->getOperand(1);
11303 auto *IdxN = dyn_cast<ConstantSDNode>(V->getOperand(2));
11307 int SubSize = SubV.getValueType().getVectorNumElements();
11308 int Idx = IdxN->getZExtValue();
11309 bool SubVectorUsed = false;
11310 SmallBitVector SubUsedElements(SubSize, false);
11311 for (int i = 0; i < SubSize; ++i)
11312 if (UsedElements[i + Idx]) {
11313 SubVectorUsed = true;
11314 SubUsedElements[i] = true;
11315 UsedElements[i + Idx] = false;
11318 // Now recurse on both the base and sub vectors.
11319 SDValue SimplifiedSubV =
11321 ? simplifyShuffleOperandRecursively(SubUsedElements, SubV, DAG)
11322 : DAG.getUNDEF(SubV.getValueType());
11323 SDValue SimplifiedBaseV = simplifyShuffleOperandRecursively(UsedElements, BaseV, DAG);
11324 if (SimplifiedSubV != SubV || SimplifiedBaseV != BaseV)
11325 V = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
11326 SimplifiedBaseV, SimplifiedSubV, V->getOperand(2));
11332 static SDValue simplifyShuffleOperands(ShuffleVectorSDNode *SVN, SDValue N0,
11333 SDValue N1, SelectionDAG &DAG) {
11334 EVT VT = SVN->getValueType(0);
11335 int NumElts = VT.getVectorNumElements();
11336 SmallBitVector N0UsedElements(NumElts, false), N1UsedElements(NumElts, false);
11337 for (int M : SVN->getMask())
11338 if (M >= 0 && M < NumElts)
11339 N0UsedElements[M] = true;
11340 else if (M >= NumElts)
11341 N1UsedElements[M - NumElts] = true;
11343 SDValue S0 = simplifyShuffleOperandRecursively(N0UsedElements, N0, DAG);
11344 SDValue S1 = simplifyShuffleOperandRecursively(N1UsedElements, N1, DAG);
11345 if (S0 == N0 && S1 == N1)
11348 return DAG.getVectorShuffle(VT, SDLoc(SVN), S0, S1, SVN->getMask());
11351 // Tries to turn a shuffle of two CONCAT_VECTORS into a single concat.
11352 static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) {
11353 EVT VT = N->getValueType(0);
11354 unsigned NumElts = VT.getVectorNumElements();
11356 SDValue N0 = N->getOperand(0);
11357 SDValue N1 = N->getOperand(1);
11358 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
11360 SmallVector<SDValue, 4> Ops;
11361 EVT ConcatVT = N0.getOperand(0).getValueType();
11362 unsigned NumElemsPerConcat = ConcatVT.getVectorNumElements();
11363 unsigned NumConcats = NumElts / NumElemsPerConcat;
11365 // Look at every vector that's inserted. We're looking for exact
11366 // subvector-sized copies from a concatenated vector
11367 for (unsigned I = 0; I != NumConcats; ++I) {
11368 // Make sure we're dealing with a copy.
11369 unsigned Begin = I * NumElemsPerConcat;
11370 bool AllUndef = true, NoUndef = true;
11371 for (unsigned J = Begin; J != Begin + NumElemsPerConcat; ++J) {
11372 if (SVN->getMaskElt(J) >= 0)
11379 if (SVN->getMaskElt(Begin) % NumElemsPerConcat != 0)
11382 for (unsigned J = 1; J != NumElemsPerConcat; ++J)
11383 if (SVN->getMaskElt(Begin + J - 1) + 1 != SVN->getMaskElt(Begin + J))
11386 unsigned FirstElt = SVN->getMaskElt(Begin) / NumElemsPerConcat;
11387 if (FirstElt < N0.getNumOperands())
11388 Ops.push_back(N0.getOperand(FirstElt));
11390 Ops.push_back(N1.getOperand(FirstElt - N0.getNumOperands()));
11392 } else if (AllUndef) {
11393 Ops.push_back(DAG.getUNDEF(N0.getOperand(0).getValueType()));
11394 } else { // Mixed with general masks and undefs, can't do optimization.
11399 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);
11402 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
11403 EVT VT = N->getValueType(0);
11404 unsigned NumElts = VT.getVectorNumElements();
11406 SDValue N0 = N->getOperand(0);
11407 SDValue N1 = N->getOperand(1);
11409 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
11411 // Canonicalize shuffle undef, undef -> undef
11412 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
11413 return DAG.getUNDEF(VT);
11415 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
11417 // Canonicalize shuffle v, v -> v, undef
11419 SmallVector<int, 8> NewMask;
11420 for (unsigned i = 0; i != NumElts; ++i) {
11421 int Idx = SVN->getMaskElt(i);
11422 if (Idx >= (int)NumElts) Idx -= NumElts;
11423 NewMask.push_back(Idx);
11425 return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT),
11429 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
11430 if (N0.getOpcode() == ISD::UNDEF) {
11431 SmallVector<int, 8> NewMask;
11432 for (unsigned i = 0; i != NumElts; ++i) {
11433 int Idx = SVN->getMaskElt(i);
11435 if (Idx >= (int)NumElts)
11438 Idx = -1; // remove reference to lhs
11440 NewMask.push_back(Idx);
11442 return DAG.getVectorShuffle(VT, SDLoc(N), N1, DAG.getUNDEF(VT),
11446 // Remove references to rhs if it is undef
11447 if (N1.getOpcode() == ISD::UNDEF) {
11448 bool Changed = false;
11449 SmallVector<int, 8> NewMask;
11450 for (unsigned i = 0; i != NumElts; ++i) {
11451 int Idx = SVN->getMaskElt(i);
11452 if (Idx >= (int)NumElts) {
11456 NewMask.push_back(Idx);
11459 return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, &NewMask[0]);
11462 // If it is a splat, check if the argument vector is another splat or a
11463 // build_vector with all scalar elements the same.
11464 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
11465 SDNode *V = N0.getNode();
11467 // If this is a bit convert that changes the element type of the vector but
11468 // not the number of vector elements, look through it. Be careful not to
11469 // look though conversions that change things like v4f32 to v2f64.
11470 if (V->getOpcode() == ISD::BITCAST) {
11471 SDValue ConvInput = V->getOperand(0);
11472 if (ConvInput.getValueType().isVector() &&
11473 ConvInput.getValueType().getVectorNumElements() == NumElts)
11474 V = ConvInput.getNode();
11477 if (V->getOpcode() == ISD::BUILD_VECTOR) {
11478 assert(V->getNumOperands() == NumElts &&
11479 "BUILD_VECTOR has wrong number of operands");
11481 bool AllSame = true;
11482 for (unsigned i = 0; i != NumElts; ++i) {
11483 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
11484 Base = V->getOperand(i);
11488 // Splat of <u, u, u, u>, return <u, u, u, u>
11489 if (!Base.getNode())
11491 for (unsigned i = 0; i != NumElts; ++i) {
11492 if (V->getOperand(i) != Base) {
11497 // Splat of <x, x, x, x>, return <x, x, x, x>
11503 // There are various patterns used to build up a vector from smaller vectors,
11504 // subvectors, or elements. Scan chains of these and replace unused insertions
11505 // or components with undef.
11506 if (SDValue S = simplifyShuffleOperands(SVN, N0, N1, DAG))
11509 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
11510 Level < AfterLegalizeVectorOps &&
11511 (N1.getOpcode() == ISD::UNDEF ||
11512 (N1.getOpcode() == ISD::CONCAT_VECTORS &&
11513 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()))) {
11514 SDValue V = partitionShuffleOfConcats(N, DAG);
11520 // Canonicalize shuffles according to rules:
11521 // shuffle(A, shuffle(A, B)) -> shuffle(shuffle(A,B), A)
11522 // shuffle(B, shuffle(A, B)) -> shuffle(shuffle(A,B), B)
11523 // shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
11524 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE &&
11525 N0.getOpcode() != ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
11526 TLI.isTypeLegal(VT)) {
11527 // The incoming shuffle must be of the same type as the result of the
11528 // current shuffle.
11529 assert(N1->getOperand(0).getValueType() == VT &&
11530 "Shuffle types don't match");
11532 SDValue SV0 = N1->getOperand(0);
11533 SDValue SV1 = N1->getOperand(1);
11534 bool HasSameOp0 = N0 == SV0;
11535 bool IsSV1Undef = SV1.getOpcode() == ISD::UNDEF;
11536 if (HasSameOp0 || IsSV1Undef || N0 == SV1)
11537 // Commute the operands of this shuffle so that next rule
11539 return DAG.getCommutedVectorShuffle(*SVN);
11542 // Try to fold according to rules:
11543 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, B, M2)
11544 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, C, M2)
11545 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, C, M2)
11546 // Don't try to fold shuffles with illegal type.
11547 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
11548 TLI.isTypeLegal(VT)) {
11549 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
11551 // The incoming shuffle must be of the same type as the result of the
11552 // current shuffle.
11553 assert(OtherSV->getOperand(0).getValueType() == VT &&
11554 "Shuffle types don't match");
11557 SmallVector<int, 4> Mask;
11558 // Compute the combined shuffle mask for a shuffle with SV0 as the first
11559 // operand, and SV1 as the second operand.
11560 for (unsigned i = 0; i != NumElts; ++i) {
11561 int Idx = SVN->getMaskElt(i);
11563 // Propagate Undef.
11564 Mask.push_back(Idx);
11568 SDValue CurrentVec;
11569 if (Idx < (int)NumElts) {
11570 // This shuffle index refers to the inner shuffle N0. Lookup the inner
11571 // shuffle mask to identify which vector is actually referenced.
11572 Idx = OtherSV->getMaskElt(Idx);
11574 // Propagate Undef.
11575 Mask.push_back(Idx);
11579 CurrentVec = (Idx < (int) NumElts) ? OtherSV->getOperand(0)
11580 : OtherSV->getOperand(1);
11582 // This shuffle index references an element within N1.
11586 // Simple case where 'CurrentVec' is UNDEF.
11587 if (CurrentVec.getOpcode() == ISD::UNDEF) {
11588 Mask.push_back(-1);
11592 // Canonicalize the shuffle index. We don't know yet if CurrentVec
11593 // will be the first or second operand of the combined shuffle.
11594 Idx = Idx % NumElts;
11595 if (!SV0.getNode() || SV0 == CurrentVec) {
11596 // Ok. CurrentVec is the left hand side.
11597 // Update the mask accordingly.
11599 Mask.push_back(Idx);
11603 // Bail out if we cannot convert the shuffle pair into a single shuffle.
11604 if (SV1.getNode() && SV1 != CurrentVec)
11607 // Ok. CurrentVec is the right hand side.
11608 // Update the mask accordingly.
11610 Mask.push_back(Idx + NumElts);
11613 // Check if all indices in Mask are Undef. In case, propagate Undef.
11614 bool isUndefMask = true;
11615 for (unsigned i = 0; i != NumElts && isUndefMask; ++i)
11616 isUndefMask &= Mask[i] < 0;
11619 return DAG.getUNDEF(VT);
11621 if (!SV0.getNode())
11622 SV0 = DAG.getUNDEF(VT);
11623 if (!SV1.getNode())
11624 SV1 = DAG.getUNDEF(VT);
11626 // Avoid introducing shuffles with illegal mask.
11627 if (!TLI.isShuffleMaskLegal(Mask, VT)) {
11628 // Compute the commuted shuffle mask and test again.
11629 for (unsigned i = 0; i != NumElts; ++i) {
11633 else if (idx < (int)NumElts)
11634 Mask[i] = idx + NumElts;
11636 Mask[i] = idx - NumElts;
11639 if (!TLI.isShuffleMaskLegal(Mask, VT))
11642 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, A, M2)
11643 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(C, A, M2)
11644 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(C, B, M2)
11645 std::swap(SV0, SV1);
11648 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, B, M2)
11649 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, C, M2)
11650 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, C, M2)
11651 return DAG.getVectorShuffle(VT, SDLoc(N), SV0, SV1, &Mask[0]);
11657 SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N) {
11658 SDValue N0 = N->getOperand(0);
11659 SDValue N2 = N->getOperand(2);
11661 // If the input vector is a concatenation, and the insert replaces
11662 // one of the halves, we can optimize into a single concat_vectors.
11663 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
11664 N0->getNumOperands() == 2 && N2.getOpcode() == ISD::Constant) {
11665 APInt InsIdx = cast<ConstantSDNode>(N2)->getAPIntValue();
11666 EVT VT = N->getValueType(0);
11668 // Lower half: fold (insert_subvector (concat_vectors X, Y), Z) ->
11669 // (concat_vectors Z, Y)
11671 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
11672 N->getOperand(1), N0.getOperand(1));
11674 // Upper half: fold (insert_subvector (concat_vectors X, Y), Z) ->
11675 // (concat_vectors X, Z)
11676 if (InsIdx == VT.getVectorNumElements()/2)
11677 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
11678 N0.getOperand(0), N->getOperand(1));
11684 /// Returns a vector_shuffle if it able to transform an AND to a vector_shuffle
11685 /// with the destination vector and a zero vector.
11686 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
11687 /// vector_shuffle V, Zero, <0, 4, 2, 4>
11688 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
11689 EVT VT = N->getValueType(0);
11691 SDValue LHS = N->getOperand(0);
11692 SDValue RHS = N->getOperand(1);
11693 if (N->getOpcode() == ISD::AND) {
11694 if (RHS.getOpcode() == ISD::BITCAST)
11695 RHS = RHS.getOperand(0);
11696 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
11697 SmallVector<int, 8> Indices;
11698 unsigned NumElts = RHS.getNumOperands();
11699 for (unsigned i = 0; i != NumElts; ++i) {
11700 SDValue Elt = RHS.getOperand(i);
11701 if (!isa<ConstantSDNode>(Elt))
11704 if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
11705 Indices.push_back(i);
11706 else if (cast<ConstantSDNode>(Elt)->isNullValue())
11707 Indices.push_back(NumElts+i);
11712 // Let's see if the target supports this vector_shuffle.
11713 EVT RVT = RHS.getValueType();
11714 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
11717 // Return the new VECTOR_SHUFFLE node.
11718 EVT EltVT = RVT.getVectorElementType();
11719 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
11720 DAG.getConstant(0, EltVT));
11721 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), RVT, ZeroOps);
11722 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
11723 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
11724 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
11731 /// Visit a binary vector operation, like ADD.
11732 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
11733 assert(N->getValueType(0).isVector() &&
11734 "SimplifyVBinOp only works on vectors!");
11736 SDValue LHS = N->getOperand(0);
11737 SDValue RHS = N->getOperand(1);
11738 SDValue Shuffle = XformToShuffleWithZero(N);
11739 if (Shuffle.getNode()) return Shuffle;
11741 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
11743 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
11744 RHS.getOpcode() == ISD::BUILD_VECTOR) {
11745 // Check if both vectors are constants. If not bail out.
11746 if (!(cast<BuildVectorSDNode>(LHS)->isConstant() &&
11747 cast<BuildVectorSDNode>(RHS)->isConstant()))
11750 SmallVector<SDValue, 8> Ops;
11751 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
11752 SDValue LHSOp = LHS.getOperand(i);
11753 SDValue RHSOp = RHS.getOperand(i);
11755 // Can't fold divide by zero.
11756 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
11757 N->getOpcode() == ISD::FDIV) {
11758 if ((RHSOp.getOpcode() == ISD::Constant &&
11759 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
11760 (RHSOp.getOpcode() == ISD::ConstantFP &&
11761 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
11765 EVT VT = LHSOp.getValueType();
11766 EVT RVT = RHSOp.getValueType();
11768 // Integer BUILD_VECTOR operands may have types larger than the element
11769 // size (e.g., when the element type is not legal). Prior to type
11770 // legalization, the types may not match between the two BUILD_VECTORS.
11771 // Truncate one of the operands to make them match.
11772 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
11773 RHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, RHSOp);
11775 LHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), RVT, LHSOp);
11779 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(LHS), VT,
11781 if (FoldOp.getOpcode() != ISD::UNDEF &&
11782 FoldOp.getOpcode() != ISD::Constant &&
11783 FoldOp.getOpcode() != ISD::ConstantFP)
11785 Ops.push_back(FoldOp);
11786 AddToWorklist(FoldOp.getNode());
11789 if (Ops.size() == LHS.getNumOperands())
11790 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), LHS.getValueType(), Ops);
11793 // Type legalization might introduce new shuffles in the DAG.
11794 // Fold (VBinOp (shuffle (A, Undef, Mask)), (shuffle (B, Undef, Mask)))
11795 // -> (shuffle (VBinOp (A, B)), Undef, Mask).
11796 if (LegalTypes && isa<ShuffleVectorSDNode>(LHS) &&
11797 isa<ShuffleVectorSDNode>(RHS) && LHS.hasOneUse() && RHS.hasOneUse() &&
11798 LHS.getOperand(1).getOpcode() == ISD::UNDEF &&
11799 RHS.getOperand(1).getOpcode() == ISD::UNDEF) {
11800 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(LHS);
11801 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(RHS);
11803 if (SVN0->getMask().equals(SVN1->getMask())) {
11804 EVT VT = N->getValueType(0);
11805 SDValue UndefVector = LHS.getOperand(1);
11806 SDValue NewBinOp = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
11807 LHS.getOperand(0), RHS.getOperand(0));
11808 AddUsersToWorklist(N);
11809 return DAG.getVectorShuffle(VT, SDLoc(N), NewBinOp, UndefVector,
11810 &SVN0->getMask()[0]);
11817 /// Visit a binary vector operation, like FABS/FNEG.
11818 SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) {
11819 assert(N->getValueType(0).isVector() &&
11820 "SimplifyVUnaryOp only works on vectors!");
11822 SDValue N0 = N->getOperand(0);
11824 if (N0.getOpcode() != ISD::BUILD_VECTOR)
11827 // Operand is a BUILD_VECTOR node, see if we can constant fold it.
11828 SmallVector<SDValue, 8> Ops;
11829 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
11830 SDValue Op = N0.getOperand(i);
11831 if (Op.getOpcode() != ISD::UNDEF &&
11832 Op.getOpcode() != ISD::ConstantFP)
11834 EVT EltVT = Op.getValueType();
11835 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(N0), EltVT, Op);
11836 if (FoldOp.getOpcode() != ISD::UNDEF &&
11837 FoldOp.getOpcode() != ISD::ConstantFP)
11839 Ops.push_back(FoldOp);
11840 AddToWorklist(FoldOp.getNode());
11843 if (Ops.size() != N0.getNumOperands())
11846 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N0.getValueType(), Ops);
11849 SDValue DAGCombiner::SimplifySelect(SDLoc DL, SDValue N0,
11850 SDValue N1, SDValue N2){
11851 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
11853 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
11854 cast<CondCodeSDNode>(N0.getOperand(2))->get());
11856 // If we got a simplified select_cc node back from SimplifySelectCC, then
11857 // break it down into a new SETCC node, and a new SELECT node, and then return
11858 // the SELECT node, since we were called with a SELECT node.
11859 if (SCC.getNode()) {
11860 // Check to see if we got a select_cc back (to turn into setcc/select).
11861 // Otherwise, just return whatever node we got back, like fabs.
11862 if (SCC.getOpcode() == ISD::SELECT_CC) {
11863 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0),
11865 SCC.getOperand(0), SCC.getOperand(1),
11866 SCC.getOperand(4));
11867 AddToWorklist(SETCC.getNode());
11868 return DAG.getSelect(SDLoc(SCC), SCC.getValueType(), SETCC,
11869 SCC.getOperand(2), SCC.getOperand(3));
11877 /// Given a SELECT or a SELECT_CC node, where LHS and RHS are the two values
11878 /// being selected between, see if we can simplify the select. Callers of this
11879 /// should assume that TheSelect is deleted if this returns true. As such, they
11880 /// should return the appropriate thing (e.g. the node) back to the top-level of
11881 /// the DAG combiner loop to avoid it being looked at.
11882 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
11885 // Cannot simplify select with vector condition
11886 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
11888 // If this is a select from two identical things, try to pull the operation
11889 // through the select.
11890 if (LHS.getOpcode() != RHS.getOpcode() ||
11891 !LHS.hasOneUse() || !RHS.hasOneUse())
11894 // If this is a load and the token chain is identical, replace the select
11895 // of two loads with a load through a select of the address to load from.
11896 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
11897 // constants have been dropped into the constant pool.
11898 if (LHS.getOpcode() == ISD::LOAD) {
11899 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
11900 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
11902 // Token chains must be identical.
11903 if (LHS.getOperand(0) != RHS.getOperand(0) ||
11904 // Do not let this transformation reduce the number of volatile loads.
11905 LLD->isVolatile() || RLD->isVolatile() ||
11906 // If this is an EXTLOAD, the VT's must match.
11907 LLD->getMemoryVT() != RLD->getMemoryVT() ||
11908 // If this is an EXTLOAD, the kind of extension must match.
11909 (LLD->getExtensionType() != RLD->getExtensionType() &&
11910 // The only exception is if one of the extensions is anyext.
11911 LLD->getExtensionType() != ISD::EXTLOAD &&
11912 RLD->getExtensionType() != ISD::EXTLOAD) ||
11913 // FIXME: this discards src value information. This is
11914 // over-conservative. It would be beneficial to be able to remember
11915 // both potential memory locations. Since we are discarding
11916 // src value info, don't do the transformation if the memory
11917 // locations are not in the default address space.
11918 LLD->getPointerInfo().getAddrSpace() != 0 ||
11919 RLD->getPointerInfo().getAddrSpace() != 0 ||
11920 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(),
11921 LLD->getBasePtr().getValueType()))
11924 // Check that the select condition doesn't reach either load. If so,
11925 // folding this will induce a cycle into the DAG. If not, this is safe to
11926 // xform, so create a select of the addresses.
11928 if (TheSelect->getOpcode() == ISD::SELECT) {
11929 SDNode *CondNode = TheSelect->getOperand(0).getNode();
11930 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
11931 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
11933 // The loads must not depend on one another.
11934 if (LLD->isPredecessorOf(RLD) ||
11935 RLD->isPredecessorOf(LLD))
11937 Addr = DAG.getSelect(SDLoc(TheSelect),
11938 LLD->getBasePtr().getValueType(),
11939 TheSelect->getOperand(0), LLD->getBasePtr(),
11940 RLD->getBasePtr());
11941 } else { // Otherwise SELECT_CC
11942 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
11943 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
11945 if ((LLD->hasAnyUseOfValue(1) &&
11946 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
11947 (RLD->hasAnyUseOfValue(1) &&
11948 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS))))
11951 Addr = DAG.getNode(ISD::SELECT_CC, SDLoc(TheSelect),
11952 LLD->getBasePtr().getValueType(),
11953 TheSelect->getOperand(0),
11954 TheSelect->getOperand(1),
11955 LLD->getBasePtr(), RLD->getBasePtr(),
11956 TheSelect->getOperand(4));
11960 // It is safe to replace the two loads if they have different alignments,
11961 // but the new load must be the minimum (most restrictive) alignment of the
11963 bool isInvariant = LLD->isInvariant() & RLD->isInvariant();
11964 unsigned Alignment = std::min(LLD->getAlignment(), RLD->getAlignment());
11965 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
11966 Load = DAG.getLoad(TheSelect->getValueType(0),
11968 // FIXME: Discards pointer and AA info.
11969 LLD->getChain(), Addr, MachinePointerInfo(),
11970 LLD->isVolatile(), LLD->isNonTemporal(),
11971 isInvariant, Alignment);
11973 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
11974 RLD->getExtensionType() : LLD->getExtensionType(),
11976 TheSelect->getValueType(0),
11977 // FIXME: Discards pointer and AA info.
11978 LLD->getChain(), Addr, MachinePointerInfo(),
11979 LLD->getMemoryVT(), LLD->isVolatile(),
11980 LLD->isNonTemporal(), isInvariant, Alignment);
11983 // Users of the select now use the result of the load.
11984 CombineTo(TheSelect, Load);
11986 // Users of the old loads now use the new load's chain. We know the
11987 // old-load value is dead now.
11988 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
11989 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
11996 /// Simplify an expression of the form (N0 cond N1) ? N2 : N3
11997 /// where 'cond' is the comparison specified by CC.
11998 SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
11999 SDValue N2, SDValue N3,
12000 ISD::CondCode CC, bool NotExtCompare) {
12001 // (x ? y : y) -> y.
12002 if (N2 == N3) return N2;
12004 EVT VT = N2.getValueType();
12005 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
12006 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
12007 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
12009 // Determine if the condition we're dealing with is constant
12010 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
12011 N0, N1, CC, DL, false);
12012 if (SCC.getNode()) AddToWorklist(SCC.getNode());
12013 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
12015 // fold select_cc true, x, y -> x
12016 if (SCCC && !SCCC->isNullValue())
12018 // fold select_cc false, x, y -> y
12019 if (SCCC && SCCC->isNullValue())
12022 // Check to see if we can simplify the select into an fabs node
12023 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
12024 // Allow either -0.0 or 0.0
12025 if (CFP->getValueAPF().isZero()) {
12026 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
12027 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
12028 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
12029 N2 == N3.getOperand(0))
12030 return DAG.getNode(ISD::FABS, DL, VT, N0);
12032 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
12033 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
12034 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
12035 N2.getOperand(0) == N3)
12036 return DAG.getNode(ISD::FABS, DL, VT, N3);
12040 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
12041 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
12042 // in it. This is a win when the constant is not otherwise available because
12043 // it replaces two constant pool loads with one. We only do this if the FP
12044 // type is known to be legal, because if it isn't, then we are before legalize
12045 // types an we want the other legalization to happen first (e.g. to avoid
12046 // messing with soft float) and if the ConstantFP is not legal, because if
12047 // it is legal, we may not need to store the FP constant in a constant pool.
12048 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
12049 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
12050 if (TLI.isTypeLegal(N2.getValueType()) &&
12051 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
12052 TargetLowering::Legal &&
12053 !TLI.isFPImmLegal(TV->getValueAPF(), TV->getValueType(0)) &&
12054 !TLI.isFPImmLegal(FV->getValueAPF(), FV->getValueType(0))) &&
12055 // If both constants have multiple uses, then we won't need to do an
12056 // extra load, they are likely around in registers for other users.
12057 (TV->hasOneUse() || FV->hasOneUse())) {
12058 Constant *Elts[] = {
12059 const_cast<ConstantFP*>(FV->getConstantFPValue()),
12060 const_cast<ConstantFP*>(TV->getConstantFPValue())
12062 Type *FPTy = Elts[0]->getType();
12063 const DataLayout &TD = *TLI.getDataLayout();
12065 // Create a ConstantArray of the two constants.
12066 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
12067 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
12068 TD.getPrefTypeAlignment(FPTy));
12069 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12071 // Get the offsets to the 0 and 1 element of the array so that we can
12072 // select between them.
12073 SDValue Zero = DAG.getIntPtrConstant(0);
12074 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
12075 SDValue One = DAG.getIntPtrConstant(EltSize);
12077 SDValue Cond = DAG.getSetCC(DL,
12078 getSetCCResultType(N0.getValueType()),
12080 AddToWorklist(Cond.getNode());
12081 SDValue CstOffset = DAG.getSelect(DL, Zero.getValueType(),
12083 AddToWorklist(CstOffset.getNode());
12084 CPIdx = DAG.getNode(ISD::ADD, DL, CPIdx.getValueType(), CPIdx,
12086 AddToWorklist(CPIdx.getNode());
12087 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
12088 MachinePointerInfo::getConstantPool(), false,
12089 false, false, Alignment);
12094 // Check to see if we can perform the "gzip trick", transforming
12095 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
12096 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
12097 (N1C->isNullValue() || // (a < 0) ? b : 0
12098 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
12099 EVT XType = N0.getValueType();
12100 EVT AType = N2.getValueType();
12101 if (XType.bitsGE(AType)) {
12102 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
12103 // single-bit constant.
12104 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
12105 unsigned ShCtV = N2C->getAPIntValue().logBase2();
12106 ShCtV = XType.getSizeInBits()-ShCtV-1;
12107 SDValue ShCt = DAG.getConstant(ShCtV,
12108 getShiftAmountTy(N0.getValueType()));
12109 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0),
12111 AddToWorklist(Shift.getNode());
12113 if (XType.bitsGT(AType)) {
12114 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
12115 AddToWorklist(Shift.getNode());
12118 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
12121 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0),
12123 DAG.getConstant(XType.getSizeInBits()-1,
12124 getShiftAmountTy(N0.getValueType())));
12125 AddToWorklist(Shift.getNode());
12127 if (XType.bitsGT(AType)) {
12128 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
12129 AddToWorklist(Shift.getNode());
12132 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
12136 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
12137 // where y is has a single bit set.
12138 // A plaintext description would be, we can turn the SELECT_CC into an AND
12139 // when the condition can be materialized as an all-ones register. Any
12140 // single bit-test can be materialized as an all-ones register with
12141 // shift-left and shift-right-arith.
12142 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
12143 N0->getValueType(0) == VT &&
12144 N1C && N1C->isNullValue() &&
12145 N2C && N2C->isNullValue()) {
12146 SDValue AndLHS = N0->getOperand(0);
12147 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
12148 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
12149 // Shift the tested bit over the sign bit.
12150 APInt AndMask = ConstAndRHS->getAPIntValue();
12152 DAG.getConstant(AndMask.countLeadingZeros(),
12153 getShiftAmountTy(AndLHS.getValueType()));
12154 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt);
12156 // Now arithmetic right shift it all the way over, so the result is either
12157 // all-ones, or zero.
12159 DAG.getConstant(AndMask.getBitWidth()-1,
12160 getShiftAmountTy(Shl.getValueType()));
12161 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
12163 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
12167 // fold select C, 16, 0 -> shl C, 4
12168 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
12169 TLI.getBooleanContents(N0.getValueType()) ==
12170 TargetLowering::ZeroOrOneBooleanContent) {
12172 // If the caller doesn't want us to simplify this into a zext of a compare,
12174 if (NotExtCompare && N2C->getAPIntValue() == 1)
12177 // Get a SetCC of the condition
12178 // NOTE: Don't create a SETCC if it's not legal on this target.
12179 if (!LegalOperations ||
12180 TLI.isOperationLegal(ISD::SETCC,
12181 LegalTypes ? getSetCCResultType(N0.getValueType()) : MVT::i1)) {
12183 // cast from setcc result type to select result type
12185 SCC = DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()),
12187 if (N2.getValueType().bitsLT(SCC.getValueType()))
12188 Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2),
12189 N2.getValueType());
12191 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
12192 N2.getValueType(), SCC);
12194 SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC);
12195 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
12196 N2.getValueType(), SCC);
12199 AddToWorklist(SCC.getNode());
12200 AddToWorklist(Temp.getNode());
12202 if (N2C->getAPIntValue() == 1)
12205 // shl setcc result by log2 n2c
12206 return DAG.getNode(
12207 ISD::SHL, DL, N2.getValueType(), Temp,
12208 DAG.getConstant(N2C->getAPIntValue().logBase2(),
12209 getShiftAmountTy(Temp.getValueType())));
12213 // Check to see if this is the equivalent of setcc
12214 // FIXME: Turn all of these into setcc if setcc if setcc is legal
12215 // otherwise, go ahead with the folds.
12216 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
12217 EVT XType = N0.getValueType();
12218 if (!LegalOperations ||
12219 TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(XType))) {
12220 SDValue Res = DAG.getSetCC(DL, getSetCCResultType(XType), N0, N1, CC);
12221 if (Res.getValueType() != VT)
12222 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
12226 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
12227 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
12228 (!LegalOperations ||
12229 TLI.isOperationLegal(ISD::CTLZ, XType))) {
12230 SDValue Ctlz = DAG.getNode(ISD::CTLZ, SDLoc(N0), XType, N0);
12231 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
12232 DAG.getConstant(Log2_32(XType.getSizeInBits()),
12233 getShiftAmountTy(Ctlz.getValueType())));
12235 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
12236 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
12237 SDValue NegN0 = DAG.getNode(ISD::SUB, SDLoc(N0),
12238 XType, DAG.getConstant(0, XType), N0);
12239 SDValue NotN0 = DAG.getNOT(SDLoc(N0), N0, XType);
12240 return DAG.getNode(ISD::SRL, DL, XType,
12241 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
12242 DAG.getConstant(XType.getSizeInBits()-1,
12243 getShiftAmountTy(XType)));
12245 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
12246 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
12247 SDValue Sign = DAG.getNode(ISD::SRL, SDLoc(N0), XType, N0,
12248 DAG.getConstant(XType.getSizeInBits()-1,
12249 getShiftAmountTy(N0.getValueType())));
12250 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
12254 // Check to see if this is an integer abs.
12255 // select_cc setg[te] X, 0, X, -X ->
12256 // select_cc setgt X, -1, X, -X ->
12257 // select_cc setl[te] X, 0, -X, X ->
12258 // select_cc setlt X, 1, -X, X ->
12259 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
12261 ConstantSDNode *SubC = nullptr;
12262 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
12263 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
12264 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
12265 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
12266 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
12267 (N1C->isOne() && CC == ISD::SETLT)) &&
12268 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
12269 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
12271 EVT XType = N0.getValueType();
12272 if (SubC && SubC->isNullValue() && XType.isInteger()) {
12273 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), XType,
12275 DAG.getConstant(XType.getSizeInBits()-1,
12276 getShiftAmountTy(N0.getValueType())));
12277 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0),
12279 AddToWorklist(Shift.getNode());
12280 AddToWorklist(Add.getNode());
12281 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
12288 /// This is a stub for TargetLowering::SimplifySetCC.
12289 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
12290 SDValue N1, ISD::CondCode Cond,
12291 SDLoc DL, bool foldBooleans) {
12292 TargetLowering::DAGCombinerInfo
12293 DagCombineInfo(DAG, Level, false, this);
12294 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
12297 /// Given an ISD::SDIV node expressing a divide by constant, return
12298 /// a DAG expression to select that will generate the same value by multiplying
12299 /// by a magic number.
12300 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
12301 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
12302 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
12306 // Avoid division by zero.
12307 if (!C->getAPIntValue())
12310 std::vector<SDNode*> Built;
12312 TLI.BuildSDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
12314 for (SDNode *N : Built)
12319 /// Given an ISD::SDIV node expressing a divide by constant power of 2, return a
12320 /// DAG expression that will generate the same value by right shifting.
12321 SDValue DAGCombiner::BuildSDIVPow2(SDNode *N) {
12322 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
12326 // Avoid division by zero.
12327 if (!C->getAPIntValue())
12330 std::vector<SDNode *> Built;
12331 SDValue S = TLI.BuildSDIVPow2(N, C->getAPIntValue(), DAG, &Built);
12333 for (SDNode *N : Built)
12338 /// Given an ISD::UDIV node expressing a divide by constant, return a DAG
12339 /// expression that will generate the same value by multiplying by a magic
12341 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
12342 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
12343 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
12347 // Avoid division by zero.
12348 if (!C->getAPIntValue())
12351 std::vector<SDNode*> Built;
12353 TLI.BuildUDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
12355 for (SDNode *N : Built)
12360 SDValue DAGCombiner::BuildReciprocalEstimate(SDValue Op) {
12361 if (Level >= AfterLegalizeDAG)
12364 // Expose the DAG combiner to the target combiner implementations.
12365 TargetLowering::DAGCombinerInfo DCI(DAG, Level, false, this);
12367 unsigned Iterations = 0;
12368 if (SDValue Est = TLI.getRecipEstimate(Op, DCI, Iterations)) {
12370 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
12371 // For the reciprocal, we need to find the zero of the function:
12372 // F(X) = A X - 1 [which has a zero at X = 1/A]
12374 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
12375 // does not require additional intermediate precision]
12376 EVT VT = Op.getValueType();
12378 SDValue FPOne = DAG.getConstantFP(1.0, VT);
12380 AddToWorklist(Est.getNode());
12382 // Newton iterations: Est = Est + Est (1 - Arg * Est)
12383 for (unsigned i = 0; i < Iterations; ++i) {
12384 SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Op, Est);
12385 AddToWorklist(NewEst.getNode());
12387 NewEst = DAG.getNode(ISD::FSUB, DL, VT, FPOne, NewEst);
12388 AddToWorklist(NewEst.getNode());
12390 NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst);
12391 AddToWorklist(NewEst.getNode());
12393 Est = DAG.getNode(ISD::FADD, DL, VT, Est, NewEst);
12394 AddToWorklist(Est.getNode());
12403 /// Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
12404 /// For the reciprocal sqrt, we need to find the zero of the function:
12405 /// F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
12407 /// X_{i+1} = X_i (1.5 - A X_i^2 / 2)
12408 /// As a result, we precompute A/2 prior to the iteration loop.
12409 SDValue DAGCombiner::BuildRsqrtNROneConst(SDValue Arg, SDValue Est,
12410 unsigned Iterations) {
12411 EVT VT = Arg.getValueType();
12413 SDValue ThreeHalves = DAG.getConstantFP(1.5, VT);
12415 // We now need 0.5 * Arg which we can write as (1.5 * Arg - Arg) so that
12416 // this entire sequence requires only one FP constant.
12417 SDValue HalfArg = DAG.getNode(ISD::FMUL, DL, VT, ThreeHalves, Arg);
12418 AddToWorklist(HalfArg.getNode());
12420 HalfArg = DAG.getNode(ISD::FSUB, DL, VT, HalfArg, Arg);
12421 AddToWorklist(HalfArg.getNode());
12423 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
12424 for (unsigned i = 0; i < Iterations; ++i) {
12425 SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, Est);
12426 AddToWorklist(NewEst.getNode());
12428 NewEst = DAG.getNode(ISD::FMUL, DL, VT, HalfArg, NewEst);
12429 AddToWorklist(NewEst.getNode());
12431 NewEst = DAG.getNode(ISD::FSUB, DL, VT, ThreeHalves, NewEst);
12432 AddToWorklist(NewEst.getNode());
12434 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst);
12435 AddToWorklist(Est.getNode());
12440 /// Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
12441 /// For the reciprocal sqrt, we need to find the zero of the function:
12442 /// F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
12444 /// X_{i+1} = (-0.5 * X_i) * (A * X_i * X_i + (-3.0))
12445 SDValue DAGCombiner::BuildRsqrtNRTwoConst(SDValue Arg, SDValue Est,
12446 unsigned Iterations) {
12447 EVT VT = Arg.getValueType();
12449 SDValue MinusThree = DAG.getConstantFP(-3.0, VT);
12450 SDValue MinusHalf = DAG.getConstantFP(-0.5, VT);
12452 // Newton iterations: Est = -0.5 * Est * (-3.0 + Arg * Est * Est)
12453 for (unsigned i = 0; i < Iterations; ++i) {
12454 SDValue HalfEst = DAG.getNode(ISD::FMUL, DL, VT, Est, MinusHalf);
12455 AddToWorklist(HalfEst.getNode());
12457 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, Est);
12458 AddToWorklist(Est.getNode());
12460 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, Arg);
12461 AddToWorklist(Est.getNode());
12463 Est = DAG.getNode(ISD::FADD, DL, VT, Est, MinusThree);
12464 AddToWorklist(Est.getNode());
12466 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, HalfEst);
12467 AddToWorklist(Est.getNode());
12472 SDValue DAGCombiner::BuildRsqrtEstimate(SDValue Op) {
12473 if (Level >= AfterLegalizeDAG)
12476 // Expose the DAG combiner to the target combiner implementations.
12477 TargetLowering::DAGCombinerInfo DCI(DAG, Level, false, this);
12478 unsigned Iterations = 0;
12479 bool UseOneConstNR = false;
12480 if (SDValue Est = TLI.getRsqrtEstimate(Op, DCI, Iterations, UseOneConstNR)) {
12481 AddToWorklist(Est.getNode());
12483 Est = UseOneConstNR ?
12484 BuildRsqrtNROneConst(Op, Est, Iterations) :
12485 BuildRsqrtNRTwoConst(Op, Est, Iterations);
12493 /// Return true if base is a frame index, which is known not to alias with
12494 /// anything but itself. Provides base object and offset as results.
12495 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
12496 const GlobalValue *&GV, const void *&CV) {
12497 // Assume it is a primitive operation.
12498 Base = Ptr; Offset = 0; GV = nullptr; CV = nullptr;
12500 // If it's an adding a simple constant then integrate the offset.
12501 if (Base.getOpcode() == ISD::ADD) {
12502 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
12503 Base = Base.getOperand(0);
12504 Offset += C->getZExtValue();
12508 // Return the underlying GlobalValue, and update the Offset. Return false
12509 // for GlobalAddressSDNode since the same GlobalAddress may be represented
12510 // by multiple nodes with different offsets.
12511 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
12512 GV = G->getGlobal();
12513 Offset += G->getOffset();
12517 // Return the underlying Constant value, and update the Offset. Return false
12518 // for ConstantSDNodes since the same constant pool entry may be represented
12519 // by multiple nodes with different offsets.
12520 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
12521 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal()
12522 : (const void *)C->getConstVal();
12523 Offset += C->getOffset();
12526 // If it's any of the following then it can't alias with anything but itself.
12527 return isa<FrameIndexSDNode>(Base);
12530 /// Return true if there is any possibility that the two addresses overlap.
12531 bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const {
12532 // If they are the same then they must be aliases.
12533 if (Op0->getBasePtr() == Op1->getBasePtr()) return true;
12535 // If they are both volatile then they cannot be reordered.
12536 if (Op0->isVolatile() && Op1->isVolatile()) return true;
12538 // Gather base node and offset information.
12539 SDValue Base1, Base2;
12540 int64_t Offset1, Offset2;
12541 const GlobalValue *GV1, *GV2;
12542 const void *CV1, *CV2;
12543 bool isFrameIndex1 = FindBaseOffset(Op0->getBasePtr(),
12544 Base1, Offset1, GV1, CV1);
12545 bool isFrameIndex2 = FindBaseOffset(Op1->getBasePtr(),
12546 Base2, Offset2, GV2, CV2);
12548 // If they have a same base address then check to see if they overlap.
12549 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
12550 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 ||
12551 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1);
12553 // It is possible for different frame indices to alias each other, mostly
12554 // when tail call optimization reuses return address slots for arguments.
12555 // To catch this case, look up the actual index of frame indices to compute
12556 // the real alias relationship.
12557 if (isFrameIndex1 && isFrameIndex2) {
12558 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12559 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
12560 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
12561 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 ||
12562 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1);
12565 // Otherwise, if we know what the bases are, and they aren't identical, then
12566 // we know they cannot alias.
12567 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
12570 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
12571 // compared to the size and offset of the access, we may be able to prove they
12572 // do not alias. This check is conservative for now to catch cases created by
12573 // splitting vector types.
12574 if ((Op0->getOriginalAlignment() == Op1->getOriginalAlignment()) &&
12575 (Op0->getSrcValueOffset() != Op1->getSrcValueOffset()) &&
12576 (Op0->getMemoryVT().getSizeInBits() >> 3 ==
12577 Op1->getMemoryVT().getSizeInBits() >> 3) &&
12578 (Op0->getOriginalAlignment() > Op0->getMemoryVT().getSizeInBits()) >> 3) {
12579 int64_t OffAlign1 = Op0->getSrcValueOffset() % Op0->getOriginalAlignment();
12580 int64_t OffAlign2 = Op1->getSrcValueOffset() % Op1->getOriginalAlignment();
12582 // There is no overlap between these relatively aligned accesses of similar
12583 // size, return no alias.
12584 if ((OffAlign1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign2 ||
12585 (OffAlign2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign1)
12589 bool UseAA = CombinerGlobalAA.getNumOccurrences() > 0
12591 : DAG.getSubtarget().useAA();
12593 if (CombinerAAOnlyFunc.getNumOccurrences() &&
12594 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
12598 Op0->getMemOperand()->getValue() && Op1->getMemOperand()->getValue()) {
12599 // Use alias analysis information.
12600 int64_t MinOffset = std::min(Op0->getSrcValueOffset(),
12601 Op1->getSrcValueOffset());
12602 int64_t Overlap1 = (Op0->getMemoryVT().getSizeInBits() >> 3) +
12603 Op0->getSrcValueOffset() - MinOffset;
12604 int64_t Overlap2 = (Op1->getMemoryVT().getSizeInBits() >> 3) +
12605 Op1->getSrcValueOffset() - MinOffset;
12606 AliasAnalysis::AliasResult AAResult =
12607 AA.alias(AliasAnalysis::Location(Op0->getMemOperand()->getValue(),
12609 UseTBAA ? Op0->getAAInfo() : AAMDNodes()),
12610 AliasAnalysis::Location(Op1->getMemOperand()->getValue(),
12612 UseTBAA ? Op1->getAAInfo() : AAMDNodes()));
12613 if (AAResult == AliasAnalysis::NoAlias)
12617 // Otherwise we have to assume they alias.
12621 /// Walk up chain skipping non-aliasing memory nodes,
12622 /// looking for aliasing nodes and adding them to the Aliases vector.
12623 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
12624 SmallVectorImpl<SDValue> &Aliases) {
12625 SmallVector<SDValue, 8> Chains; // List of chains to visit.
12626 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
12628 // Get alias information for node.
12629 bool IsLoad = isa<LoadSDNode>(N) && !cast<LSBaseSDNode>(N)->isVolatile();
12632 Chains.push_back(OriginalChain);
12633 unsigned Depth = 0;
12635 // Look at each chain and determine if it is an alias. If so, add it to the
12636 // aliases list. If not, then continue up the chain looking for the next
12638 while (!Chains.empty()) {
12639 SDValue Chain = Chains.back();
12642 // For TokenFactor nodes, look at each operand and only continue up the
12643 // chain until we find two aliases. If we've seen two aliases, assume we'll
12644 // find more and revert to original chain since the xform is unlikely to be
12647 // FIXME: The depth check could be made to return the last non-aliasing
12648 // chain we found before we hit a tokenfactor rather than the original
12650 if (Depth > 6 || Aliases.size() == 2) {
12652 Aliases.push_back(OriginalChain);
12656 // Don't bother if we've been before.
12657 if (!Visited.insert(Chain.getNode()).second)
12660 switch (Chain.getOpcode()) {
12661 case ISD::EntryToken:
12662 // Entry token is ideal chain operand, but handled in FindBetterChain.
12667 // Get alias information for Chain.
12668 bool IsOpLoad = isa<LoadSDNode>(Chain.getNode()) &&
12669 !cast<LSBaseSDNode>(Chain.getNode())->isVolatile();
12671 // If chain is alias then stop here.
12672 if (!(IsLoad && IsOpLoad) &&
12673 isAlias(cast<LSBaseSDNode>(N), cast<LSBaseSDNode>(Chain.getNode()))) {
12674 Aliases.push_back(Chain);
12676 // Look further up the chain.
12677 Chains.push_back(Chain.getOperand(0));
12683 case ISD::TokenFactor:
12684 // We have to check each of the operands of the token factor for "small"
12685 // token factors, so we queue them up. Adding the operands to the queue
12686 // (stack) in reverse order maintains the original order and increases the
12687 // likelihood that getNode will find a matching token factor (CSE.)
12688 if (Chain.getNumOperands() > 16) {
12689 Aliases.push_back(Chain);
12692 for (unsigned n = Chain.getNumOperands(); n;)
12693 Chains.push_back(Chain.getOperand(--n));
12698 // For all other instructions we will just have to take what we can get.
12699 Aliases.push_back(Chain);
12704 // We need to be careful here to also search for aliases through the
12705 // value operand of a store, etc. Consider the following situation:
12707 // L1 = load Token1, %52
12708 // S1 = store Token1, L1, %51
12709 // L2 = load Token1, %52+8
12710 // S2 = store Token1, L2, %51+8
12711 // Token2 = Token(S1, S2)
12712 // L3 = load Token2, %53
12713 // S3 = store Token2, L3, %52
12714 // L4 = load Token2, %53+8
12715 // S4 = store Token2, L4, %52+8
12716 // If we search for aliases of S3 (which loads address %52), and we look
12717 // only through the chain, then we'll miss the trivial dependence on L1
12718 // (which also loads from %52). We then might change all loads and
12719 // stores to use Token1 as their chain operand, which could result in
12720 // copying %53 into %52 before copying %52 into %51 (which should
12723 // The problem is, however, that searching for such data dependencies
12724 // can become expensive, and the cost is not directly related to the
12725 // chain depth. Instead, we'll rule out such configurations here by
12726 // insisting that we've visited all chain users (except for users
12727 // of the original chain, which is not necessary). When doing this,
12728 // we need to look through nodes we don't care about (otherwise, things
12729 // like register copies will interfere with trivial cases).
12731 SmallVector<const SDNode *, 16> Worklist;
12732 for (const SDNode *N : Visited)
12733 if (N != OriginalChain.getNode())
12734 Worklist.push_back(N);
12736 while (!Worklist.empty()) {
12737 const SDNode *M = Worklist.pop_back_val();
12739 // We have already visited M, and want to make sure we've visited any uses
12740 // of M that we care about. For uses that we've not visisted, and don't
12741 // care about, queue them to the worklist.
12743 for (SDNode::use_iterator UI = M->use_begin(),
12744 UIE = M->use_end(); UI != UIE; ++UI)
12745 if (UI.getUse().getValueType() == MVT::Other &&
12746 Visited.insert(*UI).second) {
12747 if (isa<MemIntrinsicSDNode>(*UI) || isa<MemSDNode>(*UI)) {
12748 // We've not visited this use, and we care about it (it could have an
12749 // ordering dependency with the original node).
12751 Aliases.push_back(OriginalChain);
12755 // We've not visited this use, but we don't care about it. Mark it as
12756 // visited and enqueue it to the worklist.
12757 Worklist.push_back(*UI);
12762 /// Walk up chain skipping non-aliasing memory nodes, looking for a better chain
12763 /// (aliasing node.)
12764 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
12765 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
12767 // Accumulate all the aliases to this node.
12768 GatherAllAliases(N, OldChain, Aliases);
12770 // If no operands then chain to entry token.
12771 if (Aliases.size() == 0)
12772 return DAG.getEntryNode();
12774 // If a single operand then chain to it. We don't need to revisit it.
12775 if (Aliases.size() == 1)
12778 // Construct a custom tailored token factor.
12779 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Aliases);
12782 /// This is the entry point for the file.
12783 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
12784 CodeGenOpt::Level OptLevel) {
12785 /// This is the main entry point to this class.
12786 DAGCombiner(*this, AA, OptLevel).Run(Level);