1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/ADT/SmallPtrSet.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
41 STATISTIC(NodesCombined , "Number of dag nodes combined");
42 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
43 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
44 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
45 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
49 CombinerAA("combiner-alias-analysis", cl::Hidden,
50 cl::desc("Turn on alias analysis during testing"));
53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
54 cl::desc("Include global information in alias analysis"));
56 //------------------------------ DAGCombiner ---------------------------------//
60 const TargetLowering &TLI;
62 CodeGenOpt::Level OptLevel;
66 // Worklist of all of the nodes that need to be simplified.
68 // This has the semantics that when adding to the worklist,
69 // the item added must be next to be processed. It should
70 // also only appear once. The naive approach to this takes
73 // To reduce the insert/remove time to logarithmic, we use
74 // a set and a vector to maintain our worklist.
76 // The set contains the items on the worklist, but does not
77 // maintain the order they should be visited.
79 // The vector maintains the order nodes should be visited, but may
80 // contain duplicate or removed nodes. When choosing a node to
81 // visit, we pop off the order stack until we find an item that is
82 // also in the contents set. All operations are O(log N).
83 SmallPtrSet<SDNode*, 64> WorkListContents;
84 SmallVector<SDNode*, 64> WorkListOrder;
86 // AA - Used for DAG load/store alias analysis.
89 /// AddUsersToWorkList - When an instruction is simplified, add all users of
90 /// the instruction to the work lists because they might get more simplified
93 void AddUsersToWorkList(SDNode *N) {
94 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
99 /// visit - call the node-specific routine that knows how to fold each
100 /// particular type of node.
101 SDValue visit(SDNode *N);
104 /// AddToWorkList - Add to the work list making sure its instance is at the
105 /// back (next to be processed.)
106 void AddToWorkList(SDNode *N) {
107 WorkListContents.insert(N);
108 WorkListOrder.push_back(N);
111 /// removeFromWorkList - remove all instances of N from the worklist.
113 void removeFromWorkList(SDNode *N) {
114 WorkListContents.erase(N);
117 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
120 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
121 return CombineTo(N, &Res, 1, AddTo);
124 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
126 SDValue To[] = { Res0, Res1 };
127 return CombineTo(N, To, 2, AddTo);
130 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
134 /// SimplifyDemandedBits - Check the specified integer node value to see if
135 /// it can be simplified or if things it uses can be simplified by bit
136 /// propagation. If so, return true.
137 bool SimplifyDemandedBits(SDValue Op) {
138 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
139 APInt Demanded = APInt::getAllOnesValue(BitWidth);
140 return SimplifyDemandedBits(Op, Demanded);
143 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
145 bool CombineToPreIndexedLoadStore(SDNode *N);
146 bool CombineToPostIndexedLoadStore(SDNode *N);
148 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
149 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
150 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
151 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
152 SDValue PromoteIntBinOp(SDValue Op);
153 SDValue PromoteIntShiftOp(SDValue Op);
154 SDValue PromoteExtend(SDValue Op);
155 bool PromoteLoad(SDValue Op);
157 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
158 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
159 ISD::NodeType ExtType);
161 /// combine - call the node-specific routine that knows how to fold each
162 /// particular type of node. If that doesn't do anything, try the
163 /// target-specific DAG combines.
164 SDValue combine(SDNode *N);
166 // Visitation implementation - Implement dag node combining for different
167 // node types. The semantics are as follows:
169 // SDValue.getNode() == 0 - No change was made
170 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
171 // otherwise - N should be replaced by the returned Operand.
173 SDValue visitTokenFactor(SDNode *N);
174 SDValue visitMERGE_VALUES(SDNode *N);
175 SDValue visitADD(SDNode *N);
176 SDValue visitSUB(SDNode *N);
177 SDValue visitADDC(SDNode *N);
178 SDValue visitSUBC(SDNode *N);
179 SDValue visitADDE(SDNode *N);
180 SDValue visitSUBE(SDNode *N);
181 SDValue visitMUL(SDNode *N);
182 SDValue visitSDIV(SDNode *N);
183 SDValue visitUDIV(SDNode *N);
184 SDValue visitSREM(SDNode *N);
185 SDValue visitUREM(SDNode *N);
186 SDValue visitMULHU(SDNode *N);
187 SDValue visitMULHS(SDNode *N);
188 SDValue visitSMUL_LOHI(SDNode *N);
189 SDValue visitUMUL_LOHI(SDNode *N);
190 SDValue visitSMULO(SDNode *N);
191 SDValue visitUMULO(SDNode *N);
192 SDValue visitSDIVREM(SDNode *N);
193 SDValue visitUDIVREM(SDNode *N);
194 SDValue visitAND(SDNode *N);
195 SDValue visitOR(SDNode *N);
196 SDValue visitXOR(SDNode *N);
197 SDValue SimplifyVBinOp(SDNode *N);
198 SDValue SimplifyVUnaryOp(SDNode *N);
199 SDValue visitSHL(SDNode *N);
200 SDValue visitSRA(SDNode *N);
201 SDValue visitSRL(SDNode *N);
202 SDValue visitCTLZ(SDNode *N);
203 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
204 SDValue visitCTTZ(SDNode *N);
205 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
206 SDValue visitCTPOP(SDNode *N);
207 SDValue visitSELECT(SDNode *N);
208 SDValue visitSELECT_CC(SDNode *N);
209 SDValue visitSETCC(SDNode *N);
210 SDValue visitSIGN_EXTEND(SDNode *N);
211 SDValue visitZERO_EXTEND(SDNode *N);
212 SDValue visitANY_EXTEND(SDNode *N);
213 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
214 SDValue visitTRUNCATE(SDNode *N);
215 SDValue visitBITCAST(SDNode *N);
216 SDValue visitBUILD_PAIR(SDNode *N);
217 SDValue visitFADD(SDNode *N);
218 SDValue visitFSUB(SDNode *N);
219 SDValue visitFMUL(SDNode *N);
220 SDValue visitFMA(SDNode *N);
221 SDValue visitFDIV(SDNode *N);
222 SDValue visitFREM(SDNode *N);
223 SDValue visitFCOPYSIGN(SDNode *N);
224 SDValue visitSINT_TO_FP(SDNode *N);
225 SDValue visitUINT_TO_FP(SDNode *N);
226 SDValue visitFP_TO_SINT(SDNode *N);
227 SDValue visitFP_TO_UINT(SDNode *N);
228 SDValue visitFP_ROUND(SDNode *N);
229 SDValue visitFP_ROUND_INREG(SDNode *N);
230 SDValue visitFP_EXTEND(SDNode *N);
231 SDValue visitFNEG(SDNode *N);
232 SDValue visitFABS(SDNode *N);
233 SDValue visitFCEIL(SDNode *N);
234 SDValue visitFTRUNC(SDNode *N);
235 SDValue visitFFLOOR(SDNode *N);
236 SDValue visitBRCOND(SDNode *N);
237 SDValue visitBR_CC(SDNode *N);
238 SDValue visitLOAD(SDNode *N);
239 SDValue visitSTORE(SDNode *N);
240 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
241 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
242 SDValue visitBUILD_VECTOR(SDNode *N);
243 SDValue visitCONCAT_VECTORS(SDNode *N);
244 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
245 SDValue visitVECTOR_SHUFFLE(SDNode *N);
246 SDValue visitMEMBARRIER(SDNode *N);
248 SDValue XformToShuffleWithZero(SDNode *N);
249 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
251 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
253 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
254 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
255 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
256 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
257 SDValue N3, ISD::CondCode CC,
258 bool NotExtCompare = false);
259 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
260 DebugLoc DL, bool foldBooleans = true);
261 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
263 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
264 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
265 SDValue BuildSDIV(SDNode *N);
266 SDValue BuildUDIV(SDNode *N);
267 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
268 bool DemandHighBits = true);
269 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
270 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
271 SDValue ReduceLoadWidth(SDNode *N);
272 SDValue ReduceLoadOpStoreWidth(SDNode *N);
273 SDValue TransformFPLoadStorePair(SDNode *N);
274 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
275 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N);
277 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
279 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
280 /// looking for aliasing nodes and adding them to the Aliases vector.
281 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
282 SmallVector<SDValue, 8> &Aliases);
284 /// isAlias - Return true if there is any possibility that the two addresses
286 bool isAlias(SDValue Ptr1, int64_t Size1,
287 const Value *SrcValue1, int SrcValueOffset1,
288 unsigned SrcValueAlign1,
289 const MDNode *TBAAInfo1,
290 SDValue Ptr2, int64_t Size2,
291 const Value *SrcValue2, int SrcValueOffset2,
292 unsigned SrcValueAlign2,
293 const MDNode *TBAAInfo2) const;
295 /// isAlias - Return true if there is any possibility that the two addresses
297 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1);
299 /// FindAliasInfo - Extracts the relevant alias information from the memory
300 /// node. Returns true if the operand was a load.
301 bool FindAliasInfo(SDNode *N,
302 SDValue &Ptr, int64_t &Size,
303 const Value *&SrcValue, int &SrcValueOffset,
304 unsigned &SrcValueAlignment,
305 const MDNode *&TBAAInfo) const;
307 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
308 /// looking for a better chain (aliasing node.)
309 SDValue FindBetterChain(SDNode *N, SDValue Chain);
311 /// Merge consecutive store operations into a wide store.
312 /// This optimization uses wide integers or vectors when possible.
313 /// \return True if some memory operations were changed.
314 bool MergeConsecutiveStores(StoreSDNode *N);
317 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
318 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
319 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
321 /// Run - runs the dag combiner on all nodes in the work list
322 void Run(CombineLevel AtLevel);
324 SelectionDAG &getDAG() const { return DAG; }
326 /// getShiftAmountTy - Returns a type large enough to hold any valid
327 /// shift amount - before type legalization these can be huge.
328 EVT getShiftAmountTy(EVT LHSTy) {
329 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy();
332 /// isTypeLegal - This method returns true if we are running before type
333 /// legalization or if the specified VT is legal.
334 bool isTypeLegal(const EVT &VT) {
335 if (!LegalTypes) return true;
336 return TLI.isTypeLegal(VT);
343 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
344 /// nodes from the worklist.
345 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
348 explicit WorkListRemover(DAGCombiner &dc)
349 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
351 virtual void NodeDeleted(SDNode *N, SDNode *E) {
352 DC.removeFromWorkList(N);
357 //===----------------------------------------------------------------------===//
358 // TargetLowering::DAGCombinerInfo implementation
359 //===----------------------------------------------------------------------===//
361 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
362 ((DAGCombiner*)DC)->AddToWorkList(N);
365 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
366 ((DAGCombiner*)DC)->removeFromWorkList(N);
369 SDValue TargetLowering::DAGCombinerInfo::
370 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
371 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
374 SDValue TargetLowering::DAGCombinerInfo::
375 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
376 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
380 SDValue TargetLowering::DAGCombinerInfo::
381 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
382 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
385 void TargetLowering::DAGCombinerInfo::
386 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
387 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
390 //===----------------------------------------------------------------------===//
392 //===----------------------------------------------------------------------===//
394 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
395 /// specified expression for the same cost as the expression itself, or 2 if we
396 /// can compute the negated form more cheaply than the expression itself.
397 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
398 const TargetLowering &TLI,
399 const TargetOptions *Options,
400 unsigned Depth = 0) {
401 // fneg is removable even if it has multiple uses.
402 if (Op.getOpcode() == ISD::FNEG) return 2;
404 // Don't allow anything with multiple uses.
405 if (!Op.hasOneUse()) return 0;
407 // Don't recurse exponentially.
408 if (Depth > 6) return 0;
410 switch (Op.getOpcode()) {
411 default: return false;
412 case ISD::ConstantFP:
413 // Don't invert constant FP values after legalize. The negated constant
414 // isn't necessarily legal.
415 return LegalOperations ? 0 : 1;
417 // FIXME: determine better conditions for this xform.
418 if (!Options->UnsafeFPMath) return 0;
420 // After operation legalization, it might not be legal to create new FSUBs.
421 if (LegalOperations &&
422 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
425 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
426 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
429 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
430 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
433 // We can't turn -(A-B) into B-A when we honor signed zeros.
434 if (!Options->UnsafeFPMath) return 0;
436 // fold (fneg (fsub A, B)) -> (fsub B, A)
441 if (Options->HonorSignDependentRoundingFPMath()) return 0;
443 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
444 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
448 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
454 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
459 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
460 /// returns the newly negated expression.
461 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
462 bool LegalOperations, unsigned Depth = 0) {
463 // fneg is removable even if it has multiple uses.
464 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
466 // Don't allow anything with multiple uses.
467 assert(Op.hasOneUse() && "Unknown reuse!");
469 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
470 switch (Op.getOpcode()) {
471 default: llvm_unreachable("Unknown code");
472 case ISD::ConstantFP: {
473 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
475 return DAG.getConstantFP(V, Op.getValueType());
478 // FIXME: determine better conditions for this xform.
479 assert(DAG.getTarget().Options.UnsafeFPMath);
481 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
482 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
483 DAG.getTargetLoweringInfo(),
484 &DAG.getTarget().Options, Depth+1))
485 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
486 GetNegatedExpression(Op.getOperand(0), DAG,
487 LegalOperations, Depth+1),
489 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
490 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
491 GetNegatedExpression(Op.getOperand(1), DAG,
492 LegalOperations, Depth+1),
495 // We can't turn -(A-B) into B-A when we honor signed zeros.
496 assert(DAG.getTarget().Options.UnsafeFPMath);
498 // fold (fneg (fsub 0, B)) -> B
499 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
500 if (N0CFP->getValueAPF().isZero())
501 return Op.getOperand(1);
503 // fold (fneg (fsub A, B)) -> (fsub B, A)
504 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
505 Op.getOperand(1), Op.getOperand(0));
509 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath());
511 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
512 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
513 DAG.getTargetLoweringInfo(),
514 &DAG.getTarget().Options, Depth+1))
515 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
516 GetNegatedExpression(Op.getOperand(0), DAG,
517 LegalOperations, Depth+1),
520 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
521 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
523 GetNegatedExpression(Op.getOperand(1), DAG,
524 LegalOperations, Depth+1));
528 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
529 GetNegatedExpression(Op.getOperand(0), DAG,
530 LegalOperations, Depth+1));
532 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
533 GetNegatedExpression(Op.getOperand(0), DAG,
534 LegalOperations, Depth+1),
540 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
541 // that selects between the values 1 and 0, making it equivalent to a setcc.
542 // Also, set the incoming LHS, RHS, and CC references to the appropriate
543 // nodes based on the type of node we are checking. This simplifies life a
544 // bit for the callers.
545 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
547 if (N.getOpcode() == ISD::SETCC) {
548 LHS = N.getOperand(0);
549 RHS = N.getOperand(1);
550 CC = N.getOperand(2);
553 if (N.getOpcode() == ISD::SELECT_CC &&
554 N.getOperand(2).getOpcode() == ISD::Constant &&
555 N.getOperand(3).getOpcode() == ISD::Constant &&
556 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
557 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
558 LHS = N.getOperand(0);
559 RHS = N.getOperand(1);
560 CC = N.getOperand(4);
566 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
567 // one use. If this is true, it allows the users to invert the operation for
568 // free when it is profitable to do so.
569 static bool isOneUseSetCC(SDValue N) {
571 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
576 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
577 SDValue N0, SDValue N1) {
578 EVT VT = N0.getValueType();
579 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
580 if (isa<ConstantSDNode>(N1)) {
581 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
583 DAG.FoldConstantArithmetic(Opc, VT,
584 cast<ConstantSDNode>(N0.getOperand(1)),
585 cast<ConstantSDNode>(N1));
586 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
588 if (N0.hasOneUse()) {
589 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
590 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
591 N0.getOperand(0), N1);
592 AddToWorkList(OpNode.getNode());
593 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
597 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
598 if (isa<ConstantSDNode>(N0)) {
599 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
601 DAG.FoldConstantArithmetic(Opc, VT,
602 cast<ConstantSDNode>(N1.getOperand(1)),
603 cast<ConstantSDNode>(N0));
604 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
606 if (N1.hasOneUse()) {
607 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
608 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
609 N1.getOperand(0), N0);
610 AddToWorkList(OpNode.getNode());
611 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
618 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
620 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
622 DEBUG(dbgs() << "\nReplacing.1 ";
624 dbgs() << "\nWith: ";
625 To[0].getNode()->dump(&DAG);
626 dbgs() << " and " << NumTo-1 << " other values\n";
627 for (unsigned i = 0, e = NumTo; i != e; ++i)
628 assert((!To[i].getNode() ||
629 N->getValueType(i) == To[i].getValueType()) &&
630 "Cannot combine value to value of different type!"));
631 WorkListRemover DeadNodes(*this);
632 DAG.ReplaceAllUsesWith(N, To);
634 // Push the new nodes and any users onto the worklist
635 for (unsigned i = 0, e = NumTo; i != e; ++i) {
636 if (To[i].getNode()) {
637 AddToWorkList(To[i].getNode());
638 AddUsersToWorkList(To[i].getNode());
643 // Finally, if the node is now dead, remove it from the graph. The node
644 // may not be dead if the replacement process recursively simplified to
645 // something else needing this node.
646 if (N->use_empty()) {
647 // Nodes can be reintroduced into the worklist. Make sure we do not
648 // process a node that has been replaced.
649 removeFromWorkList(N);
651 // Finally, since the node is now dead, remove it from the graph.
654 return SDValue(N, 0);
658 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
659 // Replace all uses. If any nodes become isomorphic to other nodes and
660 // are deleted, make sure to remove them from our worklist.
661 WorkListRemover DeadNodes(*this);
662 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
664 // Push the new node and any (possibly new) users onto the worklist.
665 AddToWorkList(TLO.New.getNode());
666 AddUsersToWorkList(TLO.New.getNode());
668 // Finally, if the node is now dead, remove it from the graph. The node
669 // may not be dead if the replacement process recursively simplified to
670 // something else needing this node.
671 if (TLO.Old.getNode()->use_empty()) {
672 removeFromWorkList(TLO.Old.getNode());
674 // If the operands of this node are only used by the node, they will now
675 // be dead. Make sure to visit them first to delete dead nodes early.
676 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
677 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
678 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
680 DAG.DeleteNode(TLO.Old.getNode());
684 /// SimplifyDemandedBits - Check the specified integer node value to see if
685 /// it can be simplified or if things it uses can be simplified by bit
686 /// propagation. If so, return true.
687 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
688 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
689 APInt KnownZero, KnownOne;
690 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
694 AddToWorkList(Op.getNode());
696 // Replace the old value with the new one.
698 DEBUG(dbgs() << "\nReplacing.2 ";
699 TLO.Old.getNode()->dump(&DAG);
700 dbgs() << "\nWith: ";
701 TLO.New.getNode()->dump(&DAG);
704 CommitTargetLoweringOpt(TLO);
708 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
709 DebugLoc dl = Load->getDebugLoc();
710 EVT VT = Load->getValueType(0);
711 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
713 DEBUG(dbgs() << "\nReplacing.9 ";
715 dbgs() << "\nWith: ";
716 Trunc.getNode()->dump(&DAG);
718 WorkListRemover DeadNodes(*this);
719 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
720 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
721 removeFromWorkList(Load);
722 DAG.DeleteNode(Load);
723 AddToWorkList(Trunc.getNode());
726 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
728 DebugLoc dl = Op.getDebugLoc();
729 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
730 EVT MemVT = LD->getMemoryVT();
731 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
732 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
734 : LD->getExtensionType();
736 return DAG.getExtLoad(ExtType, dl, PVT,
737 LD->getChain(), LD->getBasePtr(),
738 LD->getPointerInfo(),
739 MemVT, LD->isVolatile(),
740 LD->isNonTemporal(), LD->getAlignment());
743 unsigned Opc = Op.getOpcode();
746 case ISD::AssertSext:
747 return DAG.getNode(ISD::AssertSext, dl, PVT,
748 SExtPromoteOperand(Op.getOperand(0), PVT),
750 case ISD::AssertZext:
751 return DAG.getNode(ISD::AssertZext, dl, PVT,
752 ZExtPromoteOperand(Op.getOperand(0), PVT),
754 case ISD::Constant: {
756 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
757 return DAG.getNode(ExtOpc, dl, PVT, Op);
761 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
763 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
766 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
767 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
769 EVT OldVT = Op.getValueType();
770 DebugLoc dl = Op.getDebugLoc();
771 bool Replace = false;
772 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
773 if (NewOp.getNode() == 0)
775 AddToWorkList(NewOp.getNode());
778 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
779 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
780 DAG.getValueType(OldVT));
783 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
784 EVT OldVT = Op.getValueType();
785 DebugLoc dl = Op.getDebugLoc();
786 bool Replace = false;
787 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
788 if (NewOp.getNode() == 0)
790 AddToWorkList(NewOp.getNode());
793 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
794 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
797 /// PromoteIntBinOp - Promote the specified integer binary operation if the
798 /// target indicates it is beneficial. e.g. On x86, it's usually better to
799 /// promote i16 operations to i32 since i16 instructions are longer.
800 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
801 if (!LegalOperations)
804 EVT VT = Op.getValueType();
805 if (VT.isVector() || !VT.isInteger())
808 // If operation type is 'undesirable', e.g. i16 on x86, consider
810 unsigned Opc = Op.getOpcode();
811 if (TLI.isTypeDesirableForOp(Opc, VT))
815 // Consult target whether it is a good idea to promote this operation and
816 // what's the right type to promote it to.
817 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
818 assert(PVT != VT && "Don't know what type to promote to!");
820 bool Replace0 = false;
821 SDValue N0 = Op.getOperand(0);
822 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
823 if (NN0.getNode() == 0)
826 bool Replace1 = false;
827 SDValue N1 = Op.getOperand(1);
832 NN1 = PromoteOperand(N1, PVT, Replace1);
833 if (NN1.getNode() == 0)
837 AddToWorkList(NN0.getNode());
839 AddToWorkList(NN1.getNode());
842 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
844 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
846 DEBUG(dbgs() << "\nPromoting ";
847 Op.getNode()->dump(&DAG));
848 DebugLoc dl = Op.getDebugLoc();
849 return DAG.getNode(ISD::TRUNCATE, dl, VT,
850 DAG.getNode(Opc, dl, PVT, NN0, NN1));
855 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
856 /// target indicates it is beneficial. e.g. On x86, it's usually better to
857 /// promote i16 operations to i32 since i16 instructions are longer.
858 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
859 if (!LegalOperations)
862 EVT VT = Op.getValueType();
863 if (VT.isVector() || !VT.isInteger())
866 // If operation type is 'undesirable', e.g. i16 on x86, consider
868 unsigned Opc = Op.getOpcode();
869 if (TLI.isTypeDesirableForOp(Opc, VT))
873 // Consult target whether it is a good idea to promote this operation and
874 // what's the right type to promote it to.
875 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
876 assert(PVT != VT && "Don't know what type to promote to!");
878 bool Replace = false;
879 SDValue N0 = Op.getOperand(0);
881 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
882 else if (Opc == ISD::SRL)
883 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
885 N0 = PromoteOperand(N0, PVT, Replace);
886 if (N0.getNode() == 0)
889 AddToWorkList(N0.getNode());
891 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
893 DEBUG(dbgs() << "\nPromoting ";
894 Op.getNode()->dump(&DAG));
895 DebugLoc dl = Op.getDebugLoc();
896 return DAG.getNode(ISD::TRUNCATE, dl, VT,
897 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
902 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
903 if (!LegalOperations)
906 EVT VT = Op.getValueType();
907 if (VT.isVector() || !VT.isInteger())
910 // If operation type is 'undesirable', e.g. i16 on x86, consider
912 unsigned Opc = Op.getOpcode();
913 if (TLI.isTypeDesirableForOp(Opc, VT))
917 // Consult target whether it is a good idea to promote this operation and
918 // what's the right type to promote it to.
919 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
920 assert(PVT != VT && "Don't know what type to promote to!");
921 // fold (aext (aext x)) -> (aext x)
922 // fold (aext (zext x)) -> (zext x)
923 // fold (aext (sext x)) -> (sext x)
924 DEBUG(dbgs() << "\nPromoting ";
925 Op.getNode()->dump(&DAG));
926 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
931 bool DAGCombiner::PromoteLoad(SDValue Op) {
932 if (!LegalOperations)
935 EVT VT = Op.getValueType();
936 if (VT.isVector() || !VT.isInteger())
939 // If operation type is 'undesirable', e.g. i16 on x86, consider
941 unsigned Opc = Op.getOpcode();
942 if (TLI.isTypeDesirableForOp(Opc, VT))
946 // Consult target whether it is a good idea to promote this operation and
947 // what's the right type to promote it to.
948 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
949 assert(PVT != VT && "Don't know what type to promote to!");
951 DebugLoc dl = Op.getDebugLoc();
952 SDNode *N = Op.getNode();
953 LoadSDNode *LD = cast<LoadSDNode>(N);
954 EVT MemVT = LD->getMemoryVT();
955 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
956 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
958 : LD->getExtensionType();
959 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
960 LD->getChain(), LD->getBasePtr(),
961 LD->getPointerInfo(),
962 MemVT, LD->isVolatile(),
963 LD->isNonTemporal(), LD->getAlignment());
964 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
966 DEBUG(dbgs() << "\nPromoting ";
969 Result.getNode()->dump(&DAG);
971 WorkListRemover DeadNodes(*this);
972 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
973 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
974 removeFromWorkList(N);
976 AddToWorkList(Result.getNode());
983 //===----------------------------------------------------------------------===//
984 // Main DAG Combiner implementation
985 //===----------------------------------------------------------------------===//
987 void DAGCombiner::Run(CombineLevel AtLevel) {
988 // set the instance variables, so that the various visit routines may use it.
990 LegalOperations = Level >= AfterLegalizeVectorOps;
991 LegalTypes = Level >= AfterLegalizeTypes;
993 // Add all the dag nodes to the worklist.
994 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
995 E = DAG.allnodes_end(); I != E; ++I)
998 // Create a dummy node (which is not added to allnodes), that adds a reference
999 // to the root node, preventing it from being deleted, and tracking any
1000 // changes of the root.
1001 HandleSDNode Dummy(DAG.getRoot());
1003 // The root of the dag may dangle to deleted nodes until the dag combiner is
1004 // done. Set it to null to avoid confusion.
1005 DAG.setRoot(SDValue());
1007 // while the worklist isn't empty, find a node and
1008 // try and combine it.
1009 while (!WorkListContents.empty()) {
1011 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates.
1012 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the
1013 // worklist *should* contain, and check the node we want to visit is should
1014 // actually be visited.
1016 N = WorkListOrder.pop_back_val();
1017 } while (!WorkListContents.erase(N));
1019 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1020 // N is deleted from the DAG, since they too may now be dead or may have a
1021 // reduced number of uses, allowing other xforms.
1022 if (N->use_empty() && N != &Dummy) {
1023 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1024 AddToWorkList(N->getOperand(i).getNode());
1030 SDValue RV = combine(N);
1032 if (RV.getNode() == 0)
1037 // If we get back the same node we passed in, rather than a new node or
1038 // zero, we know that the node must have defined multiple values and
1039 // CombineTo was used. Since CombineTo takes care of the worklist
1040 // mechanics for us, we have no work to do in this case.
1041 if (RV.getNode() == N)
1044 assert(N->getOpcode() != ISD::DELETED_NODE &&
1045 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1046 "Node was deleted but visit returned new node!");
1048 DEBUG(dbgs() << "\nReplacing.3 ";
1050 dbgs() << "\nWith: ";
1051 RV.getNode()->dump(&DAG);
1054 // Transfer debug value.
1055 DAG.TransferDbgValues(SDValue(N, 0), RV);
1056 WorkListRemover DeadNodes(*this);
1057 if (N->getNumValues() == RV.getNode()->getNumValues())
1058 DAG.ReplaceAllUsesWith(N, RV.getNode());
1060 assert(N->getValueType(0) == RV.getValueType() &&
1061 N->getNumValues() == 1 && "Type mismatch");
1063 DAG.ReplaceAllUsesWith(N, &OpV);
1066 // Push the new node and any users onto the worklist
1067 AddToWorkList(RV.getNode());
1068 AddUsersToWorkList(RV.getNode());
1070 // Add any uses of the old node to the worklist in case this node is the
1071 // last one that uses them. They may become dead after this node is
1073 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1074 AddToWorkList(N->getOperand(i).getNode());
1076 // Finally, if the node is now dead, remove it from the graph. The node
1077 // may not be dead if the replacement process recursively simplified to
1078 // something else needing this node.
1079 if (N->use_empty()) {
1080 // Nodes can be reintroduced into the worklist. Make sure we do not
1081 // process a node that has been replaced.
1082 removeFromWorkList(N);
1084 // Finally, since the node is now dead, remove it from the graph.
1089 // If the root changed (e.g. it was a dead load, update the root).
1090 DAG.setRoot(Dummy.getValue());
1091 DAG.RemoveDeadNodes();
1094 SDValue DAGCombiner::visit(SDNode *N) {
1095 switch (N->getOpcode()) {
1097 case ISD::TokenFactor: return visitTokenFactor(N);
1098 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1099 case ISD::ADD: return visitADD(N);
1100 case ISD::SUB: return visitSUB(N);
1101 case ISD::ADDC: return visitADDC(N);
1102 case ISD::SUBC: return visitSUBC(N);
1103 case ISD::ADDE: return visitADDE(N);
1104 case ISD::SUBE: return visitSUBE(N);
1105 case ISD::MUL: return visitMUL(N);
1106 case ISD::SDIV: return visitSDIV(N);
1107 case ISD::UDIV: return visitUDIV(N);
1108 case ISD::SREM: return visitSREM(N);
1109 case ISD::UREM: return visitUREM(N);
1110 case ISD::MULHU: return visitMULHU(N);
1111 case ISD::MULHS: return visitMULHS(N);
1112 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1113 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1114 case ISD::SMULO: return visitSMULO(N);
1115 case ISD::UMULO: return visitUMULO(N);
1116 case ISD::SDIVREM: return visitSDIVREM(N);
1117 case ISD::UDIVREM: return visitUDIVREM(N);
1118 case ISD::AND: return visitAND(N);
1119 case ISD::OR: return visitOR(N);
1120 case ISD::XOR: return visitXOR(N);
1121 case ISD::SHL: return visitSHL(N);
1122 case ISD::SRA: return visitSRA(N);
1123 case ISD::SRL: return visitSRL(N);
1124 case ISD::CTLZ: return visitCTLZ(N);
1125 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1126 case ISD::CTTZ: return visitCTTZ(N);
1127 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1128 case ISD::CTPOP: return visitCTPOP(N);
1129 case ISD::SELECT: return visitSELECT(N);
1130 case ISD::SELECT_CC: return visitSELECT_CC(N);
1131 case ISD::SETCC: return visitSETCC(N);
1132 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1133 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1134 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1135 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1136 case ISD::TRUNCATE: return visitTRUNCATE(N);
1137 case ISD::BITCAST: return visitBITCAST(N);
1138 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1139 case ISD::FADD: return visitFADD(N);
1140 case ISD::FSUB: return visitFSUB(N);
1141 case ISD::FMUL: return visitFMUL(N);
1142 case ISD::FMA: return visitFMA(N);
1143 case ISD::FDIV: return visitFDIV(N);
1144 case ISD::FREM: return visitFREM(N);
1145 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1146 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1147 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1148 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1149 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1150 case ISD::FP_ROUND: return visitFP_ROUND(N);
1151 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1152 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1153 case ISD::FNEG: return visitFNEG(N);
1154 case ISD::FABS: return visitFABS(N);
1155 case ISD::FFLOOR: return visitFFLOOR(N);
1156 case ISD::FCEIL: return visitFCEIL(N);
1157 case ISD::FTRUNC: return visitFTRUNC(N);
1158 case ISD::BRCOND: return visitBRCOND(N);
1159 case ISD::BR_CC: return visitBR_CC(N);
1160 case ISD::LOAD: return visitLOAD(N);
1161 case ISD::STORE: return visitSTORE(N);
1162 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1163 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1164 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1165 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1166 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1167 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1168 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1173 SDValue DAGCombiner::combine(SDNode *N) {
1174 SDValue RV = visit(N);
1176 // If nothing happened, try a target-specific DAG combine.
1177 if (RV.getNode() == 0) {
1178 assert(N->getOpcode() != ISD::DELETED_NODE &&
1179 "Node was deleted but visit returned NULL!");
1181 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1182 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1184 // Expose the DAG combiner to the target combiner impls.
1185 TargetLowering::DAGCombinerInfo
1186 DagCombineInfo(DAG, Level, false, this);
1188 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1192 // If nothing happened still, try promoting the operation.
1193 if (RV.getNode() == 0) {
1194 switch (N->getOpcode()) {
1202 RV = PromoteIntBinOp(SDValue(N, 0));
1207 RV = PromoteIntShiftOp(SDValue(N, 0));
1209 case ISD::SIGN_EXTEND:
1210 case ISD::ZERO_EXTEND:
1211 case ISD::ANY_EXTEND:
1212 RV = PromoteExtend(SDValue(N, 0));
1215 if (PromoteLoad(SDValue(N, 0)))
1221 // If N is a commutative binary node, try commuting it to enable more
1223 if (RV.getNode() == 0 &&
1224 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1225 N->getNumValues() == 1) {
1226 SDValue N0 = N->getOperand(0);
1227 SDValue N1 = N->getOperand(1);
1229 // Constant operands are canonicalized to RHS.
1230 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1231 SDValue Ops[] = { N1, N0 };
1232 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1235 return SDValue(CSENode, 0);
1242 /// getInputChainForNode - Given a node, return its input chain if it has one,
1243 /// otherwise return a null sd operand.
1244 static SDValue getInputChainForNode(SDNode *N) {
1245 if (unsigned NumOps = N->getNumOperands()) {
1246 if (N->getOperand(0).getValueType() == MVT::Other)
1247 return N->getOperand(0);
1248 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1249 return N->getOperand(NumOps-1);
1250 for (unsigned i = 1; i < NumOps-1; ++i)
1251 if (N->getOperand(i).getValueType() == MVT::Other)
1252 return N->getOperand(i);
1257 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1258 // If N has two operands, where one has an input chain equal to the other,
1259 // the 'other' chain is redundant.
1260 if (N->getNumOperands() == 2) {
1261 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1262 return N->getOperand(0);
1263 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1264 return N->getOperand(1);
1267 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1268 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1269 SmallPtrSet<SDNode*, 16> SeenOps;
1270 bool Changed = false; // If we should replace this token factor.
1272 // Start out with this token factor.
1275 // Iterate through token factors. The TFs grows when new token factors are
1277 for (unsigned i = 0; i < TFs.size(); ++i) {
1278 SDNode *TF = TFs[i];
1280 // Check each of the operands.
1281 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1282 SDValue Op = TF->getOperand(i);
1284 switch (Op.getOpcode()) {
1285 case ISD::EntryToken:
1286 // Entry tokens don't need to be added to the list. They are
1291 case ISD::TokenFactor:
1292 if (Op.hasOneUse() &&
1293 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1294 // Queue up for processing.
1295 TFs.push_back(Op.getNode());
1296 // Clean up in case the token factor is removed.
1297 AddToWorkList(Op.getNode());
1304 // Only add if it isn't already in the list.
1305 if (SeenOps.insert(Op.getNode()))
1316 // If we've change things around then replace token factor.
1319 // The entry token is the only possible outcome.
1320 Result = DAG.getEntryNode();
1322 // New and improved token factor.
1323 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1324 MVT::Other, &Ops[0], Ops.size());
1327 // Don't add users to work list.
1328 return CombineTo(N, Result, false);
1334 /// MERGE_VALUES can always be eliminated.
1335 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1336 WorkListRemover DeadNodes(*this);
1337 // Replacing results may cause a different MERGE_VALUES to suddenly
1338 // be CSE'd with N, and carry its uses with it. Iterate until no
1339 // uses remain, to ensure that the node can be safely deleted.
1340 // First add the users of this node to the work list so that they
1341 // can be tried again once they have new operands.
1342 AddUsersToWorkList(N);
1344 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1345 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1346 } while (!N->use_empty());
1347 removeFromWorkList(N);
1349 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1353 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1354 SelectionDAG &DAG) {
1355 EVT VT = N0.getValueType();
1356 SDValue N00 = N0.getOperand(0);
1357 SDValue N01 = N0.getOperand(1);
1358 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1360 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1361 isa<ConstantSDNode>(N00.getOperand(1))) {
1362 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1363 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1364 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1365 N00.getOperand(0), N01),
1366 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1367 N00.getOperand(1), N01));
1368 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1374 SDValue DAGCombiner::visitADD(SDNode *N) {
1375 SDValue N0 = N->getOperand(0);
1376 SDValue N1 = N->getOperand(1);
1377 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1378 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1379 EVT VT = N0.getValueType();
1382 if (VT.isVector()) {
1383 SDValue FoldedVOp = SimplifyVBinOp(N);
1384 if (FoldedVOp.getNode()) return FoldedVOp;
1386 // fold (add x, 0) -> x, vector edition
1387 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1389 if (ISD::isBuildVectorAllZeros(N0.getNode()))
1393 // fold (add x, undef) -> undef
1394 if (N0.getOpcode() == ISD::UNDEF)
1396 if (N1.getOpcode() == ISD::UNDEF)
1398 // fold (add c1, c2) -> c1+c2
1400 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1401 // canonicalize constant to RHS
1403 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1404 // fold (add x, 0) -> x
1405 if (N1C && N1C->isNullValue())
1407 // fold (add Sym, c) -> Sym+c
1408 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1409 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1410 GA->getOpcode() == ISD::GlobalAddress)
1411 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1413 (uint64_t)N1C->getSExtValue());
1414 // fold ((c1-A)+c2) -> (c1+c2)-A
1415 if (N1C && N0.getOpcode() == ISD::SUB)
1416 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1417 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1418 DAG.getConstant(N1C->getAPIntValue()+
1419 N0C->getAPIntValue(), VT),
1422 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1423 if (RADD.getNode() != 0)
1425 // fold ((0-A) + B) -> B-A
1426 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1427 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1428 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1429 // fold (A + (0-B)) -> A-B
1430 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1431 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1432 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1433 // fold (A+(B-A)) -> B
1434 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1435 return N1.getOperand(0);
1436 // fold ((B-A)+A) -> B
1437 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1438 return N0.getOperand(0);
1439 // fold (A+(B-(A+C))) to (B-C)
1440 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1441 N0 == N1.getOperand(1).getOperand(0))
1442 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1443 N1.getOperand(1).getOperand(1));
1444 // fold (A+(B-(C+A))) to (B-C)
1445 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1446 N0 == N1.getOperand(1).getOperand(1))
1447 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1448 N1.getOperand(1).getOperand(0));
1449 // fold (A+((B-A)+or-C)) to (B+or-C)
1450 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1451 N1.getOperand(0).getOpcode() == ISD::SUB &&
1452 N0 == N1.getOperand(0).getOperand(1))
1453 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1454 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1456 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1457 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1458 SDValue N00 = N0.getOperand(0);
1459 SDValue N01 = N0.getOperand(1);
1460 SDValue N10 = N1.getOperand(0);
1461 SDValue N11 = N1.getOperand(1);
1463 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1464 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1465 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1466 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1469 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1470 return SDValue(N, 0);
1472 // fold (a+b) -> (a|b) iff a and b share no bits.
1473 if (VT.isInteger() && !VT.isVector()) {
1474 APInt LHSZero, LHSOne;
1475 APInt RHSZero, RHSOne;
1476 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1478 if (LHSZero.getBoolValue()) {
1479 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1481 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1482 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1483 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1484 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1488 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1489 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1490 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1491 if (Result.getNode()) return Result;
1493 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1494 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1495 if (Result.getNode()) return Result;
1498 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1499 if (N1.getOpcode() == ISD::SHL &&
1500 N1.getOperand(0).getOpcode() == ISD::SUB)
1501 if (ConstantSDNode *C =
1502 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1503 if (C->getAPIntValue() == 0)
1504 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1505 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1506 N1.getOperand(0).getOperand(1),
1508 if (N0.getOpcode() == ISD::SHL &&
1509 N0.getOperand(0).getOpcode() == ISD::SUB)
1510 if (ConstantSDNode *C =
1511 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1512 if (C->getAPIntValue() == 0)
1513 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1514 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1515 N0.getOperand(0).getOperand(1),
1518 if (N1.getOpcode() == ISD::AND) {
1519 SDValue AndOp0 = N1.getOperand(0);
1520 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1521 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1522 unsigned DestBits = VT.getScalarType().getSizeInBits();
1524 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1525 // and similar xforms where the inner op is either ~0 or 0.
1526 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1527 DebugLoc DL = N->getDebugLoc();
1528 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1532 // add (sext i1), X -> sub X, (zext i1)
1533 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1534 N0.getOperand(0).getValueType() == MVT::i1 &&
1535 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1536 DebugLoc DL = N->getDebugLoc();
1537 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1538 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1544 SDValue DAGCombiner::visitADDC(SDNode *N) {
1545 SDValue N0 = N->getOperand(0);
1546 SDValue N1 = N->getOperand(1);
1547 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1548 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1549 EVT VT = N0.getValueType();
1551 // If the flag result is dead, turn this into an ADD.
1552 if (!N->hasAnyUseOfValue(1))
1553 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1),
1554 DAG.getNode(ISD::CARRY_FALSE,
1555 N->getDebugLoc(), MVT::Glue));
1557 // canonicalize constant to RHS.
1559 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1561 // fold (addc x, 0) -> x + no carry out
1562 if (N1C && N1C->isNullValue())
1563 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1564 N->getDebugLoc(), MVT::Glue));
1566 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1567 APInt LHSZero, LHSOne;
1568 APInt RHSZero, RHSOne;
1569 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1571 if (LHSZero.getBoolValue()) {
1572 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1574 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1575 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1576 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1577 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1578 DAG.getNode(ISD::CARRY_FALSE,
1579 N->getDebugLoc(), MVT::Glue));
1585 SDValue DAGCombiner::visitADDE(SDNode *N) {
1586 SDValue N0 = N->getOperand(0);
1587 SDValue N1 = N->getOperand(1);
1588 SDValue CarryIn = N->getOperand(2);
1589 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1590 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1592 // canonicalize constant to RHS
1594 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1597 // fold (adde x, y, false) -> (addc x, y)
1598 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1599 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1);
1604 // Since it may not be valid to emit a fold to zero for vector initializers
1605 // check if we can before folding.
1606 static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT,
1607 SelectionDAG &DAG, bool LegalOperations) {
1608 if (!VT.isVector()) {
1609 return DAG.getConstant(0, VT);
1611 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1612 // Produce a vector of zeros.
1613 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
1614 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
1615 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
1616 &Ops[0], Ops.size());
1621 SDValue DAGCombiner::visitSUB(SDNode *N) {
1622 SDValue N0 = N->getOperand(0);
1623 SDValue N1 = N->getOperand(1);
1624 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1625 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1626 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 :
1627 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1628 EVT VT = N0.getValueType();
1631 if (VT.isVector()) {
1632 SDValue FoldedVOp = SimplifyVBinOp(N);
1633 if (FoldedVOp.getNode()) return FoldedVOp;
1635 // fold (sub x, 0) -> x, vector edition
1636 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1640 // fold (sub x, x) -> 0
1641 // FIXME: Refactor this and xor and other similar operations together.
1643 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
1644 // fold (sub c1, c2) -> c1-c2
1646 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1647 // fold (sub x, c) -> (add x, -c)
1649 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1650 DAG.getConstant(-N1C->getAPIntValue(), VT));
1651 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1652 if (N0C && N0C->isAllOnesValue())
1653 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1654 // fold A-(A-B) -> B
1655 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1656 return N1.getOperand(1);
1657 // fold (A+B)-A -> B
1658 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1659 return N0.getOperand(1);
1660 // fold (A+B)-B -> A
1661 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1662 return N0.getOperand(0);
1663 // fold C2-(A+C1) -> (C2-C1)-A
1664 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1665 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(),
1667 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC,
1670 // fold ((A+(B+or-C))-B) -> A+or-C
1671 if (N0.getOpcode() == ISD::ADD &&
1672 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1673 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1674 N0.getOperand(1).getOperand(0) == N1)
1675 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1676 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1677 // fold ((A+(C+B))-B) -> A+C
1678 if (N0.getOpcode() == ISD::ADD &&
1679 N0.getOperand(1).getOpcode() == ISD::ADD &&
1680 N0.getOperand(1).getOperand(1) == N1)
1681 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1682 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1683 // fold ((A-(B-C))-C) -> A-B
1684 if (N0.getOpcode() == ISD::SUB &&
1685 N0.getOperand(1).getOpcode() == ISD::SUB &&
1686 N0.getOperand(1).getOperand(1) == N1)
1687 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1688 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1690 // If either operand of a sub is undef, the result is undef
1691 if (N0.getOpcode() == ISD::UNDEF)
1693 if (N1.getOpcode() == ISD::UNDEF)
1696 // If the relocation model supports it, consider symbol offsets.
1697 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1698 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1699 // fold (sub Sym, c) -> Sym-c
1700 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1701 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1703 (uint64_t)N1C->getSExtValue());
1704 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1705 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1706 if (GA->getGlobal() == GB->getGlobal())
1707 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1714 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1715 SDValue N0 = N->getOperand(0);
1716 SDValue N1 = N->getOperand(1);
1717 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1718 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1719 EVT VT = N0.getValueType();
1721 // If the flag result is dead, turn this into an SUB.
1722 if (!N->hasAnyUseOfValue(1))
1723 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1),
1724 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1727 // fold (subc x, x) -> 0 + no borrow
1729 return CombineTo(N, DAG.getConstant(0, VT),
1730 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1733 // fold (subc x, 0) -> x + no borrow
1734 if (N1C && N1C->isNullValue())
1735 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1738 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1739 if (N0C && N0C->isAllOnesValue())
1740 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0),
1741 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1747 SDValue DAGCombiner::visitSUBE(SDNode *N) {
1748 SDValue N0 = N->getOperand(0);
1749 SDValue N1 = N->getOperand(1);
1750 SDValue CarryIn = N->getOperand(2);
1752 // fold (sube x, y, false) -> (subc x, y)
1753 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1754 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1);
1759 SDValue DAGCombiner::visitMUL(SDNode *N) {
1760 SDValue N0 = N->getOperand(0);
1761 SDValue N1 = N->getOperand(1);
1762 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1763 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1764 EVT VT = N0.getValueType();
1767 if (VT.isVector()) {
1768 SDValue FoldedVOp = SimplifyVBinOp(N);
1769 if (FoldedVOp.getNode()) return FoldedVOp;
1772 // fold (mul x, undef) -> 0
1773 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1774 return DAG.getConstant(0, VT);
1775 // fold (mul c1, c2) -> c1*c2
1777 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1778 // canonicalize constant to RHS
1780 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1781 // fold (mul x, 0) -> 0
1782 if (N1C && N1C->isNullValue())
1784 // fold (mul x, -1) -> 0-x
1785 if (N1C && N1C->isAllOnesValue())
1786 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1787 DAG.getConstant(0, VT), N0);
1788 // fold (mul x, (1 << c)) -> x << c
1789 if (N1C && N1C->getAPIntValue().isPowerOf2())
1790 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1791 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1792 getShiftAmountTy(N0.getValueType())));
1793 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1794 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1795 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1796 // FIXME: If the input is something that is easily negated (e.g. a
1797 // single-use add), we should put the negate there.
1798 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1799 DAG.getConstant(0, VT),
1800 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1801 DAG.getConstant(Log2Val,
1802 getShiftAmountTy(N0.getValueType()))));
1804 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1805 if (N1C && N0.getOpcode() == ISD::SHL &&
1806 isa<ConstantSDNode>(N0.getOperand(1))) {
1807 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1808 N1, N0.getOperand(1));
1809 AddToWorkList(C3.getNode());
1810 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1811 N0.getOperand(0), C3);
1814 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1817 SDValue Sh(0,0), Y(0,0);
1818 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1819 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1820 N0.getNode()->hasOneUse()) {
1822 } else if (N1.getOpcode() == ISD::SHL &&
1823 isa<ConstantSDNode>(N1.getOperand(1)) &&
1824 N1.getNode()->hasOneUse()) {
1829 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1830 Sh.getOperand(0), Y);
1831 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1832 Mul, Sh.getOperand(1));
1836 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1837 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1838 isa<ConstantSDNode>(N0.getOperand(1)))
1839 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1840 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1841 N0.getOperand(0), N1),
1842 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1843 N0.getOperand(1), N1));
1846 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1847 if (RMUL.getNode() != 0)
1853 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1854 SDValue N0 = N->getOperand(0);
1855 SDValue N1 = N->getOperand(1);
1856 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1857 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1858 EVT VT = N->getValueType(0);
1861 if (VT.isVector()) {
1862 SDValue FoldedVOp = SimplifyVBinOp(N);
1863 if (FoldedVOp.getNode()) return FoldedVOp;
1866 // fold (sdiv c1, c2) -> c1/c2
1867 if (N0C && N1C && !N1C->isNullValue())
1868 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1869 // fold (sdiv X, 1) -> X
1870 if (N1C && N1C->getAPIntValue() == 1LL)
1872 // fold (sdiv X, -1) -> 0-X
1873 if (N1C && N1C->isAllOnesValue())
1874 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1875 DAG.getConstant(0, VT), N0);
1876 // If we know the sign bits of both operands are zero, strength reduce to a
1877 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1878 if (!VT.isVector()) {
1879 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1880 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1883 // fold (sdiv X, pow2) -> simple ops after legalize
1884 if (N1C && !N1C->isNullValue() &&
1885 (N1C->getAPIntValue().isPowerOf2() ||
1886 (-N1C->getAPIntValue()).isPowerOf2())) {
1887 // If dividing by powers of two is cheap, then don't perform the following
1889 if (TLI.isPow2DivCheap())
1892 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
1894 // Splat the sign bit into the register
1895 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1896 DAG.getConstant(VT.getSizeInBits()-1,
1897 getShiftAmountTy(N0.getValueType())));
1898 AddToWorkList(SGN.getNode());
1900 // Add (N0 < 0) ? abs2 - 1 : 0;
1901 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1902 DAG.getConstant(VT.getSizeInBits() - lg2,
1903 getShiftAmountTy(SGN.getValueType())));
1904 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1905 AddToWorkList(SRL.getNode());
1906 AddToWorkList(ADD.getNode()); // Divide by pow2
1907 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1908 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1910 // If we're dividing by a positive value, we're done. Otherwise, we must
1911 // negate the result.
1912 if (N1C->getAPIntValue().isNonNegative())
1915 AddToWorkList(SRA.getNode());
1916 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1917 DAG.getConstant(0, VT), SRA);
1920 // if integer divide is expensive and we satisfy the requirements, emit an
1921 // alternate sequence.
1922 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1923 SDValue Op = BuildSDIV(N);
1924 if (Op.getNode()) return Op;
1928 if (N0.getOpcode() == ISD::UNDEF)
1929 return DAG.getConstant(0, VT);
1930 // X / undef -> undef
1931 if (N1.getOpcode() == ISD::UNDEF)
1937 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1938 SDValue N0 = N->getOperand(0);
1939 SDValue N1 = N->getOperand(1);
1940 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1941 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1942 EVT VT = N->getValueType(0);
1945 if (VT.isVector()) {
1946 SDValue FoldedVOp = SimplifyVBinOp(N);
1947 if (FoldedVOp.getNode()) return FoldedVOp;
1950 // fold (udiv c1, c2) -> c1/c2
1951 if (N0C && N1C && !N1C->isNullValue())
1952 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1953 // fold (udiv x, (1 << c)) -> x >>u c
1954 if (N1C && N1C->getAPIntValue().isPowerOf2())
1955 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1956 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1957 getShiftAmountTy(N0.getValueType())));
1958 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1959 if (N1.getOpcode() == ISD::SHL) {
1960 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1961 if (SHC->getAPIntValue().isPowerOf2()) {
1962 EVT ADDVT = N1.getOperand(1).getValueType();
1963 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1965 DAG.getConstant(SHC->getAPIntValue()
1968 AddToWorkList(Add.getNode());
1969 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1973 // fold (udiv x, c) -> alternate
1974 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1975 SDValue Op = BuildUDIV(N);
1976 if (Op.getNode()) return Op;
1980 if (N0.getOpcode() == ISD::UNDEF)
1981 return DAG.getConstant(0, VT);
1982 // X / undef -> undef
1983 if (N1.getOpcode() == ISD::UNDEF)
1989 SDValue DAGCombiner::visitSREM(SDNode *N) {
1990 SDValue N0 = N->getOperand(0);
1991 SDValue N1 = N->getOperand(1);
1992 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1993 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1994 EVT VT = N->getValueType(0);
1996 // fold (srem c1, c2) -> c1%c2
1997 if (N0C && N1C && !N1C->isNullValue())
1998 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1999 // If we know the sign bits of both operands are zero, strength reduce to a
2000 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
2001 if (!VT.isVector()) {
2002 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2003 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
2006 // If X/C can be simplified by the division-by-constant logic, lower
2007 // X%C to the equivalent of X-X/C*C.
2008 if (N1C && !N1C->isNullValue()) {
2009 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
2010 AddToWorkList(Div.getNode());
2011 SDValue OptimizedDiv = combine(Div.getNode());
2012 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2013 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
2015 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
2016 AddToWorkList(Mul.getNode());
2022 if (N0.getOpcode() == ISD::UNDEF)
2023 return DAG.getConstant(0, VT);
2024 // X % undef -> undef
2025 if (N1.getOpcode() == ISD::UNDEF)
2031 SDValue DAGCombiner::visitUREM(SDNode *N) {
2032 SDValue N0 = N->getOperand(0);
2033 SDValue N1 = N->getOperand(1);
2034 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2035 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2036 EVT VT = N->getValueType(0);
2038 // fold (urem c1, c2) -> c1%c2
2039 if (N0C && N1C && !N1C->isNullValue())
2040 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2041 // fold (urem x, pow2) -> (and x, pow2-1)
2042 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
2043 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
2044 DAG.getConstant(N1C->getAPIntValue()-1,VT));
2045 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2046 if (N1.getOpcode() == ISD::SHL) {
2047 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2048 if (SHC->getAPIntValue().isPowerOf2()) {
2050 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
2051 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
2053 AddToWorkList(Add.getNode());
2054 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
2059 // If X/C can be simplified by the division-by-constant logic, lower
2060 // X%C to the equivalent of X-X/C*C.
2061 if (N1C && !N1C->isNullValue()) {
2062 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
2063 AddToWorkList(Div.getNode());
2064 SDValue OptimizedDiv = combine(Div.getNode());
2065 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2066 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
2068 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
2069 AddToWorkList(Mul.getNode());
2075 if (N0.getOpcode() == ISD::UNDEF)
2076 return DAG.getConstant(0, VT);
2077 // X % undef -> undef
2078 if (N1.getOpcode() == ISD::UNDEF)
2084 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2085 SDValue N0 = N->getOperand(0);
2086 SDValue N1 = N->getOperand(1);
2087 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2088 EVT VT = N->getValueType(0);
2089 DebugLoc DL = N->getDebugLoc();
2091 // fold (mulhs x, 0) -> 0
2092 if (N1C && N1C->isNullValue())
2094 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2095 if (N1C && N1C->getAPIntValue() == 1)
2096 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
2097 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2098 getShiftAmountTy(N0.getValueType())));
2099 // fold (mulhs x, undef) -> 0
2100 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2101 return DAG.getConstant(0, VT);
2103 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2105 if (VT.isSimple() && !VT.isVector()) {
2106 MVT Simple = VT.getSimpleVT();
2107 unsigned SimpleSize = Simple.getSizeInBits();
2108 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2109 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2110 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2111 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2112 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2113 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2114 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2115 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2122 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2123 SDValue N0 = N->getOperand(0);
2124 SDValue N1 = N->getOperand(1);
2125 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2126 EVT VT = N->getValueType(0);
2127 DebugLoc DL = N->getDebugLoc();
2129 // fold (mulhu x, 0) -> 0
2130 if (N1C && N1C->isNullValue())
2132 // fold (mulhu x, 1) -> 0
2133 if (N1C && N1C->getAPIntValue() == 1)
2134 return DAG.getConstant(0, N0.getValueType());
2135 // fold (mulhu x, undef) -> 0
2136 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2137 return DAG.getConstant(0, VT);
2139 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2141 if (VT.isSimple() && !VT.isVector()) {
2142 MVT Simple = VT.getSimpleVT();
2143 unsigned SimpleSize = Simple.getSizeInBits();
2144 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2145 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2146 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2147 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2148 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2149 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2150 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2151 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2158 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2159 /// compute two values. LoOp and HiOp give the opcodes for the two computations
2160 /// that are being performed. Return true if a simplification was made.
2162 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2164 // If the high half is not needed, just compute the low half.
2165 bool HiExists = N->hasAnyUseOfValue(1);
2167 (!LegalOperations ||
2168 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2169 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2170 N->op_begin(), N->getNumOperands());
2171 return CombineTo(N, Res, Res);
2174 // If the low half is not needed, just compute the high half.
2175 bool LoExists = N->hasAnyUseOfValue(0);
2177 (!LegalOperations ||
2178 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2179 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2180 N->op_begin(), N->getNumOperands());
2181 return CombineTo(N, Res, Res);
2184 // If both halves are used, return as it is.
2185 if (LoExists && HiExists)
2188 // If the two computed results can be simplified separately, separate them.
2190 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2191 N->op_begin(), N->getNumOperands());
2192 AddToWorkList(Lo.getNode());
2193 SDValue LoOpt = combine(Lo.getNode());
2194 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2195 (!LegalOperations ||
2196 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2197 return CombineTo(N, LoOpt, LoOpt);
2201 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2202 N->op_begin(), N->getNumOperands());
2203 AddToWorkList(Hi.getNode());
2204 SDValue HiOpt = combine(Hi.getNode());
2205 if (HiOpt.getNode() && HiOpt != Hi &&
2206 (!LegalOperations ||
2207 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2208 return CombineTo(N, HiOpt, HiOpt);
2214 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2215 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2216 if (Res.getNode()) return Res;
2218 EVT VT = N->getValueType(0);
2219 DebugLoc DL = N->getDebugLoc();
2221 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2223 if (VT.isSimple() && !VT.isVector()) {
2224 MVT Simple = VT.getSimpleVT();
2225 unsigned SimpleSize = Simple.getSizeInBits();
2226 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2227 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2228 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2229 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2230 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2231 // Compute the high part as N1.
2232 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2233 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2234 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2235 // Compute the low part as N0.
2236 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2237 return CombineTo(N, Lo, Hi);
2244 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2245 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2246 if (Res.getNode()) return Res;
2248 EVT VT = N->getValueType(0);
2249 DebugLoc DL = N->getDebugLoc();
2251 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2253 if (VT.isSimple() && !VT.isVector()) {
2254 MVT Simple = VT.getSimpleVT();
2255 unsigned SimpleSize = Simple.getSizeInBits();
2256 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2257 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2258 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2259 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2260 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2261 // Compute the high part as N1.
2262 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2263 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2264 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2265 // Compute the low part as N0.
2266 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2267 return CombineTo(N, Lo, Hi);
2274 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2275 // (smulo x, 2) -> (saddo x, x)
2276 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2277 if (C2->getAPIntValue() == 2)
2278 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(),
2279 N->getOperand(0), N->getOperand(0));
2284 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2285 // (umulo x, 2) -> (uaddo x, x)
2286 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2287 if (C2->getAPIntValue() == 2)
2288 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(),
2289 N->getOperand(0), N->getOperand(0));
2294 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2295 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2296 if (Res.getNode()) return Res;
2301 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2302 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2303 if (Res.getNode()) return Res;
2308 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2309 /// two operands of the same opcode, try to simplify it.
2310 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2311 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2312 EVT VT = N0.getValueType();
2313 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2315 // Bail early if none of these transforms apply.
2316 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2318 // For each of OP in AND/OR/XOR:
2319 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2320 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2321 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2322 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2324 // do not sink logical op inside of a vector extend, since it may combine
2326 EVT Op0VT = N0.getOperand(0).getValueType();
2327 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2328 N0.getOpcode() == ISD::SIGN_EXTEND ||
2329 // Avoid infinite looping with PromoteIntBinOp.
2330 (N0.getOpcode() == ISD::ANY_EXTEND &&
2331 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2332 (N0.getOpcode() == ISD::TRUNCATE &&
2333 (!TLI.isZExtFree(VT, Op0VT) ||
2334 !TLI.isTruncateFree(Op0VT, VT)) &&
2335 TLI.isTypeLegal(Op0VT))) &&
2337 Op0VT == N1.getOperand(0).getValueType() &&
2338 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2339 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2340 N0.getOperand(0).getValueType(),
2341 N0.getOperand(0), N1.getOperand(0));
2342 AddToWorkList(ORNode.getNode());
2343 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2346 // For each of OP in SHL/SRL/SRA/AND...
2347 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2348 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2349 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2350 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2351 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2352 N0.getOperand(1) == N1.getOperand(1)) {
2353 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2354 N0.getOperand(0).getValueType(),
2355 N0.getOperand(0), N1.getOperand(0));
2356 AddToWorkList(ORNode.getNode());
2357 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2358 ORNode, N0.getOperand(1));
2361 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
2362 // Only perform this optimization after type legalization and before
2363 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
2364 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
2365 // we don't want to undo this promotion.
2366 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
2368 if ((N0.getOpcode() == ISD::BITCAST ||
2369 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2370 Level == AfterLegalizeTypes) {
2371 SDValue In0 = N0.getOperand(0);
2372 SDValue In1 = N1.getOperand(0);
2373 EVT In0Ty = In0.getValueType();
2374 EVT In1Ty = In1.getValueType();
2375 DebugLoc DL = N->getDebugLoc();
2376 // If both incoming values are integers, and the original types are the
2378 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
2379 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1);
2380 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
2381 AddToWorkList(Op.getNode());
2386 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
2387 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
2388 // If both shuffles use the same mask, and both shuffle within a single
2389 // vector, then it is worthwhile to move the swizzle after the operation.
2390 // The type-legalizer generates this pattern when loading illegal
2391 // vector types from memory. In many cases this allows additional shuffle
2393 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
2394 N0.getOperand(1).getOpcode() == ISD::UNDEF &&
2395 N1.getOperand(1).getOpcode() == ISD::UNDEF) {
2396 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2397 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
2399 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() &&
2400 "Inputs to shuffles are not the same type");
2402 unsigned NumElts = VT.getVectorNumElements();
2404 // Check that both shuffles use the same mask. The masks are known to be of
2405 // the same length because the result vector type is the same.
2406 bool SameMask = true;
2407 for (unsigned i = 0; i != NumElts; ++i) {
2408 int Idx0 = SVN0->getMaskElt(i);
2409 int Idx1 = SVN1->getMaskElt(i);
2417 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT,
2418 N0.getOperand(0), N1.getOperand(0));
2419 AddToWorkList(Op.getNode());
2420 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op,
2421 DAG.getUNDEF(VT), &SVN0->getMask()[0]);
2428 SDValue DAGCombiner::visitAND(SDNode *N) {
2429 SDValue N0 = N->getOperand(0);
2430 SDValue N1 = N->getOperand(1);
2431 SDValue LL, LR, RL, RR, CC0, CC1;
2432 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2433 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2434 EVT VT = N1.getValueType();
2435 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2438 if (VT.isVector()) {
2439 SDValue FoldedVOp = SimplifyVBinOp(N);
2440 if (FoldedVOp.getNode()) return FoldedVOp;
2442 // fold (and x, 0) -> 0, vector edition
2443 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2445 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2448 // fold (and x, -1) -> x, vector edition
2449 if (ISD::isBuildVectorAllOnes(N0.getNode()))
2451 if (ISD::isBuildVectorAllOnes(N1.getNode()))
2455 // fold (and x, undef) -> 0
2456 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2457 return DAG.getConstant(0, VT);
2458 // fold (and c1, c2) -> c1&c2
2460 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2461 // canonicalize constant to RHS
2463 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2464 // fold (and x, -1) -> x
2465 if (N1C && N1C->isAllOnesValue())
2467 // if (and x, c) is known to be zero, return 0
2468 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2469 APInt::getAllOnesValue(BitWidth)))
2470 return DAG.getConstant(0, VT);
2472 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2473 if (RAND.getNode() != 0)
2475 // fold (and (or x, C), D) -> D if (C & D) == D
2476 if (N1C && N0.getOpcode() == ISD::OR)
2477 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2478 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2480 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2481 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2482 SDValue N0Op0 = N0.getOperand(0);
2483 APInt Mask = ~N1C->getAPIntValue();
2484 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2485 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2486 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2487 N0.getValueType(), N0Op0);
2489 // Replace uses of the AND with uses of the Zero extend node.
2492 // We actually want to replace all uses of the any_extend with the
2493 // zero_extend, to avoid duplicating things. This will later cause this
2494 // AND to be folded.
2495 CombineTo(N0.getNode(), Zext);
2496 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2499 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2500 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2501 // already be zero by virtue of the width of the base type of the load.
2503 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2505 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2506 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2507 N0.getOpcode() == ISD::LOAD) {
2508 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2509 N0 : N0.getOperand(0) );
2511 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2512 // This can be a pure constant or a vector splat, in which case we treat the
2513 // vector as a scalar and use the splat value.
2514 APInt Constant = APInt::getNullValue(1);
2515 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2516 Constant = C->getAPIntValue();
2517 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2518 APInt SplatValue, SplatUndef;
2519 unsigned SplatBitSize;
2521 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2522 SplatBitSize, HasAnyUndefs);
2524 // Undef bits can contribute to a possible optimisation if set, so
2526 SplatValue |= SplatUndef;
2528 // The splat value may be something like "0x00FFFFFF", which means 0 for
2529 // the first vector value and FF for the rest, repeating. We need a mask
2530 // that will apply equally to all members of the vector, so AND all the
2531 // lanes of the constant together.
2532 EVT VT = Vector->getValueType(0);
2533 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2535 // If the splat value has been compressed to a bitlength lower
2536 // than the size of the vector lane, we need to re-expand it to
2538 if (BitWidth > SplatBitSize)
2539 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
2540 SplatBitSize < BitWidth;
2541 SplatBitSize = SplatBitSize * 2)
2542 SplatValue |= SplatValue.shl(SplatBitSize);
2544 Constant = APInt::getAllOnesValue(BitWidth);
2545 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
2546 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
2550 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
2551 // actually legal and isn't going to get expanded, else this is a false
2553 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2554 Load->getMemoryVT());
2556 // Resize the constant to the same size as the original memory access before
2557 // extension. If it is still the AllOnesValue then this AND is completely
2560 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
2563 switch (Load->getExtensionType()) {
2564 default: B = false; break;
2565 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2567 case ISD::NON_EXTLOAD: B = true; break;
2570 if (B && Constant.isAllOnesValue()) {
2571 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
2572 // preserve semantics once we get rid of the AND.
2573 SDValue NewLoad(Load, 0);
2574 if (Load->getExtensionType() == ISD::EXTLOAD) {
2575 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2576 Load->getValueType(0), Load->getDebugLoc(),
2577 Load->getChain(), Load->getBasePtr(),
2578 Load->getOffset(), Load->getMemoryVT(),
2579 Load->getMemOperand());
2580 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
2581 if (Load->getNumValues() == 3) {
2582 // PRE/POST_INC loads have 3 values.
2583 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
2584 NewLoad.getValue(2) };
2585 CombineTo(Load, To, 3, true);
2587 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
2591 // Fold the AND away, taking care not to fold to the old load node if we
2593 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
2595 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2598 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2599 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2600 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2601 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2603 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2604 LL.getValueType().isInteger()) {
2605 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2606 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2607 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2608 LR.getValueType(), LL, RL);
2609 AddToWorkList(ORNode.getNode());
2610 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2612 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2613 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2614 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2615 LR.getValueType(), LL, RL);
2616 AddToWorkList(ANDNode.getNode());
2617 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2619 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2620 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2621 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2622 LR.getValueType(), LL, RL);
2623 AddToWorkList(ORNode.getNode());
2624 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2627 // canonicalize equivalent to ll == rl
2628 if (LL == RR && LR == RL) {
2629 Op1 = ISD::getSetCCSwappedOperands(Op1);
2632 if (LL == RL && LR == RR) {
2633 bool isInteger = LL.getValueType().isInteger();
2634 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2635 if (Result != ISD::SETCC_INVALID &&
2636 (!LegalOperations ||
2637 TLI.isCondCodeLegal(Result, LL.getSimpleValueType())))
2638 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2643 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2644 if (N0.getOpcode() == N1.getOpcode()) {
2645 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2646 if (Tmp.getNode()) return Tmp;
2649 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2650 // fold (and (sra)) -> (and (srl)) when possible.
2651 if (!VT.isVector() &&
2652 SimplifyDemandedBits(SDValue(N, 0)))
2653 return SDValue(N, 0);
2655 // fold (zext_inreg (extload x)) -> (zextload x)
2656 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2657 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2658 EVT MemVT = LN0->getMemoryVT();
2659 // If we zero all the possible extended bits, then we can turn this into
2660 // a zextload if we are running before legalize or the operation is legal.
2661 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2662 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2663 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2664 ((!LegalOperations && !LN0->isVolatile()) ||
2665 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2666 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2667 LN0->getChain(), LN0->getBasePtr(),
2668 LN0->getPointerInfo(), MemVT,
2669 LN0->isVolatile(), LN0->isNonTemporal(),
2670 LN0->getAlignment());
2672 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2673 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2676 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2677 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2679 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2680 EVT MemVT = LN0->getMemoryVT();
2681 // If we zero all the possible extended bits, then we can turn this into
2682 // a zextload if we are running before legalize or the operation is legal.
2683 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2684 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2685 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2686 ((!LegalOperations && !LN0->isVolatile()) ||
2687 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2688 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2690 LN0->getBasePtr(), LN0->getPointerInfo(),
2692 LN0->isVolatile(), LN0->isNonTemporal(),
2693 LN0->getAlignment());
2695 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2696 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2700 // fold (and (load x), 255) -> (zextload x, i8)
2701 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2702 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2703 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2704 (N0.getOpcode() == ISD::ANY_EXTEND &&
2705 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2706 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2707 LoadSDNode *LN0 = HasAnyExt
2708 ? cast<LoadSDNode>(N0.getOperand(0))
2709 : cast<LoadSDNode>(N0);
2710 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2711 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2712 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2713 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2714 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2715 EVT LoadedVT = LN0->getMemoryVT();
2717 if (ExtVT == LoadedVT &&
2718 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2719 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2722 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2723 LN0->getChain(), LN0->getBasePtr(),
2724 LN0->getPointerInfo(),
2725 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2726 LN0->getAlignment());
2728 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2729 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2732 // Do not change the width of a volatile load.
2733 // Do not generate loads of non-round integer types since these can
2734 // be expensive (and would be wrong if the type is not byte sized).
2735 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2736 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2737 EVT PtrType = LN0->getOperand(1).getValueType();
2739 unsigned Alignment = LN0->getAlignment();
2740 SDValue NewPtr = LN0->getBasePtr();
2742 // For big endian targets, we need to add an offset to the pointer
2743 // to load the correct bytes. For little endian systems, we merely
2744 // need to read fewer bytes from the same pointer.
2745 if (TLI.isBigEndian()) {
2746 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2747 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2748 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2749 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2750 NewPtr, DAG.getConstant(PtrOff, PtrType));
2751 Alignment = MinAlign(Alignment, PtrOff);
2754 AddToWorkList(NewPtr.getNode());
2756 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2758 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2759 LN0->getChain(), NewPtr,
2760 LN0->getPointerInfo(),
2761 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2764 CombineTo(LN0, Load, Load.getValue(1));
2765 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2771 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
2772 VT.getSizeInBits() <= 64) {
2773 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2774 APInt ADDC = ADDI->getAPIntValue();
2775 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2776 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
2777 // immediate for an add, but it is legal if its top c2 bits are set,
2778 // transform the ADD so the immediate doesn't need to be materialized
2780 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
2781 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
2782 SRLI->getZExtValue());
2783 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
2785 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2787 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
2788 N0.getOperand(0), DAG.getConstant(ADDC, VT));
2789 CombineTo(N0.getNode(), NewAdd);
2790 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2801 /// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
2803 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2804 bool DemandHighBits) {
2805 if (!LegalOperations)
2808 EVT VT = N->getValueType(0);
2809 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
2811 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2814 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2815 bool LookPassAnd0 = false;
2816 bool LookPassAnd1 = false;
2817 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2819 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2821 if (N0.getOpcode() == ISD::AND) {
2822 if (!N0.getNode()->hasOneUse())
2824 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2825 if (!N01C || N01C->getZExtValue() != 0xFF00)
2827 N0 = N0.getOperand(0);
2828 LookPassAnd0 = true;
2831 if (N1.getOpcode() == ISD::AND) {
2832 if (!N1.getNode()->hasOneUse())
2834 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2835 if (!N11C || N11C->getZExtValue() != 0xFF)
2837 N1 = N1.getOperand(0);
2838 LookPassAnd1 = true;
2841 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2843 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2845 if (!N0.getNode()->hasOneUse() ||
2846 !N1.getNode()->hasOneUse())
2849 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2850 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2853 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
2856 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2857 SDValue N00 = N0->getOperand(0);
2858 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
2859 if (!N00.getNode()->hasOneUse())
2861 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
2862 if (!N001C || N001C->getZExtValue() != 0xFF)
2864 N00 = N00.getOperand(0);
2865 LookPassAnd0 = true;
2868 SDValue N10 = N1->getOperand(0);
2869 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
2870 if (!N10.getNode()->hasOneUse())
2872 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
2873 if (!N101C || N101C->getZExtValue() != 0xFF00)
2875 N10 = N10.getOperand(0);
2876 LookPassAnd1 = true;
2882 // Make sure everything beyond the low halfword is zero since the SRL 16
2883 // will clear the top bits.
2884 unsigned OpSizeInBits = VT.getSizeInBits();
2885 if (DemandHighBits && OpSizeInBits > 16 &&
2886 (!LookPassAnd0 || !LookPassAnd1) &&
2887 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16)))
2890 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00);
2891 if (OpSizeInBits > 16)
2892 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2893 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
2897 /// isBSwapHWordElement - Return true if the specified node is an element
2898 /// that makes up a 32-bit packed halfword byteswap. i.e.
2899 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2900 static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) {
2901 if (!N.getNode()->hasOneUse())
2904 unsigned Opc = N.getOpcode();
2905 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2908 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2913 switch (N1C->getZExtValue()) {
2916 case 0xFF: Num = 0; break;
2917 case 0xFF00: Num = 1; break;
2918 case 0xFF0000: Num = 2; break;
2919 case 0xFF000000: Num = 3; break;
2922 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
2923 SDValue N0 = N.getOperand(0);
2924 if (Opc == ISD::AND) {
2925 if (Num == 0 || Num == 2) {
2927 // (x >> 8) & 0xff0000
2928 if (N0.getOpcode() != ISD::SRL)
2930 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2931 if (!C || C->getZExtValue() != 8)
2934 // (x << 8) & 0xff00
2935 // (x << 8) & 0xff000000
2936 if (N0.getOpcode() != ISD::SHL)
2938 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2939 if (!C || C->getZExtValue() != 8)
2942 } else if (Opc == ISD::SHL) {
2944 // (x & 0xff0000) << 8
2945 if (Num != 0 && Num != 2)
2947 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2948 if (!C || C->getZExtValue() != 8)
2950 } else { // Opc == ISD::SRL
2951 // (x & 0xff00) >> 8
2952 // (x & 0xff000000) >> 8
2953 if (Num != 1 && Num != 3)
2955 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2956 if (!C || C->getZExtValue() != 8)
2963 Parts[Num] = N0.getOperand(0).getNode();
2967 /// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
2968 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2969 /// => (rotl (bswap x), 16)
2970 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
2971 if (!LegalOperations)
2974 EVT VT = N->getValueType(0);
2977 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2980 SmallVector<SDNode*,4> Parts(4, (SDNode*)0);
2982 // (or (or (and), (and)), (or (and), (and)))
2983 // (or (or (or (and), (and)), (and)), (and))
2984 if (N0.getOpcode() != ISD::OR)
2986 SDValue N00 = N0.getOperand(0);
2987 SDValue N01 = N0.getOperand(1);
2989 if (N1.getOpcode() == ISD::OR &&
2990 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) {
2991 // (or (or (and), (and)), (or (and), (and)))
2992 SDValue N000 = N00.getOperand(0);
2993 if (!isBSwapHWordElement(N000, Parts))
2996 SDValue N001 = N00.getOperand(1);
2997 if (!isBSwapHWordElement(N001, Parts))
2999 SDValue N010 = N01.getOperand(0);
3000 if (!isBSwapHWordElement(N010, Parts))
3002 SDValue N011 = N01.getOperand(1);
3003 if (!isBSwapHWordElement(N011, Parts))
3006 // (or (or (or (and), (and)), (and)), (and))
3007 if (!isBSwapHWordElement(N1, Parts))
3009 if (!isBSwapHWordElement(N01, Parts))
3011 if (N00.getOpcode() != ISD::OR)
3013 SDValue N000 = N00.getOperand(0);
3014 if (!isBSwapHWordElement(N000, Parts))
3016 SDValue N001 = N00.getOperand(1);
3017 if (!isBSwapHWordElement(N001, Parts))
3021 // Make sure the parts are all coming from the same node.
3022 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
3025 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT,
3026 SDValue(Parts[0],0));
3028 // Result of the bswap should be rotated by 16. If it's not legal, than
3029 // do (x << 16) | (x >> 16).
3030 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
3031 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
3032 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt);
3033 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
3034 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt);
3035 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT,
3036 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt),
3037 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
3040 SDValue DAGCombiner::visitOR(SDNode *N) {
3041 SDValue N0 = N->getOperand(0);
3042 SDValue N1 = N->getOperand(1);
3043 SDValue LL, LR, RL, RR, CC0, CC1;
3044 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3045 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3046 EVT VT = N1.getValueType();
3049 if (VT.isVector()) {
3050 SDValue FoldedVOp = SimplifyVBinOp(N);
3051 if (FoldedVOp.getNode()) return FoldedVOp;
3053 // fold (or x, 0) -> x, vector edition
3054 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3056 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3059 // fold (or x, -1) -> -1, vector edition
3060 if (ISD::isBuildVectorAllOnes(N0.getNode()))
3062 if (ISD::isBuildVectorAllOnes(N1.getNode()))
3066 // fold (or x, undef) -> -1
3067 if (!LegalOperations &&
3068 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3069 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
3070 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
3072 // fold (or c1, c2) -> c1|c2
3074 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
3075 // canonicalize constant to RHS
3077 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
3078 // fold (or x, 0) -> x
3079 if (N1C && N1C->isNullValue())
3081 // fold (or x, -1) -> -1
3082 if (N1C && N1C->isAllOnesValue())
3084 // fold (or x, c) -> c iff (x & ~c) == 0
3085 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3088 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
3089 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
3090 if (BSwap.getNode() != 0)
3092 BSwap = MatchBSwapHWordLow(N, N0, N1);
3093 if (BSwap.getNode() != 0)
3097 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
3098 if (ROR.getNode() != 0)
3100 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
3101 // iff (c1 & c2) == 0.
3102 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3103 isa<ConstantSDNode>(N0.getOperand(1))) {
3104 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3105 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
3106 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3107 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3108 N0.getOperand(0), N1),
3109 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
3111 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3112 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3113 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3114 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3116 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
3117 LL.getValueType().isInteger()) {
3118 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
3119 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
3120 if (cast<ConstantSDNode>(LR)->isNullValue() &&
3121 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3122 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
3123 LR.getValueType(), LL, RL);
3124 AddToWorkList(ORNode.getNode());
3125 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
3127 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
3128 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
3129 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
3130 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3131 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
3132 LR.getValueType(), LL, RL);
3133 AddToWorkList(ANDNode.getNode());
3134 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
3137 // canonicalize equivalent to ll == rl
3138 if (LL == RR && LR == RL) {
3139 Op1 = ISD::getSetCCSwappedOperands(Op1);
3142 if (LL == RL && LR == RR) {
3143 bool isInteger = LL.getValueType().isInteger();
3144 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3145 if (Result != ISD::SETCC_INVALID &&
3146 (!LegalOperations ||
3147 TLI.isCondCodeLegal(Result, LL.getSimpleValueType())))
3148 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
3153 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
3154 if (N0.getOpcode() == N1.getOpcode()) {
3155 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3156 if (Tmp.getNode()) return Tmp;
3159 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3160 if (N0.getOpcode() == ISD::AND &&
3161 N1.getOpcode() == ISD::AND &&
3162 N0.getOperand(1).getOpcode() == ISD::Constant &&
3163 N1.getOperand(1).getOpcode() == ISD::Constant &&
3164 // Don't increase # computations.
3165 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3166 // We can only do this xform if we know that bits from X that are set in C2
3167 // but not in C1 are already zero. Likewise for Y.
3168 const APInt &LHSMask =
3169 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3170 const APInt &RHSMask =
3171 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
3173 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3174 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3175 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3176 N0.getOperand(0), N1.getOperand(0));
3177 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
3178 DAG.getConstant(LHSMask | RHSMask, VT));
3182 // See if this is some rotate idiom.
3183 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
3184 return SDValue(Rot, 0);
3186 // Simplify the operands using demanded-bits information.
3187 if (!VT.isVector() &&
3188 SimplifyDemandedBits(SDValue(N, 0)))
3189 return SDValue(N, 0);
3194 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
3195 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3196 if (Op.getOpcode() == ISD::AND) {
3197 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3198 Mask = Op.getOperand(1);
3199 Op = Op.getOperand(0);
3205 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3213 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3214 // idioms for rotate, and if the target supports rotation instructions, generate
3216 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
3217 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3218 EVT VT = LHS.getValueType();
3219 if (!TLI.isTypeLegal(VT)) return 0;
3221 // The target must have at least one rotate flavor.
3222 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3223 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3224 if (!HasROTL && !HasROTR) return 0;
3226 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3227 SDValue LHSShift; // The shift.
3228 SDValue LHSMask; // AND value if any.
3229 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3230 return 0; // Not part of a rotate.
3232 SDValue RHSShift; // The shift.
3233 SDValue RHSMask; // AND value if any.
3234 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3235 return 0; // Not part of a rotate.
3237 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3238 return 0; // Not shifting the same value.
3240 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3241 return 0; // Shifts must disagree.
3243 // Canonicalize shl to left side in a shl/srl pair.
3244 if (RHSShift.getOpcode() == ISD::SHL) {
3245 std::swap(LHS, RHS);
3246 std::swap(LHSShift, RHSShift);
3247 std::swap(LHSMask , RHSMask );
3250 unsigned OpSizeInBits = VT.getSizeInBits();
3251 SDValue LHSShiftArg = LHSShift.getOperand(0);
3252 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3253 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3255 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3256 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3257 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3258 RHSShiftAmt.getOpcode() == ISD::Constant) {
3259 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3260 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3261 if ((LShVal + RShVal) != OpSizeInBits)
3264 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3265 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt);
3267 // If there is an AND of either shifted operand, apply it to the result.
3268 if (LHSMask.getNode() || RHSMask.getNode()) {
3269 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3271 if (LHSMask.getNode()) {
3272 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3273 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3275 if (RHSMask.getNode()) {
3276 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3277 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3280 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3283 return Rot.getNode();
3286 // If there is a mask here, and we have a variable shift, we can't be sure
3287 // that we're masking out the right stuff.
3288 if (LHSMask.getNode() || RHSMask.getNode())
3291 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
3292 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
3293 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
3294 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
3295 if (ConstantSDNode *SUBC =
3296 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
3297 if (SUBC->getAPIntValue() == OpSizeInBits) {
3298 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg,
3299 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3304 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
3305 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
3306 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
3307 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
3308 if (ConstantSDNode *SUBC =
3309 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
3310 if (SUBC->getAPIntValue() == OpSizeInBits) {
3311 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg,
3312 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3317 // Look for sign/zext/any-extended or truncate cases:
3318 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3319 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3320 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3321 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3322 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3323 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3324 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3325 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3326 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
3327 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
3328 if (RExtOp0.getOpcode() == ISD::SUB &&
3329 RExtOp0.getOperand(1) == LExtOp0) {
3330 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3332 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3333 // (rotr x, (sub 32, y))
3334 if (ConstantSDNode *SUBC =
3335 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
3336 if (SUBC->getAPIntValue() == OpSizeInBits) {
3337 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3339 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3342 } else if (LExtOp0.getOpcode() == ISD::SUB &&
3343 RExtOp0 == LExtOp0.getOperand(1)) {
3344 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3346 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3347 // (rotl x, (sub 32, y))
3348 if (ConstantSDNode *SUBC =
3349 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
3350 if (SUBC->getAPIntValue() == OpSizeInBits) {
3351 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
3353 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3362 SDValue DAGCombiner::visitXOR(SDNode *N) {
3363 SDValue N0 = N->getOperand(0);
3364 SDValue N1 = N->getOperand(1);
3365 SDValue LHS, RHS, CC;
3366 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3367 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3368 EVT VT = N0.getValueType();
3371 if (VT.isVector()) {
3372 SDValue FoldedVOp = SimplifyVBinOp(N);
3373 if (FoldedVOp.getNode()) return FoldedVOp;
3375 // fold (xor x, 0) -> x, vector edition
3376 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3378 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3382 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3383 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3384 return DAG.getConstant(0, VT);
3385 // fold (xor x, undef) -> undef
3386 if (N0.getOpcode() == ISD::UNDEF)
3388 if (N1.getOpcode() == ISD::UNDEF)
3390 // fold (xor c1, c2) -> c1^c2
3392 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3393 // canonicalize constant to RHS
3395 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
3396 // fold (xor x, 0) -> x
3397 if (N1C && N1C->isNullValue())
3400 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
3401 if (RXOR.getNode() != 0)
3404 // fold !(x cc y) -> (x !cc y)
3405 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3406 bool isInt = LHS.getValueType().isInteger();
3407 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3410 if (!LegalOperations ||
3411 TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) {
3412 switch (N0.getOpcode()) {
3414 llvm_unreachable("Unhandled SetCC Equivalent!");
3416 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
3417 case ISD::SELECT_CC:
3418 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
3419 N0.getOperand(3), NotCC);
3424 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3425 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3426 N0.getNode()->hasOneUse() &&
3427 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3428 SDValue V = N0.getOperand(0);
3429 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
3430 DAG.getConstant(1, V.getValueType()));
3431 AddToWorkList(V.getNode());
3432 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
3435 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3436 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3437 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3438 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3439 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3440 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3441 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3442 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3443 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3444 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3447 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3448 if (N1C && N1C->isAllOnesValue() &&
3449 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3450 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3451 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3452 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3453 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3454 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3455 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3456 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3459 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3460 if (N1C && N0.getOpcode() == ISD::XOR) {
3461 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3462 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3464 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
3465 DAG.getConstant(N1C->getAPIntValue() ^
3466 N00C->getAPIntValue(), VT));
3468 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
3469 DAG.getConstant(N1C->getAPIntValue() ^
3470 N01C->getAPIntValue(), VT));
3472 // fold (xor x, x) -> 0
3474 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
3476 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3477 if (N0.getOpcode() == N1.getOpcode()) {
3478 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3479 if (Tmp.getNode()) return Tmp;
3482 // Simplify the expression using non-local knowledge.
3483 if (!VT.isVector() &&
3484 SimplifyDemandedBits(SDValue(N, 0)))
3485 return SDValue(N, 0);
3490 /// visitShiftByConstant - Handle transforms common to the three shifts, when
3491 /// the shift amount is a constant.
3492 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
3493 SDNode *LHS = N->getOperand(0).getNode();
3494 if (!LHS->hasOneUse()) return SDValue();
3496 // We want to pull some binops through shifts, so that we have (and (shift))
3497 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3498 // thing happens with address calculations, so it's important to canonicalize
3500 bool HighBitSet = false; // Can we transform this if the high bit is set?
3502 switch (LHS->getOpcode()) {
3503 default: return SDValue();
3506 HighBitSet = false; // We can only transform sra if the high bit is clear.
3509 HighBitSet = true; // We can only transform sra if the high bit is set.
3512 if (N->getOpcode() != ISD::SHL)
3513 return SDValue(); // only shl(add) not sr[al](add).
3514 HighBitSet = false; // We can only transform sra if the high bit is clear.
3518 // We require the RHS of the binop to be a constant as well.
3519 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3520 if (!BinOpCst) return SDValue();
3522 // FIXME: disable this unless the input to the binop is a shift by a constant.
3523 // If it is not a shift, it pessimizes some common cases like:
3525 // void foo(int *X, int i) { X[i & 1235] = 1; }
3526 // int bar(int *X, int i) { return X[i & 255]; }
3527 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3528 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3529 BinOpLHSVal->getOpcode() != ISD::SRA &&
3530 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3531 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3534 EVT VT = N->getValueType(0);
3536 // If this is a signed shift right, and the high bit is modified by the
3537 // logical operation, do not perform the transformation. The highBitSet
3538 // boolean indicates the value of the high bit of the constant which would
3539 // cause it to be modified for this operation.
3540 if (N->getOpcode() == ISD::SRA) {
3541 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3542 if (BinOpRHSSignSet != HighBitSet)
3546 // Fold the constants, shifting the binop RHS by the shift amount.
3547 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
3549 LHS->getOperand(1), N->getOperand(1));
3551 // Create the new shift.
3552 SDValue NewShift = DAG.getNode(N->getOpcode(),
3553 LHS->getOperand(0).getDebugLoc(),
3554 VT, LHS->getOperand(0), N->getOperand(1));
3556 // Create the new binop.
3557 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
3560 SDValue DAGCombiner::visitSHL(SDNode *N) {
3561 SDValue N0 = N->getOperand(0);
3562 SDValue N1 = N->getOperand(1);
3563 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3564 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3565 EVT VT = N0.getValueType();
3566 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3568 // fold (shl c1, c2) -> c1<<c2
3570 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3571 // fold (shl 0, x) -> 0
3572 if (N0C && N0C->isNullValue())
3574 // fold (shl x, c >= size(x)) -> undef
3575 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3576 return DAG.getUNDEF(VT);
3577 // fold (shl x, 0) -> x
3578 if (N1C && N1C->isNullValue())
3580 // fold (shl undef, x) -> 0
3581 if (N0.getOpcode() == ISD::UNDEF)
3582 return DAG.getConstant(0, VT);
3583 // if (shl x, c) is known to be zero, return 0
3584 if (DAG.MaskedValueIsZero(SDValue(N, 0),
3585 APInt::getAllOnesValue(OpSizeInBits)))
3586 return DAG.getConstant(0, VT);
3587 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
3588 if (N1.getOpcode() == ISD::TRUNCATE &&
3589 N1.getOperand(0).getOpcode() == ISD::AND &&
3590 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3591 SDValue N101 = N1.getOperand(0).getOperand(1);
3592 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3593 EVT TruncVT = N1.getValueType();
3594 SDValue N100 = N1.getOperand(0).getOperand(0);
3595 APInt TruncC = N101C->getAPIntValue();
3596 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3597 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
3598 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
3599 DAG.getNode(ISD::TRUNCATE,
3602 DAG.getConstant(TruncC, TruncVT)));
3606 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3607 return SDValue(N, 0);
3609 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
3610 if (N1C && N0.getOpcode() == ISD::SHL &&
3611 N0.getOperand(1).getOpcode() == ISD::Constant) {
3612 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3613 uint64_t c2 = N1C->getZExtValue();
3614 if (c1 + c2 >= OpSizeInBits)
3615 return DAG.getConstant(0, VT);
3616 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3617 DAG.getConstant(c1 + c2, N1.getValueType()));
3620 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
3621 // For this to be valid, the second form must not preserve any of the bits
3622 // that are shifted out by the inner shift in the first form. This means
3623 // the outer shift size must be >= the number of bits added by the ext.
3624 // As a corollary, we don't care what kind of ext it is.
3625 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3626 N0.getOpcode() == ISD::ANY_EXTEND ||
3627 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3628 N0.getOperand(0).getOpcode() == ISD::SHL &&
3629 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3631 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3632 uint64_t c2 = N1C->getZExtValue();
3633 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3634 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3635 if (c2 >= OpSizeInBits - InnerShiftSize) {
3636 if (c1 + c2 >= OpSizeInBits)
3637 return DAG.getConstant(0, VT);
3638 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
3639 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT,
3640 N0.getOperand(0)->getOperand(0)),
3641 DAG.getConstant(c1 + c2, N1.getValueType()));
3645 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3646 // (and (srl x, (sub c1, c2), MASK)
3647 // Only fold this if the inner shift has no other uses -- if it does, folding
3648 // this will increase the total number of instructions.
3649 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
3650 N0.getOperand(1).getOpcode() == ISD::Constant) {
3651 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3652 if (c1 < VT.getSizeInBits()) {
3653 uint64_t c2 = N1C->getZExtValue();
3654 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3655 VT.getSizeInBits() - c1);
3658 Mask = Mask.shl(c2-c1);
3659 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3660 DAG.getConstant(c2-c1, N1.getValueType()));
3662 Mask = Mask.lshr(c1-c2);
3663 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3664 DAG.getConstant(c1-c2, N1.getValueType()));
3666 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift,
3667 DAG.getConstant(Mask, VT));
3670 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
3671 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3672 SDValue HiBitsMask =
3673 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3674 VT.getSizeInBits() -
3675 N1C->getZExtValue()),
3677 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3682 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3683 if (NewSHL.getNode())
3690 SDValue DAGCombiner::visitSRA(SDNode *N) {
3691 SDValue N0 = N->getOperand(0);
3692 SDValue N1 = N->getOperand(1);
3693 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3694 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3695 EVT VT = N0.getValueType();
3696 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3698 // fold (sra c1, c2) -> (sra c1, c2)
3700 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3701 // fold (sra 0, x) -> 0
3702 if (N0C && N0C->isNullValue())
3704 // fold (sra -1, x) -> -1
3705 if (N0C && N0C->isAllOnesValue())
3707 // fold (sra x, (setge c, size(x))) -> undef
3708 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3709 return DAG.getUNDEF(VT);
3710 // fold (sra x, 0) -> x
3711 if (N1C && N1C->isNullValue())
3713 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3715 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3716 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3717 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3719 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3720 ExtVT, VT.getVectorNumElements());
3721 if ((!LegalOperations ||
3722 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3723 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3724 N0.getOperand(0), DAG.getValueType(ExtVT));
3727 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3728 if (N1C && N0.getOpcode() == ISD::SRA) {
3729 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3730 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3731 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3732 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3733 DAG.getConstant(Sum, N1C->getValueType(0)));
3737 // fold (sra (shl X, m), (sub result_size, n))
3738 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3739 // result_size - n != m.
3740 // If truncate is free for the target sext(shl) is likely to result in better
3742 if (N0.getOpcode() == ISD::SHL) {
3743 // Get the two constanst of the shifts, CN0 = m, CN = n.
3744 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3746 // Determine what the truncate's result bitsize and type would be.
3748 EVT::getIntegerVT(*DAG.getContext(),
3749 OpSizeInBits - N1C->getZExtValue());
3750 // Determine the residual right-shift amount.
3751 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3753 // If the shift is not a no-op (in which case this should be just a sign
3754 // extend already), the truncated to type is legal, sign_extend is legal
3755 // on that type, and the truncate to that type is both legal and free,
3756 // perform the transform.
3757 if ((ShiftAmt > 0) &&
3758 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3759 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3760 TLI.isTruncateFree(VT, TruncVT)) {
3762 SDValue Amt = DAG.getConstant(ShiftAmt,
3763 getShiftAmountTy(N0.getOperand(0).getValueType()));
3764 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3765 N0.getOperand(0), Amt);
3766 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3768 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3769 N->getValueType(0), Trunc);
3774 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3775 if (N1.getOpcode() == ISD::TRUNCATE &&
3776 N1.getOperand(0).getOpcode() == ISD::AND &&
3777 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3778 SDValue N101 = N1.getOperand(0).getOperand(1);
3779 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3780 EVT TruncVT = N1.getValueType();
3781 SDValue N100 = N1.getOperand(0).getOperand(0);
3782 APInt TruncC = N101C->getAPIntValue();
3783 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3784 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3785 DAG.getNode(ISD::AND, N->getDebugLoc(),
3787 DAG.getNode(ISD::TRUNCATE,
3790 DAG.getConstant(TruncC, TruncVT)));
3794 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2))
3795 // if c1 is equal to the number of bits the trunc removes
3796 if (N0.getOpcode() == ISD::TRUNCATE &&
3797 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3798 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3799 N0.getOperand(0).hasOneUse() &&
3800 N0.getOperand(0).getOperand(1).hasOneUse() &&
3801 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3802 EVT LargeVT = N0.getOperand(0).getValueType();
3803 ConstantSDNode *LargeShiftAmt =
3804 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3806 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits ==
3807 LargeShiftAmt->getZExtValue()) {
3809 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(),
3810 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3811 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT,
3812 N0.getOperand(0).getOperand(0), Amt);
3813 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA);
3817 // Simplify, based on bits shifted out of the LHS.
3818 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3819 return SDValue(N, 0);
3822 // If the sign bit is known to be zero, switch this to a SRL.
3823 if (DAG.SignBitIsZero(N0))
3824 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3827 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3828 if (NewSRA.getNode())
3835 SDValue DAGCombiner::visitSRL(SDNode *N) {
3836 SDValue N0 = N->getOperand(0);
3837 SDValue N1 = N->getOperand(1);
3838 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3839 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3840 EVT VT = N0.getValueType();
3841 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3843 // fold (srl c1, c2) -> c1 >>u c2
3845 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3846 // fold (srl 0, x) -> 0
3847 if (N0C && N0C->isNullValue())
3849 // fold (srl x, c >= size(x)) -> undef
3850 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3851 return DAG.getUNDEF(VT);
3852 // fold (srl x, 0) -> x
3853 if (N1C && N1C->isNullValue())
3855 // if (srl x, c) is known to be zero, return 0
3856 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3857 APInt::getAllOnesValue(OpSizeInBits)))
3858 return DAG.getConstant(0, VT);
3860 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3861 if (N1C && N0.getOpcode() == ISD::SRL &&
3862 N0.getOperand(1).getOpcode() == ISD::Constant) {
3863 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3864 uint64_t c2 = N1C->getZExtValue();
3865 if (c1 + c2 >= OpSizeInBits)
3866 return DAG.getConstant(0, VT);
3867 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3868 DAG.getConstant(c1 + c2, N1.getValueType()));
3871 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3872 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3873 N0.getOperand(0).getOpcode() == ISD::SRL &&
3874 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3876 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3877 uint64_t c2 = N1C->getZExtValue();
3878 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3879 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3880 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3881 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
3882 if (c1 + OpSizeInBits == InnerShiftSize) {
3883 if (c1 + c2 >= InnerShiftSize)
3884 return DAG.getConstant(0, VT);
3885 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
3886 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3887 N0.getOperand(0)->getOperand(0),
3888 DAG.getConstant(c1 + c2, ShiftCountVT)));
3892 // fold (srl (shl x, c), c) -> (and x, cst2)
3893 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3894 N0.getValueSizeInBits() <= 64) {
3895 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3896 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3897 DAG.getConstant(~0ULL >> ShAmt, VT));
3901 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3902 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3903 // Shifting in all undef bits?
3904 EVT SmallVT = N0.getOperand(0).getValueType();
3905 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3906 return DAG.getUNDEF(VT);
3908 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3909 uint64_t ShiftAmt = N1C->getZExtValue();
3910 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3912 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
3913 AddToWorkList(SmallShift.getNode());
3914 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3918 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3919 // bit, which is unmodified by sra.
3920 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3921 if (N0.getOpcode() == ISD::SRA)
3922 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3925 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3926 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3927 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3928 APInt KnownZero, KnownOne;
3929 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne);
3931 // If any of the input bits are KnownOne, then the input couldn't be all
3932 // zeros, thus the result of the srl will always be zero.
3933 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3935 // If all of the bits input the to ctlz node are known to be zero, then
3936 // the result of the ctlz is "32" and the result of the shift is one.
3937 APInt UnknownBits = ~KnownZero;
3938 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3940 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3941 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3942 // Okay, we know that only that the single bit specified by UnknownBits
3943 // could be set on input to the CTLZ node. If this bit is set, the SRL
3944 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3945 // to an SRL/XOR pair, which is likely to simplify more.
3946 unsigned ShAmt = UnknownBits.countTrailingZeros();
3947 SDValue Op = N0.getOperand(0);
3950 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3951 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
3952 AddToWorkList(Op.getNode());
3955 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3956 Op, DAG.getConstant(1, VT));
3960 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3961 if (N1.getOpcode() == ISD::TRUNCATE &&
3962 N1.getOperand(0).getOpcode() == ISD::AND &&
3963 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3964 SDValue N101 = N1.getOperand(0).getOperand(1);
3965 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3966 EVT TruncVT = N1.getValueType();
3967 SDValue N100 = N1.getOperand(0).getOperand(0);
3968 APInt TruncC = N101C->getAPIntValue();
3969 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3970 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3971 DAG.getNode(ISD::AND, N->getDebugLoc(),
3973 DAG.getNode(ISD::TRUNCATE,
3976 DAG.getConstant(TruncC, TruncVT)));
3980 // fold operands of srl based on knowledge that the low bits are not
3982 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3983 return SDValue(N, 0);
3986 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3987 if (NewSRL.getNode())
3991 // Attempt to convert a srl of a load into a narrower zero-extending load.
3992 SDValue NarrowLoad = ReduceLoadWidth(N);
3993 if (NarrowLoad.getNode())
3996 // Here is a common situation. We want to optimize:
3999 // %b = and i32 %a, 2
4000 // %c = srl i32 %b, 1
4001 // brcond i32 %c ...
4007 // %c = setcc eq %b, 0
4010 // However when after the source operand of SRL is optimized into AND, the SRL
4011 // itself may not be optimized further. Look for it and add the BRCOND into
4013 if (N->hasOneUse()) {
4014 SDNode *Use = *N->use_begin();
4015 if (Use->getOpcode() == ISD::BRCOND)
4017 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
4018 // Also look pass the truncate.
4019 Use = *Use->use_begin();
4020 if (Use->getOpcode() == ISD::BRCOND)
4028 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
4029 SDValue N0 = N->getOperand(0);
4030 EVT VT = N->getValueType(0);
4032 // fold (ctlz c1) -> c2
4033 if (isa<ConstantSDNode>(N0))
4034 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
4038 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
4039 SDValue N0 = N->getOperand(0);
4040 EVT VT = N->getValueType(0);
4042 // fold (ctlz_zero_undef c1) -> c2
4043 if (isa<ConstantSDNode>(N0))
4044 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
4048 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
4049 SDValue N0 = N->getOperand(0);
4050 EVT VT = N->getValueType(0);
4052 // fold (cttz c1) -> c2
4053 if (isa<ConstantSDNode>(N0))
4054 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
4058 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
4059 SDValue N0 = N->getOperand(0);
4060 EVT VT = N->getValueType(0);
4062 // fold (cttz_zero_undef c1) -> c2
4063 if (isa<ConstantSDNode>(N0))
4064 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
4068 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
4069 SDValue N0 = N->getOperand(0);
4070 EVT VT = N->getValueType(0);
4072 // fold (ctpop c1) -> c2
4073 if (isa<ConstantSDNode>(N0))
4074 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
4078 SDValue DAGCombiner::visitSELECT(SDNode *N) {
4079 SDValue N0 = N->getOperand(0);
4080 SDValue N1 = N->getOperand(1);
4081 SDValue N2 = N->getOperand(2);
4082 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4083 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4084 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
4085 EVT VT = N->getValueType(0);
4086 EVT VT0 = N0.getValueType();
4088 // fold (select C, X, X) -> X
4091 // fold (select true, X, Y) -> X
4092 if (N0C && !N0C->isNullValue())
4094 // fold (select false, X, Y) -> Y
4095 if (N0C && N0C->isNullValue())
4097 // fold (select C, 1, X) -> (or C, X)
4098 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
4099 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
4100 // fold (select C, 0, 1) -> (xor C, 1)
4101 if (VT.isInteger() &&
4104 TLI.getBooleanContents(false) ==
4105 TargetLowering::ZeroOrOneBooleanContent)) &&
4106 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
4109 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
4110 N0, DAG.getConstant(1, VT0));
4111 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
4112 N0, DAG.getConstant(1, VT0));
4113 AddToWorkList(XORNode.getNode());
4115 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
4116 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
4118 // fold (select C, 0, X) -> (and (not C), X)
4119 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
4120 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
4121 AddToWorkList(NOTNode.getNode());
4122 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
4124 // fold (select C, X, 1) -> (or (not C), X)
4125 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
4126 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
4127 AddToWorkList(NOTNode.getNode());
4128 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
4130 // fold (select C, X, 0) -> (and C, X)
4131 if (VT == MVT::i1 && N2C && N2C->isNullValue())
4132 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
4133 // fold (select X, X, Y) -> (or X, Y)
4134 // fold (select X, 1, Y) -> (or X, Y)
4135 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
4136 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
4137 // fold (select X, Y, X) -> (and X, Y)
4138 // fold (select X, Y, 0) -> (and X, Y)
4139 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
4140 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
4142 // If we can fold this based on the true/false value, do so.
4143 if (SimplifySelectOps(N, N1, N2))
4144 return SDValue(N, 0); // Don't revisit N.
4146 // fold selects based on a setcc into other things, such as min/max/abs
4147 if (N0.getOpcode() == ISD::SETCC) {
4149 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
4150 // having to say they don't support SELECT_CC on every type the DAG knows
4151 // about, since there is no way to mark an opcode illegal at all value types
4152 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
4153 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
4154 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
4155 N0.getOperand(0), N0.getOperand(1),
4156 N1, N2, N0.getOperand(2));
4157 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
4163 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
4164 SDValue N0 = N->getOperand(0);
4165 SDValue N1 = N->getOperand(1);
4166 SDValue N2 = N->getOperand(2);
4167 SDValue N3 = N->getOperand(3);
4168 SDValue N4 = N->getOperand(4);
4169 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
4171 // fold select_cc lhs, rhs, x, x, cc -> x
4175 // Determine if the condition we're dealing with is constant
4176 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
4177 N0, N1, CC, N->getDebugLoc(), false);
4178 if (SCC.getNode()) AddToWorkList(SCC.getNode());
4180 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
4181 if (!SCCC->isNullValue())
4182 return N2; // cond always true -> true val
4184 return N3; // cond always false -> false val
4187 // Fold to a simpler select_cc
4188 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
4189 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
4190 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
4193 // If we can fold this based on the true/false value, do so.
4194 if (SimplifySelectOps(N, N2, N3))
4195 return SDValue(N, 0); // Don't revisit N.
4197 // fold select_cc into other things, such as min/max/abs
4198 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
4201 SDValue DAGCombiner::visitSETCC(SDNode *N) {
4202 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
4203 cast<CondCodeSDNode>(N->getOperand(2))->get(),
4207 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
4208 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
4209 // transformation. Returns true if extension are possible and the above
4210 // mentioned transformation is profitable.
4211 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
4213 SmallVector<SDNode*, 4> &ExtendNodes,
4214 const TargetLowering &TLI) {
4215 bool HasCopyToRegUses = false;
4216 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
4217 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
4218 UE = N0.getNode()->use_end();
4223 if (UI.getUse().getResNo() != N0.getResNo())
4225 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
4226 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
4227 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
4228 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
4229 // Sign bits will be lost after a zext.
4232 for (unsigned i = 0; i != 2; ++i) {
4233 SDValue UseOp = User->getOperand(i);
4236 if (!isa<ConstantSDNode>(UseOp))
4241 ExtendNodes.push_back(User);
4244 // If truncates aren't free and there are users we can't
4245 // extend, it isn't worthwhile.
4248 // Remember if this value is live-out.
4249 if (User->getOpcode() == ISD::CopyToReg)
4250 HasCopyToRegUses = true;
4253 if (HasCopyToRegUses) {
4254 bool BothLiveOut = false;
4255 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4257 SDUse &Use = UI.getUse();
4258 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
4264 // Both unextended and extended values are live out. There had better be
4265 // a good reason for the transformation.
4266 return ExtendNodes.size();
4271 void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
4272 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
4273 ISD::NodeType ExtType) {
4274 // Extend SetCC uses if necessary.
4275 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
4276 SDNode *SetCC = SetCCs[i];
4277 SmallVector<SDValue, 4> Ops;
4279 for (unsigned j = 0; j != 2; ++j) {
4280 SDValue SOp = SetCC->getOperand(j);
4282 Ops.push_back(ExtLoad);
4284 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
4287 Ops.push_back(SetCC->getOperand(2));
4288 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
4289 &Ops[0], Ops.size()));
4293 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
4294 SDValue N0 = N->getOperand(0);
4295 EVT VT = N->getValueType(0);
4297 // fold (sext c1) -> c1
4298 if (isa<ConstantSDNode>(N0))
4299 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
4301 // fold (sext (sext x)) -> (sext x)
4302 // fold (sext (aext x)) -> (sext x)
4303 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4304 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
4307 if (N0.getOpcode() == ISD::TRUNCATE) {
4308 // fold (sext (truncate (load x))) -> (sext (smaller load x))
4309 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
4310 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4311 if (NarrowLoad.getNode()) {
4312 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4313 if (NarrowLoad.getNode() != N0.getNode()) {
4314 CombineTo(N0.getNode(), NarrowLoad);
4315 // CombineTo deleted the truncate, if needed, but not what's under it.
4318 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4321 // See if the value being truncated is already sign extended. If so, just
4322 // eliminate the trunc/sext pair.
4323 SDValue Op = N0.getOperand(0);
4324 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
4325 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
4326 unsigned DestBits = VT.getScalarType().getSizeInBits();
4327 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
4329 if (OpBits == DestBits) {
4330 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
4331 // bits, it is already ready.
4332 if (NumSignBits > DestBits-MidBits)
4334 } else if (OpBits < DestBits) {
4335 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
4336 // bits, just sext from i32.
4337 if (NumSignBits > OpBits-MidBits)
4338 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
4340 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
4341 // bits, just truncate to i32.
4342 if (NumSignBits > OpBits-MidBits)
4343 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4346 // fold (sext (truncate x)) -> (sextinreg x).
4347 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
4348 N0.getValueType())) {
4349 if (OpBits < DestBits)
4350 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
4351 else if (OpBits > DestBits)
4352 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
4353 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
4354 DAG.getValueType(N0.getValueType()));
4358 // fold (sext (load x)) -> (sext (truncate (sextload x)))
4359 // None of the supported targets knows how to perform load and sign extend
4360 // on vectors in one instruction. We only perform this transformation on
4362 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4363 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4364 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4365 bool DoXform = true;
4366 SmallVector<SDNode*, 4> SetCCs;
4367 if (!N0.hasOneUse())
4368 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4370 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4371 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4373 LN0->getBasePtr(), LN0->getPointerInfo(),
4375 LN0->isVolatile(), LN0->isNonTemporal(),
4376 LN0->getAlignment());
4377 CombineTo(N, ExtLoad);
4378 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4379 N0.getValueType(), ExtLoad);
4380 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4381 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4383 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4387 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
4388 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
4389 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4390 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4391 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4392 EVT MemVT = LN0->getMemoryVT();
4393 if ((!LegalOperations && !LN0->isVolatile()) ||
4394 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
4395 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4397 LN0->getBasePtr(), LN0->getPointerInfo(),
4399 LN0->isVolatile(), LN0->isNonTemporal(),
4400 LN0->getAlignment());
4401 CombineTo(N, ExtLoad);
4402 CombineTo(N0.getNode(),
4403 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4404 N0.getValueType(), ExtLoad),
4405 ExtLoad.getValue(1));
4406 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4410 // fold (sext (and/or/xor (load x), cst)) ->
4411 // (and/or/xor (sextload x), (sext cst))
4412 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4413 N0.getOpcode() == ISD::XOR) &&
4414 isa<LoadSDNode>(N0.getOperand(0)) &&
4415 N0.getOperand(1).getOpcode() == ISD::Constant &&
4416 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4417 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4418 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4419 if (LN0->getExtensionType() != ISD::ZEXTLOAD) {
4420 bool DoXform = true;
4421 SmallVector<SDNode*, 4> SetCCs;
4422 if (!N0.hasOneUse())
4423 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4426 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT,
4427 LN0->getChain(), LN0->getBasePtr(),
4428 LN0->getPointerInfo(),
4431 LN0->isNonTemporal(),
4432 LN0->getAlignment());
4433 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4434 Mask = Mask.sext(VT.getSizeInBits());
4435 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4436 ExtLoad, DAG.getConstant(Mask, VT));
4437 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4438 N0.getOperand(0).getDebugLoc(),
4439 N0.getOperand(0).getValueType(), ExtLoad);
4441 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4442 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4444 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4449 if (N0.getOpcode() == ISD::SETCC) {
4450 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
4451 // Only do this before legalize for now.
4452 if (VT.isVector() && !LegalOperations) {
4453 EVT N0VT = N0.getOperand(0).getValueType();
4454 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
4455 // of the same size as the compared operands. Only optimize sext(setcc())
4456 // if this is the case.
4457 EVT SVT = TLI.getSetCCResultType(N0VT);
4459 // We know that the # elements of the results is the same as the
4460 // # elements of the compare (and the # elements of the compare result
4461 // for that matter). Check to see that they are the same size. If so,
4462 // we know that the element size of the sext'd result matches the
4463 // element size of the compare operands.
4464 if (VT.getSizeInBits() == SVT.getSizeInBits())
4465 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4467 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4468 // If the desired elements are smaller or larger than the source
4469 // elements we can use a matching integer vector type and then
4470 // truncate/sign extend
4471 EVT MatchingElementType =
4472 EVT::getIntegerVT(*DAG.getContext(),
4473 N0VT.getScalarType().getSizeInBits());
4474 EVT MatchingVectorType =
4475 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4476 N0VT.getVectorNumElements());
4478 if (SVT == MatchingVectorType) {
4479 SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType,
4480 N0.getOperand(0), N0.getOperand(1),
4481 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4482 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4486 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
4487 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
4489 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
4491 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4492 NegOne, DAG.getConstant(0, VT),
4493 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4494 if (SCC.getNode()) return SCC;
4495 if (!LegalOperations ||
4496 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
4497 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4498 DAG.getSetCC(N->getDebugLoc(),
4499 TLI.getSetCCResultType(VT),
4500 N0.getOperand(0), N0.getOperand(1),
4501 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4502 NegOne, DAG.getConstant(0, VT));
4505 // fold (sext x) -> (zext x) if the sign bit is known zero.
4506 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
4507 DAG.SignBitIsZero(N0))
4508 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4513 // isTruncateOf - If N is a truncate of some other value, return true, record
4514 // the value being truncated in Op and which of Op's bits are zero in KnownZero.
4515 // This function computes KnownZero to avoid a duplicated call to
4516 // ComputeMaskedBits in the caller.
4517 static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
4520 if (N->getOpcode() == ISD::TRUNCATE) {
4521 Op = N->getOperand(0);
4522 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4526 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
4527 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
4530 SDValue Op0 = N->getOperand(0);
4531 SDValue Op1 = N->getOperand(1);
4532 assert(Op0.getValueType() == Op1.getValueType());
4534 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0);
4535 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1);
4536 if (COp0 && COp0->isNullValue())
4538 else if (COp1 && COp1->isNullValue())
4543 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4545 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
4551 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
4552 SDValue N0 = N->getOperand(0);
4553 EVT VT = N->getValueType(0);
4555 // fold (zext c1) -> c1
4556 if (isa<ConstantSDNode>(N0))
4557 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4558 // fold (zext (zext x)) -> (zext x)
4559 // fold (zext (aext x)) -> (zext x)
4560 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4561 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
4564 // fold (zext (truncate x)) -> (zext x) or
4565 // (zext (truncate x)) -> (truncate x)
4566 // This is valid when the truncated bits of x are already zero.
4567 // FIXME: We should extend this to work for vectors too.
4570 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
4571 APInt TruncatedBits =
4572 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
4573 APInt(Op.getValueSizeInBits(), 0) :
4574 APInt::getBitsSet(Op.getValueSizeInBits(),
4575 N0.getValueSizeInBits(),
4576 std::min(Op.getValueSizeInBits(),
4577 VT.getSizeInBits()));
4578 if (TruncatedBits == (KnownZero & TruncatedBits)) {
4579 if (VT.bitsGT(Op.getValueType()))
4580 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op);
4581 if (VT.bitsLT(Op.getValueType()))
4582 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4588 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4589 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
4590 if (N0.getOpcode() == ISD::TRUNCATE) {
4591 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4592 if (NarrowLoad.getNode()) {
4593 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4594 if (NarrowLoad.getNode() != N0.getNode()) {
4595 CombineTo(N0.getNode(), NarrowLoad);
4596 // CombineTo deleted the truncate, if needed, but not what's under it.
4599 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4603 // fold (zext (truncate x)) -> (and x, mask)
4604 if (N0.getOpcode() == ISD::TRUNCATE &&
4605 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
4607 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4608 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
4609 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4610 if (NarrowLoad.getNode()) {
4611 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4612 if (NarrowLoad.getNode() != N0.getNode()) {
4613 CombineTo(N0.getNode(), NarrowLoad);
4614 // CombineTo deleted the truncate, if needed, but not what's under it.
4617 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4620 SDValue Op = N0.getOperand(0);
4621 if (Op.getValueType().bitsLT(VT)) {
4622 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
4623 AddToWorkList(Op.getNode());
4624 } else if (Op.getValueType().bitsGT(VT)) {
4625 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4626 AddToWorkList(Op.getNode());
4628 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
4629 N0.getValueType().getScalarType());
4632 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
4633 // if either of the casts is not free.
4634 if (N0.getOpcode() == ISD::AND &&
4635 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4636 N0.getOperand(1).getOpcode() == ISD::Constant &&
4637 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4638 N0.getValueType()) ||
4639 !TLI.isZExtFree(N0.getValueType(), VT))) {
4640 SDValue X = N0.getOperand(0).getOperand(0);
4641 if (X.getValueType().bitsLT(VT)) {
4642 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
4643 } else if (X.getValueType().bitsGT(VT)) {
4644 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4646 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4647 Mask = Mask.zext(VT.getSizeInBits());
4648 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4649 X, DAG.getConstant(Mask, VT));
4652 // fold (zext (load x)) -> (zext (truncate (zextload x)))
4653 // None of the supported targets knows how to perform load and vector_zext
4654 // on vectors in one instruction. We only perform this transformation on
4656 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4657 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4658 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4659 bool DoXform = true;
4660 SmallVector<SDNode*, 4> SetCCs;
4661 if (!N0.hasOneUse())
4662 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4664 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4665 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4667 LN0->getBasePtr(), LN0->getPointerInfo(),
4669 LN0->isVolatile(), LN0->isNonTemporal(),
4670 LN0->getAlignment());
4671 CombineTo(N, ExtLoad);
4672 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4673 N0.getValueType(), ExtLoad);
4674 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4676 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4678 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4682 // fold (zext (and/or/xor (load x), cst)) ->
4683 // (and/or/xor (zextload x), (zext cst))
4684 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4685 N0.getOpcode() == ISD::XOR) &&
4686 isa<LoadSDNode>(N0.getOperand(0)) &&
4687 N0.getOperand(1).getOpcode() == ISD::Constant &&
4688 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4689 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4690 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4691 if (LN0->getExtensionType() != ISD::SEXTLOAD) {
4692 bool DoXform = true;
4693 SmallVector<SDNode*, 4> SetCCs;
4694 if (!N0.hasOneUse())
4695 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4698 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT,
4699 LN0->getChain(), LN0->getBasePtr(),
4700 LN0->getPointerInfo(),
4703 LN0->isNonTemporal(),
4704 LN0->getAlignment());
4705 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4706 Mask = Mask.zext(VT.getSizeInBits());
4707 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4708 ExtLoad, DAG.getConstant(Mask, VT));
4709 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4710 N0.getOperand(0).getDebugLoc(),
4711 N0.getOperand(0).getValueType(), ExtLoad);
4713 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4714 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4716 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4721 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
4722 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
4723 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4724 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4725 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4726 EVT MemVT = LN0->getMemoryVT();
4727 if ((!LegalOperations && !LN0->isVolatile()) ||
4728 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
4729 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4731 LN0->getBasePtr(), LN0->getPointerInfo(),
4733 LN0->isVolatile(), LN0->isNonTemporal(),
4734 LN0->getAlignment());
4735 CombineTo(N, ExtLoad);
4736 CombineTo(N0.getNode(),
4737 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
4739 ExtLoad.getValue(1));
4740 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4744 if (N0.getOpcode() == ISD::SETCC) {
4745 if (!LegalOperations && VT.isVector()) {
4746 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4747 // Only do this before legalize for now.
4748 EVT N0VT = N0.getOperand(0).getValueType();
4749 EVT EltVT = VT.getVectorElementType();
4750 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
4751 DAG.getConstant(1, EltVT));
4752 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4753 // We know that the # elements of the results is the same as the
4754 // # elements of the compare (and the # elements of the compare result
4755 // for that matter). Check to see that they are the same size. If so,
4756 // we know that the element size of the sext'd result matches the
4757 // element size of the compare operands.
4758 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4759 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4761 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4762 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4763 &OneOps[0], OneOps.size()));
4765 // If the desired elements are smaller or larger than the source
4766 // elements we can use a matching integer vector type and then
4767 // truncate/sign extend
4768 EVT MatchingElementType =
4769 EVT::getIntegerVT(*DAG.getContext(),
4770 N0VT.getScalarType().getSizeInBits());
4771 EVT MatchingVectorType =
4772 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4773 N0VT.getVectorNumElements());
4775 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4777 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4778 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4779 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
4780 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4781 &OneOps[0], OneOps.size()));
4784 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4786 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4787 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4788 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4789 if (SCC.getNode()) return SCC;
4792 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
4793 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4794 isa<ConstantSDNode>(N0.getOperand(1)) &&
4795 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4797 SDValue ShAmt = N0.getOperand(1);
4798 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4799 if (N0.getOpcode() == ISD::SHL) {
4800 SDValue InnerZExt = N0.getOperand(0);
4801 // If the original shl may be shifting out bits, do not perform this
4803 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
4804 InnerZExt.getOperand(0).getValueType().getSizeInBits();
4805 if (ShAmtVal > KnownZeroBits)
4809 DebugLoc DL = N->getDebugLoc();
4811 // Ensure that the shift amount is wide enough for the shifted value.
4812 if (VT.getSizeInBits() >= 256)
4813 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
4815 return DAG.getNode(N0.getOpcode(), DL, VT,
4816 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4823 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
4824 SDValue N0 = N->getOperand(0);
4825 EVT VT = N->getValueType(0);
4827 // fold (aext c1) -> c1
4828 if (isa<ConstantSDNode>(N0))
4829 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
4830 // fold (aext (aext x)) -> (aext x)
4831 // fold (aext (zext x)) -> (zext x)
4832 // fold (aext (sext x)) -> (sext x)
4833 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4834 N0.getOpcode() == ISD::ZERO_EXTEND ||
4835 N0.getOpcode() == ISD::SIGN_EXTEND)
4836 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
4838 // fold (aext (truncate (load x))) -> (aext (smaller load x))
4839 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4840 if (N0.getOpcode() == ISD::TRUNCATE) {
4841 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4842 if (NarrowLoad.getNode()) {
4843 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4844 if (NarrowLoad.getNode() != N0.getNode()) {
4845 CombineTo(N0.getNode(), NarrowLoad);
4846 // CombineTo deleted the truncate, if needed, but not what's under it.
4849 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4853 // fold (aext (truncate x))
4854 if (N0.getOpcode() == ISD::TRUNCATE) {
4855 SDValue TruncOp = N0.getOperand(0);
4856 if (TruncOp.getValueType() == VT)
4857 return TruncOp; // x iff x size == zext size.
4858 if (TruncOp.getValueType().bitsGT(VT))
4859 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
4860 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
4863 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
4864 // if the trunc is not free.
4865 if (N0.getOpcode() == ISD::AND &&
4866 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4867 N0.getOperand(1).getOpcode() == ISD::Constant &&
4868 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4869 N0.getValueType())) {
4870 SDValue X = N0.getOperand(0).getOperand(0);
4871 if (X.getValueType().bitsLT(VT)) {
4872 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
4873 } else if (X.getValueType().bitsGT(VT)) {
4874 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
4876 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4877 Mask = Mask.zext(VT.getSizeInBits());
4878 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4879 X, DAG.getConstant(Mask, VT));
4882 // fold (aext (load x)) -> (aext (truncate (extload x)))
4883 // None of the supported targets knows how to perform load and any_ext
4884 // on vectors in one instruction. We only perform this transformation on
4886 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4887 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4888 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4889 bool DoXform = true;
4890 SmallVector<SDNode*, 4> SetCCs;
4891 if (!N0.hasOneUse())
4892 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4894 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4895 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4897 LN0->getBasePtr(), LN0->getPointerInfo(),
4899 LN0->isVolatile(), LN0->isNonTemporal(),
4900 LN0->getAlignment());
4901 CombineTo(N, ExtLoad);
4902 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4903 N0.getValueType(), ExtLoad);
4904 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4905 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4907 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4911 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
4912 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4913 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
4914 if (N0.getOpcode() == ISD::LOAD &&
4915 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4917 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4918 EVT MemVT = LN0->getMemoryVT();
4919 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
4920 VT, LN0->getChain(), LN0->getBasePtr(),
4921 LN0->getPointerInfo(), MemVT,
4922 LN0->isVolatile(), LN0->isNonTemporal(),
4923 LN0->getAlignment());
4924 CombineTo(N, ExtLoad);
4925 CombineTo(N0.getNode(),
4926 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4927 N0.getValueType(), ExtLoad),
4928 ExtLoad.getValue(1));
4929 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4932 if (N0.getOpcode() == ISD::SETCC) {
4933 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
4934 // Only do this before legalize for now.
4935 if (VT.isVector() && !LegalOperations) {
4936 EVT N0VT = N0.getOperand(0).getValueType();
4937 // We know that the # elements of the results is the same as the
4938 // # elements of the compare (and the # elements of the compare result
4939 // for that matter). Check to see that they are the same size. If so,
4940 // we know that the element size of the sext'd result matches the
4941 // element size of the compare operands.
4942 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4943 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4945 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4946 // If the desired elements are smaller or larger than the source
4947 // elements we can use a matching integer vector type and then
4948 // truncate/sign extend
4950 EVT MatchingElementType =
4951 EVT::getIntegerVT(*DAG.getContext(),
4952 N0VT.getScalarType().getSizeInBits());
4953 EVT MatchingVectorType =
4954 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4955 N0VT.getVectorNumElements());
4957 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4959 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4960 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4964 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4966 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4967 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4968 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4976 /// GetDemandedBits - See if the specified operand can be simplified with the
4977 /// knowledge that only the bits specified by Mask are used. If so, return the
4978 /// simpler operand, otherwise return a null SDValue.
4979 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4980 switch (V.getOpcode()) {
4982 case ISD::Constant: {
4983 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
4984 assert(CV != 0 && "Const value should be ConstSDNode.");
4985 const APInt &CVal = CV->getAPIntValue();
4986 APInt NewVal = CVal & Mask;
4987 if (NewVal != CVal) {
4988 return DAG.getConstant(NewVal, V.getValueType());
4994 // If the LHS or RHS don't contribute bits to the or, drop them.
4995 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4996 return V.getOperand(1);
4997 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4998 return V.getOperand(0);
5001 // Only look at single-use SRLs.
5002 if (!V.getNode()->hasOneUse())
5004 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
5005 // See if we can recursively simplify the LHS.
5006 unsigned Amt = RHSC->getZExtValue();
5008 // Watch out for shift count overflow though.
5009 if (Amt >= Mask.getBitWidth()) break;
5010 APInt NewMask = Mask << Amt;
5011 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
5012 if (SimplifyLHS.getNode())
5013 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
5014 SimplifyLHS, V.getOperand(1));
5020 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
5021 /// bits and then truncated to a narrower type and where N is a multiple
5022 /// of number of bits of the narrower type, transform it to a narrower load
5023 /// from address + N / num of bits of new type. If the result is to be
5024 /// extended, also fold the extension to form a extending load.
5025 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
5026 unsigned Opc = N->getOpcode();
5028 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
5029 SDValue N0 = N->getOperand(0);
5030 EVT VT = N->getValueType(0);
5033 // This transformation isn't valid for vector loads.
5037 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
5039 if (Opc == ISD::SIGN_EXTEND_INREG) {
5040 ExtType = ISD::SEXTLOAD;
5041 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5042 } else if (Opc == ISD::SRL) {
5043 // Another special-case: SRL is basically zero-extending a narrower value.
5044 ExtType = ISD::ZEXTLOAD;
5046 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5047 if (!N01) return SDValue();
5048 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
5049 VT.getSizeInBits() - N01->getZExtValue());
5051 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
5054 unsigned EVTBits = ExtVT.getSizeInBits();
5056 // Do not generate loads of non-round integer types since these can
5057 // be expensive (and would be wrong if the type is not byte sized).
5058 if (!ExtVT.isRound())
5062 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5063 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5064 ShAmt = N01->getZExtValue();
5065 // Is the shift amount a multiple of size of VT?
5066 if ((ShAmt & (EVTBits-1)) == 0) {
5067 N0 = N0.getOperand(0);
5068 // Is the load width a multiple of size of VT?
5069 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
5073 // At this point, we must have a load or else we can't do the transform.
5074 if (!isa<LoadSDNode>(N0)) return SDValue();
5076 // Because a SRL must be assumed to *need* to zero-extend the high bits
5077 // (as opposed to anyext the high bits), we can't combine the zextload
5078 // lowering of SRL and an sextload.
5079 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD)
5082 // If the shift amount is larger than the input type then we're not
5083 // accessing any of the loaded bytes. If the load was a zextload/extload
5084 // then the result of the shift+trunc is zero/undef (handled elsewhere).
5085 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
5090 // If the load is shifted left (and the result isn't shifted back right),
5091 // we can fold the truncate through the shift.
5092 unsigned ShLeftAmt = 0;
5093 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
5094 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
5095 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5096 ShLeftAmt = N01->getZExtValue();
5097 N0 = N0.getOperand(0);
5101 // If we haven't found a load, we can't narrow it. Don't transform one with
5102 // multiple uses, this would require adding a new load.
5103 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse())
5106 // Don't change the width of a volatile load.
5107 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5108 if (LN0->isVolatile())
5111 // Verify that we are actually reducing a load width here.
5112 if (LN0->getMemoryVT().getSizeInBits() < EVTBits)
5115 // For the transform to be legal, the load must produce only two values
5116 // (the value loaded and the chain). Don't transform a pre-increment
5117 // load, for example, which produces an extra value. Otherwise the
5118 // transformation is not equivalent, and the downstream logic to replace
5119 // uses gets things wrong.
5120 if (LN0->getNumValues() > 2)
5123 EVT PtrType = N0.getOperand(1).getValueType();
5125 if (PtrType == MVT::Untyped || PtrType.isExtended())
5126 // It's not possible to generate a constant of extended or untyped type.
5129 // For big endian targets, we need to adjust the offset to the pointer to
5130 // load the correct bytes.
5131 if (TLI.isBigEndian()) {
5132 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
5133 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
5134 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
5137 uint64_t PtrOff = ShAmt / 8;
5138 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
5139 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
5140 PtrType, LN0->getBasePtr(),
5141 DAG.getConstant(PtrOff, PtrType));
5142 AddToWorkList(NewPtr.getNode());
5145 if (ExtType == ISD::NON_EXTLOAD)
5146 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
5147 LN0->getPointerInfo().getWithOffset(PtrOff),
5148 LN0->isVolatile(), LN0->isNonTemporal(),
5149 LN0->isInvariant(), NewAlign);
5151 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr,
5152 LN0->getPointerInfo().getWithOffset(PtrOff),
5153 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
5156 // Replace the old load's chain with the new load's chain.
5157 WorkListRemover DeadNodes(*this);
5158 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
5160 // Shift the result left, if we've swallowed a left shift.
5161 SDValue Result = Load;
5162 if (ShLeftAmt != 0) {
5163 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
5164 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
5166 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
5167 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
5170 // Return the new loaded value.
5174 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
5175 SDValue N0 = N->getOperand(0);
5176 SDValue N1 = N->getOperand(1);
5177 EVT VT = N->getValueType(0);
5178 EVT EVT = cast<VTSDNode>(N1)->getVT();
5179 unsigned VTBits = VT.getScalarType().getSizeInBits();
5180 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
5182 // fold (sext_in_reg c1) -> c1
5183 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
5184 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
5186 // If the input is already sign extended, just drop the extension.
5187 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
5190 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
5191 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
5192 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
5193 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5194 N0.getOperand(0), N1);
5197 // fold (sext_in_reg (sext x)) -> (sext x)
5198 // fold (sext_in_reg (aext x)) -> (sext x)
5199 // if x is small enough.
5200 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
5201 SDValue N00 = N0.getOperand(0);
5202 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
5203 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
5204 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
5207 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
5208 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
5209 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
5211 // fold operands of sext_in_reg based on knowledge that the top bits are not
5213 if (SimplifyDemandedBits(SDValue(N, 0)))
5214 return SDValue(N, 0);
5216 // fold (sext_in_reg (load x)) -> (smaller sextload x)
5217 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
5218 SDValue NarrowLoad = ReduceLoadWidth(N);
5219 if (NarrowLoad.getNode())
5222 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
5223 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
5224 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
5225 if (N0.getOpcode() == ISD::SRL) {
5226 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
5227 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
5228 // We can turn this into an SRA iff the input to the SRL is already sign
5230 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
5231 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
5232 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
5233 N0.getOperand(0), N0.getOperand(1));
5237 // fold (sext_inreg (extload x)) -> (sextload x)
5238 if (ISD::isEXTLoad(N0.getNode()) &&
5239 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5240 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5241 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5242 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5243 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5244 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5246 LN0->getBasePtr(), LN0->getPointerInfo(),
5248 LN0->isVolatile(), LN0->isNonTemporal(),
5249 LN0->getAlignment());
5250 CombineTo(N, ExtLoad);
5251 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5252 AddToWorkList(ExtLoad.getNode());
5253 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5255 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
5256 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5258 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5259 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5260 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5261 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5262 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5264 LN0->getBasePtr(), LN0->getPointerInfo(),
5266 LN0->isVolatile(), LN0->isNonTemporal(),
5267 LN0->getAlignment());
5268 CombineTo(N, ExtLoad);
5269 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5270 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5273 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
5274 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
5275 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5276 N0.getOperand(1), false);
5277 if (BSwap.getNode() != 0)
5278 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5285 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
5286 SDValue N0 = N->getOperand(0);
5287 EVT VT = N->getValueType(0);
5288 bool isLE = TLI.isLittleEndian();
5291 if (N0.getValueType() == N->getValueType(0))
5293 // fold (truncate c1) -> c1
5294 if (isa<ConstantSDNode>(N0))
5295 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
5296 // fold (truncate (truncate x)) -> (truncate x)
5297 if (N0.getOpcode() == ISD::TRUNCATE)
5298 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5299 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
5300 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
5301 N0.getOpcode() == ISD::SIGN_EXTEND ||
5302 N0.getOpcode() == ISD::ANY_EXTEND) {
5303 if (N0.getOperand(0).getValueType().bitsLT(VT))
5304 // if the source is smaller than the dest, we still need an extend
5305 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
5307 if (N0.getOperand(0).getValueType().bitsGT(VT))
5308 // if the source is larger than the dest, than we just need the truncate
5309 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5310 // if the source and dest are the same type, we can drop both the extend
5311 // and the truncate.
5312 return N0.getOperand(0);
5315 // Fold extract-and-trunc into a narrow extract. For example:
5316 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
5317 // i32 y = TRUNCATE(i64 x)
5319 // v16i8 b = BITCAST (v2i64 val)
5320 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
5322 // Note: We only run this optimization after type legalization (which often
5323 // creates this pattern) and before operation legalization after which
5324 // we need to be more careful about the vector instructions that we generate.
5325 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5326 LegalTypes && !LegalOperations && N0->hasOneUse()) {
5328 EVT VecTy = N0.getOperand(0).getValueType();
5329 EVT ExTy = N0.getValueType();
5330 EVT TrTy = N->getValueType(0);
5332 unsigned NumElem = VecTy.getVectorNumElements();
5333 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
5335 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
5336 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
5338 SDValue EltNo = N0->getOperand(1);
5339 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
5340 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5341 EVT IndexTy = N0->getOperand(1).getValueType();
5342 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
5344 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5345 NVT, N0.getOperand(0));
5347 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
5348 N->getDebugLoc(), TrTy, V,
5349 DAG.getConstant(Index, IndexTy));
5353 // See if we can simplify the input to this truncate through knowledge that
5354 // only the low bits are being used.
5355 // For example "trunc (or (shl x, 8), y)" // -> trunc y
5356 // Currently we only perform this optimization on scalars because vectors
5357 // may have different active low bits.
5358 if (!VT.isVector()) {
5360 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
5361 VT.getSizeInBits()));
5362 if (Shorter.getNode())
5363 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
5365 // fold (truncate (load x)) -> (smaller load x)
5366 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
5367 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
5368 SDValue Reduced = ReduceLoadWidth(N);
5369 if (Reduced.getNode())
5372 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)),
5373 // where ... are all 'undef'.
5374 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
5375 SmallVector<EVT, 8> VTs;
5378 unsigned NumDefs = 0;
5380 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
5381 SDValue X = N0.getOperand(i);
5382 if (X.getOpcode() != ISD::UNDEF) {
5387 // Stop if more than one members are non-undef.
5390 VTs.push_back(EVT::getVectorVT(*DAG.getContext(),
5391 VT.getVectorElementType(),
5392 X.getValueType().getVectorNumElements()));
5396 return DAG.getUNDEF(VT);
5399 assert(V.getNode() && "The single defined operand is empty!");
5400 SmallVector<SDValue, 8> Opnds;
5401 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
5403 Opnds.push_back(DAG.getUNDEF(VTs[i]));
5406 SDValue NV = DAG.getNode(ISD::TRUNCATE, V.getDebugLoc(), VTs[i], V);
5407 AddToWorkList(NV.getNode());
5408 Opnds.push_back(NV);
5410 return DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
5411 &Opnds[0], Opnds.size());
5415 // Simplify the operands using demanded-bits information.
5416 if (!VT.isVector() &&
5417 SimplifyDemandedBits(SDValue(N, 0)))
5418 return SDValue(N, 0);
5423 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
5424 SDValue Elt = N->getOperand(i);
5425 if (Elt.getOpcode() != ISD::MERGE_VALUES)
5426 return Elt.getNode();
5427 return Elt.getOperand(Elt.getResNo()).getNode();
5430 /// CombineConsecutiveLoads - build_pair (load, load) -> load
5431 /// if load locations are consecutive.
5432 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
5433 assert(N->getOpcode() == ISD::BUILD_PAIR);
5435 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
5436 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
5437 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
5438 LD1->getPointerInfo().getAddrSpace() !=
5439 LD2->getPointerInfo().getAddrSpace())
5441 EVT LD1VT = LD1->getValueType(0);
5443 if (ISD::isNON_EXTLoad(LD2) &&
5445 // If both are volatile this would reduce the number of volatile loads.
5446 // If one is volatile it might be ok, but play conservative and bail out.
5447 !LD1->isVolatile() &&
5448 !LD2->isVolatile() &&
5449 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
5450 unsigned Align = LD1->getAlignment();
5451 unsigned NewAlign = TLI.getDataLayout()->
5452 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5454 if (NewAlign <= Align &&
5455 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
5456 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
5457 LD1->getBasePtr(), LD1->getPointerInfo(),
5458 false, false, false, Align);
5464 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
5465 SDValue N0 = N->getOperand(0);
5466 EVT VT = N->getValueType(0);
5468 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
5469 // Only do this before legalize, since afterward the target may be depending
5470 // on the bitconvert.
5471 // First check to see if this is all constant.
5473 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
5475 bool isSimple = true;
5476 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
5477 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
5478 N0.getOperand(i).getOpcode() != ISD::Constant &&
5479 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
5484 EVT DestEltVT = N->getValueType(0).getVectorElementType();
5485 assert(!DestEltVT.isVector() &&
5486 "Element type of vector ValueType must not be vector!");
5488 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
5491 // If the input is a constant, let getNode fold it.
5492 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
5493 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
5494 if (Res.getNode() != N) {
5495 if (!LegalOperations ||
5496 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
5499 // Folding it resulted in an illegal node, and it's too late to
5500 // do that. Clean up the old node and forego the transformation.
5501 // Ideally this won't happen very often, because instcombine
5502 // and the earlier dagcombine runs (where illegal nodes are
5503 // permitted) should have folded most of them already.
5504 DAG.DeleteNode(Res.getNode());
5508 // (conv (conv x, t1), t2) -> (conv x, t2)
5509 if (N0.getOpcode() == ISD::BITCAST)
5510 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
5513 // fold (conv (load x)) -> (load (conv*)x)
5514 // If the resultant load doesn't need a higher alignment than the original!
5515 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
5516 // Do not change the width of a volatile load.
5517 !cast<LoadSDNode>(N0)->isVolatile() &&
5518 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
5519 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5520 unsigned Align = TLI.getDataLayout()->
5521 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5522 unsigned OrigAlign = LN0->getAlignment();
5524 if (Align <= OrigAlign) {
5525 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
5526 LN0->getBasePtr(), LN0->getPointerInfo(),
5527 LN0->isVolatile(), LN0->isNonTemporal(),
5528 LN0->isInvariant(), OrigAlign);
5530 CombineTo(N0.getNode(),
5531 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5532 N0.getValueType(), Load),
5538 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5539 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
5540 // This often reduces constant pool loads.
5541 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) ||
5542 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) &&
5543 N0.getNode()->hasOneUse() && VT.isInteger() &&
5544 !VT.isVector() && !N0.getValueType().isVector()) {
5545 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
5547 AddToWorkList(NewConv.getNode());
5549 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5550 if (N0.getOpcode() == ISD::FNEG)
5551 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
5552 NewConv, DAG.getConstant(SignBit, VT));
5553 assert(N0.getOpcode() == ISD::FABS);
5554 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
5555 NewConv, DAG.getConstant(~SignBit, VT));
5558 // fold (bitconvert (fcopysign cst, x)) ->
5559 // (or (and (bitconvert x), sign), (and cst, (not sign)))
5560 // Note that we don't handle (copysign x, cst) because this can always be
5561 // folded to an fneg or fabs.
5562 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5563 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
5564 VT.isInteger() && !VT.isVector()) {
5565 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
5566 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
5567 if (isTypeLegal(IntXVT)) {
5568 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5569 IntXVT, N0.getOperand(1));
5570 AddToWorkList(X.getNode());
5572 // If X has a different width than the result/lhs, sext it or truncate it.
5573 unsigned VTWidth = VT.getSizeInBits();
5574 if (OrigXWidth < VTWidth) {
5575 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
5576 AddToWorkList(X.getNode());
5577 } else if (OrigXWidth > VTWidth) {
5578 // To get the sign bit in the right place, we have to shift it right
5579 // before truncating.
5580 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
5581 X.getValueType(), X,
5582 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
5583 AddToWorkList(X.getNode());
5584 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
5585 AddToWorkList(X.getNode());
5588 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5589 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
5590 X, DAG.getConstant(SignBit, VT));
5591 AddToWorkList(X.getNode());
5593 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5594 VT, N0.getOperand(0));
5595 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
5596 Cst, DAG.getConstant(~SignBit, VT));
5597 AddToWorkList(Cst.getNode());
5599 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
5603 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
5604 if (N0.getOpcode() == ISD::BUILD_PAIR) {
5605 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
5606 if (CombineLD.getNode())
5613 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
5614 EVT VT = N->getValueType(0);
5615 return CombineConsecutiveLoads(N, VT);
5618 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
5619 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
5620 /// destination element value type.
5621 SDValue DAGCombiner::
5622 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
5623 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
5625 // If this is already the right type, we're done.
5626 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
5628 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
5629 unsigned DstBitSize = DstEltVT.getSizeInBits();
5631 // If this is a conversion of N elements of one type to N elements of another
5632 // type, convert each element. This handles FP<->INT cases.
5633 if (SrcBitSize == DstBitSize) {
5634 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5635 BV->getValueType(0).getVectorNumElements());
5637 // Due to the FP element handling below calling this routine recursively,
5638 // we can end up with a scalar-to-vector node here.
5639 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
5640 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5641 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5642 DstEltVT, BV->getOperand(0)));
5644 SmallVector<SDValue, 8> Ops;
5645 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5646 SDValue Op = BV->getOperand(i);
5647 // If the vector element type is not legal, the BUILD_VECTOR operands
5648 // are promoted and implicitly truncated. Make that explicit here.
5649 if (Op.getValueType() != SrcEltVT)
5650 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
5651 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5653 AddToWorkList(Ops.back().getNode());
5655 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5656 &Ops[0], Ops.size());
5659 // Otherwise, we're growing or shrinking the elements. To avoid having to
5660 // handle annoying details of growing/shrinking FP values, we convert them to
5662 if (SrcEltVT.isFloatingPoint()) {
5663 // Convert the input float vector to a int vector where the elements are the
5665 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
5666 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
5667 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
5671 // Now we know the input is an integer vector. If the output is a FP type,
5672 // convert to integer first, then to FP of the right size.
5673 if (DstEltVT.isFloatingPoint()) {
5674 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
5675 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
5676 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
5678 // Next, convert to FP elements of the same size.
5679 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
5682 // Okay, we know the src/dst types are both integers of differing types.
5683 // Handling growing first.
5684 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
5685 if (SrcBitSize < DstBitSize) {
5686 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
5688 SmallVector<SDValue, 8> Ops;
5689 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
5690 i += NumInputsPerOutput) {
5691 bool isLE = TLI.isLittleEndian();
5692 APInt NewBits = APInt(DstBitSize, 0);
5693 bool EltIsUndef = true;
5694 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
5695 // Shift the previously computed bits over.
5696 NewBits <<= SrcBitSize;
5697 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
5698 if (Op.getOpcode() == ISD::UNDEF) continue;
5701 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
5702 zextOrTrunc(SrcBitSize).zext(DstBitSize);
5706 Ops.push_back(DAG.getUNDEF(DstEltVT));
5708 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
5711 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
5712 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5713 &Ops[0], Ops.size());
5716 // Finally, this must be the case where we are shrinking elements: each input
5717 // turns into multiple outputs.
5718 bool isS2V = ISD::isScalarToVector(BV);
5719 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
5720 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5721 NumOutputsPerInput*BV->getNumOperands());
5722 SmallVector<SDValue, 8> Ops;
5724 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5725 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
5726 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
5727 Ops.push_back(DAG.getUNDEF(DstEltVT));
5731 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
5732 getAPIntValue().zextOrTrunc(SrcBitSize);
5734 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
5735 APInt ThisVal = OpVal.trunc(DstBitSize);
5736 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
5737 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
5738 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
5739 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5741 OpVal = OpVal.lshr(DstBitSize);
5744 // For big endian targets, swap the order of the pieces of each element.
5745 if (TLI.isBigEndian())
5746 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
5749 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5750 &Ops[0], Ops.size());
5753 SDValue DAGCombiner::visitFADD(SDNode *N) {
5754 SDValue N0 = N->getOperand(0);
5755 SDValue N1 = N->getOperand(1);
5756 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5757 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5758 EVT VT = N->getValueType(0);
5761 if (VT.isVector()) {
5762 SDValue FoldedVOp = SimplifyVBinOp(N);
5763 if (FoldedVOp.getNode()) return FoldedVOp;
5766 // fold (fadd c1, c2) -> c1 + c2
5768 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
5769 // canonicalize constant to RHS
5770 if (N0CFP && !N1CFP)
5771 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
5772 // fold (fadd A, 0) -> A
5773 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5774 N1CFP->getValueAPF().isZero())
5776 // fold (fadd A, (fneg B)) -> (fsub A, B)
5777 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5778 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5779 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5780 GetNegatedExpression(N1, DAG, LegalOperations));
5781 // fold (fadd (fneg A), B) -> (fsub B, A)
5782 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5783 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5784 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
5785 GetNegatedExpression(N0, DAG, LegalOperations));
5787 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
5788 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5789 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
5790 isa<ConstantFPSDNode>(N0.getOperand(1)))
5791 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
5792 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5793 N0.getOperand(1), N1));
5795 // If allow, fold (fadd (fneg x), x) -> 0.0
5796 if (DAG.getTarget().Options.UnsafeFPMath &&
5797 N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) {
5798 return DAG.getConstantFP(0.0, VT);
5801 // If allow, fold (fadd x, (fneg x)) -> 0.0
5802 if (DAG.getTarget().Options.UnsafeFPMath &&
5803 N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) {
5804 return DAG.getConstantFP(0.0, VT);
5807 // In unsafe math mode, we can fold chains of FADD's of the same value
5808 // into multiplications. This transform is not safe in general because
5809 // we are reducing the number of rounding steps.
5810 if (DAG.getTarget().Options.UnsafeFPMath &&
5811 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) &&
5813 if (N0.getOpcode() == ISD::FMUL) {
5814 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
5815 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
5817 // (fadd (fmul c, x), x) -> (fmul c+1, x)
5818 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) {
5819 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5821 DAG.getConstantFP(1.0, VT));
5822 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5826 // (fadd (fmul x, c), x) -> (fmul c+1, x)
5827 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
5828 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5830 DAG.getConstantFP(1.0, VT));
5831 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5835 // (fadd (fmul c, x), (fadd x, x)) -> (fmul c+2, x)
5836 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD &&
5837 N1.getOperand(0) == N1.getOperand(1) &&
5838 N0.getOperand(1) == N1.getOperand(0)) {
5839 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5841 DAG.getConstantFP(2.0, VT));
5842 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5843 N0.getOperand(1), NewCFP);
5846 // (fadd (fmul x, c), (fadd x, x)) -> (fmul c+2, x)
5847 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
5848 N1.getOperand(0) == N1.getOperand(1) &&
5849 N0.getOperand(0) == N1.getOperand(0)) {
5850 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5852 DAG.getConstantFP(2.0, VT));
5853 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5854 N0.getOperand(0), NewCFP);
5858 if (N1.getOpcode() == ISD::FMUL) {
5859 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
5860 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1));
5862 // (fadd x, (fmul c, x)) -> (fmul c+1, x)
5863 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) {
5864 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5866 DAG.getConstantFP(1.0, VT));
5867 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5871 // (fadd x, (fmul x, c)) -> (fmul c+1, x)
5872 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
5873 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5875 DAG.getConstantFP(1.0, VT));
5876 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5881 // (fadd (fadd x, x), (fmul c, x)) -> (fmul c+2, x)
5882 if (CFP10 && !CFP11 && N1.getOpcode() == ISD::FADD &&
5883 N1.getOperand(0) == N1.getOperand(1) &&
5884 N0.getOperand(1) == N1.getOperand(0)) {
5885 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5887 DAG.getConstantFP(2.0, VT));
5888 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5889 N0.getOperand(1), NewCFP);
5892 // (fadd (fadd x, x), (fmul x, c)) -> (fmul c+2, x)
5893 if (CFP11 && !CFP10 && N1.getOpcode() == ISD::FADD &&
5894 N1.getOperand(0) == N1.getOperand(1) &&
5895 N0.getOperand(0) == N1.getOperand(0)) {
5896 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5898 DAG.getConstantFP(2.0, VT));
5899 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5900 N0.getOperand(0), NewCFP);
5904 if (N0.getOpcode() == ISD::FADD) {
5905 ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
5906 // (fadd (fadd x, x), x) -> (fmul 3.0, x)
5907 if (!CFP && N0.getOperand(0) == N0.getOperand(1) &&
5908 (N0.getOperand(0) == N1)) {
5909 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5910 N1, DAG.getConstantFP(3.0, VT));
5914 if (N1.getOpcode() == ISD::FADD) {
5915 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
5916 // (fadd x, (fadd x, x)) -> (fmul 3.0, x)
5917 if (!CFP10 && N1.getOperand(0) == N1.getOperand(1) &&
5918 N1.getOperand(0) == N0) {
5919 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5920 N0, DAG.getConstantFP(3.0, VT));
5924 // (fadd (fadd x, x), (fadd x, x)) -> (fmul 4.0, x)
5925 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
5926 N0.getOperand(0) == N0.getOperand(1) &&
5927 N1.getOperand(0) == N1.getOperand(1) &&
5928 N0.getOperand(0) == N1.getOperand(0)) {
5929 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5931 DAG.getConstantFP(4.0, VT));
5935 // FADD -> FMA combines:
5936 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
5937 DAG.getTarget().Options.UnsafeFPMath) &&
5938 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) &&
5939 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) {
5941 // fold (fadd (fmul x, y), z) -> (fma x, y, z)
5942 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) {
5943 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT,
5944 N0.getOperand(0), N0.getOperand(1), N1);
5947 // fold (fadd x, (fmul y, z)) -> (fma y, z, x)
5948 // Note: Commutes FADD operands.
5949 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) {
5950 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT,
5951 N1.getOperand(0), N1.getOperand(1), N0);
5958 SDValue DAGCombiner::visitFSUB(SDNode *N) {
5959 SDValue N0 = N->getOperand(0);
5960 SDValue N1 = N->getOperand(1);
5961 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5962 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5963 EVT VT = N->getValueType(0);
5964 DebugLoc dl = N->getDebugLoc();
5967 if (VT.isVector()) {
5968 SDValue FoldedVOp = SimplifyVBinOp(N);
5969 if (FoldedVOp.getNode()) return FoldedVOp;
5972 // fold (fsub c1, c2) -> c1-c2
5974 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
5975 // fold (fsub A, 0) -> A
5976 if (DAG.getTarget().Options.UnsafeFPMath &&
5977 N1CFP && N1CFP->getValueAPF().isZero())
5979 // fold (fsub 0, B) -> -B
5980 if (DAG.getTarget().Options.UnsafeFPMath &&
5981 N0CFP && N0CFP->getValueAPF().isZero()) {
5982 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
5983 return GetNegatedExpression(N1, DAG, LegalOperations);
5984 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5985 return DAG.getNode(ISD::FNEG, dl, VT, N1);
5987 // fold (fsub A, (fneg B)) -> (fadd A, B)
5988 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
5989 return DAG.getNode(ISD::FADD, dl, VT, N0,
5990 GetNegatedExpression(N1, DAG, LegalOperations));
5992 // If 'unsafe math' is enabled, fold
5993 // (fsub x, x) -> 0.0 &
5994 // (fsub x, (fadd x, y)) -> (fneg y) &
5995 // (fsub x, (fadd y, x)) -> (fneg y)
5996 if (DAG.getTarget().Options.UnsafeFPMath) {
5998 return DAG.getConstantFP(0.0f, VT);
6000 if (N1.getOpcode() == ISD::FADD) {
6001 SDValue N10 = N1->getOperand(0);
6002 SDValue N11 = N1->getOperand(1);
6004 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI,
6005 &DAG.getTarget().Options))
6006 return GetNegatedExpression(N11, DAG, LegalOperations);
6007 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI,
6008 &DAG.getTarget().Options))
6009 return GetNegatedExpression(N10, DAG, LegalOperations);
6013 // FSUB -> FMA combines:
6014 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
6015 DAG.getTarget().Options.UnsafeFPMath) &&
6016 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) &&
6017 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) {
6019 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
6020 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) {
6021 return DAG.getNode(ISD::FMA, dl, VT,
6022 N0.getOperand(0), N0.getOperand(1),
6023 DAG.getNode(ISD::FNEG, dl, VT, N1));
6026 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
6027 // Note: Commutes FSUB operands.
6028 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) {
6029 return DAG.getNode(ISD::FMA, dl, VT,
6030 DAG.getNode(ISD::FNEG, dl, VT,
6032 N1.getOperand(1), N0);
6035 // fold (fsub (-(fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
6036 if (N0.getOpcode() == ISD::FNEG &&
6037 N0.getOperand(0).getOpcode() == ISD::FMUL &&
6038 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) {
6039 SDValue N00 = N0.getOperand(0).getOperand(0);
6040 SDValue N01 = N0.getOperand(0).getOperand(1);
6041 return DAG.getNode(ISD::FMA, dl, VT,
6042 DAG.getNode(ISD::FNEG, dl, VT, N00), N01,
6043 DAG.getNode(ISD::FNEG, dl, VT, N1));
6050 SDValue DAGCombiner::visitFMUL(SDNode *N) {
6051 SDValue N0 = N->getOperand(0);
6052 SDValue N1 = N->getOperand(1);
6053 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6054 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6055 EVT VT = N->getValueType(0);
6056 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6059 if (VT.isVector()) {
6060 SDValue FoldedVOp = SimplifyVBinOp(N);
6061 if (FoldedVOp.getNode()) return FoldedVOp;
6064 // fold (fmul c1, c2) -> c1*c2
6066 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
6067 // canonicalize constant to RHS
6068 if (N0CFP && !N1CFP)
6069 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
6070 // fold (fmul A, 0) -> 0
6071 if (DAG.getTarget().Options.UnsafeFPMath &&
6072 N1CFP && N1CFP->getValueAPF().isZero())
6074 // fold (fmul A, 0) -> 0, vector edition.
6075 if (DAG.getTarget().Options.UnsafeFPMath &&
6076 ISD::isBuildVectorAllZeros(N1.getNode()))
6078 // fold (fmul A, 1.0) -> A
6079 if (N1CFP && N1CFP->isExactlyValue(1.0))
6081 // fold (fmul X, 2.0) -> (fadd X, X)
6082 if (N1CFP && N1CFP->isExactlyValue(+2.0))
6083 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
6084 // fold (fmul X, -1.0) -> (fneg X)
6085 if (N1CFP && N1CFP->isExactlyValue(-1.0))
6086 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6087 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
6089 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
6090 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
6091 &DAG.getTarget().Options)) {
6092 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
6093 &DAG.getTarget().Options)) {
6094 // Both can be negated for free, check to see if at least one is cheaper
6096 if (LHSNeg == 2 || RHSNeg == 2)
6097 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
6098 GetNegatedExpression(N0, DAG, LegalOperations),
6099 GetNegatedExpression(N1, DAG, LegalOperations));
6103 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
6104 if (DAG.getTarget().Options.UnsafeFPMath &&
6105 N1CFP && N0.getOpcode() == ISD::FMUL &&
6106 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
6107 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
6108 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
6109 N0.getOperand(1), N1));
6114 SDValue DAGCombiner::visitFMA(SDNode *N) {
6115 SDValue N0 = N->getOperand(0);
6116 SDValue N1 = N->getOperand(1);
6117 SDValue N2 = N->getOperand(2);
6118 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6119 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6120 EVT VT = N->getValueType(0);
6121 DebugLoc dl = N->getDebugLoc();
6123 if (DAG.getTarget().Options.UnsafeFPMath) {
6124 if (N0CFP && N0CFP->isZero())
6126 if (N1CFP && N1CFP->isZero())
6129 if (N0CFP && N0CFP->isExactlyValue(1.0))
6130 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2);
6131 if (N1CFP && N1CFP->isExactlyValue(1.0))
6132 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2);
6134 // Canonicalize (fma c, x, y) -> (fma x, c, y)
6135 if (N0CFP && !N1CFP)
6136 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, N1, N0, N2);
6138 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)
6139 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6140 N2.getOpcode() == ISD::FMUL &&
6141 N0 == N2.getOperand(0) &&
6142 N2.getOperand(1).getOpcode() == ISD::ConstantFP) {
6143 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6144 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1)));
6148 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y)
6149 if (DAG.getTarget().Options.UnsafeFPMath &&
6150 N0.getOpcode() == ISD::FMUL && N1CFP &&
6151 N0.getOperand(1).getOpcode() == ISD::ConstantFP) {
6152 return DAG.getNode(ISD::FMA, dl, VT,
6154 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)),
6158 // (fma x, 1, y) -> (fadd x, y)
6159 // (fma x, -1, y) -> (fadd (fneg x), y)
6161 if (N1CFP->isExactlyValue(1.0))
6162 return DAG.getNode(ISD::FADD, dl, VT, N0, N2);
6164 if (N1CFP->isExactlyValue(-1.0) &&
6165 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {
6166 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0);
6167 AddToWorkList(RHSNeg.getNode());
6168 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg);
6172 // (fma x, c, x) -> (fmul x, (c+1))
6173 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2) {
6174 return DAG.getNode(ISD::FMUL, dl, VT,
6176 DAG.getNode(ISD::FADD, dl, VT,
6177 N1, DAG.getConstantFP(1.0, VT)));
6180 // (fma x, c, (fneg x)) -> (fmul x, (c-1))
6181 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6182 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) {
6183 return DAG.getNode(ISD::FMUL, dl, VT,
6185 DAG.getNode(ISD::FADD, dl, VT,
6186 N1, DAG.getConstantFP(-1.0, VT)));
6193 SDValue DAGCombiner::visitFDIV(SDNode *N) {
6194 SDValue N0 = N->getOperand(0);
6195 SDValue N1 = N->getOperand(1);
6196 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6197 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6198 EVT VT = N->getValueType(0);
6199 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6202 if (VT.isVector()) {
6203 SDValue FoldedVOp = SimplifyVBinOp(N);
6204 if (FoldedVOp.getNode()) return FoldedVOp;
6207 // fold (fdiv c1, c2) -> c1/c2
6209 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
6211 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
6212 if (N1CFP && DAG.getTarget().Options.UnsafeFPMath) {
6213 // Compute the reciprocal 1.0 / c2.
6214 APFloat N1APF = N1CFP->getValueAPF();
6215 APFloat Recip(N1APF.getSemantics(), 1); // 1.0
6216 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven);
6217 // Only do the transform if the reciprocal is a legal fp immediate that
6218 // isn't too nasty (eg NaN, denormal, ...).
6219 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty
6220 (!LegalOperations ||
6221 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
6222 // backend)... we should handle this gracefully after Legalize.
6223 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
6224 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
6225 TLI.isFPImmLegal(Recip, VT)))
6226 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0,
6227 DAG.getConstantFP(Recip, VT));
6230 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
6231 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
6232 &DAG.getTarget().Options)) {
6233 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
6234 &DAG.getTarget().Options)) {
6235 // Both can be negated for free, check to see if at least one is cheaper
6237 if (LHSNeg == 2 || RHSNeg == 2)
6238 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
6239 GetNegatedExpression(N0, DAG, LegalOperations),
6240 GetNegatedExpression(N1, DAG, LegalOperations));
6247 SDValue DAGCombiner::visitFREM(SDNode *N) {
6248 SDValue N0 = N->getOperand(0);
6249 SDValue N1 = N->getOperand(1);
6250 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6251 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6252 EVT VT = N->getValueType(0);
6254 // fold (frem c1, c2) -> fmod(c1,c2)
6256 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
6261 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
6262 SDValue N0 = N->getOperand(0);
6263 SDValue N1 = N->getOperand(1);
6264 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6265 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6266 EVT VT = N->getValueType(0);
6268 if (N0CFP && N1CFP) // Constant fold
6269 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
6272 const APFloat& V = N1CFP->getValueAPF();
6273 // copysign(x, c1) -> fabs(x) iff ispos(c1)
6274 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
6275 if (!V.isNegative()) {
6276 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
6277 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6279 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6280 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
6281 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
6285 // copysign(fabs(x), y) -> copysign(x, y)
6286 // copysign(fneg(x), y) -> copysign(x, y)
6287 // copysign(copysign(x,z), y) -> copysign(x, y)
6288 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
6289 N0.getOpcode() == ISD::FCOPYSIGN)
6290 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6291 N0.getOperand(0), N1);
6293 // copysign(x, abs(y)) -> abs(x)
6294 if (N1.getOpcode() == ISD::FABS)
6295 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6297 // copysign(x, copysign(y,z)) -> copysign(x, z)
6298 if (N1.getOpcode() == ISD::FCOPYSIGN)
6299 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6300 N0, N1.getOperand(1));
6302 // copysign(x, fp_extend(y)) -> copysign(x, y)
6303 // copysign(x, fp_round(y)) -> copysign(x, y)
6304 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
6305 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6306 N0, N1.getOperand(0));
6311 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
6312 SDValue N0 = N->getOperand(0);
6313 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
6314 EVT VT = N->getValueType(0);
6315 EVT OpVT = N0.getValueType();
6317 // fold (sint_to_fp c1) -> c1fp
6319 // ...but only if the target supports immediate floating-point values
6320 (!LegalOperations ||
6321 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
6322 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
6324 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
6325 // but UINT_TO_FP is legal on this target, try to convert.
6326 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
6327 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
6328 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
6329 if (DAG.SignBitIsZero(N0))
6330 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
6333 // The next optimizations are desireable only if SELECT_CC can be lowered.
6334 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
6335 // having to say they don't support SELECT_CC on every type the DAG knows
6336 // about, since there is no way to mark an opcode illegal at all value types
6337 // (See also visitSELECT)
6338 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) {
6339 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6340 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
6342 (!LegalOperations ||
6343 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6345 { N0.getOperand(0), N0.getOperand(1),
6346 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT),
6348 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6351 // fold (sint_to_fp (zext (setcc x, y, cc))) ->
6352 // (select_cc x, y, 1.0, 0.0,, cc)
6353 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
6354 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
6355 (!LegalOperations ||
6356 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6358 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
6359 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT),
6360 N0.getOperand(0).getOperand(2) };
6361 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6368 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
6369 SDValue N0 = N->getOperand(0);
6370 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
6371 EVT VT = N->getValueType(0);
6372 EVT OpVT = N0.getValueType();
6374 // fold (uint_to_fp c1) -> c1fp
6376 // ...but only if the target supports immediate floating-point values
6377 (!LegalOperations ||
6378 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
6379 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
6381 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
6382 // but SINT_TO_FP is legal on this target, try to convert.
6383 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
6384 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
6385 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
6386 if (DAG.SignBitIsZero(N0))
6387 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
6390 // The next optimizations are desireable only if SELECT_CC can be lowered.
6391 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
6392 // having to say they don't support SELECT_CC on every type the DAG knows
6393 // about, since there is no way to mark an opcode illegal at all value types
6394 // (See also visitSELECT)
6395 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) {
6396 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6398 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
6399 (!LegalOperations ||
6400 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6402 { N0.getOperand(0), N0.getOperand(1),
6403 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT),
6405 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6412 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
6413 SDValue N0 = N->getOperand(0);
6414 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6415 EVT VT = N->getValueType(0);
6417 // fold (fp_to_sint c1fp) -> c1
6419 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
6424 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
6425 SDValue N0 = N->getOperand(0);
6426 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6427 EVT VT = N->getValueType(0);
6429 // fold (fp_to_uint c1fp) -> c1
6431 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
6436 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
6437 SDValue N0 = N->getOperand(0);
6438 SDValue N1 = N->getOperand(1);
6439 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6440 EVT VT = N->getValueType(0);
6442 // fold (fp_round c1fp) -> c1fp
6444 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
6446 // fold (fp_round (fp_extend x)) -> x
6447 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
6448 return N0.getOperand(0);
6450 // fold (fp_round (fp_round x)) -> (fp_round x)
6451 if (N0.getOpcode() == ISD::FP_ROUND) {
6452 // This is a value preserving truncation if both round's are.
6453 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
6454 N0.getNode()->getConstantOperandVal(1) == 1;
6455 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
6456 DAG.getIntPtrConstant(IsTrunc));
6459 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
6460 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
6461 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
6462 N0.getOperand(0), N1);
6463 AddToWorkList(Tmp.getNode());
6464 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6465 Tmp, N0.getOperand(1));
6471 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
6472 SDValue N0 = N->getOperand(0);
6473 EVT VT = N->getValueType(0);
6474 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
6475 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6477 // fold (fp_round_inreg c1fp) -> c1fp
6478 if (N0CFP && isTypeLegal(EVT)) {
6479 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
6480 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
6486 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
6487 SDValue N0 = N->getOperand(0);
6488 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6489 EVT VT = N->getValueType(0);
6491 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
6492 if (N->hasOneUse() &&
6493 N->use_begin()->getOpcode() == ISD::FP_ROUND)
6496 // fold (fp_extend c1fp) -> c1fp
6498 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
6500 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
6502 if (N0.getOpcode() == ISD::FP_ROUND
6503 && N0.getNode()->getConstantOperandVal(1) == 1) {
6504 SDValue In = N0.getOperand(0);
6505 if (In.getValueType() == VT) return In;
6506 if (VT.bitsLT(In.getValueType()))
6507 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
6508 In, N0.getOperand(1));
6509 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
6512 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
6513 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
6514 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6515 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
6516 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6517 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
6519 LN0->getBasePtr(), LN0->getPointerInfo(),
6521 LN0->isVolatile(), LN0->isNonTemporal(),
6522 LN0->getAlignment());
6523 CombineTo(N, ExtLoad);
6524 CombineTo(N0.getNode(),
6525 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
6526 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
6527 ExtLoad.getValue(1));
6528 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6534 SDValue DAGCombiner::visitFNEG(SDNode *N) {
6535 SDValue N0 = N->getOperand(0);
6536 EVT VT = N->getValueType(0);
6538 if (VT.isVector()) {
6539 SDValue FoldedVOp = SimplifyVUnaryOp(N);
6540 if (FoldedVOp.getNode()) return FoldedVOp;
6543 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
6544 &DAG.getTarget().Options))
6545 return GetNegatedExpression(N0, DAG, LegalOperations);
6547 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
6548 // constant pool values.
6549 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST &&
6551 N0.getNode()->hasOneUse() &&
6552 N0.getOperand(0).getValueType().isInteger()) {
6553 SDValue Int = N0.getOperand(0);
6554 EVT IntVT = Int.getValueType();
6555 if (IntVT.isInteger() && !IntVT.isVector()) {
6556 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
6557 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6558 AddToWorkList(Int.getNode());
6559 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6564 // (fneg (fmul c, x)) -> (fmul -c, x)
6565 if (N0.getOpcode() == ISD::FMUL) {
6566 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
6568 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
6570 DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
6578 SDValue DAGCombiner::visitFCEIL(SDNode *N) {
6579 SDValue N0 = N->getOperand(0);
6580 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6581 EVT VT = N->getValueType(0);
6583 // fold (fceil c1) -> fceil(c1)
6585 return DAG.getNode(ISD::FCEIL, N->getDebugLoc(), VT, N0);
6590 SDValue DAGCombiner::visitFTRUNC(SDNode *N) {
6591 SDValue N0 = N->getOperand(0);
6592 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6593 EVT VT = N->getValueType(0);
6595 // fold (ftrunc c1) -> ftrunc(c1)
6597 return DAG.getNode(ISD::FTRUNC, N->getDebugLoc(), VT, N0);
6602 SDValue DAGCombiner::visitFFLOOR(SDNode *N) {
6603 SDValue N0 = N->getOperand(0);
6604 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6605 EVT VT = N->getValueType(0);
6607 // fold (ffloor c1) -> ffloor(c1)
6609 return DAG.getNode(ISD::FFLOOR, N->getDebugLoc(), VT, N0);
6614 SDValue DAGCombiner::visitFABS(SDNode *N) {
6615 SDValue N0 = N->getOperand(0);
6616 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6617 EVT VT = N->getValueType(0);
6619 if (VT.isVector()) {
6620 SDValue FoldedVOp = SimplifyVUnaryOp(N);
6621 if (FoldedVOp.getNode()) return FoldedVOp;
6624 // fold (fabs c1) -> fabs(c1)
6626 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6627 // fold (fabs (fabs x)) -> (fabs x)
6628 if (N0.getOpcode() == ISD::FABS)
6629 return N->getOperand(0);
6630 // fold (fabs (fneg x)) -> (fabs x)
6631 // fold (fabs (fcopysign x, y)) -> (fabs x)
6632 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
6633 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
6635 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
6636 // constant pool values.
6637 if (!TLI.isFAbsFree(VT) &&
6638 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
6639 N0.getOperand(0).getValueType().isInteger() &&
6640 !N0.getOperand(0).getValueType().isVector()) {
6641 SDValue Int = N0.getOperand(0);
6642 EVT IntVT = Int.getValueType();
6643 if (IntVT.isInteger() && !IntVT.isVector()) {
6644 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
6645 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6646 AddToWorkList(Int.getNode());
6647 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6648 N->getValueType(0), Int);
6655 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
6656 SDValue Chain = N->getOperand(0);
6657 SDValue N1 = N->getOperand(1);
6658 SDValue N2 = N->getOperand(2);
6660 // If N is a constant we could fold this into a fallthrough or unconditional
6661 // branch. However that doesn't happen very often in normal code, because
6662 // Instcombine/SimplifyCFG should have handled the available opportunities.
6663 // If we did this folding here, it would be necessary to update the
6664 // MachineBasicBlock CFG, which is awkward.
6666 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
6668 if (N1.getOpcode() == ISD::SETCC &&
6669 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
6670 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6671 Chain, N1.getOperand(2),
6672 N1.getOperand(0), N1.getOperand(1), N2);
6675 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
6676 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
6677 (N1.getOperand(0).hasOneUse() &&
6678 N1.getOperand(0).getOpcode() == ISD::SRL))) {
6680 if (N1.getOpcode() == ISD::TRUNCATE) {
6681 // Look pass the truncate.
6682 Trunc = N1.getNode();
6683 N1 = N1.getOperand(0);
6686 // Match this pattern so that we can generate simpler code:
6689 // %b = and i32 %a, 2
6690 // %c = srl i32 %b, 1
6691 // brcond i32 %c ...
6696 // %b = and i32 %a, 2
6697 // %c = setcc eq %b, 0
6700 // This applies only when the AND constant value has one bit set and the
6701 // SRL constant is equal to the log2 of the AND constant. The back-end is
6702 // smart enough to convert the result into a TEST/JMP sequence.
6703 SDValue Op0 = N1.getOperand(0);
6704 SDValue Op1 = N1.getOperand(1);
6706 if (Op0.getOpcode() == ISD::AND &&
6707 Op1.getOpcode() == ISD::Constant) {
6708 SDValue AndOp1 = Op0.getOperand(1);
6710 if (AndOp1.getOpcode() == ISD::Constant) {
6711 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
6713 if (AndConst.isPowerOf2() &&
6714 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
6716 DAG.getSetCC(N->getDebugLoc(),
6717 TLI.getSetCCResultType(Op0.getValueType()),
6718 Op0, DAG.getConstant(0, Op0.getValueType()),
6721 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6722 MVT::Other, Chain, SetCC, N2);
6723 // Don't add the new BRCond into the worklist or else SimplifySelectCC
6724 // will convert it back to (X & C1) >> C2.
6725 CombineTo(N, NewBRCond, false);
6726 // Truncate is dead.
6728 removeFromWorkList(Trunc);
6729 DAG.DeleteNode(Trunc);
6731 // Replace the uses of SRL with SETCC
6732 WorkListRemover DeadNodes(*this);
6733 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6734 removeFromWorkList(N1.getNode());
6735 DAG.DeleteNode(N1.getNode());
6736 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6742 // Restore N1 if the above transformation doesn't match.
6743 N1 = N->getOperand(1);
6746 // Transform br(xor(x, y)) -> br(x != y)
6747 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
6748 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
6749 SDNode *TheXor = N1.getNode();
6750 SDValue Op0 = TheXor->getOperand(0);
6751 SDValue Op1 = TheXor->getOperand(1);
6752 if (Op0.getOpcode() == Op1.getOpcode()) {
6753 // Avoid missing important xor optimizations.
6754 SDValue Tmp = visitXOR(TheXor);
6755 if (Tmp.getNode()) {
6756 if (Tmp.getNode() != TheXor) {
6757 DEBUG(dbgs() << "\nReplacing.8 ";
6759 dbgs() << "\nWith: ";
6760 Tmp.getNode()->dump(&DAG);
6762 WorkListRemover DeadNodes(*this);
6763 DAG.ReplaceAllUsesOfValueWith(N1, Tmp);
6764 removeFromWorkList(TheXor);
6765 DAG.DeleteNode(TheXor);
6766 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6767 MVT::Other, Chain, Tmp, N2);
6770 // visitXOR has changed XOR's operands.
6771 Op0 = TheXor->getOperand(0);
6772 Op1 = TheXor->getOperand(1);
6776 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
6778 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
6779 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
6780 Op0.getOpcode() == ISD::XOR) {
6781 TheXor = Op0.getNode();
6785 EVT SetCCVT = N1.getValueType();
6787 SetCCVT = TLI.getSetCCResultType(SetCCVT);
6788 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
6791 Equal ? ISD::SETEQ : ISD::SETNE);
6792 // Replace the uses of XOR with SETCC
6793 WorkListRemover DeadNodes(*this);
6794 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6795 removeFromWorkList(N1.getNode());
6796 DAG.DeleteNode(N1.getNode());
6797 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6798 MVT::Other, Chain, SetCC, N2);
6805 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
6807 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
6808 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
6809 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
6811 // If N is a constant we could fold this into a fallthrough or unconditional
6812 // branch. However that doesn't happen very often in normal code, because
6813 // Instcombine/SimplifyCFG should have handled the available opportunities.
6814 // If we did this folding here, it would be necessary to update the
6815 // MachineBasicBlock CFG, which is awkward.
6817 // Use SimplifySetCC to simplify SETCC's.
6818 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
6819 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
6821 if (Simp.getNode()) AddToWorkList(Simp.getNode());
6823 // fold to a simpler setcc
6824 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
6825 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6826 N->getOperand(0), Simp.getOperand(2),
6827 Simp.getOperand(0), Simp.getOperand(1),
6833 /// canFoldInAddressingMode - Return true if 'Use' is a load or a store that
6834 /// uses N as its base pointer and that N may be folded in the load / store
6835 /// addressing mode.
6836 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
6838 const TargetLowering &TLI) {
6840 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
6841 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
6843 VT = Use->getValueType(0);
6844 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
6845 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
6847 VT = ST->getValue().getValueType();
6851 TargetLowering::AddrMode AM;
6852 if (N->getOpcode() == ISD::ADD) {
6853 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6856 AM.BaseOffs = Offset->getSExtValue();
6860 } else if (N->getOpcode() == ISD::SUB) {
6861 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6864 AM.BaseOffs = -Offset->getSExtValue();
6871 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
6874 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
6875 /// pre-indexed load / store when the base pointer is an add or subtract
6876 /// and it has other uses besides the load / store. After the
6877 /// transformation, the new indexed load / store has effectively folded
6878 /// the add / subtract in and all of its other uses are redirected to the
6879 /// new load / store.
6880 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
6881 if (Level < AfterLegalizeDAG)
6887 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6888 if (LD->isIndexed())
6890 VT = LD->getMemoryVT();
6891 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
6892 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
6894 Ptr = LD->getBasePtr();
6895 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6896 if (ST->isIndexed())
6898 VT = ST->getMemoryVT();
6899 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
6900 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
6902 Ptr = ST->getBasePtr();
6908 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
6909 // out. There is no reason to make this a preinc/predec.
6910 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
6911 Ptr.getNode()->hasOneUse())
6914 // Ask the target to do addressing mode selection.
6917 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6918 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
6920 // Don't create a indexed load / store with zero offset.
6921 if (isa<ConstantSDNode>(Offset) &&
6922 cast<ConstantSDNode>(Offset)->isNullValue())
6925 // Try turning it into a pre-indexed load / store except when:
6926 // 1) The new base ptr is a frame index.
6927 // 2) If N is a store and the new base ptr is either the same as or is a
6928 // predecessor of the value being stored.
6929 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
6930 // that would create a cycle.
6931 // 4) All uses are load / store ops that use it as old base ptr.
6933 // Check #1. Preinc'ing a frame index would require copying the stack pointer
6934 // (plus the implicit offset) to a register to preinc anyway.
6935 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6940 SDValue Val = cast<StoreSDNode>(N)->getValue();
6941 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
6945 // Now check for #3 and #4.
6946 bool RealUse = false;
6948 // Caches for hasPredecessorHelper
6949 SmallPtrSet<const SDNode *, 32> Visited;
6950 SmallVector<const SDNode *, 16> Worklist;
6952 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6953 E = Ptr.getNode()->use_end(); I != E; ++I) {
6957 if (N->hasPredecessorHelper(Use, Visited, Worklist))
6960 // If Ptr may be folded in addressing mode of other use, then it's
6961 // not profitable to do this transformation.
6962 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
6971 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6972 BasePtr, Offset, AM);
6974 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6975 BasePtr, Offset, AM);
6978 DEBUG(dbgs() << "\nReplacing.4 ";
6980 dbgs() << "\nWith: ";
6981 Result.getNode()->dump(&DAG);
6983 WorkListRemover DeadNodes(*this);
6985 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
6986 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
6988 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
6991 // Finally, since the node is now dead, remove it from the graph.
6994 // Replace the uses of Ptr with uses of the updated base value.
6995 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0));
6996 removeFromWorkList(Ptr.getNode());
6997 DAG.DeleteNode(Ptr.getNode());
7002 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
7003 /// add / sub of the base pointer node into a post-indexed load / store.
7004 /// The transformation folded the add / subtract into the new indexed
7005 /// load / store effectively and all of its uses are redirected to the
7006 /// new load / store.
7007 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
7008 if (Level < AfterLegalizeDAG)
7014 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7015 if (LD->isIndexed())
7017 VT = LD->getMemoryVT();
7018 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
7019 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
7021 Ptr = LD->getBasePtr();
7022 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7023 if (ST->isIndexed())
7025 VT = ST->getMemoryVT();
7026 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
7027 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
7029 Ptr = ST->getBasePtr();
7035 if (Ptr.getNode()->hasOneUse())
7038 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
7039 E = Ptr.getNode()->use_end(); I != E; ++I) {
7042 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
7047 ISD::MemIndexedMode AM = ISD::UNINDEXED;
7048 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
7049 // Don't create a indexed load / store with zero offset.
7050 if (isa<ConstantSDNode>(Offset) &&
7051 cast<ConstantSDNode>(Offset)->isNullValue())
7054 // Try turning it into a post-indexed load / store except when
7055 // 1) All uses are load / store ops that use it as base ptr (and
7056 // it may be folded as addressing mmode).
7057 // 2) Op must be independent of N, i.e. Op is neither a predecessor
7058 // nor a successor of N. Otherwise, if Op is folded that would
7061 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
7065 bool TryNext = false;
7066 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
7067 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
7069 if (Use == Ptr.getNode())
7072 // If all the uses are load / store addresses, then don't do the
7074 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
7075 bool RealUse = false;
7076 for (SDNode::use_iterator III = Use->use_begin(),
7077 EEE = Use->use_end(); III != EEE; ++III) {
7078 SDNode *UseUse = *III;
7079 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
7094 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
7095 SDValue Result = isLoad
7096 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
7097 BasePtr, Offset, AM)
7098 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
7099 BasePtr, Offset, AM);
7102 DEBUG(dbgs() << "\nReplacing.5 ";
7104 dbgs() << "\nWith: ";
7105 Result.getNode()->dump(&DAG);
7107 WorkListRemover DeadNodes(*this);
7109 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
7110 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
7112 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
7115 // Finally, since the node is now dead, remove it from the graph.
7118 // Replace the uses of Use with uses of the updated base value.
7119 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
7120 Result.getValue(isLoad ? 1 : 0));
7121 removeFromWorkList(Op);
7131 SDValue DAGCombiner::visitLOAD(SDNode *N) {
7132 LoadSDNode *LD = cast<LoadSDNode>(N);
7133 SDValue Chain = LD->getChain();
7134 SDValue Ptr = LD->getBasePtr();
7136 // If load is not volatile and there are no uses of the loaded value (and
7137 // the updated indexed value in case of indexed loads), change uses of the
7138 // chain value into uses of the chain input (i.e. delete the dead load).
7139 if (!LD->isVolatile()) {
7140 if (N->getValueType(1) == MVT::Other) {
7142 if (!N->hasAnyUseOfValue(0)) {
7143 // It's not safe to use the two value CombineTo variant here. e.g.
7144 // v1, chain2 = load chain1, loc
7145 // v2, chain3 = load chain2, loc
7147 // Now we replace use of chain2 with chain1. This makes the second load
7148 // isomorphic to the one we are deleting, and thus makes this load live.
7149 DEBUG(dbgs() << "\nReplacing.6 ";
7151 dbgs() << "\nWith chain: ";
7152 Chain.getNode()->dump(&DAG);
7154 WorkListRemover DeadNodes(*this);
7155 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
7157 if (N->use_empty()) {
7158 removeFromWorkList(N);
7162 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7166 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
7167 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) {
7168 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
7169 DEBUG(dbgs() << "\nReplacing.7 ";
7171 dbgs() << "\nWith: ";
7172 Undef.getNode()->dump(&DAG);
7173 dbgs() << " and 2 other values\n");
7174 WorkListRemover DeadNodes(*this);
7175 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef);
7176 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
7177 DAG.getUNDEF(N->getValueType(1)));
7178 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain);
7179 removeFromWorkList(N);
7181 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7186 // If this load is directly stored, replace the load value with the stored
7188 // TODO: Handle store large -> read small portion.
7189 // TODO: Handle TRUNCSTORE/LOADEXT
7190 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
7191 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
7192 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
7193 if (PrevST->getBasePtr() == Ptr &&
7194 PrevST->getValue().getValueType() == N->getValueType(0))
7195 return CombineTo(N, Chain.getOperand(1), Chain);
7199 // Try to infer better alignment information than the load already has.
7200 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
7201 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
7202 if (Align > LD->getMemOperand()->getBaseAlignment()) {
7204 DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
7205 LD->getValueType(0),
7206 Chain, Ptr, LD->getPointerInfo(),
7208 LD->isVolatile(), LD->isNonTemporal(), Align);
7209 return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true);
7215 // Walk up chain skipping non-aliasing memory nodes.
7216 SDValue BetterChain = FindBetterChain(N, Chain);
7218 // If there is a better chain.
7219 if (Chain != BetterChain) {
7222 // Replace the chain to void dependency.
7223 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
7224 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
7225 BetterChain, Ptr, LD->getPointerInfo(),
7226 LD->isVolatile(), LD->isNonTemporal(),
7227 LD->isInvariant(), LD->getAlignment());
7229 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
7230 LD->getValueType(0),
7231 BetterChain, Ptr, LD->getPointerInfo(),
7234 LD->isNonTemporal(),
7235 LD->getAlignment());
7238 // Create token factor to keep old chain connected.
7239 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
7240 MVT::Other, Chain, ReplLoad.getValue(1));
7242 // Make sure the new and old chains are cleaned up.
7243 AddToWorkList(Token.getNode());
7245 // Replace uses with load result and token factor. Don't add users
7247 return CombineTo(N, ReplLoad.getValue(0), Token, false);
7251 // Try transforming N to an indexed load.
7252 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
7253 return SDValue(N, 0);
7258 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
7259 /// load is having specific bytes cleared out. If so, return the byte size
7260 /// being masked out and the shift amount.
7261 static std::pair<unsigned, unsigned>
7262 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
7263 std::pair<unsigned, unsigned> Result(0, 0);
7265 // Check for the structure we're looking for.
7266 if (V->getOpcode() != ISD::AND ||
7267 !isa<ConstantSDNode>(V->getOperand(1)) ||
7268 !ISD::isNormalLoad(V->getOperand(0).getNode()))
7271 // Check the chain and pointer.
7272 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
7273 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
7275 // The store should be chained directly to the load or be an operand of a
7277 if (LD == Chain.getNode())
7279 else if (Chain->getOpcode() != ISD::TokenFactor)
7280 return Result; // Fail.
7283 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
7284 if (Chain->getOperand(i).getNode() == LD) {
7288 if (!isOk) return Result;
7291 // This only handles simple types.
7292 if (V.getValueType() != MVT::i16 &&
7293 V.getValueType() != MVT::i32 &&
7294 V.getValueType() != MVT::i64)
7297 // Check the constant mask. Invert it so that the bits being masked out are
7298 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
7299 // follow the sign bit for uniformity.
7300 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
7301 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
7302 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
7303 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
7304 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
7305 if (NotMaskLZ == 64) return Result; // All zero mask.
7307 // See if we have a continuous run of bits. If so, we have 0*1+0*
7308 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
7311 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
7312 if (V.getValueType() != MVT::i64 && NotMaskLZ)
7313 NotMaskLZ -= 64-V.getValueSizeInBits();
7315 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
7316 switch (MaskedBytes) {
7320 default: return Result; // All one mask, or 5-byte mask.
7323 // Verify that the first bit starts at a multiple of mask so that the access
7324 // is aligned the same as the access width.
7325 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
7327 Result.first = MaskedBytes;
7328 Result.second = NotMaskTZ/8;
7333 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
7334 /// provides a value as specified by MaskInfo. If so, replace the specified
7335 /// store with a narrower store of truncated IVal.
7337 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
7338 SDValue IVal, StoreSDNode *St,
7340 unsigned NumBytes = MaskInfo.first;
7341 unsigned ByteShift = MaskInfo.second;
7342 SelectionDAG &DAG = DC->getDAG();
7344 // Check to see if IVal is all zeros in the part being masked in by the 'or'
7345 // that uses this. If not, this is not a replacement.
7346 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
7347 ByteShift*8, (ByteShift+NumBytes)*8);
7348 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
7350 // Check that it is legal on the target to do this. It is legal if the new
7351 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
7353 MVT VT = MVT::getIntegerVT(NumBytes*8);
7354 if (!DC->isTypeLegal(VT))
7357 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
7358 // shifted by ByteShift and truncated down to NumBytes.
7360 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
7361 DAG.getConstant(ByteShift*8,
7362 DC->getShiftAmountTy(IVal.getValueType())));
7364 // Figure out the offset for the store and the alignment of the access.
7366 unsigned NewAlign = St->getAlignment();
7368 if (DAG.getTargetLoweringInfo().isLittleEndian())
7369 StOffset = ByteShift;
7371 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
7373 SDValue Ptr = St->getBasePtr();
7375 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
7376 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
7377 NewAlign = MinAlign(NewAlign, StOffset);
7380 // Truncate down to the new size.
7381 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
7384 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
7385 St->getPointerInfo().getWithOffset(StOffset),
7386 false, false, NewAlign).getNode();
7390 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
7391 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
7392 /// of the loaded bits, try narrowing the load and store if it would end up
7393 /// being a win for performance or code size.
7394 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
7395 StoreSDNode *ST = cast<StoreSDNode>(N);
7396 if (ST->isVolatile())
7399 SDValue Chain = ST->getChain();
7400 SDValue Value = ST->getValue();
7401 SDValue Ptr = ST->getBasePtr();
7402 EVT VT = Value.getValueType();
7404 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
7407 unsigned Opc = Value.getOpcode();
7409 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
7410 // is a byte mask indicating a consecutive number of bytes, check to see if
7411 // Y is known to provide just those bytes. If so, we try to replace the
7412 // load + replace + store sequence with a single (narrower) store, which makes
7414 if (Opc == ISD::OR) {
7415 std::pair<unsigned, unsigned> MaskedLoad;
7416 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
7417 if (MaskedLoad.first)
7418 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
7419 Value.getOperand(1), ST,this))
7420 return SDValue(NewST, 0);
7422 // Or is commutative, so try swapping X and Y.
7423 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
7424 if (MaskedLoad.first)
7425 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
7426 Value.getOperand(0), ST,this))
7427 return SDValue(NewST, 0);
7430 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
7431 Value.getOperand(1).getOpcode() != ISD::Constant)
7434 SDValue N0 = Value.getOperand(0);
7435 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7436 Chain == SDValue(N0.getNode(), 1)) {
7437 LoadSDNode *LD = cast<LoadSDNode>(N0);
7438 if (LD->getBasePtr() != Ptr ||
7439 LD->getPointerInfo().getAddrSpace() !=
7440 ST->getPointerInfo().getAddrSpace())
7443 // Find the type to narrow it the load / op / store to.
7444 SDValue N1 = Value.getOperand(1);
7445 unsigned BitWidth = N1.getValueSizeInBits();
7446 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
7447 if (Opc == ISD::AND)
7448 Imm ^= APInt::getAllOnesValue(BitWidth);
7449 if (Imm == 0 || Imm.isAllOnesValue())
7451 unsigned ShAmt = Imm.countTrailingZeros();
7452 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
7453 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
7454 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
7455 while (NewBW < BitWidth &&
7456 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
7457 TLI.isNarrowingProfitable(VT, NewVT))) {
7458 NewBW = NextPowerOf2(NewBW);
7459 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
7461 if (NewBW >= BitWidth)
7464 // If the lsb changed does not start at the type bitwidth boundary,
7465 // start at the previous one.
7467 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
7468 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt,
7469 std::min(BitWidth, ShAmt + NewBW));
7470 if ((Imm & Mask) == Imm) {
7471 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
7472 if (Opc == ISD::AND)
7473 NewImm ^= APInt::getAllOnesValue(NewBW);
7474 uint64_t PtrOff = ShAmt / 8;
7475 // For big endian targets, we need to adjust the offset to the pointer to
7476 // load the correct bytes.
7477 if (TLI.isBigEndian())
7478 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
7480 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
7481 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
7482 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy))
7485 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
7486 Ptr.getValueType(), Ptr,
7487 DAG.getConstant(PtrOff, Ptr.getValueType()));
7488 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
7489 LD->getChain(), NewPtr,
7490 LD->getPointerInfo().getWithOffset(PtrOff),
7491 LD->isVolatile(), LD->isNonTemporal(),
7492 LD->isInvariant(), NewAlign);
7493 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
7494 DAG.getConstant(NewImm, NewVT));
7495 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
7497 ST->getPointerInfo().getWithOffset(PtrOff),
7498 false, false, NewAlign);
7500 AddToWorkList(NewPtr.getNode());
7501 AddToWorkList(NewLD.getNode());
7502 AddToWorkList(NewVal.getNode());
7503 WorkListRemover DeadNodes(*this);
7504 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
7513 /// TransformFPLoadStorePair - For a given floating point load / store pair,
7514 /// if the load value isn't used by any other operations, then consider
7515 /// transforming the pair to integer load / store operations if the target
7516 /// deems the transformation profitable.
7517 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
7518 StoreSDNode *ST = cast<StoreSDNode>(N);
7519 SDValue Chain = ST->getChain();
7520 SDValue Value = ST->getValue();
7521 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
7522 Value.hasOneUse() &&
7523 Chain == SDValue(Value.getNode(), 1)) {
7524 LoadSDNode *LD = cast<LoadSDNode>(Value);
7525 EVT VT = LD->getMemoryVT();
7526 if (!VT.isFloatingPoint() ||
7527 VT != ST->getMemoryVT() ||
7528 LD->isNonTemporal() ||
7529 ST->isNonTemporal() ||
7530 LD->getPointerInfo().getAddrSpace() != 0 ||
7531 ST->getPointerInfo().getAddrSpace() != 0)
7534 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
7535 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
7536 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
7537 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
7538 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
7541 unsigned LDAlign = LD->getAlignment();
7542 unsigned STAlign = ST->getAlignment();
7543 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
7544 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy);
7545 if (LDAlign < ABIAlign || STAlign < ABIAlign)
7548 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(),
7549 LD->getChain(), LD->getBasePtr(),
7550 LD->getPointerInfo(),
7551 false, false, false, LDAlign);
7553 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(),
7554 NewLD, ST->getBasePtr(),
7555 ST->getPointerInfo(),
7556 false, false, STAlign);
7558 AddToWorkList(NewLD.getNode());
7559 AddToWorkList(NewST.getNode());
7560 WorkListRemover DeadNodes(*this);
7561 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1));
7569 /// Returns the base pointer and an integer offset from that object.
7570 static std::pair<SDValue, int64_t> GetPointerBaseAndOffset(SDValue Ptr) {
7571 if (Ptr->getOpcode() == ISD::ADD && isa<ConstantSDNode>(Ptr->getOperand(1))) {
7572 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
7573 SDValue Base = Ptr->getOperand(0);
7574 return std::make_pair(Base, Offset);
7577 return std::make_pair(Ptr, 0);
7580 /// Holds a pointer to an LSBaseSDNode as well as information on where it
7581 /// is located in a sequence of memory operations connected by a chain.
7583 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq):
7584 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { }
7585 // Ptr to the mem node.
7586 LSBaseSDNode *MemNode;
7587 // Offset from the base ptr.
7588 int64_t OffsetFromBase;
7589 // What is the sequence number of this mem node.
7590 // Lowest mem operand in the DAG starts at zero.
7591 unsigned SequenceNum;
7594 /// Sorts store nodes in a link according to their offset from a shared
7596 struct ConsecutiveMemoryChainSorter {
7597 bool operator()(MemOpLink LHS, MemOpLink RHS) {
7598 return LHS.OffsetFromBase < RHS.OffsetFromBase;
7602 bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
7603 EVT MemVT = St->getMemoryVT();
7604 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8;
7606 // Don't merge vectors into wider inputs.
7607 if (MemVT.isVector() || !MemVT.isSimple())
7610 // Perform an early exit check. Do not bother looking at stored values that
7611 // are not constants or loads.
7612 SDValue StoredVal = St->getValue();
7613 bool IsLoadSrc = isa<LoadSDNode>(StoredVal);
7614 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) &&
7618 // Only look at ends of store sequences.
7619 SDValue Chain = SDValue(St, 1);
7620 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE)
7623 // This holds the base pointer and the offset in bytes from the base pointer.
7624 std::pair<SDValue, int64_t> BasePtr =
7625 GetPointerBaseAndOffset(St->getBasePtr());
7627 // We must have a base and an offset.
7628 if (!BasePtr.first.getNode())
7631 // Do not handle stores to undef base pointers.
7632 if (BasePtr.first.getOpcode() == ISD::UNDEF)
7635 // Save the LoadSDNodes that we find in the chain.
7636 // We need to make sure that these nodes do not interfere with
7637 // any of the store nodes.
7638 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes;
7640 // Save the StoreSDNodes that we find in the chain.
7641 SmallVector<MemOpLink, 8> StoreNodes;
7643 // Walk up the chain and look for nodes with offsets from the same
7644 // base pointer. Stop when reaching an instruction with a different kind
7645 // or instruction which has a different base pointer.
7647 StoreSDNode *Index = St;
7649 // If the chain has more than one use, then we can't reorder the mem ops.
7650 if (Index != St && !SDValue(Index, 1)->hasOneUse())
7653 // Find the base pointer and offset for this memory node.
7654 std::pair<SDValue, int64_t> Ptr =
7655 GetPointerBaseAndOffset(Index->getBasePtr());
7657 // Check that the base pointer is the same as the original one.
7658 if (Ptr.first.getNode() != BasePtr.first.getNode())
7661 // Check that the alignment is the same.
7662 if (Index->getAlignment() != St->getAlignment())
7665 // The memory operands must not be volatile.
7666 if (Index->isVolatile() || Index->isIndexed())
7670 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index))
7671 if (St->isTruncatingStore())
7674 // The stored memory type must be the same.
7675 if (Index->getMemoryVT() != MemVT)
7678 // We do not allow unaligned stores because we want to prevent overriding
7680 if (Index->getAlignment()*8 != MemVT.getSizeInBits())
7683 // We found a potential memory operand to merge.
7684 StoreNodes.push_back(MemOpLink(Index, Ptr.second, Seq++));
7686 // Find the next memory operand in the chain. If the next operand in the
7687 // chain is a store then move up and continue the scan with the next
7688 // memory operand. If the next operand is a load save it and use alias
7689 // information to check if it interferes with anything.
7690 SDNode *NextInChain = Index->getChain().getNode();
7692 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) {
7693 // We found a store node. Use it for the next iteration.
7696 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) {
7697 // Save the load node for later. Continue the scan.
7698 AliasLoadNodes.push_back(Ldn);
7699 NextInChain = Ldn->getChain().getNode();
7708 // Check if there is anything to merge.
7709 if (StoreNodes.size() < 2)
7712 // Sort the memory operands according to their distance from the base pointer.
7713 std::sort(StoreNodes.begin(), StoreNodes.end(),
7714 ConsecutiveMemoryChainSorter());
7716 // Scan the memory operations on the chain and find the first non-consecutive
7717 // store memory address.
7718 unsigned LastConsecutiveStore = 0;
7719 int64_t StartAddress = StoreNodes[0].OffsetFromBase;
7720 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) {
7722 // Check that the addresses are consecutive starting from the second
7723 // element in the list of stores.
7725 int64_t CurrAddress = StoreNodes[i].OffsetFromBase;
7726 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
7731 // Check if this store interferes with any of the loads that we found.
7732 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld)
7733 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) {
7737 // We found a load that alias with this store. Stop the sequence.
7741 // Mark this node as useful.
7742 LastConsecutiveStore = i;
7745 // The node with the lowest store address.
7746 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;
7748 // Store the constants into memory as one consecutive store.
7750 unsigned LastLegalType = 0;
7751 unsigned LastLegalVectorType = 0;
7752 bool NonZero = false;
7753 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
7754 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
7755 SDValue StoredVal = St->getValue();
7757 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) {
7758 NonZero |= !C->isNullValue();
7759 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) {
7760 NonZero |= !C->getConstantFPValue()->isNullValue();
7766 // Find a legal type for the constant store.
7767 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
7768 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
7769 if (TLI.isTypeLegal(StoreTy))
7770 LastLegalType = i+1;
7772 // Find a legal type for the vector store.
7773 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
7774 if (TLI.isTypeLegal(Ty))
7775 LastLegalVectorType = i + 1;
7778 // We only use vectors if the constant is known to be zero and the
7779 // function is not marked with the noimplicitfloat attribute.
7780 if (NonZero || (DAG.getMachineFunction().getFunction()->getAttributes().
7781 hasAttribute(AttributeSet::FunctionIndex,
7782 Attribute::NoImplicitFloat)))
7783 LastLegalVectorType = 0;
7785 // Check if we found a legal integer type to store.
7786 if (LastLegalType == 0 && LastLegalVectorType == 0)
7789 bool UseVector = LastLegalVectorType > LastLegalType;
7790 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType;
7792 // Make sure we have something to merge.
7796 unsigned EarliestNodeUsed = 0;
7797 for (unsigned i=0; i < NumElem; ++i) {
7798 // Find a chain for the new wide-store operand. Notice that some
7799 // of the store nodes that we found may not be selected for inclusion
7800 // in the wide store. The chain we use needs to be the chain of the
7801 // earliest store node which is *used* and replaced by the wide store.
7802 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
7803 EarliestNodeUsed = i;
7806 // The earliest Node in the DAG.
7807 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
7808 DebugLoc DL = StoreNodes[0].MemNode->getDebugLoc();
7812 // Find a legal type for the vector store.
7813 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
7814 assert(TLI.isTypeLegal(Ty) && "Illegal vector store");
7815 StoredVal = DAG.getConstant(0, Ty);
7817 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
7818 APInt StoreInt(StoreBW, 0);
7820 // Construct a single integer constant which is made of the smaller
7822 bool IsLE = TLI.isLittleEndian();
7823 for (unsigned i = 0; i < NumElem ; ++i) {
7824 unsigned Idx = IsLE ?(NumElem - 1 - i) : i;
7825 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode);
7826 SDValue Val = St->getValue();
7827 StoreInt<<=ElementSizeBytes*8;
7828 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) {
7829 StoreInt|=C->getAPIntValue().zext(StoreBW);
7830 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) {
7831 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW);
7833 assert(false && "Invalid constant element type");
7837 // Create the new Load and Store operations.
7838 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
7839 StoredVal = DAG.getConstant(StoreInt, StoreTy);
7842 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal,
7843 FirstInChain->getBasePtr(),
7844 FirstInChain->getPointerInfo(),
7846 FirstInChain->getAlignment());
7848 // Replace the first store with the new store
7849 CombineTo(EarliestOp, NewStore);
7850 // Erase all other stores.
7851 for (unsigned i = 0; i < NumElem ; ++i) {
7852 if (StoreNodes[i].MemNode == EarliestOp)
7854 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
7855 // ReplaceAllUsesWith will replace all uses that existed when it was
7856 // called, but graph optimizations may cause new ones to appear. For
7857 // example, the case in pr14333 looks like
7859 // St's chain -> St -> another store -> X
7861 // And the only difference from St to the other store is the chain.
7862 // When we change it's chain to be St's chain they become identical,
7863 // get CSEed and the net result is that X is now a use of St.
7864 // Since we know that St is redundant, just iterate.
7865 while (!St->use_empty())
7866 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain());
7867 removeFromWorkList(St);
7874 // Below we handle the case of multiple consecutive stores that
7875 // come from multiple consecutive loads. We merge them into a single
7876 // wide load and a single wide store.
7878 // Look for load nodes which are used by the stored values.
7879 SmallVector<MemOpLink, 8> LoadNodes;
7881 // Find acceptable loads. Loads need to have the same chain (token factor),
7882 // must not be zext, volatile, indexed, and they must be consecutive.
7884 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
7885 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
7886 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue());
7889 // Loads must only have one use.
7890 if (!Ld->hasNUsesOfValue(1, 0))
7893 // Check that the alignment is the same as the stores.
7894 if (Ld->getAlignment() != St->getAlignment())
7897 // The memory operands must not be volatile.
7898 if (Ld->isVolatile() || Ld->isIndexed())
7901 // We do not accept ext loads.
7902 if (Ld->getExtensionType() != ISD::NON_EXTLOAD)
7905 // The stored memory type must be the same.
7906 if (Ld->getMemoryVT() != MemVT)
7909 std::pair<SDValue, int64_t> LdPtr =
7910 GetPointerBaseAndOffset(Ld->getBasePtr());
7912 // If this is not the first ptr that we check.
7913 if (LdBasePtr.getNode()) {
7914 // The base ptr must be the same.
7915 if (LdPtr.first != LdBasePtr)
7918 // Check that all other base pointers are the same as this one.
7919 LdBasePtr = LdPtr.first;
7922 // We found a potential memory operand to merge.
7923 LoadNodes.push_back(MemOpLink(Ld, LdPtr.second, 0));
7926 if (LoadNodes.size() < 2)
7929 // Scan the memory operations on the chain and find the first non-consecutive
7930 // load memory address. These variables hold the index in the store node
7932 unsigned LastConsecutiveLoad = 0;
7933 // This variable refers to the size and not index in the array.
7934 unsigned LastLegalVectorType = 0;
7935 unsigned LastLegalIntegerType = 0;
7936 StartAddress = LoadNodes[0].OffsetFromBase;
7937 SDValue FirstChain = LoadNodes[0].MemNode->getChain();
7938 for (unsigned i = 1; i < LoadNodes.size(); ++i) {
7939 // All loads much share the same chain.
7940 if (LoadNodes[i].MemNode->getChain() != FirstChain)
7943 int64_t CurrAddress = LoadNodes[i].OffsetFromBase;
7944 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
7946 LastConsecutiveLoad = i;
7948 // Find a legal type for the vector store.
7949 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
7950 if (TLI.isTypeLegal(StoreTy))
7951 LastLegalVectorType = i + 1;
7953 // Find a legal type for the integer store.
7954 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
7955 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
7956 if (TLI.isTypeLegal(StoreTy))
7957 LastLegalIntegerType = i + 1;
7960 // Only use vector types if the vector type is larger than the integer type.
7961 // If they are the same, use integers.
7962 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType;
7963 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType);
7965 // We add +1 here because the LastXXX variables refer to location while
7966 // the NumElem refers to array/index size.
7967 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1;
7968 NumElem = std::min(LastLegalType, NumElem);
7973 // The earliest Node in the DAG.
7974 unsigned EarliestNodeUsed = 0;
7975 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
7976 for (unsigned i=1; i<NumElem; ++i) {
7977 // Find a chain for the new wide-store operand. Notice that some
7978 // of the store nodes that we found may not be selected for inclusion
7979 // in the wide store. The chain we use needs to be the chain of the
7980 // earliest store node which is *used* and replaced by the wide store.
7981 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
7982 EarliestNodeUsed = i;
7985 // Find if it is better to use vectors or integers to load and store
7989 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
7991 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
7992 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
7995 DebugLoc LoadDL = LoadNodes[0].MemNode->getDebugLoc();
7996 DebugLoc StoreDL = StoreNodes[0].MemNode->getDebugLoc();
7998 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode);
7999 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL,
8000 FirstLoad->getChain(),
8001 FirstLoad->getBasePtr(),
8002 FirstLoad->getPointerInfo(),
8003 false, false, false,
8004 FirstLoad->getAlignment());
8006 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad,
8007 FirstInChain->getBasePtr(),
8008 FirstInChain->getPointerInfo(), false, false,
8009 FirstInChain->getAlignment());
8011 // Replace one of the loads with the new load.
8012 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode);
8013 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1),
8014 SDValue(NewLoad.getNode(), 1));
8016 // Remove the rest of the load chains.
8017 for (unsigned i = 1; i < NumElem ; ++i) {
8018 // Replace all chain users of the old load nodes with the chain of the new
8020 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode);
8021 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain());
8024 // Replace the first store with the new store.
8025 CombineTo(EarliestOp, NewStore);
8026 // Erase all other stores.
8027 for (unsigned i = 0; i < NumElem ; ++i) {
8028 // Remove all Store nodes.
8029 if (StoreNodes[i].MemNode == EarliestOp)
8031 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
8032 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain());
8033 removeFromWorkList(St);
8040 SDValue DAGCombiner::visitSTORE(SDNode *N) {
8041 StoreSDNode *ST = cast<StoreSDNode>(N);
8042 SDValue Chain = ST->getChain();
8043 SDValue Value = ST->getValue();
8044 SDValue Ptr = ST->getBasePtr();
8046 // If this is a store of a bit convert, store the input value if the
8047 // resultant store does not need a higher alignment than the original.
8048 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
8049 ST->isUnindexed()) {
8050 unsigned OrigAlign = ST->getAlignment();
8051 EVT SVT = Value.getOperand(0).getValueType();
8052 unsigned Align = TLI.getDataLayout()->
8053 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
8054 if (Align <= OrigAlign &&
8055 ((!LegalOperations && !ST->isVolatile()) ||
8056 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
8057 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
8058 Ptr, ST->getPointerInfo(), ST->isVolatile(),
8059 ST->isNonTemporal(), OrigAlign);
8062 // Turn 'store undef, Ptr' -> nothing.
8063 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
8066 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
8067 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
8068 // NOTE: If the original store is volatile, this transform must not increase
8069 // the number of stores. For example, on x86-32 an f64 can be stored in one
8070 // processor operation but an i64 (which is not legal) requires two. So the
8071 // transform should not be done in this case.
8072 if (Value.getOpcode() != ISD::TargetConstantFP) {
8074 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
8075 default: llvm_unreachable("Unknown FP type");
8076 case MVT::f16: // We don't do this for these yet.
8082 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
8083 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
8084 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
8085 bitcastToAPInt().getZExtValue(), MVT::i32);
8086 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
8087 Ptr, ST->getPointerInfo(), ST->isVolatile(),
8088 ST->isNonTemporal(), ST->getAlignment());
8092 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
8093 !ST->isVolatile()) ||
8094 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
8095 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
8096 getZExtValue(), MVT::i64);
8097 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
8098 Ptr, ST->getPointerInfo(), ST->isVolatile(),
8099 ST->isNonTemporal(), ST->getAlignment());
8102 if (!ST->isVolatile() &&
8103 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
8104 // Many FP stores are not made apparent until after legalize, e.g. for
8105 // argument passing. Since this is so common, custom legalize the
8106 // 64-bit integer store into two 32-bit stores.
8107 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
8108 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
8109 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
8110 if (TLI.isBigEndian()) std::swap(Lo, Hi);
8112 unsigned Alignment = ST->getAlignment();
8113 bool isVolatile = ST->isVolatile();
8114 bool isNonTemporal = ST->isNonTemporal();
8116 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
8117 Ptr, ST->getPointerInfo(),
8118 isVolatile, isNonTemporal,
8119 ST->getAlignment());
8120 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
8121 DAG.getConstant(4, Ptr.getValueType()));
8122 Alignment = MinAlign(Alignment, 4U);
8123 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
8124 Ptr, ST->getPointerInfo().getWithOffset(4),
8125 isVolatile, isNonTemporal,
8127 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
8136 // Try to infer better alignment information than the store already has.
8137 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
8138 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
8139 if (Align > ST->getAlignment())
8140 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
8141 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
8142 ST->isVolatile(), ST->isNonTemporal(), Align);
8146 // Try transforming a pair floating point load / store ops to integer
8147 // load / store ops.
8148 SDValue NewST = TransformFPLoadStorePair(N);
8149 if (NewST.getNode())
8153 // Walk up chain skipping non-aliasing memory nodes.
8154 SDValue BetterChain = FindBetterChain(N, Chain);
8156 // If there is a better chain.
8157 if (Chain != BetterChain) {
8160 // Replace the chain to avoid dependency.
8161 if (ST->isTruncatingStore()) {
8162 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
8163 ST->getPointerInfo(),
8164 ST->getMemoryVT(), ST->isVolatile(),
8165 ST->isNonTemporal(), ST->getAlignment());
8167 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
8168 ST->getPointerInfo(),
8169 ST->isVolatile(), ST->isNonTemporal(),
8170 ST->getAlignment());
8173 // Create token to keep both nodes around.
8174 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
8175 MVT::Other, Chain, ReplStore);
8177 // Make sure the new and old chains are cleaned up.
8178 AddToWorkList(Token.getNode());
8180 // Don't add users to work list.
8181 return CombineTo(N, Token, false);
8185 // Try transforming N to an indexed store.
8186 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
8187 return SDValue(N, 0);
8189 // FIXME: is there such a thing as a truncating indexed store?
8190 if (ST->isTruncatingStore() && ST->isUnindexed() &&
8191 Value.getValueType().isInteger()) {
8192 // See if we can simplify the input to this truncstore with knowledge that
8193 // only the low bits are being used. For example:
8194 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
8196 GetDemandedBits(Value,
8197 APInt::getLowBitsSet(
8198 Value.getValueType().getScalarType().getSizeInBits(),
8199 ST->getMemoryVT().getScalarType().getSizeInBits()));
8200 AddToWorkList(Value.getNode());
8201 if (Shorter.getNode())
8202 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
8203 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
8204 ST->isVolatile(), ST->isNonTemporal(),
8205 ST->getAlignment());
8207 // Otherwise, see if we can simplify the operation with
8208 // SimplifyDemandedBits, which only works if the value has a single use.
8209 if (SimplifyDemandedBits(Value,
8210 APInt::getLowBitsSet(
8211 Value.getValueType().getScalarType().getSizeInBits(),
8212 ST->getMemoryVT().getScalarType().getSizeInBits())))
8213 return SDValue(N, 0);
8216 // If this is a load followed by a store to the same location, then the store
8218 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
8219 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
8220 ST->isUnindexed() && !ST->isVolatile() &&
8221 // There can't be any side effects between the load and store, such as
8223 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
8224 // The store is dead, remove it.
8229 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
8230 // truncating store. We can do this even if this is already a truncstore.
8231 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
8232 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
8233 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
8234 ST->getMemoryVT())) {
8235 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
8236 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
8237 ST->isVolatile(), ST->isNonTemporal(),
8238 ST->getAlignment());
8241 // Only perform this optimization before the types are legal, because we
8242 // don't want to perform this optimization on every DAGCombine invocation.
8244 bool EverChanged = false;
8247 // There can be multiple store sequences on the same chain.
8248 // Keep trying to merge store sequences until we are unable to do so
8249 // or until we merge the last store on the chain.
8250 bool Changed = MergeConsecutiveStores(ST);
8251 EverChanged |= Changed;
8252 if (!Changed) break;
8253 } while (ST->getOpcode() != ISD::DELETED_NODE);
8256 return SDValue(N, 0);
8259 return ReduceLoadOpStoreWidth(N);
8262 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
8263 SDValue InVec = N->getOperand(0);
8264 SDValue InVal = N->getOperand(1);
8265 SDValue EltNo = N->getOperand(2);
8266 DebugLoc dl = N->getDebugLoc();
8268 // If the inserted element is an UNDEF, just use the input vector.
8269 if (InVal.getOpcode() == ISD::UNDEF)
8272 EVT VT = InVec.getValueType();
8274 // If we can't generate a legal BUILD_VECTOR, exit
8275 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
8278 // Check that we know which element is being inserted
8279 if (!isa<ConstantSDNode>(EltNo))
8281 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
8283 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
8284 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
8286 SmallVector<SDValue, 8> Ops;
8287 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
8288 Ops.append(InVec.getNode()->op_begin(),
8289 InVec.getNode()->op_end());
8290 } else if (InVec.getOpcode() == ISD::UNDEF) {
8291 unsigned NElts = VT.getVectorNumElements();
8292 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
8297 // Insert the element
8298 if (Elt < Ops.size()) {
8299 // All the operands of BUILD_VECTOR must have the same type;
8300 // we enforce that here.
8301 EVT OpVT = Ops[0].getValueType();
8302 if (InVal.getValueType() != OpVT)
8303 InVal = OpVT.bitsGT(InVal.getValueType()) ?
8304 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
8305 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
8309 // Return the new vector
8310 return DAG.getNode(ISD::BUILD_VECTOR, dl,
8311 VT, &Ops[0], Ops.size());
8314 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
8315 // (vextract (scalar_to_vector val, 0) -> val
8316 SDValue InVec = N->getOperand(0);
8317 EVT VT = InVec.getValueType();
8318 EVT NVT = N->getValueType(0);
8320 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
8321 // Check if the result type doesn't match the inserted element type. A
8322 // SCALAR_TO_VECTOR may truncate the inserted element and the
8323 // EXTRACT_VECTOR_ELT may widen the extracted vector.
8324 SDValue InOp = InVec.getOperand(0);
8325 if (InOp.getValueType() != NVT) {
8326 assert(InOp.getValueType().isInteger() && NVT.isInteger());
8327 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
8332 SDValue EltNo = N->getOperand(1);
8333 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
8335 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
8336 // We only perform this optimization before the op legalization phase because
8337 // we may introduce new vector instructions which are not backed by TD
8338 // patterns. For example on AVX, extracting elements from a wide vector
8339 // without using extract_subvector.
8340 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
8341 && ConstEltNo && !LegalOperations) {
8342 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
8343 int NumElem = VT.getVectorNumElements();
8344 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
8345 // Find the new index to extract from.
8346 int OrigElt = SVOp->getMaskElt(Elt);
8348 // Extracting an undef index is undef.
8350 return DAG.getUNDEF(NVT);
8352 // Select the right vector half to extract from.
8353 if (OrigElt < NumElem) {
8354 InVec = InVec->getOperand(0);
8356 InVec = InVec->getOperand(1);
8360 EVT IndexTy = N->getOperand(1).getValueType();
8361 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT,
8362 InVec, DAG.getConstant(OrigElt, IndexTy));
8365 // Perform only after legalization to ensure build_vector / vector_shuffle
8366 // optimizations have already been done.
8367 if (!LegalOperations) return SDValue();
8369 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
8370 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
8371 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
8374 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
8375 bool NewLoad = false;
8376 bool BCNumEltsChanged = false;
8377 EVT ExtVT = VT.getVectorElementType();
8380 // If the result of load has to be truncated, then it's not necessarily
8382 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT))
8385 if (InVec.getOpcode() == ISD::BITCAST) {
8386 // Don't duplicate a load with other uses.
8387 if (!InVec.hasOneUse())
8390 EVT BCVT = InVec.getOperand(0).getValueType();
8391 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
8393 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
8394 BCNumEltsChanged = true;
8395 InVec = InVec.getOperand(0);
8396 ExtVT = BCVT.getVectorElementType();
8400 LoadSDNode *LN0 = NULL;
8401 const ShuffleVectorSDNode *SVN = NULL;
8402 if (ISD::isNormalLoad(InVec.getNode())) {
8403 LN0 = cast<LoadSDNode>(InVec);
8404 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
8405 InVec.getOperand(0).getValueType() == ExtVT &&
8406 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
8407 // Don't duplicate a load with other uses.
8408 if (!InVec.hasOneUse())
8411 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
8412 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
8413 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
8415 // (load $addr+1*size)
8417 // Don't duplicate a load with other uses.
8418 if (!InVec.hasOneUse())
8421 // If the bit convert changed the number of elements, it is unsafe
8422 // to examine the mask.
8423 if (BCNumEltsChanged)
8426 // Select the input vector, guarding against out of range extract vector.
8427 unsigned NumElems = VT.getVectorNumElements();
8428 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
8429 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
8431 if (InVec.getOpcode() == ISD::BITCAST) {
8432 // Don't duplicate a load with other uses.
8433 if (!InVec.hasOneUse())
8436 InVec = InVec.getOperand(0);
8438 if (ISD::isNormalLoad(InVec.getNode())) {
8439 LN0 = cast<LoadSDNode>(InVec);
8440 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
8444 // Make sure we found a non-volatile load and the extractelement is
8446 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
8449 // If Idx was -1 above, Elt is going to be -1, so just return undef.
8451 return DAG.getUNDEF(LVT);
8453 unsigned Align = LN0->getAlignment();
8455 // Check the resultant load doesn't need a higher alignment than the
8459 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
8461 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
8467 SDValue NewPtr = LN0->getBasePtr();
8468 unsigned PtrOff = 0;
8471 PtrOff = LVT.getSizeInBits() * Elt / 8;
8472 EVT PtrType = NewPtr.getValueType();
8473 if (TLI.isBigEndian())
8474 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
8475 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
8476 DAG.getConstant(PtrOff, PtrType));
8479 // The replacement we need to do here is a little tricky: we need to
8480 // replace an extractelement of a load with a load.
8481 // Use ReplaceAllUsesOfValuesWith to do the replacement.
8482 // Note that this replacement assumes that the extractvalue is the only
8483 // use of the load; that's okay because we don't want to perform this
8484 // transformation in other cases anyway.
8487 if (NVT.bitsGT(LVT)) {
8488 // If the result type of vextract is wider than the load, then issue an
8489 // extending load instead.
8490 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT)
8491 ? ISD::ZEXTLOAD : ISD::EXTLOAD;
8492 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(),
8493 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff),
8494 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align);
8495 Chain = Load.getValue(1);
8497 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
8498 LN0->getPointerInfo().getWithOffset(PtrOff),
8499 LN0->isVolatile(), LN0->isNonTemporal(),
8500 LN0->isInvariant(), Align);
8501 Chain = Load.getValue(1);
8502 if (NVT.bitsLT(LVT))
8503 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load);
8505 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load);
8507 WorkListRemover DeadNodes(*this);
8508 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) };
8509 SDValue To[] = { Load, Chain };
8510 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
8511 // Since we're explcitly calling ReplaceAllUses, add the new node to the
8512 // worklist explicitly as well.
8513 AddToWorkList(Load.getNode());
8514 AddUsersToWorkList(Load.getNode()); // Add users too
8515 // Make sure to revisit this node to clean it up; it will usually be dead.
8517 return SDValue(N, 0);
8523 // Simplify (build_vec (ext )) to (bitcast (build_vec ))
8524 SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) {
8525 // We perform this optimization post type-legalization because
8526 // the type-legalizer often scalarizes integer-promoted vectors.
8527 // Performing this optimization before may create bit-casts which
8528 // will be type-legalized to complex code sequences.
8529 // We perform this optimization only before the operation legalizer because we
8530 // may introduce illegal operations.
8531 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes)
8534 unsigned NumInScalars = N->getNumOperands();
8535 DebugLoc dl = N->getDebugLoc();
8536 EVT VT = N->getValueType(0);
8538 // Check to see if this is a BUILD_VECTOR of a bunch of values
8539 // which come from any_extend or zero_extend nodes. If so, we can create
8540 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
8541 // optimizations. We do not handle sign-extend because we can't fill the sign
8543 EVT SourceType = MVT::Other;
8544 bool AllAnyExt = true;
8546 for (unsigned i = 0; i != NumInScalars; ++i) {
8547 SDValue In = N->getOperand(i);
8548 // Ignore undef inputs.
8549 if (In.getOpcode() == ISD::UNDEF) continue;
8551 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
8552 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
8554 // Abort if the element is not an extension.
8555 if (!ZeroExt && !AnyExt) {
8556 SourceType = MVT::Other;
8560 // The input is a ZeroExt or AnyExt. Check the original type.
8561 EVT InTy = In.getOperand(0).getValueType();
8563 // Check that all of the widened source types are the same.
8564 if (SourceType == MVT::Other)
8567 else if (InTy != SourceType) {
8568 // Multiple income types. Abort.
8569 SourceType = MVT::Other;
8573 // Check if all of the extends are ANY_EXTENDs.
8574 AllAnyExt &= AnyExt;
8577 // In order to have valid types, all of the inputs must be extended from the
8578 // same source type and all of the inputs must be any or zero extend.
8579 // Scalar sizes must be a power of two.
8580 EVT OutScalarTy = VT.getScalarType();
8581 bool ValidTypes = SourceType != MVT::Other &&
8582 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
8583 isPowerOf2_32(SourceType.getSizeInBits());
8585 // Create a new simpler BUILD_VECTOR sequence which other optimizations can
8586 // turn into a single shuffle instruction.
8590 bool isLE = TLI.isLittleEndian();
8591 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
8592 assert(ElemRatio > 1 && "Invalid element size ratio");
8593 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
8594 DAG.getConstant(0, SourceType);
8596 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements();
8597 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
8599 // Populate the new build_vector
8600 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
8601 SDValue Cast = N->getOperand(i);
8602 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
8603 Cast.getOpcode() == ISD::ZERO_EXTEND ||
8604 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
8606 if (Cast.getOpcode() == ISD::UNDEF)
8607 In = DAG.getUNDEF(SourceType);
8609 In = Cast->getOperand(0);
8610 unsigned Index = isLE ? (i * ElemRatio) :
8611 (i * ElemRatio + (ElemRatio - 1));
8613 assert(Index < Ops.size() && "Invalid index");
8617 // The type of the new BUILD_VECTOR node.
8618 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
8619 assert(VecVT.getSizeInBits() == VT.getSizeInBits() &&
8620 "Invalid vector size");
8621 // Check if the new vector type is legal.
8622 if (!isTypeLegal(VecVT)) return SDValue();
8624 // Make the new BUILD_VECTOR.
8625 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], Ops.size());
8627 // The new BUILD_VECTOR node has the potential to be further optimized.
8628 AddToWorkList(BV.getNode());
8629 // Bitcast to the desired type.
8630 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
8633 SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) {
8634 EVT VT = N->getValueType(0);
8636 unsigned NumInScalars = N->getNumOperands();
8637 DebugLoc dl = N->getDebugLoc();
8639 EVT SrcVT = MVT::Other;
8640 unsigned Opcode = ISD::DELETED_NODE;
8641 unsigned NumDefs = 0;
8643 for (unsigned i = 0; i != NumInScalars; ++i) {
8644 SDValue In = N->getOperand(i);
8645 unsigned Opc = In.getOpcode();
8647 if (Opc == ISD::UNDEF)
8650 // If all scalar values are floats and converted from integers.
8651 if (Opcode == ISD::DELETED_NODE &&
8652 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) {
8659 EVT InVT = In.getOperand(0).getValueType();
8661 // If all scalar values are typed differently, bail out. It's chosen to
8662 // simplify BUILD_VECTOR of integer types.
8663 if (SrcVT == MVT::Other)
8670 // If the vector has just one element defined, it's not worth to fold it into
8671 // a vectorized one.
8675 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP)
8676 && "Should only handle conversion from integer to float.");
8677 assert(SrcVT != MVT::Other && "Cannot determine source type!");
8679 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars);
8681 if (!TLI.isOperationLegalOrCustom(Opcode, NVT))
8684 SmallVector<SDValue, 8> Opnds;
8685 for (unsigned i = 0; i != NumInScalars; ++i) {
8686 SDValue In = N->getOperand(i);
8688 if (In.getOpcode() == ISD::UNDEF)
8689 Opnds.push_back(DAG.getUNDEF(SrcVT));
8691 Opnds.push_back(In.getOperand(0));
8693 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT,
8694 &Opnds[0], Opnds.size());
8695 AddToWorkList(BV.getNode());
8697 return DAG.getNode(Opcode, dl, VT, BV);
8700 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
8701 unsigned NumInScalars = N->getNumOperands();
8702 DebugLoc dl = N->getDebugLoc();
8703 EVT VT = N->getValueType(0);
8705 // A vector built entirely of undefs is undef.
8706 if (ISD::allOperandsUndef(N))
8707 return DAG.getUNDEF(VT);
8709 SDValue V = reduceBuildVecExtToExtBuildVec(N);
8713 V = reduceBuildVecConvertToConvertBuildVec(N);
8717 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
8718 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
8719 // at most two distinct vectors, turn this into a shuffle node.
8721 // May only combine to shuffle after legalize if shuffle is legal.
8722 if (LegalOperations &&
8723 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))
8726 SDValue VecIn1, VecIn2;
8727 for (unsigned i = 0; i != NumInScalars; ++i) {
8728 // Ignore undef inputs.
8729 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
8731 // If this input is something other than a EXTRACT_VECTOR_ELT with a
8732 // constant index, bail out.
8733 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
8734 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
8735 VecIn1 = VecIn2 = SDValue(0, 0);
8739 // We allow up to two distinct input vectors.
8740 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
8741 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
8744 if (VecIn1.getNode() == 0) {
8745 VecIn1 = ExtractedFromVec;
8746 } else if (VecIn2.getNode() == 0) {
8747 VecIn2 = ExtractedFromVec;
8750 VecIn1 = VecIn2 = SDValue(0, 0);
8755 // If everything is good, we can make a shuffle operation.
8756 if (VecIn1.getNode()) {
8757 SmallVector<int, 8> Mask;
8758 for (unsigned i = 0; i != NumInScalars; ++i) {
8759 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
8764 // If extracting from the first vector, just use the index directly.
8765 SDValue Extract = N->getOperand(i);
8766 SDValue ExtVal = Extract.getOperand(1);
8767 if (Extract.getOperand(0) == VecIn1) {
8768 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
8769 if (ExtIndex > VT.getVectorNumElements())
8772 Mask.push_back(ExtIndex);
8776 // Otherwise, use InIdx + VecSize
8777 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
8778 Mask.push_back(Idx+NumInScalars);
8781 // We can't generate a shuffle node with mismatched input and output types.
8782 // Attempt to transform a single input vector to the correct type.
8783 if ((VT != VecIn1.getValueType())) {
8784 // We don't support shuffeling between TWO values of different types.
8785 if (VecIn2.getNode() != 0)
8788 // We only support widening of vectors which are half the size of the
8789 // output registers. For example XMM->YMM widening on X86 with AVX.
8790 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits())
8793 // If the input vector type has a different base type to the output
8794 // vector type, bail out.
8795 if (VecIn1.getValueType().getVectorElementType() !=
8796 VT.getVectorElementType())
8799 // Widen the input vector by adding undef values.
8800 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8801 VecIn1, DAG.getUNDEF(VecIn1.getValueType()));
8804 // If VecIn2 is unused then change it to undef.
8805 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
8807 // Check that we were able to transform all incoming values to the same
8809 if (VecIn2.getValueType() != VecIn1.getValueType() ||
8810 VecIn1.getValueType() != VT)
8813 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
8814 if (!isTypeLegal(VT))
8817 // Return the new VECTOR_SHUFFLE node.
8821 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]);
8827 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
8828 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
8829 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
8830 // inputs come from at most two distinct vectors, turn this into a shuffle
8833 // If we only have one input vector, we don't need to do any concatenation.
8834 if (N->getNumOperands() == 1)
8835 return N->getOperand(0);
8837 // Check if all of the operands are undefs.
8838 if (ISD::allOperandsUndef(N))
8839 return DAG.getUNDEF(N->getValueType(0));
8844 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
8845 EVT NVT = N->getValueType(0);
8846 SDValue V = N->getOperand(0);
8848 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
8849 // Handle only simple case where vector being inserted and vector
8850 // being extracted are of same type, and are half size of larger vectors.
8851 EVT BigVT = V->getOperand(0).getValueType();
8852 EVT SmallVT = V->getOperand(1).getValueType();
8853 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
8856 // Only handle cases where both indexes are constants with the same type.
8857 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
8858 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
8860 if (InsIdx && ExtIdx &&
8861 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
8862 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
8864 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
8866 // indices are equal => V1
8867 // otherwise => (extract_subvec V1, ExtIdx)
8868 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue())
8869 return V->getOperand(1);
8870 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT,
8871 V->getOperand(0), N->getOperand(1));
8875 if (V->getOpcode() == ISD::CONCAT_VECTORS) {
8877 // (extract_subvec (concat V1, V2, ...), i)
8880 // Only operand 0 is checked as 'concat' assumes all inputs of the same type.
8881 if (V->getOperand(0).getValueType() != NVT)
8883 unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8884 unsigned NumElems = NVT.getVectorNumElements();
8885 assert((Idx % NumElems) == 0 &&
8886 "IDX in concat is not a multiple of the result vector length.");
8887 return V->getOperand(Idx / NumElems);
8893 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
8894 EVT VT = N->getValueType(0);
8895 unsigned NumElts = VT.getVectorNumElements();
8897 SDValue N0 = N->getOperand(0);
8898 SDValue N1 = N->getOperand(1);
8900 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
8902 // Canonicalize shuffle undef, undef -> undef
8903 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
8904 return DAG.getUNDEF(VT);
8906 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8908 // Canonicalize shuffle v, v -> v, undef
8910 SmallVector<int, 8> NewMask;
8911 for (unsigned i = 0; i != NumElts; ++i) {
8912 int Idx = SVN->getMaskElt(i);
8913 if (Idx >= (int)NumElts) Idx -= NumElts;
8914 NewMask.push_back(Idx);
8916 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT),
8920 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
8921 if (N0.getOpcode() == ISD::UNDEF) {
8922 SmallVector<int, 8> NewMask;
8923 for (unsigned i = 0; i != NumElts; ++i) {
8924 int Idx = SVN->getMaskElt(i);
8926 if (Idx < (int)NumElts)
8931 NewMask.push_back(Idx);
8933 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT),
8937 // Remove references to rhs if it is undef
8938 if (N1.getOpcode() == ISD::UNDEF) {
8939 bool Changed = false;
8940 SmallVector<int, 8> NewMask;
8941 for (unsigned i = 0; i != NumElts; ++i) {
8942 int Idx = SVN->getMaskElt(i);
8943 if (Idx >= (int)NumElts) {
8947 NewMask.push_back(Idx);
8950 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]);
8953 // If it is a splat, check if the argument vector is another splat or a
8954 // build_vector with all scalar elements the same.
8955 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
8956 SDNode *V = N0.getNode();
8958 // If this is a bit convert that changes the element type of the vector but
8959 // not the number of vector elements, look through it. Be careful not to
8960 // look though conversions that change things like v4f32 to v2f64.
8961 if (V->getOpcode() == ISD::BITCAST) {
8962 SDValue ConvInput = V->getOperand(0);
8963 if (ConvInput.getValueType().isVector() &&
8964 ConvInput.getValueType().getVectorNumElements() == NumElts)
8965 V = ConvInput.getNode();
8968 if (V->getOpcode() == ISD::BUILD_VECTOR) {
8969 assert(V->getNumOperands() == NumElts &&
8970 "BUILD_VECTOR has wrong number of operands");
8972 bool AllSame = true;
8973 for (unsigned i = 0; i != NumElts; ++i) {
8974 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
8975 Base = V->getOperand(i);
8979 // Splat of <u, u, u, u>, return <u, u, u, u>
8980 if (!Base.getNode())
8982 for (unsigned i = 0; i != NumElts; ++i) {
8983 if (V->getOperand(i) != Base) {
8988 // Splat of <x, x, x, x>, return <x, x, x, x>
8994 // If this shuffle node is simply a swizzle of another shuffle node,
8995 // and it reverses the swizzle of the previous shuffle then we can
8996 // optimize shuffle(shuffle(x, undef), undef) -> x.
8997 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
8998 N1.getOpcode() == ISD::UNDEF) {
9000 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
9002 // Shuffle nodes can only reverse shuffles with a single non-undef value.
9003 if (N0.getOperand(1).getOpcode() != ISD::UNDEF)
9006 // The incoming shuffle must be of the same type as the result of the
9008 assert(OtherSV->getOperand(0).getValueType() == VT &&
9009 "Shuffle types don't match");
9011 for (unsigned i = 0; i != NumElts; ++i) {
9012 int Idx = SVN->getMaskElt(i);
9013 assert(Idx < (int)NumElts && "Index references undef operand");
9014 // Next, this index comes from the first value, which is the incoming
9015 // shuffle. Adopt the incoming index.
9017 Idx = OtherSV->getMaskElt(Idx);
9019 // The combined shuffle must map each index to itself.
9020 if (Idx >= 0 && (unsigned)Idx != i)
9024 return OtherSV->getOperand(0);
9030 SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
9031 if (!TLI.getShouldFoldAtomicFences())
9034 SDValue atomic = N->getOperand(0);
9035 switch (atomic.getOpcode()) {
9036 case ISD::ATOMIC_CMP_SWAP:
9037 case ISD::ATOMIC_SWAP:
9038 case ISD::ATOMIC_LOAD_ADD:
9039 case ISD::ATOMIC_LOAD_SUB:
9040 case ISD::ATOMIC_LOAD_AND:
9041 case ISD::ATOMIC_LOAD_OR:
9042 case ISD::ATOMIC_LOAD_XOR:
9043 case ISD::ATOMIC_LOAD_NAND:
9044 case ISD::ATOMIC_LOAD_MIN:
9045 case ISD::ATOMIC_LOAD_MAX:
9046 case ISD::ATOMIC_LOAD_UMIN:
9047 case ISD::ATOMIC_LOAD_UMAX:
9053 SDValue fence = atomic.getOperand(0);
9054 if (fence.getOpcode() != ISD::MEMBARRIER)
9057 switch (atomic.getOpcode()) {
9058 case ISD::ATOMIC_CMP_SWAP:
9059 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
9060 fence.getOperand(0),
9061 atomic.getOperand(1), atomic.getOperand(2),
9062 atomic.getOperand(3)), atomic.getResNo());
9063 case ISD::ATOMIC_SWAP:
9064 case ISD::ATOMIC_LOAD_ADD:
9065 case ISD::ATOMIC_LOAD_SUB:
9066 case ISD::ATOMIC_LOAD_AND:
9067 case ISD::ATOMIC_LOAD_OR:
9068 case ISD::ATOMIC_LOAD_XOR:
9069 case ISD::ATOMIC_LOAD_NAND:
9070 case ISD::ATOMIC_LOAD_MIN:
9071 case ISD::ATOMIC_LOAD_MAX:
9072 case ISD::ATOMIC_LOAD_UMIN:
9073 case ISD::ATOMIC_LOAD_UMAX:
9074 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
9075 fence.getOperand(0),
9076 atomic.getOperand(1), atomic.getOperand(2)),
9083 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
9084 /// an AND to a vector_shuffle with the destination vector and a zero vector.
9085 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
9086 /// vector_shuffle V, Zero, <0, 4, 2, 4>
9087 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
9088 EVT VT = N->getValueType(0);
9089 DebugLoc dl = N->getDebugLoc();
9090 SDValue LHS = N->getOperand(0);
9091 SDValue RHS = N->getOperand(1);
9092 if (N->getOpcode() == ISD::AND) {
9093 if (RHS.getOpcode() == ISD::BITCAST)
9094 RHS = RHS.getOperand(0);
9095 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
9096 SmallVector<int, 8> Indices;
9097 unsigned NumElts = RHS.getNumOperands();
9098 for (unsigned i = 0; i != NumElts; ++i) {
9099 SDValue Elt = RHS.getOperand(i);
9100 if (!isa<ConstantSDNode>(Elt))
9103 if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
9104 Indices.push_back(i);
9105 else if (cast<ConstantSDNode>(Elt)->isNullValue())
9106 Indices.push_back(NumElts);
9111 // Let's see if the target supports this vector_shuffle.
9112 EVT RVT = RHS.getValueType();
9113 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
9116 // Return the new VECTOR_SHUFFLE node.
9117 EVT EltVT = RVT.getVectorElementType();
9118 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
9119 DAG.getConstant(0, EltVT));
9120 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
9121 RVT, &ZeroOps[0], ZeroOps.size());
9122 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
9123 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
9124 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
9131 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
9132 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
9133 // After legalize, the target may be depending on adds and other
9134 // binary ops to provide legal ways to construct constants or other
9135 // things. Simplifying them may result in a loss of legality.
9136 if (LegalOperations) return SDValue();
9138 assert(N->getValueType(0).isVector() &&
9139 "SimplifyVBinOp only works on vectors!");
9141 SDValue LHS = N->getOperand(0);
9142 SDValue RHS = N->getOperand(1);
9143 SDValue Shuffle = XformToShuffleWithZero(N);
9144 if (Shuffle.getNode()) return Shuffle;
9146 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
9148 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
9149 RHS.getOpcode() == ISD::BUILD_VECTOR) {
9150 SmallVector<SDValue, 8> Ops;
9151 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
9152 SDValue LHSOp = LHS.getOperand(i);
9153 SDValue RHSOp = RHS.getOperand(i);
9154 // If these two elements can't be folded, bail out.
9155 if ((LHSOp.getOpcode() != ISD::UNDEF &&
9156 LHSOp.getOpcode() != ISD::Constant &&
9157 LHSOp.getOpcode() != ISD::ConstantFP) ||
9158 (RHSOp.getOpcode() != ISD::UNDEF &&
9159 RHSOp.getOpcode() != ISD::Constant &&
9160 RHSOp.getOpcode() != ISD::ConstantFP))
9163 // Can't fold divide by zero.
9164 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
9165 N->getOpcode() == ISD::FDIV) {
9166 if ((RHSOp.getOpcode() == ISD::Constant &&
9167 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
9168 (RHSOp.getOpcode() == ISD::ConstantFP &&
9169 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
9173 EVT VT = LHSOp.getValueType();
9174 EVT RVT = RHSOp.getValueType();
9176 // Integer BUILD_VECTOR operands may have types larger than the element
9177 // size (e.g., when the element type is not legal). Prior to type
9178 // legalization, the types may not match between the two BUILD_VECTORS.
9179 // Truncate one of the operands to make them match.
9180 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
9181 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp);
9183 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp);
9187 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT,
9189 if (FoldOp.getOpcode() != ISD::UNDEF &&
9190 FoldOp.getOpcode() != ISD::Constant &&
9191 FoldOp.getOpcode() != ISD::ConstantFP)
9193 Ops.push_back(FoldOp);
9194 AddToWorkList(FoldOp.getNode());
9197 if (Ops.size() == LHS.getNumOperands())
9198 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
9199 LHS.getValueType(), &Ops[0], Ops.size());
9205 /// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG.
9206 SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) {
9207 // After legalize, the target may be depending on adds and other
9208 // binary ops to provide legal ways to construct constants or other
9209 // things. Simplifying them may result in a loss of legality.
9210 if (LegalOperations) return SDValue();
9212 assert(N->getValueType(0).isVector() &&
9213 "SimplifyVUnaryOp only works on vectors!");
9215 SDValue N0 = N->getOperand(0);
9217 if (N0.getOpcode() != ISD::BUILD_VECTOR)
9220 // Operand is a BUILD_VECTOR node, see if we can constant fold it.
9221 SmallVector<SDValue, 8> Ops;
9222 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
9223 SDValue Op = N0.getOperand(i);
9224 if (Op.getOpcode() != ISD::UNDEF &&
9225 Op.getOpcode() != ISD::ConstantFP)
9227 EVT EltVT = Op.getValueType();
9228 SDValue FoldOp = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), EltVT, Op);
9229 if (FoldOp.getOpcode() != ISD::UNDEF &&
9230 FoldOp.getOpcode() != ISD::ConstantFP)
9232 Ops.push_back(FoldOp);
9233 AddToWorkList(FoldOp.getNode());
9236 if (Ops.size() != N0.getNumOperands())
9239 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
9240 N0.getValueType(), &Ops[0], Ops.size());
9243 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
9244 SDValue N1, SDValue N2){
9245 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
9247 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
9248 cast<CondCodeSDNode>(N0.getOperand(2))->get());
9250 // If we got a simplified select_cc node back from SimplifySelectCC, then
9251 // break it down into a new SETCC node, and a new SELECT node, and then return
9252 // the SELECT node, since we were called with a SELECT node.
9253 if (SCC.getNode()) {
9254 // Check to see if we got a select_cc back (to turn into setcc/select).
9255 // Otherwise, just return whatever node we got back, like fabs.
9256 if (SCC.getOpcode() == ISD::SELECT_CC) {
9257 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
9259 SCC.getOperand(0), SCC.getOperand(1),
9261 AddToWorkList(SETCC.getNode());
9262 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
9263 SCC.getOperand(2), SCC.getOperand(3), SETCC);
9271 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
9272 /// are the two values being selected between, see if we can simplify the
9273 /// select. Callers of this should assume that TheSelect is deleted if this
9274 /// returns true. As such, they should return the appropriate thing (e.g. the
9275 /// node) back to the top-level of the DAG combiner loop to avoid it being
9277 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
9280 // Cannot simplify select with vector condition
9281 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
9283 // If this is a select from two identical things, try to pull the operation
9284 // through the select.
9285 if (LHS.getOpcode() != RHS.getOpcode() ||
9286 !LHS.hasOneUse() || !RHS.hasOneUse())
9289 // If this is a load and the token chain is identical, replace the select
9290 // of two loads with a load through a select of the address to load from.
9291 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
9292 // constants have been dropped into the constant pool.
9293 if (LHS.getOpcode() == ISD::LOAD) {
9294 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
9295 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
9297 // Token chains must be identical.
9298 if (LHS.getOperand(0) != RHS.getOperand(0) ||
9299 // Do not let this transformation reduce the number of volatile loads.
9300 LLD->isVolatile() || RLD->isVolatile() ||
9301 // If this is an EXTLOAD, the VT's must match.
9302 LLD->getMemoryVT() != RLD->getMemoryVT() ||
9303 // If this is an EXTLOAD, the kind of extension must match.
9304 (LLD->getExtensionType() != RLD->getExtensionType() &&
9305 // The only exception is if one of the extensions is anyext.
9306 LLD->getExtensionType() != ISD::EXTLOAD &&
9307 RLD->getExtensionType() != ISD::EXTLOAD) ||
9308 // FIXME: this discards src value information. This is
9309 // over-conservative. It would be beneficial to be able to remember
9310 // both potential memory locations. Since we are discarding
9311 // src value info, don't do the transformation if the memory
9312 // locations are not in the default address space.
9313 LLD->getPointerInfo().getAddrSpace() != 0 ||
9314 RLD->getPointerInfo().getAddrSpace() != 0)
9317 // Check that the select condition doesn't reach either load. If so,
9318 // folding this will induce a cycle into the DAG. If not, this is safe to
9319 // xform, so create a select of the addresses.
9321 if (TheSelect->getOpcode() == ISD::SELECT) {
9322 SDNode *CondNode = TheSelect->getOperand(0).getNode();
9323 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
9324 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
9326 // The loads must not depend on one another.
9327 if (LLD->isPredecessorOf(RLD) ||
9328 RLD->isPredecessorOf(LLD))
9330 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
9331 LLD->getBasePtr().getValueType(),
9332 TheSelect->getOperand(0), LLD->getBasePtr(),
9334 } else { // Otherwise SELECT_CC
9335 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
9336 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
9338 if ((LLD->hasAnyUseOfValue(1) &&
9339 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
9340 (RLD->hasAnyUseOfValue(1) &&
9341 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS))))
9344 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
9345 LLD->getBasePtr().getValueType(),
9346 TheSelect->getOperand(0),
9347 TheSelect->getOperand(1),
9348 LLD->getBasePtr(), RLD->getBasePtr(),
9349 TheSelect->getOperand(4));
9353 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
9354 Load = DAG.getLoad(TheSelect->getValueType(0),
9355 TheSelect->getDebugLoc(),
9356 // FIXME: Discards pointer info.
9357 LLD->getChain(), Addr, MachinePointerInfo(),
9358 LLD->isVolatile(), LLD->isNonTemporal(),
9359 LLD->isInvariant(), LLD->getAlignment());
9361 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
9362 RLD->getExtensionType() : LLD->getExtensionType(),
9363 TheSelect->getDebugLoc(),
9364 TheSelect->getValueType(0),
9365 // FIXME: Discards pointer info.
9366 LLD->getChain(), Addr, MachinePointerInfo(),
9367 LLD->getMemoryVT(), LLD->isVolatile(),
9368 LLD->isNonTemporal(), LLD->getAlignment());
9371 // Users of the select now use the result of the load.
9372 CombineTo(TheSelect, Load);
9374 // Users of the old loads now use the new load's chain. We know the
9375 // old-load value is dead now.
9376 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
9377 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
9384 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
9385 /// where 'cond' is the comparison specified by CC.
9386 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
9387 SDValue N2, SDValue N3,
9388 ISD::CondCode CC, bool NotExtCompare) {
9389 // (x ? y : y) -> y.
9390 if (N2 == N3) return N2;
9392 EVT VT = N2.getValueType();
9393 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
9394 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
9395 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
9397 // Determine if the condition we're dealing with is constant
9398 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
9399 N0, N1, CC, DL, false);
9400 if (SCC.getNode()) AddToWorkList(SCC.getNode());
9401 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
9403 // fold select_cc true, x, y -> x
9404 if (SCCC && !SCCC->isNullValue())
9406 // fold select_cc false, x, y -> y
9407 if (SCCC && SCCC->isNullValue())
9410 // Check to see if we can simplify the select into an fabs node
9411 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
9412 // Allow either -0.0 or 0.0
9413 if (CFP->getValueAPF().isZero()) {
9414 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
9415 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
9416 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
9417 N2 == N3.getOperand(0))
9418 return DAG.getNode(ISD::FABS, DL, VT, N0);
9420 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
9421 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
9422 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
9423 N2.getOperand(0) == N3)
9424 return DAG.getNode(ISD::FABS, DL, VT, N3);
9428 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
9429 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
9430 // in it. This is a win when the constant is not otherwise available because
9431 // it replaces two constant pool loads with one. We only do this if the FP
9432 // type is known to be legal, because if it isn't, then we are before legalize
9433 // types an we want the other legalization to happen first (e.g. to avoid
9434 // messing with soft float) and if the ConstantFP is not legal, because if
9435 // it is legal, we may not need to store the FP constant in a constant pool.
9436 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
9437 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
9438 if (TLI.isTypeLegal(N2.getValueType()) &&
9439 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
9440 TargetLowering::Legal) &&
9441 // If both constants have multiple uses, then we won't need to do an
9442 // extra load, they are likely around in registers for other users.
9443 (TV->hasOneUse() || FV->hasOneUse())) {
9444 Constant *Elts[] = {
9445 const_cast<ConstantFP*>(FV->getConstantFPValue()),
9446 const_cast<ConstantFP*>(TV->getConstantFPValue())
9448 Type *FPTy = Elts[0]->getType();
9449 const DataLayout &TD = *TLI.getDataLayout();
9451 // Create a ConstantArray of the two constants.
9452 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
9453 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
9454 TD.getPrefTypeAlignment(FPTy));
9455 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9457 // Get the offsets to the 0 and 1 element of the array so that we can
9458 // select between them.
9459 SDValue Zero = DAG.getIntPtrConstant(0);
9460 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
9461 SDValue One = DAG.getIntPtrConstant(EltSize);
9463 SDValue Cond = DAG.getSetCC(DL,
9464 TLI.getSetCCResultType(N0.getValueType()),
9466 AddToWorkList(Cond.getNode());
9467 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
9469 AddToWorkList(CstOffset.getNode());
9470 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
9472 AddToWorkList(CPIdx.getNode());
9473 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
9474 MachinePointerInfo::getConstantPool(), false,
9475 false, false, Alignment);
9480 // Check to see if we can perform the "gzip trick", transforming
9481 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
9482 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
9483 (N1C->isNullValue() || // (a < 0) ? b : 0
9484 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
9485 EVT XType = N0.getValueType();
9486 EVT AType = N2.getValueType();
9487 if (XType.bitsGE(AType)) {
9488 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
9489 // single-bit constant.
9490 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
9491 unsigned ShCtV = N2C->getAPIntValue().logBase2();
9492 ShCtV = XType.getSizeInBits()-ShCtV-1;
9493 SDValue ShCt = DAG.getConstant(ShCtV,
9494 getShiftAmountTy(N0.getValueType()));
9495 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
9497 AddToWorkList(Shift.getNode());
9499 if (XType.bitsGT(AType)) {
9500 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
9501 AddToWorkList(Shift.getNode());
9504 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
9507 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
9509 DAG.getConstant(XType.getSizeInBits()-1,
9510 getShiftAmountTy(N0.getValueType())));
9511 AddToWorkList(Shift.getNode());
9513 if (XType.bitsGT(AType)) {
9514 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
9515 AddToWorkList(Shift.getNode());
9518 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
9522 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
9523 // where y is has a single bit set.
9524 // A plaintext description would be, we can turn the SELECT_CC into an AND
9525 // when the condition can be materialized as an all-ones register. Any
9526 // single bit-test can be materialized as an all-ones register with
9527 // shift-left and shift-right-arith.
9528 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
9529 N0->getValueType(0) == VT &&
9530 N1C && N1C->isNullValue() &&
9531 N2C && N2C->isNullValue()) {
9532 SDValue AndLHS = N0->getOperand(0);
9533 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
9534 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
9535 // Shift the tested bit over the sign bit.
9536 APInt AndMask = ConstAndRHS->getAPIntValue();
9538 DAG.getConstant(AndMask.countLeadingZeros(),
9539 getShiftAmountTy(AndLHS.getValueType()));
9540 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
9542 // Now arithmetic right shift it all the way over, so the result is either
9543 // all-ones, or zero.
9545 DAG.getConstant(AndMask.getBitWidth()-1,
9546 getShiftAmountTy(Shl.getValueType()));
9547 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
9549 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
9553 // fold select C, 16, 0 -> shl C, 4
9554 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
9555 TLI.getBooleanContents(N0.getValueType().isVector()) ==
9556 TargetLowering::ZeroOrOneBooleanContent) {
9558 // If the caller doesn't want us to simplify this into a zext of a compare,
9560 if (NotExtCompare && N2C->getAPIntValue() == 1)
9563 // Get a SetCC of the condition
9564 // NOTE: Don't create a SETCC if it's not legal on this target.
9565 if (!LegalOperations ||
9566 TLI.isOperationLegal(ISD::SETCC,
9567 LegalTypes ? TLI.getSetCCResultType(N0.getValueType()) : MVT::i1)) {
9569 // cast from setcc result type to select result type
9571 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
9573 if (N2.getValueType().bitsLT(SCC.getValueType()))
9574 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(),
9577 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
9578 N2.getValueType(), SCC);
9580 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
9581 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
9582 N2.getValueType(), SCC);
9585 AddToWorkList(SCC.getNode());
9586 AddToWorkList(Temp.getNode());
9588 if (N2C->getAPIntValue() == 1)
9591 // shl setcc result by log2 n2c
9592 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
9593 DAG.getConstant(N2C->getAPIntValue().logBase2(),
9594 getShiftAmountTy(Temp.getValueType())));
9598 // Check to see if this is the equivalent of setcc
9599 // FIXME: Turn all of these into setcc if setcc if setcc is legal
9600 // otherwise, go ahead with the folds.
9601 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
9602 EVT XType = N0.getValueType();
9603 if (!LegalOperations ||
9604 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
9605 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
9606 if (Res.getValueType() != VT)
9607 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
9611 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
9612 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
9613 (!LegalOperations ||
9614 TLI.isOperationLegal(ISD::CTLZ, XType))) {
9615 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
9616 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
9617 DAG.getConstant(Log2_32(XType.getSizeInBits()),
9618 getShiftAmountTy(Ctlz.getValueType())));
9620 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
9621 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
9622 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
9623 XType, DAG.getConstant(0, XType), N0);
9624 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
9625 return DAG.getNode(ISD::SRL, DL, XType,
9626 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
9627 DAG.getConstant(XType.getSizeInBits()-1,
9628 getShiftAmountTy(XType)));
9630 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
9631 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
9632 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
9633 DAG.getConstant(XType.getSizeInBits()-1,
9634 getShiftAmountTy(N0.getValueType())));
9635 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
9639 // Check to see if this is an integer abs.
9640 // select_cc setg[te] X, 0, X, -X ->
9641 // select_cc setgt X, -1, X, -X ->
9642 // select_cc setl[te] X, 0, -X, X ->
9643 // select_cc setlt X, 1, -X, X ->
9644 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
9646 ConstantSDNode *SubC = NULL;
9647 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
9648 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
9649 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
9650 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
9651 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
9652 (N1C->isOne() && CC == ISD::SETLT)) &&
9653 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
9654 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
9656 EVT XType = N0.getValueType();
9657 if (SubC && SubC->isNullValue() && XType.isInteger()) {
9658 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
9660 DAG.getConstant(XType.getSizeInBits()-1,
9661 getShiftAmountTy(N0.getValueType())));
9662 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
9664 AddToWorkList(Shift.getNode());
9665 AddToWorkList(Add.getNode());
9666 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
9673 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
9674 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
9675 SDValue N1, ISD::CondCode Cond,
9676 DebugLoc DL, bool foldBooleans) {
9677 TargetLowering::DAGCombinerInfo
9678 DagCombineInfo(DAG, Level, false, this);
9679 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
9682 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
9683 /// return a DAG expression to select that will generate the same value by
9684 /// multiplying by a magic number. See:
9685 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
9686 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
9687 std::vector<SDNode*> Built;
9688 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built);
9690 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
9696 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
9697 /// return a DAG expression to select that will generate the same value by
9698 /// multiplying by a magic number. See:
9699 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
9700 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
9701 std::vector<SDNode*> Built;
9702 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built);
9704 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
9710 /// FindBaseOffset - Return true if base is a frame index, which is known not
9711 // to alias with anything but itself. Provides base object and offset as
9713 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
9714 const GlobalValue *&GV, const void *&CV) {
9715 // Assume it is a primitive operation.
9716 Base = Ptr; Offset = 0; GV = 0; CV = 0;
9718 // If it's an adding a simple constant then integrate the offset.
9719 if (Base.getOpcode() == ISD::ADD) {
9720 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
9721 Base = Base.getOperand(0);
9722 Offset += C->getZExtValue();
9726 // Return the underlying GlobalValue, and update the Offset. Return false
9727 // for GlobalAddressSDNode since the same GlobalAddress may be represented
9728 // by multiple nodes with different offsets.
9729 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
9730 GV = G->getGlobal();
9731 Offset += G->getOffset();
9735 // Return the underlying Constant value, and update the Offset. Return false
9736 // for ConstantSDNodes since the same constant pool entry may be represented
9737 // by multiple nodes with different offsets.
9738 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
9739 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal()
9740 : (const void *)C->getConstVal();
9741 Offset += C->getOffset();
9744 // If it's any of the following then it can't alias with anything but itself.
9745 return isa<FrameIndexSDNode>(Base);
9748 /// isAlias - Return true if there is any possibility that the two addresses
9750 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
9751 const Value *SrcValue1, int SrcValueOffset1,
9752 unsigned SrcValueAlign1,
9753 const MDNode *TBAAInfo1,
9754 SDValue Ptr2, int64_t Size2,
9755 const Value *SrcValue2, int SrcValueOffset2,
9756 unsigned SrcValueAlign2,
9757 const MDNode *TBAAInfo2) const {
9758 // If they are the same then they must be aliases.
9759 if (Ptr1 == Ptr2) return true;
9761 // Gather base node and offset information.
9762 SDValue Base1, Base2;
9763 int64_t Offset1, Offset2;
9764 const GlobalValue *GV1, *GV2;
9765 const void *CV1, *CV2;
9766 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
9767 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
9769 // If they have a same base address then check to see if they overlap.
9770 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
9771 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
9773 // It is possible for different frame indices to alias each other, mostly
9774 // when tail call optimization reuses return address slots for arguments.
9775 // To catch this case, look up the actual index of frame indices to compute
9776 // the real alias relationship.
9777 if (isFrameIndex1 && isFrameIndex2) {
9778 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9779 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
9780 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
9781 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
9784 // Otherwise, if we know what the bases are, and they aren't identical, then
9785 // we know they cannot alias.
9786 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
9789 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
9790 // compared to the size and offset of the access, we may be able to prove they
9791 // do not alias. This check is conservative for now to catch cases created by
9792 // splitting vector types.
9793 if ((SrcValueAlign1 == SrcValueAlign2) &&
9794 (SrcValueOffset1 != SrcValueOffset2) &&
9795 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
9796 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
9797 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
9799 // There is no overlap between these relatively aligned accesses of similar
9800 // size, return no alias.
9801 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
9805 if (CombinerGlobalAA) {
9806 // Use alias analysis information.
9807 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
9808 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
9809 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
9810 AliasAnalysis::AliasResult AAResult =
9811 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
9812 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
9813 if (AAResult == AliasAnalysis::NoAlias)
9817 // Otherwise we have to assume they alias.
9821 bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) {
9823 int64_t Size0, Size1;
9824 const Value *SrcValue0, *SrcValue1;
9825 int SrcValueOffset0, SrcValueOffset1;
9826 unsigned SrcValueAlign0, SrcValueAlign1;
9827 const MDNode *SrcTBAAInfo0, *SrcTBAAInfo1;
9828 FindAliasInfo(Op0, Ptr0, Size0, SrcValue0, SrcValueOffset0,
9829 SrcValueAlign0, SrcTBAAInfo0);
9830 FindAliasInfo(Op1, Ptr1, Size1, SrcValue1, SrcValueOffset1,
9831 SrcValueAlign1, SrcTBAAInfo1);
9832 return isAlias(Ptr0, Size0, SrcValue0, SrcValueOffset0,
9833 SrcValueAlign0, SrcTBAAInfo0,
9834 Ptr1, Size1, SrcValue1, SrcValueOffset1,
9835 SrcValueAlign1, SrcTBAAInfo1);
9838 /// FindAliasInfo - Extracts the relevant alias information from the memory
9839 /// node. Returns true if the operand was a load.
9840 bool DAGCombiner::FindAliasInfo(SDNode *N,
9841 SDValue &Ptr, int64_t &Size,
9842 const Value *&SrcValue,
9843 int &SrcValueOffset,
9844 unsigned &SrcValueAlign,
9845 const MDNode *&TBAAInfo) const {
9846 LSBaseSDNode *LS = cast<LSBaseSDNode>(N);
9848 Ptr = LS->getBasePtr();
9849 Size = LS->getMemoryVT().getSizeInBits() >> 3;
9850 SrcValue = LS->getSrcValue();
9851 SrcValueOffset = LS->getSrcValueOffset();
9852 SrcValueAlign = LS->getOriginalAlignment();
9853 TBAAInfo = LS->getTBAAInfo();
9854 return isa<LoadSDNode>(LS);
9857 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
9858 /// looking for aliasing nodes and adding them to the Aliases vector.
9859 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
9860 SmallVector<SDValue, 8> &Aliases) {
9861 SmallVector<SDValue, 8> Chains; // List of chains to visit.
9862 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
9864 // Get alias information for node.
9867 const Value *SrcValue;
9869 unsigned SrcValueAlign;
9870 const MDNode *SrcTBAAInfo;
9871 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
9872 SrcValueAlign, SrcTBAAInfo);
9875 Chains.push_back(OriginalChain);
9878 // Look at each chain and determine if it is an alias. If so, add it to the
9879 // aliases list. If not, then continue up the chain looking for the next
9881 while (!Chains.empty()) {
9882 SDValue Chain = Chains.back();
9885 // For TokenFactor nodes, look at each operand and only continue up the
9886 // chain until we find two aliases. If we've seen two aliases, assume we'll
9887 // find more and revert to original chain since the xform is unlikely to be
9890 // FIXME: The depth check could be made to return the last non-aliasing
9891 // chain we found before we hit a tokenfactor rather than the original
9893 if (Depth > 6 || Aliases.size() == 2) {
9895 Aliases.push_back(OriginalChain);
9899 // Don't bother if we've been before.
9900 if (!Visited.insert(Chain.getNode()))
9903 switch (Chain.getOpcode()) {
9904 case ISD::EntryToken:
9905 // Entry token is ideal chain operand, but handled in FindBetterChain.
9910 // Get alias information for Chain.
9913 const Value *OpSrcValue;
9914 int OpSrcValueOffset;
9915 unsigned OpSrcValueAlign;
9916 const MDNode *OpSrcTBAAInfo;
9917 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
9918 OpSrcValue, OpSrcValueOffset,
9922 // If chain is alias then stop here.
9923 if (!(IsLoad && IsOpLoad) &&
9924 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
9926 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
9927 OpSrcValueAlign, OpSrcTBAAInfo)) {
9928 Aliases.push_back(Chain);
9930 // Look further up the chain.
9931 Chains.push_back(Chain.getOperand(0));
9937 case ISD::TokenFactor:
9938 // We have to check each of the operands of the token factor for "small"
9939 // token factors, so we queue them up. Adding the operands to the queue
9940 // (stack) in reverse order maintains the original order and increases the
9941 // likelihood that getNode will find a matching token factor (CSE.)
9942 if (Chain.getNumOperands() > 16) {
9943 Aliases.push_back(Chain);
9946 for (unsigned n = Chain.getNumOperands(); n;)
9947 Chains.push_back(Chain.getOperand(--n));
9952 // For all other instructions we will just have to take what we can get.
9953 Aliases.push_back(Chain);
9959 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
9960 /// for a better chain (aliasing node.)
9961 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
9962 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
9964 // Accumulate all the aliases to this node.
9965 GatherAllAliases(N, OldChain, Aliases);
9967 // If no operands then chain to entry token.
9968 if (Aliases.size() == 0)
9969 return DAG.getEntryNode();
9971 // If a single operand then chain to it. We don't need to revisit it.
9972 if (Aliases.size() == 1)
9975 // Construct a custom tailored token factor.
9976 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
9977 &Aliases[0], Aliases.size());
9980 // SelectionDAG::Combine - This is the entry point for the file.
9982 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
9983 CodeGenOpt::Level OptLevel) {
9984 /// run - This is the main entry point to this class.
9986 DAGCombiner(*this, AA, OptLevel).Run(Level);