1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "dagcombine"
16 #include "llvm/CodeGen/SelectionDAG.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Target/TargetData.h"
21 #include "llvm/Target/TargetFrameInfo.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/SmallPtrSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
35 STATISTIC(NodesCombined , "Number of dag nodes combined");
36 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
37 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
41 CombinerAA("combiner-alias-analysis", cl::Hidden,
42 cl::desc("Turn on alias analysis during testing"));
45 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
46 cl::desc("Include global information in alias analysis"));
48 //------------------------------ DAGCombiner ---------------------------------//
50 class VISIBILITY_HIDDEN DAGCombiner {
56 // Worklist of all of the nodes that need to be simplified.
57 std::vector<SDNode*> WorkList;
59 // AA - Used for DAG load/store alias analysis.
62 /// AddUsersToWorkList - When an instruction is simplified, add all users of
63 /// the instruction to the work lists because they might get more simplified
66 void AddUsersToWorkList(SDNode *N) {
67 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
72 /// visit - call the node-specific routine that knows how to fold each
73 /// particular type of node.
74 SDValue visit(SDNode *N);
77 /// AddToWorkList - Add to the work list making sure it's instance is at the
78 /// the back (next to be processed.)
79 void AddToWorkList(SDNode *N) {
80 removeFromWorkList(N);
81 WorkList.push_back(N);
84 /// removeFromWorkList - remove all instances of N from the worklist.
86 void removeFromWorkList(SDNode *N) {
87 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
91 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
94 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
95 return CombineTo(N, &Res, 1, AddTo);
98 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
100 SDValue To[] = { Res0, Res1 };
101 return CombineTo(N, To, 2, AddTo);
106 /// SimplifyDemandedBits - Check the specified integer node value to see if
107 /// it can be simplified or if things it uses can be simplified by bit
108 /// propagation. If so, return true.
109 bool SimplifyDemandedBits(SDValue Op) {
110 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits());
111 return SimplifyDemandedBits(Op, Demanded);
114 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
116 bool CombineToPreIndexedLoadStore(SDNode *N);
117 bool CombineToPostIndexedLoadStore(SDNode *N);
120 /// combine - call the node-specific routine that knows how to fold each
121 /// particular type of node. If that doesn't do anything, try the
122 /// target-specific DAG combines.
123 SDValue combine(SDNode *N);
125 // Visitation implementation - Implement dag node combining for different
126 // node types. The semantics are as follows:
128 // SDValue.getNode() == 0 - No change was made
129 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
130 // otherwise - N should be replaced by the returned Operand.
132 SDValue visitTokenFactor(SDNode *N);
133 SDValue visitMERGE_VALUES(SDNode *N);
134 SDValue visitADD(SDNode *N);
135 SDValue visitSUB(SDNode *N);
136 SDValue visitADDC(SDNode *N);
137 SDValue visitADDE(SDNode *N);
138 SDValue visitMUL(SDNode *N);
139 SDValue visitSDIV(SDNode *N);
140 SDValue visitUDIV(SDNode *N);
141 SDValue visitSREM(SDNode *N);
142 SDValue visitUREM(SDNode *N);
143 SDValue visitMULHU(SDNode *N);
144 SDValue visitMULHS(SDNode *N);
145 SDValue visitSMUL_LOHI(SDNode *N);
146 SDValue visitUMUL_LOHI(SDNode *N);
147 SDValue visitSDIVREM(SDNode *N);
148 SDValue visitUDIVREM(SDNode *N);
149 SDValue visitAND(SDNode *N);
150 SDValue visitOR(SDNode *N);
151 SDValue visitXOR(SDNode *N);
152 SDValue SimplifyVBinOp(SDNode *N);
153 SDValue visitSHL(SDNode *N);
154 SDValue visitSRA(SDNode *N);
155 SDValue visitSRL(SDNode *N);
156 SDValue visitCTLZ(SDNode *N);
157 SDValue visitCTTZ(SDNode *N);
158 SDValue visitCTPOP(SDNode *N);
159 SDValue visitSELECT(SDNode *N);
160 SDValue visitSELECT_CC(SDNode *N);
161 SDValue visitSETCC(SDNode *N);
162 SDValue visitSIGN_EXTEND(SDNode *N);
163 SDValue visitZERO_EXTEND(SDNode *N);
164 SDValue visitANY_EXTEND(SDNode *N);
165 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
166 SDValue visitTRUNCATE(SDNode *N);
167 SDValue visitBIT_CONVERT(SDNode *N);
168 SDValue visitBUILD_PAIR(SDNode *N);
169 SDValue visitFADD(SDNode *N);
170 SDValue visitFSUB(SDNode *N);
171 SDValue visitFMUL(SDNode *N);
172 SDValue visitFDIV(SDNode *N);
173 SDValue visitFREM(SDNode *N);
174 SDValue visitFCOPYSIGN(SDNode *N);
175 SDValue visitSINT_TO_FP(SDNode *N);
176 SDValue visitUINT_TO_FP(SDNode *N);
177 SDValue visitFP_TO_SINT(SDNode *N);
178 SDValue visitFP_TO_UINT(SDNode *N);
179 SDValue visitFP_ROUND(SDNode *N);
180 SDValue visitFP_ROUND_INREG(SDNode *N);
181 SDValue visitFP_EXTEND(SDNode *N);
182 SDValue visitFNEG(SDNode *N);
183 SDValue visitFABS(SDNode *N);
184 SDValue visitBRCOND(SDNode *N);
185 SDValue visitBR_CC(SDNode *N);
186 SDValue visitLOAD(SDNode *N);
187 SDValue visitSTORE(SDNode *N);
188 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
189 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
190 SDValue visitBUILD_VECTOR(SDNode *N);
191 SDValue visitCONCAT_VECTORS(SDNode *N);
192 SDValue visitVECTOR_SHUFFLE(SDNode *N);
194 SDValue XformToShuffleWithZero(SDNode *N);
195 SDValue ReassociateOps(unsigned Opc, SDValue LHS, SDValue RHS);
197 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
199 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
200 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
201 SDValue SimplifySelect(SDValue N0, SDValue N1, SDValue N2);
202 SDValue SimplifySelectCC(SDValue N0, SDValue N1, SDValue N2,
203 SDValue N3, ISD::CondCode CC,
204 bool NotExtCompare = false);
205 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
206 ISD::CondCode Cond, bool foldBooleans = true);
207 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
209 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT);
210 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT);
211 SDValue BuildSDIV(SDNode *N);
212 SDValue BuildUDIV(SDNode *N);
213 SDNode *MatchRotate(SDValue LHS, SDValue RHS);
214 SDValue ReduceLoadWidth(SDNode *N);
216 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
218 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
219 /// looking for aliasing nodes and adding them to the Aliases vector.
220 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
221 SmallVector<SDValue, 8> &Aliases);
223 /// isAlias - Return true if there is any possibility that the two addresses
225 bool isAlias(SDValue Ptr1, int64_t Size1,
226 const Value *SrcValue1, int SrcValueOffset1,
227 SDValue Ptr2, int64_t Size2,
228 const Value *SrcValue2, int SrcValueOffset2);
230 /// FindAliasInfo - Extracts the relevant alias information from the memory
231 /// node. Returns true if the operand was a load.
232 bool FindAliasInfo(SDNode *N,
233 SDValue &Ptr, int64_t &Size,
234 const Value *&SrcValue, int &SrcValueOffset);
236 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
237 /// looking for a better chain (aliasing node.)
238 SDValue FindBetterChain(SDNode *N, SDValue Chain);
241 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast)
243 TLI(D.getTargetLoweringInfo()),
244 AfterLegalize(false),
248 /// Run - runs the dag combiner on all nodes in the work list
249 void Run(bool RunningAfterLegalize);
255 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
256 /// nodes from the worklist.
257 class VISIBILITY_HIDDEN WorkListRemover :
258 public SelectionDAG::DAGUpdateListener {
261 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
263 virtual void NodeDeleted(SDNode *N, SDNode *E) {
264 DC.removeFromWorkList(N);
267 virtual void NodeUpdated(SDNode *N) {
273 //===----------------------------------------------------------------------===//
274 // TargetLowering::DAGCombinerInfo implementation
275 //===----------------------------------------------------------------------===//
277 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
278 ((DAGCombiner*)DC)->AddToWorkList(N);
281 SDValue TargetLowering::DAGCombinerInfo::
282 CombineTo(SDNode *N, const std::vector<SDValue> &To) {
283 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
286 SDValue TargetLowering::DAGCombinerInfo::
287 CombineTo(SDNode *N, SDValue Res) {
288 return ((DAGCombiner*)DC)->CombineTo(N, Res);
292 SDValue TargetLowering::DAGCombinerInfo::
293 CombineTo(SDNode *N, SDValue Res0, SDValue Res1) {
294 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
298 //===----------------------------------------------------------------------===//
300 //===----------------------------------------------------------------------===//
302 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
303 /// specified expression for the same cost as the expression itself, or 2 if we
304 /// can compute the negated form more cheaply than the expression itself.
305 static char isNegatibleForFree(SDValue Op, bool AfterLegalize,
306 unsigned Depth = 0) {
307 // No compile time optimizations on this type.
308 if (Op.getValueType() == MVT::ppcf128)
311 // fneg is removable even if it has multiple uses.
312 if (Op.getOpcode() == ISD::FNEG) return 2;
314 // Don't allow anything with multiple uses.
315 if (!Op.hasOneUse()) return 0;
317 // Don't recurse exponentially.
318 if (Depth > 6) return 0;
320 switch (Op.getOpcode()) {
321 default: return false;
322 case ISD::ConstantFP:
323 // Don't invert constant FP values after legalize. The negated constant
324 // isn't necessarily legal.
325 return AfterLegalize ? 0 : 1;
327 // FIXME: determine better conditions for this xform.
328 if (!UnsafeFPMath) return 0;
331 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1))
334 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1);
336 // We can't turn -(A-B) into B-A when we honor signed zeros.
337 if (!UnsafeFPMath) return 0;
344 if (HonorSignDependentRoundingFPMath()) return 0;
346 // -(X*Y) -> (-X * Y) or (X*-Y)
347 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1))
350 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1);
355 return isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1);
359 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
360 /// returns the newly negated expression.
361 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
362 bool AfterLegalize, unsigned Depth = 0) {
363 // fneg is removable even if it has multiple uses.
364 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
366 // Don't allow anything with multiple uses.
367 assert(Op.hasOneUse() && "Unknown reuse!");
369 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
370 switch (Op.getOpcode()) {
371 default: assert(0 && "Unknown code");
372 case ISD::ConstantFP: {
373 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
375 return DAG.getConstantFP(V, Op.getValueType());
378 // FIXME: determine better conditions for this xform.
379 assert(UnsafeFPMath);
382 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1))
383 return DAG.getNode(ISD::FSUB, Op.getValueType(),
384 GetNegatedExpression(Op.getOperand(0), DAG,
385 AfterLegalize, Depth+1),
388 return DAG.getNode(ISD::FSUB, Op.getValueType(),
389 GetNegatedExpression(Op.getOperand(1), DAG,
390 AfterLegalize, Depth+1),
393 // We can't turn -(A-B) into B-A when we honor signed zeros.
394 assert(UnsafeFPMath);
397 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
398 if (N0CFP->getValueAPF().isZero())
399 return Op.getOperand(1);
402 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1),
407 assert(!HonorSignDependentRoundingFPMath());
410 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1))
411 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
412 GetNegatedExpression(Op.getOperand(0), DAG,
413 AfterLegalize, Depth+1),
417 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
419 GetNegatedExpression(Op.getOperand(1), DAG,
420 AfterLegalize, Depth+1));
424 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
425 GetNegatedExpression(Op.getOperand(0), DAG,
426 AfterLegalize, Depth+1));
428 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(),
429 GetNegatedExpression(Op.getOperand(0), DAG,
430 AfterLegalize, Depth+1),
436 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
437 // that selects between the values 1 and 0, making it equivalent to a setcc.
438 // Also, set the incoming LHS, RHS, and CC references to the appropriate
439 // nodes based on the type of node we are checking. This simplifies life a
440 // bit for the callers.
441 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
443 if (N.getOpcode() == ISD::SETCC) {
444 LHS = N.getOperand(0);
445 RHS = N.getOperand(1);
446 CC = N.getOperand(2);
449 if (N.getOpcode() == ISD::SELECT_CC &&
450 N.getOperand(2).getOpcode() == ISD::Constant &&
451 N.getOperand(3).getOpcode() == ISD::Constant &&
452 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
453 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
454 LHS = N.getOperand(0);
455 RHS = N.getOperand(1);
456 CC = N.getOperand(4);
462 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
463 // one use. If this is true, it allows the users to invert the operation for
464 // free when it is profitable to do so.
465 static bool isOneUseSetCC(SDValue N) {
467 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
472 SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDValue N0, SDValue N1){
473 MVT VT = N0.getValueType();
474 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
475 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
476 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
477 if (isa<ConstantSDNode>(N1)) {
478 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
479 AddToWorkList(OpNode.getNode());
480 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
481 } else if (N0.hasOneUse()) {
482 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
483 AddToWorkList(OpNode.getNode());
484 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
487 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
488 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
489 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
490 if (isa<ConstantSDNode>(N0)) {
491 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
492 AddToWorkList(OpNode.getNode());
493 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
494 } else if (N1.hasOneUse()) {
495 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
496 AddToWorkList(OpNode.getNode());
497 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
503 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
505 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
507 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
508 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG));
509 DOUT << " and " << NumTo-1 << " other values\n";
510 WorkListRemover DeadNodes(*this);
511 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
514 // Push the new nodes and any users onto the worklist
515 for (unsigned i = 0, e = NumTo; i != e; ++i) {
516 AddToWorkList(To[i].getNode());
517 AddUsersToWorkList(To[i].getNode());
521 // Nodes can be reintroduced into the worklist. Make sure we do not
522 // process a node that has been replaced.
523 removeFromWorkList(N);
525 // Finally, since the node is now dead, remove it from the graph.
527 return SDValue(N, 0);
530 /// SimplifyDemandedBits - Check the specified integer node value to see if
531 /// it can be simplified or if things it uses can be simplified by bit
532 /// propagation. If so, return true.
533 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
534 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize);
535 APInt KnownZero, KnownOne;
536 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
540 AddToWorkList(Op.getNode());
542 // Replace the old value with the new one.
544 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG));
545 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG));
548 // Replace all uses. If any nodes become isomorphic to other nodes and
549 // are deleted, make sure to remove them from our worklist.
550 WorkListRemover DeadNodes(*this);
551 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
553 // Push the new node and any (possibly new) users onto the worklist.
554 AddToWorkList(TLO.New.getNode());
555 AddUsersToWorkList(TLO.New.getNode());
557 // Finally, if the node is now dead, remove it from the graph. The node
558 // may not be dead if the replacement process recursively simplified to
559 // something else needing this node.
560 if (TLO.Old.getNode()->use_empty()) {
561 removeFromWorkList(TLO.Old.getNode());
563 // If the operands of this node are only used by the node, they will now
564 // be dead. Make sure to visit them first to delete dead nodes early.
565 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
566 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
567 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
569 DAG.DeleteNode(TLO.Old.getNode());
574 //===----------------------------------------------------------------------===//
575 // Main DAG Combiner implementation
576 //===----------------------------------------------------------------------===//
578 void DAGCombiner::Run(bool RunningAfterLegalize) {
579 // set the instance variable, so that the various visit routines may use it.
580 AfterLegalize = RunningAfterLegalize;
582 // Add all the dag nodes to the worklist.
583 WorkList.reserve(DAG.allnodes_size());
584 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
585 E = DAG.allnodes_end(); I != E; ++I)
586 WorkList.push_back(I);
588 // Create a dummy node (which is not added to allnodes), that adds a reference
589 // to the root node, preventing it from being deleted, and tracking any
590 // changes of the root.
591 HandleSDNode Dummy(DAG.getRoot());
593 // The root of the dag may dangle to deleted nodes until the dag combiner is
594 // done. Set it to null to avoid confusion.
595 DAG.setRoot(SDValue());
597 // while the worklist isn't empty, inspect the node on the end of it and
598 // try and combine it.
599 while (!WorkList.empty()) {
600 SDNode *N = WorkList.back();
603 // If N has no uses, it is dead. Make sure to revisit all N's operands once
604 // N is deleted from the DAG, since they too may now be dead or may have a
605 // reduced number of uses, allowing other xforms.
606 if (N->use_empty() && N != &Dummy) {
607 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
608 AddToWorkList(N->getOperand(i).getNode());
614 SDValue RV = combine(N);
616 if (RV.getNode() == 0)
621 // If we get back the same node we passed in, rather than a new node or
622 // zero, we know that the node must have defined multiple values and
623 // CombineTo was used. Since CombineTo takes care of the worklist
624 // mechanics for us, we have no work to do in this case.
625 if (RV.getNode() == N)
628 assert(N->getOpcode() != ISD::DELETED_NODE &&
629 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
630 "Node was deleted but visit returned new node!");
632 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
633 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG));
635 WorkListRemover DeadNodes(*this);
636 if (N->getNumValues() == RV.getNode()->getNumValues())
637 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
639 assert(N->getValueType(0) == RV.getValueType() &&
640 N->getNumValues() == 1 && "Type mismatch");
642 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
645 // Push the new node and any users onto the worklist
646 AddToWorkList(RV.getNode());
647 AddUsersToWorkList(RV.getNode());
649 // Add any uses of the old node to the worklist in case this node is the
650 // last one that uses them. They may become dead after this node is
652 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
653 AddToWorkList(N->getOperand(i).getNode());
655 // Nodes can be reintroduced into the worklist. Make sure we do not
656 // process a node that has been replaced.
657 removeFromWorkList(N);
659 // Finally, since the node is now dead, remove it from the graph.
663 // If the root changed (e.g. it was a dead load, update the root).
664 DAG.setRoot(Dummy.getValue());
667 SDValue DAGCombiner::visit(SDNode *N) {
668 switch(N->getOpcode()) {
670 case ISD::TokenFactor: return visitTokenFactor(N);
671 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
672 case ISD::ADD: return visitADD(N);
673 case ISD::SUB: return visitSUB(N);
674 case ISD::ADDC: return visitADDC(N);
675 case ISD::ADDE: return visitADDE(N);
676 case ISD::MUL: return visitMUL(N);
677 case ISD::SDIV: return visitSDIV(N);
678 case ISD::UDIV: return visitUDIV(N);
679 case ISD::SREM: return visitSREM(N);
680 case ISD::UREM: return visitUREM(N);
681 case ISD::MULHU: return visitMULHU(N);
682 case ISD::MULHS: return visitMULHS(N);
683 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
684 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
685 case ISD::SDIVREM: return visitSDIVREM(N);
686 case ISD::UDIVREM: return visitUDIVREM(N);
687 case ISD::AND: return visitAND(N);
688 case ISD::OR: return visitOR(N);
689 case ISD::XOR: return visitXOR(N);
690 case ISD::SHL: return visitSHL(N);
691 case ISD::SRA: return visitSRA(N);
692 case ISD::SRL: return visitSRL(N);
693 case ISD::CTLZ: return visitCTLZ(N);
694 case ISD::CTTZ: return visitCTTZ(N);
695 case ISD::CTPOP: return visitCTPOP(N);
696 case ISD::SELECT: return visitSELECT(N);
697 case ISD::SELECT_CC: return visitSELECT_CC(N);
698 case ISD::SETCC: return visitSETCC(N);
699 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
700 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
701 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
702 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
703 case ISD::TRUNCATE: return visitTRUNCATE(N);
704 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
705 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
706 case ISD::FADD: return visitFADD(N);
707 case ISD::FSUB: return visitFSUB(N);
708 case ISD::FMUL: return visitFMUL(N);
709 case ISD::FDIV: return visitFDIV(N);
710 case ISD::FREM: return visitFREM(N);
711 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
712 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
713 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
714 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
715 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
716 case ISD::FP_ROUND: return visitFP_ROUND(N);
717 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
718 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
719 case ISD::FNEG: return visitFNEG(N);
720 case ISD::FABS: return visitFABS(N);
721 case ISD::BRCOND: return visitBRCOND(N);
722 case ISD::BR_CC: return visitBR_CC(N);
723 case ISD::LOAD: return visitLOAD(N);
724 case ISD::STORE: return visitSTORE(N);
725 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
726 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
727 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
728 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
729 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
734 SDValue DAGCombiner::combine(SDNode *N) {
736 SDValue RV = visit(N);
738 // If nothing happened, try a target-specific DAG combine.
739 if (RV.getNode() == 0) {
740 assert(N->getOpcode() != ISD::DELETED_NODE &&
741 "Node was deleted but visit returned NULL!");
743 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
744 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
746 // Expose the DAG combiner to the target combiner impls.
747 TargetLowering::DAGCombinerInfo
748 DagCombineInfo(DAG, !AfterLegalize, false, this);
750 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
754 // If N is a commutative binary node, try commuting it to enable more
756 if (RV.getNode() == 0 &&
757 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
758 N->getNumValues() == 1) {
759 SDValue N0 = N->getOperand(0);
760 SDValue N1 = N->getOperand(1);
761 // Constant operands are canonicalized to RHS.
762 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
763 SDValue Ops[] = { N1, N0 };
764 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
767 return SDValue(CSENode, 0);
774 /// getInputChainForNode - Given a node, return its input chain if it has one,
775 /// otherwise return a null sd operand.
776 static SDValue getInputChainForNode(SDNode *N) {
777 if (unsigned NumOps = N->getNumOperands()) {
778 if (N->getOperand(0).getValueType() == MVT::Other)
779 return N->getOperand(0);
780 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
781 return N->getOperand(NumOps-1);
782 for (unsigned i = 1; i < NumOps-1; ++i)
783 if (N->getOperand(i).getValueType() == MVT::Other)
784 return N->getOperand(i);
786 return SDValue(0, 0);
789 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
790 // If N has two operands, where one has an input chain equal to the other,
791 // the 'other' chain is redundant.
792 if (N->getNumOperands() == 2) {
793 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
794 return N->getOperand(0);
795 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
796 return N->getOperand(1);
799 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
800 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
801 SmallPtrSet<SDNode*, 16> SeenOps;
802 bool Changed = false; // If we should replace this token factor.
804 // Start out with this token factor.
807 // Iterate through token factors. The TFs grows when new token factors are
809 for (unsigned i = 0; i < TFs.size(); ++i) {
812 // Check each of the operands.
813 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
814 SDValue Op = TF->getOperand(i);
816 switch (Op.getOpcode()) {
817 case ISD::EntryToken:
818 // Entry tokens don't need to be added to the list. They are
823 case ISD::TokenFactor:
824 if ((CombinerAA || Op.hasOneUse()) &&
825 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
826 // Queue up for processing.
827 TFs.push_back(Op.getNode());
828 // Clean up in case the token factor is removed.
829 AddToWorkList(Op.getNode());
836 // Only add if it isn't already in the list.
837 if (SeenOps.insert(Op.getNode()))
848 // If we've change things around then replace token factor.
851 // The entry token is the only possible outcome.
852 Result = DAG.getEntryNode();
854 // New and improved token factor.
855 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
858 // Don't add users to work list.
859 return CombineTo(N, Result, false);
865 /// MERGE_VALUES can always be eliminated.
866 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
867 WorkListRemover DeadNodes(*this);
868 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
869 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
871 removeFromWorkList(N);
873 return SDValue(N, 0); // Return N so it doesn't get rechecked!
878 SDValue combineShlAddConstant(SDValue N0, SDValue N1, SelectionDAG &DAG) {
879 MVT VT = N0.getValueType();
880 SDValue N00 = N0.getOperand(0);
881 SDValue N01 = N0.getOperand(1);
882 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
883 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
884 isa<ConstantSDNode>(N00.getOperand(1))) {
885 N0 = DAG.getNode(ISD::ADD, VT,
886 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
887 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
888 return DAG.getNode(ISD::ADD, VT, N0, N1);
894 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
896 MVT VT = N->getValueType(0);
897 unsigned Opc = N->getOpcode();
898 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
899 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
900 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
901 ISD::CondCode CC = ISD::SETCC_INVALID;
903 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
905 SDValue CCOp = Slct.getOperand(0);
906 if (CCOp.getOpcode() == ISD::SETCC)
907 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
910 bool DoXform = false;
912 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
914 if (LHS.getOpcode() == ISD::Constant &&
915 cast<ConstantSDNode>(LHS)->isNullValue())
917 else if (CC != ISD::SETCC_INVALID &&
918 RHS.getOpcode() == ISD::Constant &&
919 cast<ConstantSDNode>(RHS)->isNullValue()) {
921 SDValue Op0 = Slct.getOperand(0);
922 bool isInt = (isSlctCC ? Op0.getValueType() :
923 Op0.getOperand(0).getValueType()).isInteger();
924 CC = ISD::getSetCCInverse(CC, isInt);
930 SDValue Result = DAG.getNode(Opc, VT, OtherOp, RHS);
932 return DAG.getSelectCC(OtherOp, Result,
933 Slct.getOperand(0), Slct.getOperand(1), CC);
934 SDValue CCOp = Slct.getOperand(0);
936 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0),
937 CCOp.getOperand(1), CC);
938 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result);
943 SDValue DAGCombiner::visitADD(SDNode *N) {
944 SDValue N0 = N->getOperand(0);
945 SDValue N1 = N->getOperand(1);
946 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
947 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
948 MVT VT = N0.getValueType();
952 SDValue FoldedVOp = SimplifyVBinOp(N);
953 if (FoldedVOp.getNode()) return FoldedVOp;
956 // fold (add x, undef) -> undef
957 if (N0.getOpcode() == ISD::UNDEF)
959 if (N1.getOpcode() == ISD::UNDEF)
961 // fold (add c1, c2) -> c1+c2
963 return DAG.getConstant(N0C->getAPIntValue() + N1C->getAPIntValue(), VT);
964 // canonicalize constant to RHS
966 return DAG.getNode(ISD::ADD, VT, N1, N0);
967 // fold (add x, 0) -> x
968 if (N1C && N1C->isNullValue())
970 // fold ((c1-A)+c2) -> (c1+c2)-A
971 if (N1C && N0.getOpcode() == ISD::SUB)
972 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
973 return DAG.getNode(ISD::SUB, VT,
974 DAG.getConstant(N1C->getAPIntValue()+
975 N0C->getAPIntValue(), VT),
978 SDValue RADD = ReassociateOps(ISD::ADD, N0, N1);
979 if (RADD.getNode() != 0)
981 // fold ((0-A) + B) -> B-A
982 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
983 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
984 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
985 // fold (A + (0-B)) -> A-B
986 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
987 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
988 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
989 // fold (A+(B-A)) -> B
990 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
991 return N1.getOperand(0);
993 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
994 return SDValue(N, 0);
996 // fold (a+b) -> (a|b) iff a and b share no bits.
997 if (VT.isInteger() && !VT.isVector()) {
998 APInt LHSZero, LHSOne;
999 APInt RHSZero, RHSOne;
1000 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
1001 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1002 if (LHSZero.getBoolValue()) {
1003 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1005 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1006 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1007 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1008 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1009 return DAG.getNode(ISD::OR, VT, N0, N1);
1013 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1014 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1015 SDValue Result = combineShlAddConstant(N0, N1, DAG);
1016 if (Result.getNode()) return Result;
1018 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1019 SDValue Result = combineShlAddConstant(N1, N0, DAG);
1020 if (Result.getNode()) return Result;
1023 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1024 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
1025 SDValue Result = combineSelectAndUse(N, N0, N1, DAG);
1026 if (Result.getNode()) return Result;
1028 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
1029 SDValue Result = combineSelectAndUse(N, N1, N0, DAG);
1030 if (Result.getNode()) return Result;
1036 SDValue DAGCombiner::visitADDC(SDNode *N) {
1037 SDValue N0 = N->getOperand(0);
1038 SDValue N1 = N->getOperand(1);
1039 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1040 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1041 MVT VT = N0.getValueType();
1043 // If the flag result is dead, turn this into an ADD.
1044 if (N->hasNUsesOfValue(0, 1))
1045 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
1046 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
1048 // canonicalize constant to RHS.
1050 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0);
1052 // fold (addc x, 0) -> x + no carry out
1053 if (N1C && N1C->isNullValue())
1054 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
1056 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1057 APInt LHSZero, LHSOne;
1058 APInt RHSZero, RHSOne;
1059 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
1060 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1061 if (LHSZero.getBoolValue()) {
1062 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1064 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1065 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1066 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1067 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1068 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
1069 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
1075 SDValue DAGCombiner::visitADDE(SDNode *N) {
1076 SDValue N0 = N->getOperand(0);
1077 SDValue N1 = N->getOperand(1);
1078 SDValue CarryIn = N->getOperand(2);
1079 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1080 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1081 //MVT VT = N0.getValueType();
1083 // canonicalize constant to RHS
1085 return DAG.getNode(ISD::ADDE, N->getVTList(), N1, N0, CarryIn);
1087 // fold (adde x, y, false) -> (addc x, y)
1088 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1089 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0);
1096 SDValue DAGCombiner::visitSUB(SDNode *N) {
1097 SDValue N0 = N->getOperand(0);
1098 SDValue N1 = N->getOperand(1);
1099 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1100 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1101 MVT VT = N0.getValueType();
1104 if (VT.isVector()) {
1105 SDValue FoldedVOp = SimplifyVBinOp(N);
1106 if (FoldedVOp.getNode()) return FoldedVOp;
1109 // fold (sub x, x) -> 0
1111 return DAG.getConstant(0, N->getValueType(0));
1112 // fold (sub c1, c2) -> c1-c2
1114 return DAG.getNode(ISD::SUB, VT, N0, N1);
1115 // fold (sub x, c) -> (add x, -c)
1117 return DAG.getNode(ISD::ADD, VT, N0,
1118 DAG.getConstant(-N1C->getAPIntValue(), VT));
1119 // fold (A+B)-A -> B
1120 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1121 return N0.getOperand(1);
1122 // fold (A+B)-B -> A
1123 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1124 return N0.getOperand(0);
1125 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1126 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
1127 SDValue Result = combineSelectAndUse(N, N1, N0, DAG);
1128 if (Result.getNode()) return Result;
1130 // If either operand of a sub is undef, the result is undef
1131 if (N0.getOpcode() == ISD::UNDEF)
1133 if (N1.getOpcode() == ISD::UNDEF)
1139 SDValue DAGCombiner::visitMUL(SDNode *N) {
1140 SDValue N0 = N->getOperand(0);
1141 SDValue N1 = N->getOperand(1);
1142 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1143 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1144 MVT VT = N0.getValueType();
1147 if (VT.isVector()) {
1148 SDValue FoldedVOp = SimplifyVBinOp(N);
1149 if (FoldedVOp.getNode()) return FoldedVOp;
1152 // fold (mul x, undef) -> 0
1153 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1154 return DAG.getConstant(0, VT);
1155 // fold (mul c1, c2) -> c1*c2
1157 return DAG.getNode(ISD::MUL, VT, N0, N1);
1158 // canonicalize constant to RHS
1160 return DAG.getNode(ISD::MUL, VT, N1, N0);
1161 // fold (mul x, 0) -> 0
1162 if (N1C && N1C->isNullValue())
1164 // fold (mul x, -1) -> 0-x
1165 if (N1C && N1C->isAllOnesValue())
1166 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1167 // fold (mul x, (1 << c)) -> x << c
1168 if (N1C && N1C->getAPIntValue().isPowerOf2())
1169 return DAG.getNode(ISD::SHL, VT, N0,
1170 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1171 TLI.getShiftAmountTy()));
1172 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1173 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
1174 // FIXME: If the input is something that is easily negated (e.g. a
1175 // single-use add), we should put the negate there.
1176 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
1177 DAG.getNode(ISD::SHL, VT, N0,
1178 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
1179 TLI.getShiftAmountTy())));
1182 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1183 if (N1C && N0.getOpcode() == ISD::SHL &&
1184 isa<ConstantSDNode>(N0.getOperand(1))) {
1185 SDValue C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
1186 AddToWorkList(C3.getNode());
1187 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
1190 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1193 SDValue Sh(0,0), Y(0,0);
1194 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1195 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1196 N0.getNode()->hasOneUse()) {
1198 } else if (N1.getOpcode() == ISD::SHL &&
1199 isa<ConstantSDNode>(N1.getOperand(1)) && N1.getNode()->hasOneUse()) {
1203 SDValue Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
1204 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
1207 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1208 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1209 isa<ConstantSDNode>(N0.getOperand(1))) {
1210 return DAG.getNode(ISD::ADD, VT,
1211 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
1212 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
1216 SDValue RMUL = ReassociateOps(ISD::MUL, N0, N1);
1217 if (RMUL.getNode() != 0)
1223 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1224 SDValue N0 = N->getOperand(0);
1225 SDValue N1 = N->getOperand(1);
1226 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1227 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1228 MVT VT = N->getValueType(0);
1231 if (VT.isVector()) {
1232 SDValue FoldedVOp = SimplifyVBinOp(N);
1233 if (FoldedVOp.getNode()) return FoldedVOp;
1236 // fold (sdiv c1, c2) -> c1/c2
1237 if (N0C && N1C && !N1C->isNullValue())
1238 return DAG.getNode(ISD::SDIV, VT, N0, N1);
1239 // fold (sdiv X, 1) -> X
1240 if (N1C && N1C->getSignExtended() == 1LL)
1242 // fold (sdiv X, -1) -> 0-X
1243 if (N1C && N1C->isAllOnesValue())
1244 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1245 // If we know the sign bits of both operands are zero, strength reduce to a
1246 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1247 if (!VT.isVector()) {
1248 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1249 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
1251 // fold (sdiv X, pow2) -> simple ops after legalize
1252 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1253 (isPowerOf2_64(N1C->getSignExtended()) ||
1254 isPowerOf2_64(-N1C->getSignExtended()))) {
1255 // If dividing by powers of two is cheap, then don't perform the following
1257 if (TLI.isPow2DivCheap())
1259 int64_t pow2 = N1C->getSignExtended();
1260 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1261 unsigned lg2 = Log2_64(abs2);
1262 // Splat the sign bit into the register
1263 SDValue SGN = DAG.getNode(ISD::SRA, VT, N0,
1264 DAG.getConstant(VT.getSizeInBits()-1,
1265 TLI.getShiftAmountTy()));
1266 AddToWorkList(SGN.getNode());
1267 // Add (N0 < 0) ? abs2 - 1 : 0;
1268 SDValue SRL = DAG.getNode(ISD::SRL, VT, SGN,
1269 DAG.getConstant(VT.getSizeInBits()-lg2,
1270 TLI.getShiftAmountTy()));
1271 SDValue ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
1272 AddToWorkList(SRL.getNode());
1273 AddToWorkList(ADD.getNode()); // Divide by pow2
1274 SDValue SRA = DAG.getNode(ISD::SRA, VT, ADD,
1275 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
1276 // If we're dividing by a positive value, we're done. Otherwise, we must
1277 // negate the result.
1280 AddToWorkList(SRA.getNode());
1281 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
1283 // if integer divide is expensive and we satisfy the requirements, emit an
1284 // alternate sequence.
1285 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
1286 !TLI.isIntDivCheap()) {
1287 SDValue Op = BuildSDIV(N);
1288 if (Op.getNode()) return Op;
1292 if (N0.getOpcode() == ISD::UNDEF)
1293 return DAG.getConstant(0, VT);
1294 // X / undef -> undef
1295 if (N1.getOpcode() == ISD::UNDEF)
1301 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1302 SDValue N0 = N->getOperand(0);
1303 SDValue N1 = N->getOperand(1);
1304 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1305 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1306 MVT VT = N->getValueType(0);
1309 if (VT.isVector()) {
1310 SDValue FoldedVOp = SimplifyVBinOp(N);
1311 if (FoldedVOp.getNode()) return FoldedVOp;
1314 // fold (udiv c1, c2) -> c1/c2
1315 if (N0C && N1C && !N1C->isNullValue())
1316 return DAG.getNode(ISD::UDIV, VT, N0, N1);
1317 // fold (udiv x, (1 << c)) -> x >>u c
1318 if (N1C && N1C->getAPIntValue().isPowerOf2())
1319 return DAG.getNode(ISD::SRL, VT, N0,
1320 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1321 TLI.getShiftAmountTy()));
1322 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1323 if (N1.getOpcode() == ISD::SHL) {
1324 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1325 if (SHC->getAPIntValue().isPowerOf2()) {
1326 MVT ADDVT = N1.getOperand(1).getValueType();
1327 SDValue Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
1328 DAG.getConstant(SHC->getAPIntValue()
1331 AddToWorkList(Add.getNode());
1332 return DAG.getNode(ISD::SRL, VT, N0, Add);
1336 // fold (udiv x, c) -> alternate
1337 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1338 SDValue Op = BuildUDIV(N);
1339 if (Op.getNode()) return Op;
1343 if (N0.getOpcode() == ISD::UNDEF)
1344 return DAG.getConstant(0, VT);
1345 // X / undef -> undef
1346 if (N1.getOpcode() == ISD::UNDEF)
1352 SDValue DAGCombiner::visitSREM(SDNode *N) {
1353 SDValue N0 = N->getOperand(0);
1354 SDValue N1 = N->getOperand(1);
1355 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1356 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1357 MVT VT = N->getValueType(0);
1359 // fold (srem c1, c2) -> c1%c2
1360 if (N0C && N1C && !N1C->isNullValue())
1361 return DAG.getNode(ISD::SREM, VT, N0, N1);
1362 // If we know the sign bits of both operands are zero, strength reduce to a
1363 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1364 if (!VT.isVector()) {
1365 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1366 return DAG.getNode(ISD::UREM, VT, N0, N1);
1369 // If X/C can be simplified by the division-by-constant logic, lower
1370 // X%C to the equivalent of X-X/C*C.
1371 if (N1C && !N1C->isNullValue()) {
1372 SDValue Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
1373 AddToWorkList(Div.getNode());
1374 SDValue OptimizedDiv = combine(Div.getNode());
1375 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1376 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
1377 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1378 AddToWorkList(Mul.getNode());
1384 if (N0.getOpcode() == ISD::UNDEF)
1385 return DAG.getConstant(0, VT);
1386 // X % undef -> undef
1387 if (N1.getOpcode() == ISD::UNDEF)
1393 SDValue DAGCombiner::visitUREM(SDNode *N) {
1394 SDValue N0 = N->getOperand(0);
1395 SDValue N1 = N->getOperand(1);
1396 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1397 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1398 MVT VT = N->getValueType(0);
1400 // fold (urem c1, c2) -> c1%c2
1401 if (N0C && N1C && !N1C->isNullValue())
1402 return DAG.getNode(ISD::UREM, VT, N0, N1);
1403 // fold (urem x, pow2) -> (and x, pow2-1)
1404 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1405 return DAG.getNode(ISD::AND, VT, N0,
1406 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1407 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1408 if (N1.getOpcode() == ISD::SHL) {
1409 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1410 if (SHC->getAPIntValue().isPowerOf2()) {
1412 DAG.getNode(ISD::ADD, VT, N1,
1413 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1415 AddToWorkList(Add.getNode());
1416 return DAG.getNode(ISD::AND, VT, N0, Add);
1421 // If X/C can be simplified by the division-by-constant logic, lower
1422 // X%C to the equivalent of X-X/C*C.
1423 if (N1C && !N1C->isNullValue()) {
1424 SDValue Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
1425 SDValue OptimizedDiv = combine(Div.getNode());
1426 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1427 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
1428 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1429 AddToWorkList(Mul.getNode());
1435 if (N0.getOpcode() == ISD::UNDEF)
1436 return DAG.getConstant(0, VT);
1437 // X % undef -> undef
1438 if (N1.getOpcode() == ISD::UNDEF)
1444 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1445 SDValue N0 = N->getOperand(0);
1446 SDValue N1 = N->getOperand(1);
1447 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1448 MVT VT = N->getValueType(0);
1450 // fold (mulhs x, 0) -> 0
1451 if (N1C && N1C->isNullValue())
1453 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1454 if (N1C && N1C->getAPIntValue() == 1)
1455 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1456 DAG.getConstant(N0.getValueType().getSizeInBits()-1,
1457 TLI.getShiftAmountTy()));
1458 // fold (mulhs x, undef) -> 0
1459 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1460 return DAG.getConstant(0, VT);
1465 SDValue DAGCombiner::visitMULHU(SDNode *N) {
1466 SDValue N0 = N->getOperand(0);
1467 SDValue N1 = N->getOperand(1);
1468 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1469 MVT VT = N->getValueType(0);
1471 // fold (mulhu x, 0) -> 0
1472 if (N1C && N1C->isNullValue())
1474 // fold (mulhu x, 1) -> 0
1475 if (N1C && N1C->getAPIntValue() == 1)
1476 return DAG.getConstant(0, N0.getValueType());
1477 // fold (mulhu x, undef) -> 0
1478 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1479 return DAG.getConstant(0, VT);
1484 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1485 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1486 /// that are being performed. Return true if a simplification was made.
1488 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
1490 // If the high half is not needed, just compute the low half.
1491 bool HiExists = N->hasAnyUseOfValue(1);
1494 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1495 SDValue Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(),
1496 N->getNumOperands());
1497 return CombineTo(N, Res, Res);
1500 // If the low half is not needed, just compute the high half.
1501 bool LoExists = N->hasAnyUseOfValue(0);
1504 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1505 SDValue Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(),
1506 N->getNumOperands());
1507 return CombineTo(N, Res, Res);
1510 // If both halves are used, return as it is.
1511 if (LoExists && HiExists)
1514 // If the two computed results can be simplified separately, separate them.
1516 SDValue Lo = DAG.getNode(LoOp, N->getValueType(0),
1517 N->op_begin(), N->getNumOperands());
1518 AddToWorkList(Lo.getNode());
1519 SDValue LoOpt = combine(Lo.getNode());
1520 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
1522 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
1523 return CombineTo(N, LoOpt, LoOpt);
1527 SDValue Hi = DAG.getNode(HiOp, N->getValueType(1),
1528 N->op_begin(), N->getNumOperands());
1529 AddToWorkList(Hi.getNode());
1530 SDValue HiOpt = combine(Hi.getNode());
1531 if (HiOpt.getNode() && HiOpt != Hi &&
1533 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
1534 return CombineTo(N, HiOpt, HiOpt);
1539 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1540 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
1541 if (Res.getNode()) return Res;
1546 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1547 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
1548 if (Res.getNode()) return Res;
1553 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
1554 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
1555 if (Res.getNode()) return Res;
1560 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
1561 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
1562 if (Res.getNode()) return Res;
1567 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1568 /// two operands of the same opcode, try to simplify it.
1569 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1570 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1571 MVT VT = N0.getValueType();
1572 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1574 // For each of OP in AND/OR/XOR:
1575 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1576 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1577 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1578 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1579 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1580 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1581 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1582 SDValue ORNode = DAG.getNode(N->getOpcode(),
1583 N0.getOperand(0).getValueType(),
1584 N0.getOperand(0), N1.getOperand(0));
1585 AddToWorkList(ORNode.getNode());
1586 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1589 // For each of OP in SHL/SRL/SRA/AND...
1590 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1591 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1592 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1593 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1594 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1595 N0.getOperand(1) == N1.getOperand(1)) {
1596 SDValue ORNode = DAG.getNode(N->getOpcode(),
1597 N0.getOperand(0).getValueType(),
1598 N0.getOperand(0), N1.getOperand(0));
1599 AddToWorkList(ORNode.getNode());
1600 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1606 SDValue DAGCombiner::visitAND(SDNode *N) {
1607 SDValue N0 = N->getOperand(0);
1608 SDValue N1 = N->getOperand(1);
1609 SDValue LL, LR, RL, RR, CC0, CC1;
1610 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1611 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1612 MVT VT = N1.getValueType();
1613 unsigned BitWidth = VT.getSizeInBits();
1616 if (VT.isVector()) {
1617 SDValue FoldedVOp = SimplifyVBinOp(N);
1618 if (FoldedVOp.getNode()) return FoldedVOp;
1621 // fold (and x, undef) -> 0
1622 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1623 return DAG.getConstant(0, VT);
1624 // fold (and c1, c2) -> c1&c2
1626 return DAG.getNode(ISD::AND, VT, N0, N1);
1627 // canonicalize constant to RHS
1629 return DAG.getNode(ISD::AND, VT, N1, N0);
1630 // fold (and x, -1) -> x
1631 if (N1C && N1C->isAllOnesValue())
1633 // if (and x, c) is known to be zero, return 0
1634 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
1635 APInt::getAllOnesValue(BitWidth)))
1636 return DAG.getConstant(0, VT);
1638 SDValue RAND = ReassociateOps(ISD::AND, N0, N1);
1639 if (RAND.getNode() != 0)
1641 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1642 if (N1C && N0.getOpcode() == ISD::OR)
1643 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1644 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
1646 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1647 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1648 SDValue N0Op0 = N0.getOperand(0);
1649 APInt Mask = ~N1C->getAPIntValue();
1650 Mask.trunc(N0Op0.getValueSizeInBits());
1651 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
1652 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1655 // Replace uses of the AND with uses of the Zero extend node.
1658 // We actually want to replace all uses of the any_extend with the
1659 // zero_extend, to avoid duplicating things. This will later cause this
1660 // AND to be folded.
1661 CombineTo(N0.getNode(), Zext);
1662 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1665 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1666 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1667 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1668 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1670 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1671 LL.getValueType().isInteger()) {
1672 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1673 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
1674 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1675 AddToWorkList(ORNode.getNode());
1676 return DAG.getSetCC(VT, ORNode, LR, Op1);
1678 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1679 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1680 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1681 AddToWorkList(ANDNode.getNode());
1682 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1684 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1685 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1686 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1687 AddToWorkList(ORNode.getNode());
1688 return DAG.getSetCC(VT, ORNode, LR, Op1);
1691 // canonicalize equivalent to ll == rl
1692 if (LL == RR && LR == RL) {
1693 Op1 = ISD::getSetCCSwappedOperands(Op1);
1696 if (LL == RL && LR == RR) {
1697 bool isInteger = LL.getValueType().isInteger();
1698 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1699 if (Result != ISD::SETCC_INVALID)
1700 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1704 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1705 if (N0.getOpcode() == N1.getOpcode()) {
1706 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1707 if (Tmp.getNode()) return Tmp;
1710 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1711 // fold (and (sra)) -> (and (srl)) when possible.
1712 if (!VT.isVector() &&
1713 SimplifyDemandedBits(SDValue(N, 0)))
1714 return SDValue(N, 0);
1715 // fold (zext_inreg (extload x)) -> (zextload x)
1716 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
1717 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1718 MVT EVT = LN0->getMemoryVT();
1719 // If we zero all the possible extended bits, then we can turn this into
1720 // a zextload if we are running before legalize or the operation is legal.
1721 unsigned BitWidth = N1.getValueSizeInBits();
1722 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1723 BitWidth - EVT.getSizeInBits())) &&
1724 ((!AfterLegalize && !LN0->isVolatile()) ||
1725 TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1726 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1727 LN0->getBasePtr(), LN0->getSrcValue(),
1728 LN0->getSrcValueOffset(), EVT,
1730 LN0->getAlignment());
1732 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1733 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1736 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1737 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
1739 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1740 MVT EVT = LN0->getMemoryVT();
1741 // If we zero all the possible extended bits, then we can turn this into
1742 // a zextload if we are running before legalize or the operation is legal.
1743 unsigned BitWidth = N1.getValueSizeInBits();
1744 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1745 BitWidth - EVT.getSizeInBits())) &&
1746 ((!AfterLegalize && !LN0->isVolatile()) ||
1747 TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1748 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1749 LN0->getBasePtr(), LN0->getSrcValue(),
1750 LN0->getSrcValueOffset(), EVT,
1752 LN0->getAlignment());
1754 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1755 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1759 // fold (and (load x), 255) -> (zextload x, i8)
1760 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1761 if (N1C && N0.getOpcode() == ISD::LOAD) {
1762 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1763 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1764 LN0->isUnindexed() && N0.hasOneUse() &&
1765 // Do not change the width of a volatile load.
1766 !LN0->isVolatile()) {
1767 MVT EVT = MVT::Other;
1768 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
1769 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue()))
1770 EVT = MVT::getIntegerVT(ActiveBits);
1772 MVT LoadedVT = LN0->getMemoryVT();
1773 // Do not generate loads of non-round integer types since these can
1774 // be expensive (and would be wrong if the type is not byte sized).
1775 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() &&
1776 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1777 MVT PtrType = N0.getOperand(1).getValueType();
1778 // For big endian targets, we need to add an offset to the pointer to
1779 // load the correct bytes. For little endian systems, we merely need to
1780 // read fewer bytes from the same pointer.
1781 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8;
1782 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8;
1783 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
1784 unsigned Alignment = LN0->getAlignment();
1785 SDValue NewPtr = LN0->getBasePtr();
1786 if (TLI.isBigEndian()) {
1787 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1788 DAG.getConstant(PtrOff, PtrType));
1789 Alignment = MinAlign(Alignment, PtrOff);
1791 AddToWorkList(NewPtr.getNode());
1793 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1794 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
1795 LN0->isVolatile(), Alignment);
1797 CombineTo(N0.getNode(), Load, Load.getValue(1));
1798 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1806 SDValue DAGCombiner::visitOR(SDNode *N) {
1807 SDValue N0 = N->getOperand(0);
1808 SDValue N1 = N->getOperand(1);
1809 SDValue LL, LR, RL, RR, CC0, CC1;
1810 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1811 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1812 MVT VT = N1.getValueType();
1815 if (VT.isVector()) {
1816 SDValue FoldedVOp = SimplifyVBinOp(N);
1817 if (FoldedVOp.getNode()) return FoldedVOp;
1820 // fold (or x, undef) -> -1
1821 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1822 return DAG.getConstant(~0ULL, VT);
1823 // fold (or c1, c2) -> c1|c2
1825 return DAG.getNode(ISD::OR, VT, N0, N1);
1826 // canonicalize constant to RHS
1828 return DAG.getNode(ISD::OR, VT, N1, N0);
1829 // fold (or x, 0) -> x
1830 if (N1C && N1C->isNullValue())
1832 // fold (or x, -1) -> -1
1833 if (N1C && N1C->isAllOnesValue())
1835 // fold (or x, c) -> c iff (x & ~c) == 0
1836 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
1839 SDValue ROR = ReassociateOps(ISD::OR, N0, N1);
1840 if (ROR.getNode() != 0)
1842 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1843 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
1844 isa<ConstantSDNode>(N0.getOperand(1))) {
1845 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1846 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1848 DAG.getConstant(N1C->getAPIntValue() |
1849 C1->getAPIntValue(), VT));
1851 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1852 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1853 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1854 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1856 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1857 LL.getValueType().isInteger()) {
1858 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1859 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1860 if (cast<ConstantSDNode>(LR)->isNullValue() &&
1861 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1862 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1863 AddToWorkList(ORNode.getNode());
1864 return DAG.getSetCC(VT, ORNode, LR, Op1);
1866 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1867 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1868 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1869 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1870 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1871 AddToWorkList(ANDNode.getNode());
1872 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1875 // canonicalize equivalent to ll == rl
1876 if (LL == RR && LR == RL) {
1877 Op1 = ISD::getSetCCSwappedOperands(Op1);
1880 if (LL == RL && LR == RR) {
1881 bool isInteger = LL.getValueType().isInteger();
1882 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1883 if (Result != ISD::SETCC_INVALID)
1884 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1888 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1889 if (N0.getOpcode() == N1.getOpcode()) {
1890 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1891 if (Tmp.getNode()) return Tmp;
1894 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1895 if (N0.getOpcode() == ISD::AND &&
1896 N1.getOpcode() == ISD::AND &&
1897 N0.getOperand(1).getOpcode() == ISD::Constant &&
1898 N1.getOperand(1).getOpcode() == ISD::Constant &&
1899 // Don't increase # computations.
1900 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
1901 // We can only do this xform if we know that bits from X that are set in C2
1902 // but not in C1 are already zero. Likewise for Y.
1903 const APInt &LHSMask =
1904 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1905 const APInt &RHSMask =
1906 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
1908 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1909 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1910 SDValue X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1911 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1916 // See if this is some rotate idiom.
1917 if (SDNode *Rot = MatchRotate(N0, N1))
1918 return SDValue(Rot, 0);
1924 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1925 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
1926 if (Op.getOpcode() == ISD::AND) {
1927 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1928 Mask = Op.getOperand(1);
1929 Op = Op.getOperand(0);
1935 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1943 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1944 // idioms for rotate, and if the target supports rotation instructions, generate
1946 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) {
1947 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
1948 MVT VT = LHS.getValueType();
1949 if (!TLI.isTypeLegal(VT)) return 0;
1951 // The target must have at least one rotate flavor.
1952 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1953 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1954 if (!HasROTL && !HasROTR) return 0;
1956 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1957 SDValue LHSShift; // The shift.
1958 SDValue LHSMask; // AND value if any.
1959 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1960 return 0; // Not part of a rotate.
1962 SDValue RHSShift; // The shift.
1963 SDValue RHSMask; // AND value if any.
1964 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1965 return 0; // Not part of a rotate.
1967 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1968 return 0; // Not shifting the same value.
1970 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1971 return 0; // Shifts must disagree.
1973 // Canonicalize shl to left side in a shl/srl pair.
1974 if (RHSShift.getOpcode() == ISD::SHL) {
1975 std::swap(LHS, RHS);
1976 std::swap(LHSShift, RHSShift);
1977 std::swap(LHSMask , RHSMask );
1980 unsigned OpSizeInBits = VT.getSizeInBits();
1981 SDValue LHSShiftArg = LHSShift.getOperand(0);
1982 SDValue LHSShiftAmt = LHSShift.getOperand(1);
1983 SDValue RHSShiftAmt = RHSShift.getOperand(1);
1985 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1986 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1987 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
1988 RHSShiftAmt.getOpcode() == ISD::Constant) {
1989 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue();
1990 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue();
1991 if ((LShVal + RShVal) != OpSizeInBits)
1996 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
1998 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
2000 // If there is an AND of either shifted operand, apply it to the result.
2001 if (LHSMask.getNode() || RHSMask.getNode()) {
2002 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2004 if (LHSMask.getNode()) {
2005 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2006 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2008 if (RHSMask.getNode()) {
2009 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2010 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2013 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
2016 return Rot.getNode();
2019 // If there is a mask here, and we have a variable shift, we can't be sure
2020 // that we're masking out the right stuff.
2021 if (LHSMask.getNode() || RHSMask.getNode())
2024 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2025 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2026 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2027 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2028 if (ConstantSDNode *SUBC =
2029 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2030 if (SUBC->getAPIntValue() == OpSizeInBits) {
2032 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode();
2034 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode();
2039 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2040 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2041 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2042 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2043 if (ConstantSDNode *SUBC =
2044 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2045 if (SUBC->getAPIntValue() == OpSizeInBits) {
2047 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode();
2049 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode();
2054 // Look for sign/zext/any-extended cases:
2055 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2056 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2057 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) &&
2058 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2059 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2060 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
2061 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
2062 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
2063 if (RExtOp0.getOpcode() == ISD::SUB &&
2064 RExtOp0.getOperand(1) == LExtOp0) {
2065 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2067 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2068 // (rotl x, (sub 32, y))
2069 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2070 if (SUBC->getAPIntValue() == OpSizeInBits) {
2072 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode();
2074 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode();
2077 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2078 RExtOp0 == LExtOp0.getOperand(1)) {
2079 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2081 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
2082 // (rotr x, (sub 32, y))
2083 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2084 if (SUBC->getAPIntValue() == OpSizeInBits) {
2086 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).getNode();
2088 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode();
2098 SDValue DAGCombiner::visitXOR(SDNode *N) {
2099 SDValue N0 = N->getOperand(0);
2100 SDValue N1 = N->getOperand(1);
2101 SDValue LHS, RHS, CC;
2102 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2103 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2104 MVT VT = N0.getValueType();
2107 if (VT.isVector()) {
2108 SDValue FoldedVOp = SimplifyVBinOp(N);
2109 if (FoldedVOp.getNode()) return FoldedVOp;
2112 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
2113 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
2114 return DAG.getConstant(0, VT);
2115 // fold (xor x, undef) -> undef
2116 if (N0.getOpcode() == ISD::UNDEF)
2118 if (N1.getOpcode() == ISD::UNDEF)
2120 // fold (xor c1, c2) -> c1^c2
2122 return DAG.getNode(ISD::XOR, VT, N0, N1);
2123 // canonicalize constant to RHS
2125 return DAG.getNode(ISD::XOR, VT, N1, N0);
2126 // fold (xor x, 0) -> x
2127 if (N1C && N1C->isNullValue())
2130 SDValue RXOR = ReassociateOps(ISD::XOR, N0, N1);
2131 if (RXOR.getNode() != 0)
2133 // fold !(x cc y) -> (x !cc y)
2134 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2135 bool isInt = LHS.getValueType().isInteger();
2136 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2138 if (N0.getOpcode() == ISD::SETCC)
2139 return DAG.getSetCC(VT, LHS, RHS, NotCC);
2140 if (N0.getOpcode() == ISD::SELECT_CC)
2141 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
2142 assert(0 && "Unhandled SetCC Equivalent!");
2145 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2146 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2147 N0.getNode()->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2148 SDValue V = N0.getOperand(0);
2149 V = DAG.getNode(ISD::XOR, V.getValueType(), V,
2150 DAG.getConstant(1, V.getValueType()));
2151 AddToWorkList(V.getNode());
2152 return DAG.getNode(ISD::ZERO_EXTEND, VT, V);
2155 // fold !(x or y) -> (!x and !y) iff x or y are setcc
2156 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2157 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2158 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2159 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2160 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2161 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2162 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2163 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2164 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2167 // fold !(x or y) -> (!x and !y) iff x or y are constants
2168 if (N1C && N1C->isAllOnesValue() &&
2169 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2170 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2171 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2172 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2173 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
2174 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
2175 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2176 return DAG.getNode(NewOpcode, VT, LHS, RHS);
2179 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
2180 if (N1C && N0.getOpcode() == ISD::XOR) {
2181 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2182 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2184 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
2185 DAG.getConstant(N1C->getAPIntValue()^
2186 N00C->getAPIntValue(), VT));
2188 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
2189 DAG.getConstant(N1C->getAPIntValue()^
2190 N01C->getAPIntValue(), VT));
2192 // fold (xor x, x) -> 0
2194 if (!VT.isVector()) {
2195 return DAG.getConstant(0, VT);
2196 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
2197 // Produce a vector of zeros.
2198 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
2199 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
2200 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
2204 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2205 if (N0.getOpcode() == N1.getOpcode()) {
2206 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2207 if (Tmp.getNode()) return Tmp;
2210 // Simplify the expression using non-local knowledge.
2211 if (!VT.isVector() &&
2212 SimplifyDemandedBits(SDValue(N, 0)))
2213 return SDValue(N, 0);
2218 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2219 /// the shift amount is a constant.
2220 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2221 SDNode *LHS = N->getOperand(0).getNode();
2222 if (!LHS->hasOneUse()) return SDValue();
2224 // We want to pull some binops through shifts, so that we have (and (shift))
2225 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2226 // thing happens with address calculations, so it's important to canonicalize
2228 bool HighBitSet = false; // Can we transform this if the high bit is set?
2230 switch (LHS->getOpcode()) {
2231 default: return SDValue();
2234 HighBitSet = false; // We can only transform sra if the high bit is clear.
2237 HighBitSet = true; // We can only transform sra if the high bit is set.
2240 if (N->getOpcode() != ISD::SHL)
2241 return SDValue(); // only shl(add) not sr[al](add).
2242 HighBitSet = false; // We can only transform sra if the high bit is clear.
2246 // We require the RHS of the binop to be a constant as well.
2247 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2248 if (!BinOpCst) return SDValue();
2251 // FIXME: disable this for unless the input to the binop is a shift by a
2252 // constant. If it is not a shift, it pessimizes some common cases like:
2254 //void foo(int *X, int i) { X[i & 1235] = 1; }
2255 //int bar(int *X, int i) { return X[i & 255]; }
2256 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
2257 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2258 BinOpLHSVal->getOpcode() != ISD::SRA &&
2259 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2260 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2263 MVT VT = N->getValueType(0);
2265 // If this is a signed shift right, and the high bit is modified
2266 // by the logical operation, do not perform the transformation.
2267 // The highBitSet boolean indicates the value of the high bit of
2268 // the constant which would cause it to be modified for this
2270 if (N->getOpcode() == ISD::SRA) {
2271 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
2272 if (BinOpRHSSignSet != HighBitSet)
2276 // Fold the constants, shifting the binop RHS by the shift amount.
2277 SDValue NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0),
2278 LHS->getOperand(1), N->getOperand(1));
2280 // Create the new shift.
2281 SDValue NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0),
2284 // Create the new binop.
2285 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS);
2289 SDValue DAGCombiner::visitSHL(SDNode *N) {
2290 SDValue N0 = N->getOperand(0);
2291 SDValue N1 = N->getOperand(1);
2292 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2293 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2294 MVT VT = N0.getValueType();
2295 unsigned OpSizeInBits = VT.getSizeInBits();
2297 // fold (shl c1, c2) -> c1<<c2
2299 return DAG.getNode(ISD::SHL, VT, N0, N1);
2300 // fold (shl 0, x) -> 0
2301 if (N0C && N0C->isNullValue())
2303 // fold (shl x, c >= size(x)) -> undef
2304 if (N1C && N1C->getValue() >= OpSizeInBits)
2305 return DAG.getNode(ISD::UNDEF, VT);
2306 // fold (shl x, 0) -> x
2307 if (N1C && N1C->isNullValue())
2309 // if (shl x, c) is known to be zero, return 0
2310 if (DAG.MaskedValueIsZero(SDValue(N, 0),
2311 APInt::getAllOnesValue(VT.getSizeInBits())))
2312 return DAG.getConstant(0, VT);
2313 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2314 return SDValue(N, 0);
2315 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
2316 if (N1C && N0.getOpcode() == ISD::SHL &&
2317 N0.getOperand(1).getOpcode() == ISD::Constant) {
2318 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2319 uint64_t c2 = N1C->getValue();
2320 if (c1 + c2 > OpSizeInBits)
2321 return DAG.getConstant(0, VT);
2322 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
2323 DAG.getConstant(c1 + c2, N1.getValueType()));
2325 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
2326 // (srl (and x, -1 << c1), c1-c2)
2327 if (N1C && N0.getOpcode() == ISD::SRL &&
2328 N0.getOperand(1).getOpcode() == ISD::Constant) {
2329 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2330 uint64_t c2 = N1C->getValue();
2331 SDValue Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2332 DAG.getConstant(~0ULL << c1, VT));
2334 return DAG.getNode(ISD::SHL, VT, Mask,
2335 DAG.getConstant(c2-c1, N1.getValueType()));
2337 return DAG.getNode(ISD::SRL, VT, Mask,
2338 DAG.getConstant(c1-c2, N1.getValueType()));
2340 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
2341 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2342 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2343 DAG.getConstant(~0ULL << N1C->getValue(), VT));
2345 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDValue();
2348 SDValue DAGCombiner::visitSRA(SDNode *N) {
2349 SDValue N0 = N->getOperand(0);
2350 SDValue N1 = N->getOperand(1);
2351 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2352 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2353 MVT VT = N0.getValueType();
2355 // fold (sra c1, c2) -> c1>>c2
2357 return DAG.getNode(ISD::SRA, VT, N0, N1);
2358 // fold (sra 0, x) -> 0
2359 if (N0C && N0C->isNullValue())
2361 // fold (sra -1, x) -> -1
2362 if (N0C && N0C->isAllOnesValue())
2364 // fold (sra x, c >= size(x)) -> undef
2365 if (N1C && N1C->getValue() >= VT.getSizeInBits())
2366 return DAG.getNode(ISD::UNDEF, VT);
2367 // fold (sra x, 0) -> x
2368 if (N1C && N1C->isNullValue())
2370 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2372 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2373 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getValue();
2374 MVT EVT = MVT::getIntegerVT(LowBits);
2375 if (EVT.isSimple() && // TODO: remove when apint codegen support lands.
2376 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)))
2377 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
2378 DAG.getValueType(EVT));
2381 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
2382 if (N1C && N0.getOpcode() == ISD::SRA) {
2383 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2384 unsigned Sum = N1C->getValue() + C1->getValue();
2385 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1;
2386 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
2387 DAG.getConstant(Sum, N1C->getValueType(0)));
2391 // fold sra (shl X, m), result_size - n
2392 // -> (sign_extend (trunc (shl X, result_size - n - m))) for
2393 // result_size - n != m.
2394 // If truncate is free for the target sext(shl) is likely to result in better
2396 if (N0.getOpcode() == ISD::SHL) {
2397 // Get the two constanst of the shifts, CN0 = m, CN = n.
2398 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2400 // Determine what the truncate's result bitsize and type would be.
2401 unsigned VTValSize = VT.getSizeInBits();
2403 MVT::getIntegerVT(VTValSize - N1C->getValue());
2404 // Determine the residual right-shift amount.
2405 unsigned ShiftAmt = N1C->getValue() - N01C->getValue();
2407 // If the shift is not a no-op (in which case this should be just a sign
2408 // extend already), the truncated to type is legal, sign_extend is legal
2409 // on that type, and the the truncate to that type is both legal and free,
2410 // perform the transform.
2412 TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) &&
2413 TLI.isOperationLegal(ISD::TRUNCATE, VT) &&
2414 TLI.isTruncateFree(VT, TruncVT)) {
2416 SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy());
2417 SDValue Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt);
2418 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift);
2419 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc);
2424 // Simplify, based on bits shifted out of the LHS.
2425 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2426 return SDValue(N, 0);
2429 // If the sign bit is known to be zero, switch this to a SRL.
2430 if (DAG.SignBitIsZero(N0))
2431 return DAG.getNode(ISD::SRL, VT, N0, N1);
2433 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDValue();
2436 SDValue DAGCombiner::visitSRL(SDNode *N) {
2437 SDValue N0 = N->getOperand(0);
2438 SDValue N1 = N->getOperand(1);
2439 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2440 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2441 MVT VT = N0.getValueType();
2442 unsigned OpSizeInBits = VT.getSizeInBits();
2444 // fold (srl c1, c2) -> c1 >>u c2
2446 return DAG.getNode(ISD::SRL, VT, N0, N1);
2447 // fold (srl 0, x) -> 0
2448 if (N0C && N0C->isNullValue())
2450 // fold (srl x, c >= size(x)) -> undef
2451 if (N1C && N1C->getValue() >= OpSizeInBits)
2452 return DAG.getNode(ISD::UNDEF, VT);
2453 // fold (srl x, 0) -> x
2454 if (N1C && N1C->isNullValue())
2456 // if (srl x, c) is known to be zero, return 0
2457 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2458 APInt::getAllOnesValue(OpSizeInBits)))
2459 return DAG.getConstant(0, VT);
2461 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
2462 if (N1C && N0.getOpcode() == ISD::SRL &&
2463 N0.getOperand(1).getOpcode() == ISD::Constant) {
2464 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2465 uint64_t c2 = N1C->getValue();
2466 if (c1 + c2 > OpSizeInBits)
2467 return DAG.getConstant(0, VT);
2468 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
2469 DAG.getConstant(c1 + c2, N1.getValueType()));
2472 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2473 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2474 // Shifting in all undef bits?
2475 MVT SmallVT = N0.getOperand(0).getValueType();
2476 if (N1C->getValue() >= SmallVT.getSizeInBits())
2477 return DAG.getNode(ISD::UNDEF, VT);
2479 SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
2480 AddToWorkList(SmallShift.getNode());
2481 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
2484 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2485 // bit, which is unmodified by sra.
2486 if (N1C && N1C->getValue()+1 == VT.getSizeInBits()) {
2487 if (N0.getOpcode() == ISD::SRA)
2488 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
2491 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2492 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2493 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
2494 APInt KnownZero, KnownOne;
2495 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
2496 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2498 // If any of the input bits are KnownOne, then the input couldn't be all
2499 // zeros, thus the result of the srl will always be zero.
2500 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
2502 // If all of the bits input the to ctlz node are known to be zero, then
2503 // the result of the ctlz is "32" and the result of the shift is one.
2504 APInt UnknownBits = ~KnownZero & Mask;
2505 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2507 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2508 if ((UnknownBits & (UnknownBits-1)) == 0) {
2509 // Okay, we know that only that the single bit specified by UnknownBits
2510 // could be set on input to the CTLZ node. If this bit is set, the SRL
2511 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2512 // to an SRL,XOR pair, which is likely to simplify more.
2513 unsigned ShAmt = UnknownBits.countTrailingZeros();
2514 SDValue Op = N0.getOperand(0);
2516 Op = DAG.getNode(ISD::SRL, VT, Op,
2517 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
2518 AddToWorkList(Op.getNode());
2520 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
2524 // fold operands of srl based on knowledge that the low bits are not
2526 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2527 return SDValue(N, 0);
2529 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDValue();
2532 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
2533 SDValue N0 = N->getOperand(0);
2534 MVT VT = N->getValueType(0);
2536 // fold (ctlz c1) -> c2
2537 if (isa<ConstantSDNode>(N0))
2538 return DAG.getNode(ISD::CTLZ, VT, N0);
2542 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
2543 SDValue N0 = N->getOperand(0);
2544 MVT VT = N->getValueType(0);
2546 // fold (cttz c1) -> c2
2547 if (isa<ConstantSDNode>(N0))
2548 return DAG.getNode(ISD::CTTZ, VT, N0);
2552 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
2553 SDValue N0 = N->getOperand(0);
2554 MVT VT = N->getValueType(0);
2556 // fold (ctpop c1) -> c2
2557 if (isa<ConstantSDNode>(N0))
2558 return DAG.getNode(ISD::CTPOP, VT, N0);
2562 SDValue DAGCombiner::visitSELECT(SDNode *N) {
2563 SDValue N0 = N->getOperand(0);
2564 SDValue N1 = N->getOperand(1);
2565 SDValue N2 = N->getOperand(2);
2566 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2567 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2568 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2569 MVT VT = N->getValueType(0);
2570 MVT VT0 = N0.getValueType();
2572 // fold select C, X, X -> X
2575 // fold select true, X, Y -> X
2576 if (N0C && !N0C->isNullValue())
2578 // fold select false, X, Y -> Y
2579 if (N0C && N0C->isNullValue())
2581 // fold select C, 1, X -> C | X
2582 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
2583 return DAG.getNode(ISD::OR, VT, N0, N2);
2584 // fold select C, 0, 1 -> ~C
2585 if (VT.isInteger() && VT0.isInteger() &&
2586 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
2587 SDValue XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
2590 AddToWorkList(XORNode.getNode());
2592 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
2593 return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
2595 // fold select C, 0, X -> ~C & X
2596 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
2597 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2598 AddToWorkList(XORNode.getNode());
2599 return DAG.getNode(ISD::AND, VT, XORNode, N2);
2601 // fold select C, X, 1 -> ~C | X
2602 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
2603 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2604 AddToWorkList(XORNode.getNode());
2605 return DAG.getNode(ISD::OR, VT, XORNode, N1);
2607 // fold select C, X, 0 -> C & X
2608 // FIXME: this should check for C type == X type, not i1?
2609 if (VT == MVT::i1 && N2C && N2C->isNullValue())
2610 return DAG.getNode(ISD::AND, VT, N0, N1);
2611 // fold X ? X : Y --> X ? 1 : Y --> X | Y
2612 if (VT == MVT::i1 && N0 == N1)
2613 return DAG.getNode(ISD::OR, VT, N0, N2);
2614 // fold X ? Y : X --> X ? Y : 0 --> X & Y
2615 if (VT == MVT::i1 && N0 == N2)
2616 return DAG.getNode(ISD::AND, VT, N0, N1);
2618 // If we can fold this based on the true/false value, do so.
2619 if (SimplifySelectOps(N, N1, N2))
2620 return SDValue(N, 0); // Don't revisit N.
2622 // fold selects based on a setcc into other things, such as min/max/abs
2623 if (N0.getOpcode() == ISD::SETCC) {
2625 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2626 // having to say they don't support SELECT_CC on every type the DAG knows
2627 // about, since there is no way to mark an opcode illegal at all value types
2628 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
2629 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
2630 N1, N2, N0.getOperand(2));
2632 return SimplifySelect(N0, N1, N2);
2637 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
2638 SDValue N0 = N->getOperand(0);
2639 SDValue N1 = N->getOperand(1);
2640 SDValue N2 = N->getOperand(2);
2641 SDValue N3 = N->getOperand(3);
2642 SDValue N4 = N->getOperand(4);
2643 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2645 // fold select_cc lhs, rhs, x, x, cc -> x
2649 // Determine if the condition we're dealing with is constant
2650 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
2651 if (SCC.getNode()) AddToWorkList(SCC.getNode());
2653 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
2654 if (!SCCC->isNullValue())
2655 return N2; // cond always true -> true val
2657 return N3; // cond always false -> false val
2660 // Fold to a simpler select_cc
2661 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
2662 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
2663 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2666 // If we can fold this based on the true/false value, do so.
2667 if (SimplifySelectOps(N, N2, N3))
2668 return SDValue(N, 0); // Don't revisit N.
2670 // fold select_cc into other things, such as min/max/abs
2671 return SimplifySelectCC(N0, N1, N2, N3, CC);
2674 SDValue DAGCombiner::visitSETCC(SDNode *N) {
2675 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2676 cast<CondCodeSDNode>(N->getOperand(2))->get());
2679 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
2680 // "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))"
2681 // transformation. Returns true if extension are possible and the above
2682 // mentioned transformation is profitable.
2683 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
2685 SmallVector<SDNode*, 4> &ExtendNodes,
2686 TargetLowering &TLI) {
2687 bool HasCopyToRegUses = false;
2688 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
2689 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), UE = N0.getNode()->use_end();
2694 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
2695 if (User->getOpcode() == ISD::SETCC) {
2696 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
2697 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
2698 // Sign bits will be lost after a zext.
2701 for (unsigned i = 0; i != 2; ++i) {
2702 SDValue UseOp = User->getOperand(i);
2705 if (!isa<ConstantSDNode>(UseOp))
2710 ExtendNodes.push_back(User);
2712 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2713 SDValue UseOp = User->getOperand(i);
2715 // If truncate from extended type to original load type is free
2716 // on this target, then it's ok to extend a CopyToReg.
2717 if (isTruncFree && User->getOpcode() == ISD::CopyToReg)
2718 HasCopyToRegUses = true;
2726 if (HasCopyToRegUses) {
2727 bool BothLiveOut = false;
2728 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
2731 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2732 SDValue UseOp = User->getOperand(i);
2733 if (UseOp.getNode() == N && UseOp.getResNo() == 0) {
2740 // Both unextended and extended values are live out. There had better be
2741 // good a reason for the transformation.
2742 return ExtendNodes.size();
2747 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2748 SDValue N0 = N->getOperand(0);
2749 MVT VT = N->getValueType(0);
2751 // fold (sext c1) -> c1
2752 if (isa<ConstantSDNode>(N0))
2753 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
2755 // fold (sext (sext x)) -> (sext x)
2756 // fold (sext (aext x)) -> (sext x)
2757 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2758 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
2760 if (N0.getOpcode() == ISD::TRUNCATE) {
2761 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2762 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2763 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
2764 if (NarrowLoad.getNode()) {
2765 if (NarrowLoad.getNode() != N0.getNode())
2766 CombineTo(N0.getNode(), NarrowLoad);
2767 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
2770 // See if the value being truncated is already sign extended. If so, just
2771 // eliminate the trunc/sext pair.
2772 SDValue Op = N0.getOperand(0);
2773 unsigned OpBits = Op.getValueType().getSizeInBits();
2774 unsigned MidBits = N0.getValueType().getSizeInBits();
2775 unsigned DestBits = VT.getSizeInBits();
2776 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
2778 if (OpBits == DestBits) {
2779 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2780 // bits, it is already ready.
2781 if (NumSignBits > DestBits-MidBits)
2783 } else if (OpBits < DestBits) {
2784 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2785 // bits, just sext from i32.
2786 if (NumSignBits > OpBits-MidBits)
2787 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
2789 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2790 // bits, just truncate to i32.
2791 if (NumSignBits > OpBits-MidBits)
2792 return DAG.getNode(ISD::TRUNCATE, VT, Op);
2795 // fold (sext (truncate x)) -> (sextinreg x).
2796 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2797 N0.getValueType())) {
2798 if (Op.getValueType().bitsLT(VT))
2799 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2800 else if (Op.getValueType().bitsGT(VT))
2801 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2802 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
2803 DAG.getValueType(N0.getValueType()));
2807 // fold (sext (load x)) -> (sext (truncate (sextload x)))
2808 if (ISD::isNON_EXTLoad(N0.getNode()) &&
2809 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
2810 TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))) {
2811 bool DoXform = true;
2812 SmallVector<SDNode*, 4> SetCCs;
2813 if (!N0.hasOneUse())
2814 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
2816 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2817 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2818 LN0->getBasePtr(), LN0->getSrcValue(),
2819 LN0->getSrcValueOffset(),
2822 LN0->getAlignment());
2823 CombineTo(N, ExtLoad);
2824 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
2825 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
2826 // Extend SetCC uses if necessary.
2827 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
2828 SDNode *SetCC = SetCCs[i];
2829 SmallVector<SDValue, 4> Ops;
2830 for (unsigned j = 0; j != 2; ++j) {
2831 SDValue SOp = SetCC->getOperand(j);
2833 Ops.push_back(ExtLoad);
2835 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp));
2837 Ops.push_back(SetCC->getOperand(2));
2838 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
2839 &Ops[0], Ops.size()));
2841 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2845 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
2846 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
2847 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
2848 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
2849 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2850 MVT EVT = LN0->getMemoryVT();
2851 if ((!AfterLegalize && !LN0->isVolatile()) ||
2852 TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
2853 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2854 LN0->getBasePtr(), LN0->getSrcValue(),
2855 LN0->getSrcValueOffset(), EVT,
2857 LN0->getAlignment());
2858 CombineTo(N, ExtLoad);
2859 CombineTo(N0.getNode(), DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2860 ExtLoad.getValue(1));
2861 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2865 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
2866 if (N0.getOpcode() == ISD::SETCC) {
2868 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2869 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
2870 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2871 if (SCC.getNode()) return SCC;
2874 // fold (sext x) -> (zext x) if the sign bit is known zero.
2875 if ((!AfterLegalize || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
2876 DAG.SignBitIsZero(N0))
2877 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2882 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
2883 SDValue N0 = N->getOperand(0);
2884 MVT VT = N->getValueType(0);
2886 // fold (zext c1) -> c1
2887 if (isa<ConstantSDNode>(N0))
2888 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2889 // fold (zext (zext x)) -> (zext x)
2890 // fold (zext (aext x)) -> (zext x)
2891 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2892 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
2894 // fold (zext (truncate (load x))) -> (zext (smaller load x))
2895 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
2896 if (N0.getOpcode() == ISD::TRUNCATE) {
2897 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
2898 if (NarrowLoad.getNode()) {
2899 if (NarrowLoad.getNode() != N0.getNode())
2900 CombineTo(N0.getNode(), NarrowLoad);
2901 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
2905 // fold (zext (truncate x)) -> (and x, mask)
2906 if (N0.getOpcode() == ISD::TRUNCATE &&
2907 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
2908 SDValue Op = N0.getOperand(0);
2909 if (Op.getValueType().bitsLT(VT)) {
2910 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2911 } else if (Op.getValueType().bitsGT(VT)) {
2912 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2914 return DAG.getZeroExtendInReg(Op, N0.getValueType());
2917 // fold (zext (and (trunc x), cst)) -> (and x, cst).
2918 if (N0.getOpcode() == ISD::AND &&
2919 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2920 N0.getOperand(1).getOpcode() == ISD::Constant) {
2921 SDValue X = N0.getOperand(0).getOperand(0);
2922 if (X.getValueType().bitsLT(VT)) {
2923 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2924 } else if (X.getValueType().bitsGT(VT)) {
2925 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2927 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2928 Mask.zext(VT.getSizeInBits());
2929 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2932 // fold (zext (load x)) -> (zext (truncate (zextload x)))
2933 if (ISD::isNON_EXTLoad(N0.getNode()) &&
2934 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
2935 TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2936 bool DoXform = true;
2937 SmallVector<SDNode*, 4> SetCCs;
2938 if (!N0.hasOneUse())
2939 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
2941 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2942 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2943 LN0->getBasePtr(), LN0->getSrcValue(),
2944 LN0->getSrcValueOffset(),
2947 LN0->getAlignment());
2948 CombineTo(N, ExtLoad);
2949 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
2950 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
2951 // Extend SetCC uses if necessary.
2952 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
2953 SDNode *SetCC = SetCCs[i];
2954 SmallVector<SDValue, 4> Ops;
2955 for (unsigned j = 0; j != 2; ++j) {
2956 SDValue SOp = SetCC->getOperand(j);
2958 Ops.push_back(ExtLoad);
2960 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp));
2962 Ops.push_back(SetCC->getOperand(2));
2963 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0),
2964 &Ops[0], Ops.size()));
2966 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2970 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2971 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2972 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
2973 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
2974 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2975 MVT EVT = LN0->getMemoryVT();
2976 if ((!AfterLegalize && !LN0->isVolatile()) ||
2977 TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT)) {
2978 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2979 LN0->getBasePtr(), LN0->getSrcValue(),
2980 LN0->getSrcValueOffset(), EVT,
2982 LN0->getAlignment());
2983 CombineTo(N, ExtLoad);
2984 CombineTo(N0.getNode(), DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2985 ExtLoad.getValue(1));
2986 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2990 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2991 if (N0.getOpcode() == ISD::SETCC) {
2993 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2994 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2995 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2996 if (SCC.getNode()) return SCC;
3002 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
3003 SDValue N0 = N->getOperand(0);
3004 MVT VT = N->getValueType(0);
3006 // fold (aext c1) -> c1
3007 if (isa<ConstantSDNode>(N0))
3008 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
3009 // fold (aext (aext x)) -> (aext x)
3010 // fold (aext (zext x)) -> (zext x)
3011 // fold (aext (sext x)) -> (sext x)
3012 if (N0.getOpcode() == ISD::ANY_EXTEND ||
3013 N0.getOpcode() == ISD::ZERO_EXTEND ||
3014 N0.getOpcode() == ISD::SIGN_EXTEND)
3015 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
3017 // fold (aext (truncate (load x))) -> (aext (smaller load x))
3018 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
3019 if (N0.getOpcode() == ISD::TRUNCATE) {
3020 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3021 if (NarrowLoad.getNode()) {
3022 if (NarrowLoad.getNode() != N0.getNode())
3023 CombineTo(N0.getNode(), NarrowLoad);
3024 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
3028 // fold (aext (truncate x))
3029 if (N0.getOpcode() == ISD::TRUNCATE) {
3030 SDValue TruncOp = N0.getOperand(0);
3031 if (TruncOp.getValueType() == VT)
3032 return TruncOp; // x iff x size == zext size.
3033 if (TruncOp.getValueType().bitsGT(VT))
3034 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
3035 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
3038 // fold (aext (and (trunc x), cst)) -> (and x, cst).
3039 if (N0.getOpcode() == ISD::AND &&
3040 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3041 N0.getOperand(1).getOpcode() == ISD::Constant) {
3042 SDValue X = N0.getOperand(0).getOperand(0);
3043 if (X.getValueType().bitsLT(VT)) {
3044 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
3045 } else if (X.getValueType().bitsGT(VT)) {
3046 X = DAG.getNode(ISD::TRUNCATE, VT, X);
3048 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3049 Mask.zext(VT.getSizeInBits());
3050 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
3053 // fold (aext (load x)) -> (aext (truncate (extload x)))
3054 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
3055 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
3056 TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
3057 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3058 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
3059 LN0->getBasePtr(), LN0->getSrcValue(),
3060 LN0->getSrcValueOffset(),
3063 LN0->getAlignment());
3064 CombineTo(N, ExtLoad);
3065 // Redirect any chain users to the new load.
3066 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1),
3067 SDValue(ExtLoad.getNode(), 1));
3068 // If any node needs the original loaded value, recompute it.
3069 if (!LN0->use_empty())
3070 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
3071 ExtLoad.getValue(1));
3072 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3075 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
3076 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
3077 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
3078 if (N0.getOpcode() == ISD::LOAD &&
3079 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3081 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3082 MVT EVT = LN0->getMemoryVT();
3083 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
3084 LN0->getChain(), LN0->getBasePtr(),
3086 LN0->getSrcValueOffset(), EVT,
3088 LN0->getAlignment());
3089 CombineTo(N, ExtLoad);
3090 CombineTo(N0.getNode(),
3091 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
3092 ExtLoad.getValue(1));
3093 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3096 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3097 if (N0.getOpcode() == ISD::SETCC) {
3099 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
3100 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3101 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3109 /// GetDemandedBits - See if the specified operand can be simplified with the
3110 /// knowledge that only the bits specified by Mask are used. If so, return the
3111 /// simpler operand, otherwise return a null SDValue.
3112 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
3113 switch (V.getOpcode()) {
3117 // If the LHS or RHS don't contribute bits to the or, drop them.
3118 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
3119 return V.getOperand(1);
3120 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
3121 return V.getOperand(0);
3124 // Only look at single-use SRLs.
3125 if (!V.getNode()->hasOneUse())
3127 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
3128 // See if we can recursively simplify the LHS.
3129 unsigned Amt = RHSC->getValue();
3130 APInt NewMask = Mask << Amt;
3131 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
3132 if (SimplifyLHS.getNode()) {
3133 return DAG.getNode(ISD::SRL, V.getValueType(),
3134 SimplifyLHS, V.getOperand(1));
3141 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
3142 /// bits and then truncated to a narrower type and where N is a multiple
3143 /// of number of bits of the narrower type, transform it to a narrower load
3144 /// from address + N / num of bits of new type. If the result is to be
3145 /// extended, also fold the extension to form a extending load.
3146 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
3147 unsigned Opc = N->getOpcode();
3148 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
3149 SDValue N0 = N->getOperand(0);
3150 MVT VT = N->getValueType(0);
3151 MVT EVT = N->getValueType(0);
3153 // This transformation isn't valid for vector loads.
3157 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
3159 if (Opc == ISD::SIGN_EXTEND_INREG) {
3160 ExtType = ISD::SEXTLOAD;
3161 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3162 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
3166 unsigned EVTBits = EVT.getSizeInBits();
3168 bool CombineSRL = false;
3169 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
3170 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3171 ShAmt = N01->getValue();
3172 // Is the shift amount a multiple of size of VT?
3173 if ((ShAmt & (EVTBits-1)) == 0) {
3174 N0 = N0.getOperand(0);
3175 if (N0.getValueType().getSizeInBits() <= EVTBits)
3182 // Do not generate loads of non-round integer types since these can
3183 // be expensive (and would be wrong if the type is not byte sized).
3184 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && VT.isRound() &&
3185 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
3186 // Do not change the width of a volatile load.
3187 !cast<LoadSDNode>(N0)->isVolatile()) {
3188 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3189 MVT PtrType = N0.getOperand(1).getValueType();
3190 // For big endian targets, we need to adjust the offset to the pointer to
3191 // load the correct bytes.
3192 if (TLI.isBigEndian()) {
3193 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
3194 unsigned EVTStoreBits = EVT.getStoreSizeInBits();
3195 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
3197 uint64_t PtrOff = ShAmt / 8;
3198 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
3199 SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
3200 DAG.getConstant(PtrOff, PtrType));
3201 AddToWorkList(NewPtr.getNode());
3202 SDValue Load = (ExtType == ISD::NON_EXTLOAD)
3203 ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
3204 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3205 LN0->isVolatile(), NewAlign)
3206 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
3207 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3208 EVT, LN0->isVolatile(), NewAlign);
3211 WorkListRemover DeadNodes(*this);
3212 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
3214 CombineTo(N->getOperand(0).getNode(), Load);
3216 CombineTo(N0.getNode(), Load, Load.getValue(1));
3218 if (Opc == ISD::SIGN_EXTEND_INREG)
3219 return DAG.getNode(Opc, VT, Load, N->getOperand(1));
3221 return DAG.getNode(Opc, VT, Load);
3223 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3230 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
3231 SDValue N0 = N->getOperand(0);
3232 SDValue N1 = N->getOperand(1);
3233 MVT VT = N->getValueType(0);
3234 MVT EVT = cast<VTSDNode>(N1)->getVT();
3235 unsigned VTBits = VT.getSizeInBits();
3236 unsigned EVTBits = EVT.getSizeInBits();
3238 // fold (sext_in_reg c1) -> c1
3239 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
3240 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
3242 // If the input is already sign extended, just drop the extension.
3243 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1)
3246 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
3247 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3248 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
3249 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
3252 // fold (sext_in_reg (sext x)) -> (sext x)
3253 // fold (sext_in_reg (aext x)) -> (sext x)
3254 // if x is small enough.
3255 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
3256 SDValue N00 = N0.getOperand(0);
3257 if (N00.getValueType().getSizeInBits() < EVTBits)
3258 return DAG.getNode(ISD::SIGN_EXTEND, VT, N00, N1);
3261 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
3262 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
3263 return DAG.getZeroExtendInReg(N0, EVT);
3265 // fold operands of sext_in_reg based on knowledge that the top bits are not
3267 if (SimplifyDemandedBits(SDValue(N, 0)))
3268 return SDValue(N, 0);
3270 // fold (sext_in_reg (load x)) -> (smaller sextload x)
3271 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
3272 SDValue NarrowLoad = ReduceLoadWidth(N);
3273 if (NarrowLoad.getNode())
3276 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
3277 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
3278 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
3279 if (N0.getOpcode() == ISD::SRL) {
3280 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
3281 if (ShAmt->getValue()+EVTBits <= VT.getSizeInBits()) {
3282 // We can turn this into an SRA iff the input to the SRL is already sign
3284 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
3285 if (VT.getSizeInBits()-(ShAmt->getValue()+EVTBits) < InSignBits)
3286 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
3290 // fold (sext_inreg (extload x)) -> (sextload x)
3291 if (ISD::isEXTLoad(N0.getNode()) &&
3292 ISD::isUNINDEXEDLoad(N0.getNode()) &&
3293 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3294 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
3295 TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
3296 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3297 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
3298 LN0->getBasePtr(), LN0->getSrcValue(),
3299 LN0->getSrcValueOffset(), EVT,
3301 LN0->getAlignment());
3302 CombineTo(N, ExtLoad);
3303 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3304 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3306 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
3307 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3309 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3310 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
3311 TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
3312 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3313 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
3314 LN0->getBasePtr(), LN0->getSrcValue(),
3315 LN0->getSrcValueOffset(), EVT,
3317 LN0->getAlignment());
3318 CombineTo(N, ExtLoad);
3319 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3320 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3325 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
3326 SDValue N0 = N->getOperand(0);
3327 MVT VT = N->getValueType(0);
3330 if (N0.getValueType() == N->getValueType(0))
3332 // fold (truncate c1) -> c1
3333 if (isa<ConstantSDNode>(N0))
3334 return DAG.getNode(ISD::TRUNCATE, VT, N0);
3335 // fold (truncate (truncate x)) -> (truncate x)
3336 if (N0.getOpcode() == ISD::TRUNCATE)
3337 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
3338 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
3339 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
3340 N0.getOpcode() == ISD::ANY_EXTEND) {
3341 if (N0.getOperand(0).getValueType().bitsLT(VT))
3342 // if the source is smaller than the dest, we still need an extend
3343 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
3344 else if (N0.getOperand(0).getValueType().bitsGT(VT))
3345 // if the source is larger than the dest, than we just need the truncate
3346 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
3348 // if the source and dest are the same type, we can drop both the extend
3350 return N0.getOperand(0);
3353 // See if we can simplify the input to this truncate through knowledge that
3354 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
3357 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
3358 VT.getSizeInBits()));
3359 if (Shorter.getNode())
3360 return DAG.getNode(ISD::TRUNCATE, VT, Shorter);
3362 // fold (truncate (load x)) -> (smaller load x)
3363 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
3364 return ReduceLoadWidth(N);
3367 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
3368 SDValue Elt = N->getOperand(i);
3369 if (Elt.getOpcode() != ISD::MERGE_VALUES)
3370 return Elt.getNode();
3371 return Elt.getOperand(Elt.getResNo()).getNode();
3374 /// CombineConsecutiveLoads - build_pair (load, load) -> load
3375 /// if load locations are consecutive.
3376 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) {
3377 assert(N->getOpcode() == ISD::BUILD_PAIR);
3379 SDNode *LD1 = getBuildPairElt(N, 0);
3380 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
3382 MVT LD1VT = LD1->getValueType(0);
3383 SDNode *LD2 = getBuildPairElt(N, 1);
3384 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3385 if (ISD::isNON_EXTLoad(LD2) &&
3387 // If both are volatile this would reduce the number of volatile loads.
3388 // If one is volatile it might be ok, but play conservative and bail out.
3389 !cast<LoadSDNode>(LD1)->isVolatile() &&
3390 !cast<LoadSDNode>(LD2)->isVolatile() &&
3391 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) {
3392 LoadSDNode *LD = cast<LoadSDNode>(LD1);
3393 unsigned Align = LD->getAlignment();
3394 unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
3395 getABITypeAlignment(VT.getTypeForMVT());
3396 if (NewAlign <= Align &&
3397 (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT)))
3398 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(),
3399 LD->getSrcValue(), LD->getSrcValueOffset(),
3405 SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
3406 SDValue N0 = N->getOperand(0);
3407 MVT VT = N->getValueType(0);
3409 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
3410 // Only do this before legalize, since afterward the target may be depending
3411 // on the bitconvert.
3412 // First check to see if this is all constant.
3413 if (!AfterLegalize &&
3414 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
3416 bool isSimple = true;
3417 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3418 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3419 N0.getOperand(i).getOpcode() != ISD::Constant &&
3420 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3425 MVT DestEltVT = N->getValueType(0).getVectorElementType();
3426 assert(!DestEltVT.isVector() &&
3427 "Element type of vector ValueType must not be vector!");
3429 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT);
3433 // If the input is a constant, let Val fold it.
3434 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
3435 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
3436 if (Res.getNode() != N) return Res;
3439 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
3440 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3442 // fold (conv (load x)) -> (load (conv*)x)
3443 // If the resultant load doesn't need a higher alignment than the original!
3444 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
3445 // Do not change the width of a volatile load.
3446 !cast<LoadSDNode>(N0)->isVolatile() &&
3447 (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) {
3448 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3449 unsigned Align = TLI.getTargetMachine().getTargetData()->
3450 getABITypeAlignment(VT.getTypeForMVT());
3451 unsigned OrigAlign = LN0->getAlignment();
3452 if (Align <= OrigAlign) {
3453 SDValue Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
3454 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3455 LN0->isVolatile(), OrigAlign);
3457 CombineTo(N0.getNode(), DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
3463 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit)
3464 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit)
3465 // This often reduces constant pool loads.
3466 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
3467 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
3468 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3469 AddToWorkList(NewConv.getNode());
3471 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3472 if (N0.getOpcode() == ISD::FNEG)
3473 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT));
3474 assert(N0.getOpcode() == ISD::FABS);
3475 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT));
3478 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign'
3479 // Note that we don't handle copysign(x,cst) because this can always be folded
3480 // to an fneg or fabs.
3481 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
3482 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
3483 VT.isInteger() && !VT.isVector()) {
3484 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
3485 SDValue X = DAG.getNode(ISD::BIT_CONVERT,
3486 MVT::getIntegerVT(OrigXWidth),
3488 AddToWorkList(X.getNode());
3490 // If X has a different width than the result/lhs, sext it or truncate it.
3491 unsigned VTWidth = VT.getSizeInBits();
3492 if (OrigXWidth < VTWidth) {
3493 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X);
3494 AddToWorkList(X.getNode());
3495 } else if (OrigXWidth > VTWidth) {
3496 // To get the sign bit in the right place, we have to shift it right
3497 // before truncating.
3498 X = DAG.getNode(ISD::SRL, X.getValueType(), X,
3499 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
3500 AddToWorkList(X.getNode());
3501 X = DAG.getNode(ISD::TRUNCATE, VT, X);
3502 AddToWorkList(X.getNode());
3505 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3506 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT));
3507 AddToWorkList(X.getNode());
3509 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3510 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT));
3511 AddToWorkList(Cst.getNode());
3513 return DAG.getNode(ISD::OR, VT, X, Cst);
3516 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
3517 if (N0.getOpcode() == ISD::BUILD_PAIR) {
3518 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
3519 if (CombineLD.getNode())
3526 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
3527 MVT VT = N->getValueType(0);
3528 return CombineConsecutiveLoads(N, VT);
3531 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
3532 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
3533 /// destination element value type.
3534 SDValue DAGCombiner::
3535 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) {
3536 MVT SrcEltVT = BV->getOperand(0).getValueType();
3538 // If this is already the right type, we're done.
3539 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
3541 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
3542 unsigned DstBitSize = DstEltVT.getSizeInBits();
3544 // If this is a conversion of N elements of one type to N elements of another
3545 // type, convert each element. This handles FP<->INT cases.
3546 if (SrcBitSize == DstBitSize) {
3547 SmallVector<SDValue, 8> Ops;
3548 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3549 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
3550 AddToWorkList(Ops.back().getNode());
3552 MVT VT = MVT::getVectorVT(DstEltVT,
3553 BV->getValueType(0).getVectorNumElements());
3554 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3557 // Otherwise, we're growing or shrinking the elements. To avoid having to
3558 // handle annoying details of growing/shrinking FP values, we convert them to
3560 if (SrcEltVT.isFloatingPoint()) {
3561 // Convert the input float vector to a int vector where the elements are the
3563 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
3564 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits());
3565 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
3569 // Now we know the input is an integer vector. If the output is a FP type,
3570 // convert to integer first, then to FP of the right size.
3571 if (DstEltVT.isFloatingPoint()) {
3572 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
3573 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits());
3574 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
3576 // Next, convert to FP elements of the same size.
3577 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
3580 // Okay, we know the src/dst types are both integers of differing types.
3581 // Handling growing first.
3582 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
3583 if (SrcBitSize < DstBitSize) {
3584 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
3586 SmallVector<SDValue, 8> Ops;
3587 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
3588 i += NumInputsPerOutput) {
3589 bool isLE = TLI.isLittleEndian();
3590 APInt NewBits = APInt(DstBitSize, 0);
3591 bool EltIsUndef = true;
3592 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
3593 // Shift the previously computed bits over.
3594 NewBits <<= SrcBitSize;
3595 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
3596 if (Op.getOpcode() == ISD::UNDEF) continue;
3600 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize);
3604 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3606 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
3609 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size());
3610 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3613 // Finally, this must be the case where we are shrinking elements: each input
3614 // turns into multiple outputs.
3615 bool isS2V = ISD::isScalarToVector(BV);
3616 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3617 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands());
3618 SmallVector<SDValue, 8> Ops;
3619 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3620 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3621 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3622 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3625 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue();
3626 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3627 APInt ThisVal = APInt(OpVal).trunc(DstBitSize);
3628 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3629 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal)
3630 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
3631 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]);
3632 OpVal = OpVal.lshr(DstBitSize);
3635 // For big endian targets, swap the order of the pieces of each element.
3636 if (TLI.isBigEndian())
3637 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3639 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3644 SDValue DAGCombiner::visitFADD(SDNode *N) {
3645 SDValue N0 = N->getOperand(0);
3646 SDValue N1 = N->getOperand(1);
3647 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3648 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3649 MVT VT = N->getValueType(0);
3652 if (VT.isVector()) {
3653 SDValue FoldedVOp = SimplifyVBinOp(N);
3654 if (FoldedVOp.getNode()) return FoldedVOp;
3657 // fold (fadd c1, c2) -> c1+c2
3658 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3659 return DAG.getNode(ISD::FADD, VT, N0, N1);
3660 // canonicalize constant to RHS
3661 if (N0CFP && !N1CFP)
3662 return DAG.getNode(ISD::FADD, VT, N1, N0);
3663 // fold (A + (-B)) -> A-B
3664 if (isNegatibleForFree(N1, AfterLegalize) == 2)
3665 return DAG.getNode(ISD::FSUB, VT, N0,
3666 GetNegatedExpression(N1, DAG, AfterLegalize));
3667 // fold ((-A) + B) -> B-A
3668 if (isNegatibleForFree(N0, AfterLegalize) == 2)
3669 return DAG.getNode(ISD::FSUB, VT, N1,
3670 GetNegatedExpression(N0, DAG, AfterLegalize));
3672 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3673 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3674 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3675 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
3676 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
3681 SDValue DAGCombiner::visitFSUB(SDNode *N) {
3682 SDValue N0 = N->getOperand(0);
3683 SDValue N1 = N->getOperand(1);
3684 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3685 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3686 MVT VT = N->getValueType(0);
3689 if (VT.isVector()) {
3690 SDValue FoldedVOp = SimplifyVBinOp(N);
3691 if (FoldedVOp.getNode()) return FoldedVOp;
3694 // fold (fsub c1, c2) -> c1-c2
3695 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3696 return DAG.getNode(ISD::FSUB, VT, N0, N1);
3698 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
3699 if (isNegatibleForFree(N1, AfterLegalize))
3700 return GetNegatedExpression(N1, DAG, AfterLegalize);
3701 return DAG.getNode(ISD::FNEG, VT, N1);
3703 // fold (A-(-B)) -> A+B
3704 if (isNegatibleForFree(N1, AfterLegalize))
3705 return DAG.getNode(ISD::FADD, VT, N0,
3706 GetNegatedExpression(N1, DAG, AfterLegalize));
3711 SDValue DAGCombiner::visitFMUL(SDNode *N) {
3712 SDValue N0 = N->getOperand(0);
3713 SDValue N1 = N->getOperand(1);
3714 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3715 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3716 MVT VT = N->getValueType(0);
3719 if (VT.isVector()) {
3720 SDValue FoldedVOp = SimplifyVBinOp(N);
3721 if (FoldedVOp.getNode()) return FoldedVOp;
3724 // fold (fmul c1, c2) -> c1*c2
3725 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3726 return DAG.getNode(ISD::FMUL, VT, N0, N1);
3727 // canonicalize constant to RHS
3728 if (N0CFP && !N1CFP)
3729 return DAG.getNode(ISD::FMUL, VT, N1, N0);
3730 // fold (fmul X, 2.0) -> (fadd X, X)
3731 if (N1CFP && N1CFP->isExactlyValue(+2.0))
3732 return DAG.getNode(ISD::FADD, VT, N0, N0);
3733 // fold (fmul X, -1.0) -> (fneg X)
3734 if (N1CFP && N1CFP->isExactlyValue(-1.0))
3735 return DAG.getNode(ISD::FNEG, VT, N0);
3738 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) {
3739 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) {
3740 // Both can be negated for free, check to see if at least one is cheaper
3742 if (LHSNeg == 2 || RHSNeg == 2)
3743 return DAG.getNode(ISD::FMUL, VT,
3744 GetNegatedExpression(N0, DAG, AfterLegalize),
3745 GetNegatedExpression(N1, DAG, AfterLegalize));
3749 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
3750 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
3751 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3752 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
3753 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
3758 SDValue DAGCombiner::visitFDIV(SDNode *N) {
3759 SDValue N0 = N->getOperand(0);
3760 SDValue N1 = N->getOperand(1);
3761 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3762 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3763 MVT VT = N->getValueType(0);
3766 if (VT.isVector()) {
3767 SDValue FoldedVOp = SimplifyVBinOp(N);
3768 if (FoldedVOp.getNode()) return FoldedVOp;
3771 // fold (fdiv c1, c2) -> c1/c2
3772 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3773 return DAG.getNode(ISD::FDIV, VT, N0, N1);
3777 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) {
3778 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) {
3779 // Both can be negated for free, check to see if at least one is cheaper
3781 if (LHSNeg == 2 || RHSNeg == 2)
3782 return DAG.getNode(ISD::FDIV, VT,
3783 GetNegatedExpression(N0, DAG, AfterLegalize),
3784 GetNegatedExpression(N1, DAG, AfterLegalize));
3791 SDValue DAGCombiner::visitFREM(SDNode *N) {
3792 SDValue N0 = N->getOperand(0);
3793 SDValue N1 = N->getOperand(1);
3794 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3795 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3796 MVT VT = N->getValueType(0);
3798 // fold (frem c1, c2) -> fmod(c1,c2)
3799 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3800 return DAG.getNode(ISD::FREM, VT, N0, N1);
3805 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
3806 SDValue N0 = N->getOperand(0);
3807 SDValue N1 = N->getOperand(1);
3808 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3809 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3810 MVT VT = N->getValueType(0);
3812 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
3813 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
3816 const APFloat& V = N1CFP->getValueAPF();
3817 // copysign(x, c1) -> fabs(x) iff ispos(c1)
3818 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
3819 if (!V.isNegative())
3820 return DAG.getNode(ISD::FABS, VT, N0);
3822 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
3825 // copysign(fabs(x), y) -> copysign(x, y)
3826 // copysign(fneg(x), y) -> copysign(x, y)
3827 // copysign(copysign(x,z), y) -> copysign(x, y)
3828 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
3829 N0.getOpcode() == ISD::FCOPYSIGN)
3830 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
3832 // copysign(x, abs(y)) -> abs(x)
3833 if (N1.getOpcode() == ISD::FABS)
3834 return DAG.getNode(ISD::FABS, VT, N0);
3836 // copysign(x, copysign(y,z)) -> copysign(x, z)
3837 if (N1.getOpcode() == ISD::FCOPYSIGN)
3838 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
3840 // copysign(x, fp_extend(y)) -> copysign(x, y)
3841 // copysign(x, fp_round(y)) -> copysign(x, y)
3842 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
3843 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
3850 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
3851 SDValue N0 = N->getOperand(0);
3852 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3853 MVT VT = N->getValueType(0);
3854 MVT OpVT = N0.getValueType();
3856 // fold (sint_to_fp c1) -> c1fp
3857 if (N0C && OpVT != MVT::ppcf128)
3858 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
3860 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
3861 // but UINT_TO_FP is legal on this target, try to convert.
3862 if (!TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT) &&
3863 TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT)) {
3864 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
3865 if (DAG.SignBitIsZero(N0))
3866 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
3873 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
3874 SDValue N0 = N->getOperand(0);
3875 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3876 MVT VT = N->getValueType(0);
3877 MVT OpVT = N0.getValueType();
3879 // fold (uint_to_fp c1) -> c1fp
3880 if (N0C && OpVT != MVT::ppcf128)
3881 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
3883 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
3884 // but SINT_TO_FP is legal on this target, try to convert.
3885 if (!TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT) &&
3886 TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT)) {
3887 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
3888 if (DAG.SignBitIsZero(N0))
3889 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
3895 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
3896 SDValue N0 = N->getOperand(0);
3897 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3898 MVT VT = N->getValueType(0);
3900 // fold (fp_to_sint c1fp) -> c1
3902 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
3906 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
3907 SDValue N0 = N->getOperand(0);
3908 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3909 MVT VT = N->getValueType(0);
3911 // fold (fp_to_uint c1fp) -> c1
3912 if (N0CFP && VT != MVT::ppcf128)
3913 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
3917 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
3918 SDValue N0 = N->getOperand(0);
3919 SDValue N1 = N->getOperand(1);
3920 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3921 MVT VT = N->getValueType(0);
3923 // fold (fp_round c1fp) -> c1fp
3924 if (N0CFP && N0.getValueType() != MVT::ppcf128)
3925 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1);
3927 // fold (fp_round (fp_extend x)) -> x
3928 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
3929 return N0.getOperand(0);
3931 // fold (fp_round (fp_round x)) -> (fp_round x)
3932 if (N0.getOpcode() == ISD::FP_ROUND) {
3933 // This is a value preserving truncation if both round's are.
3934 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
3935 N0.getNode()->getConstantOperandVal(1) == 1;
3936 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0),
3937 DAG.getIntPtrConstant(IsTrunc));
3940 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
3941 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
3942 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1);
3943 AddToWorkList(Tmp.getNode());
3944 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
3950 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
3951 SDValue N0 = N->getOperand(0);
3952 MVT VT = N->getValueType(0);
3953 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3954 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3956 // fold (fp_round_inreg c1fp) -> c1fp
3958 SDValue Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT);
3959 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
3964 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
3965 SDValue N0 = N->getOperand(0);
3966 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3967 MVT VT = N->getValueType(0);
3969 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
3970 if (N->hasOneUse() &&
3971 N->use_begin().getUse().getSDValue().getOpcode() == ISD::FP_ROUND)
3974 // fold (fp_extend c1fp) -> c1fp
3975 if (N0CFP && VT != MVT::ppcf128)
3976 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
3978 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
3980 if (N0.getOpcode() == ISD::FP_ROUND && N0.getNode()->getConstantOperandVal(1) == 1){
3981 SDValue In = N0.getOperand(0);
3982 if (In.getValueType() == VT) return In;
3983 if (VT.bitsLT(In.getValueType()))
3984 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1));
3985 return DAG.getNode(ISD::FP_EXTEND, VT, In);
3988 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
3989 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
3990 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
3991 TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
3992 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3993 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
3994 LN0->getBasePtr(), LN0->getSrcValue(),
3995 LN0->getSrcValueOffset(),
3998 LN0->getAlignment());
3999 CombineTo(N, ExtLoad);
4000 CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad,
4001 DAG.getIntPtrConstant(1)),
4002 ExtLoad.getValue(1));
4003 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4009 SDValue DAGCombiner::visitFNEG(SDNode *N) {
4010 SDValue N0 = N->getOperand(0);
4012 if (isNegatibleForFree(N0, AfterLegalize))
4013 return GetNegatedExpression(N0, DAG, AfterLegalize);
4015 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
4016 // constant pool values.
4017 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
4018 N0.getOperand(0).getValueType().isInteger() &&
4019 !N0.getOperand(0).getValueType().isVector()) {
4020 SDValue Int = N0.getOperand(0);
4021 MVT IntVT = Int.getValueType();
4022 if (IntVT.isInteger() && !IntVT.isVector()) {
4023 Int = DAG.getNode(ISD::XOR, IntVT, Int,
4024 DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT));
4025 AddToWorkList(Int.getNode());
4026 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
4033 SDValue DAGCombiner::visitFABS(SDNode *N) {
4034 SDValue N0 = N->getOperand(0);
4035 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4036 MVT VT = N->getValueType(0);
4038 // fold (fabs c1) -> fabs(c1)
4039 if (N0CFP && VT != MVT::ppcf128)
4040 return DAG.getNode(ISD::FABS, VT, N0);
4041 // fold (fabs (fabs x)) -> (fabs x)
4042 if (N0.getOpcode() == ISD::FABS)
4043 return N->getOperand(0);
4044 // fold (fabs (fneg x)) -> (fabs x)
4045 // fold (fabs (fcopysign x, y)) -> (fabs x)
4046 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
4047 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
4049 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
4050 // constant pool values.
4051 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
4052 N0.getOperand(0).getValueType().isInteger() &&
4053 !N0.getOperand(0).getValueType().isVector()) {
4054 SDValue Int = N0.getOperand(0);
4055 MVT IntVT = Int.getValueType();
4056 if (IntVT.isInteger() && !IntVT.isVector()) {
4057 Int = DAG.getNode(ISD::AND, IntVT, Int,
4058 DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT));
4059 AddToWorkList(Int.getNode());
4060 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
4067 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
4068 SDValue Chain = N->getOperand(0);
4069 SDValue N1 = N->getOperand(1);
4070 SDValue N2 = N->getOperand(2);
4071 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4073 // never taken branch, fold to chain
4074 if (N1C && N1C->isNullValue())
4076 // unconditional branch
4077 if (N1C && N1C->getAPIntValue() == 1)
4078 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
4079 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
4081 if (N1.getOpcode() == ISD::SETCC &&
4082 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
4083 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
4084 N1.getOperand(0), N1.getOperand(1), N2);
4089 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
4091 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
4092 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
4093 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
4095 // Use SimplifySetCC to simplify SETCC's.
4096 SDValue Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
4097 if (Simp.getNode()) AddToWorkList(Simp.getNode());
4099 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode());
4101 // fold br_cc true, dest -> br dest (unconditional branch)
4102 if (SCCC && !SCCC->isNullValue())
4103 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
4105 // fold br_cc false, dest -> unconditional fall through
4106 if (SCCC && SCCC->isNullValue())
4107 return N->getOperand(0);
4109 // fold to a simpler setcc
4110 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
4111 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
4112 Simp.getOperand(2), Simp.getOperand(0),
4113 Simp.getOperand(1), N->getOperand(4));
4118 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
4119 /// pre-indexed load / store when the base pointer is an add or subtract
4120 /// and it has other uses besides the load / store. After the
4121 /// transformation, the new indexed load / store has effectively folded
4122 /// the add / subtract in and all of its other uses are redirected to the
4123 /// new load / store.
4124 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
4131 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4132 if (LD->isIndexed())
4134 VT = LD->getMemoryVT();
4135 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
4136 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
4138 Ptr = LD->getBasePtr();
4139 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4140 if (ST->isIndexed())
4142 VT = ST->getMemoryVT();
4143 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
4144 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
4146 Ptr = ST->getBasePtr();
4151 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
4152 // out. There is no reason to make this a preinc/predec.
4153 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
4154 Ptr.getNode()->hasOneUse())
4157 // Ask the target to do addressing mode selection.
4160 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4161 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
4163 // Don't create a indexed load / store with zero offset.
4164 if (isa<ConstantSDNode>(Offset) &&
4165 cast<ConstantSDNode>(Offset)->isNullValue())
4168 // Try turning it into a pre-indexed load / store except when:
4169 // 1) The new base ptr is a frame index.
4170 // 2) If N is a store and the new base ptr is either the same as or is a
4171 // predecessor of the value being stored.
4172 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
4173 // that would create a cycle.
4174 // 4) All uses are load / store ops that use it as old base ptr.
4176 // Check #1. Preinc'ing a frame index would require copying the stack pointer
4177 // (plus the implicit offset) to a register to preinc anyway.
4178 if (isa<FrameIndexSDNode>(BasePtr))
4183 SDValue Val = cast<StoreSDNode>(N)->getValue();
4184 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
4188 // Now check for #3 and #4.
4189 bool RealUse = false;
4190 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4191 E = Ptr.getNode()->use_end(); I != E; ++I) {
4195 if (Use->isPredecessorOf(N))
4198 if (!((Use->getOpcode() == ISD::LOAD &&
4199 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
4200 (Use->getOpcode() == ISD::STORE &&
4201 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
4209 Result = DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM);
4211 Result = DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM);
4214 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
4215 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
4217 WorkListRemover DeadNodes(*this);
4219 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4221 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4224 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
4228 // Finally, since the node is now dead, remove it from the graph.
4231 // Replace the uses of Ptr with uses of the updated base value.
4232 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
4234 removeFromWorkList(Ptr.getNode());
4235 DAG.DeleteNode(Ptr.getNode());
4240 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
4241 /// add / sub of the base pointer node into a post-indexed load / store.
4242 /// The transformation folded the add / subtract into the new indexed
4243 /// load / store effectively and all of its uses are redirected to the
4244 /// new load / store.
4245 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
4252 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4253 if (LD->isIndexed())
4255 VT = LD->getMemoryVT();
4256 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
4257 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
4259 Ptr = LD->getBasePtr();
4260 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4261 if (ST->isIndexed())
4263 VT = ST->getMemoryVT();
4264 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
4265 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
4267 Ptr = ST->getBasePtr();
4272 if (Ptr.getNode()->hasOneUse())
4275 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4276 E = Ptr.getNode()->use_end(); I != E; ++I) {
4279 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
4284 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4285 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
4287 std::swap(BasePtr, Offset);
4290 // Don't create a indexed load / store with zero offset.
4291 if (isa<ConstantSDNode>(Offset) &&
4292 cast<ConstantSDNode>(Offset)->isNullValue())
4295 // Try turning it into a post-indexed load / store except when
4296 // 1) All uses are load / store ops that use it as base ptr.
4297 // 2) Op must be independent of N, i.e. Op is neither a predecessor
4298 // nor a successor of N. Otherwise, if Op is folded that would
4302 bool TryNext = false;
4303 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
4304 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
4306 if (Use == Ptr.getNode())
4309 // If all the uses are load / store addresses, then don't do the
4311 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
4312 bool RealUse = false;
4313 for (SDNode::use_iterator III = Use->use_begin(),
4314 EEE = Use->use_end(); III != EEE; ++III) {
4315 SDNode *UseUse = *III;
4316 if (!((UseUse->getOpcode() == ISD::LOAD &&
4317 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
4318 (UseUse->getOpcode() == ISD::STORE &&
4319 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
4333 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
4334 SDValue Result = isLoad
4335 ? DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM)
4336 : DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM);
4339 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
4340 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
4342 WorkListRemover DeadNodes(*this);
4344 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4346 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4349 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
4353 // Finally, since the node is now dead, remove it from the graph.
4356 // Replace the uses of Use with uses of the updated base value.
4357 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
4358 Result.getValue(isLoad ? 1 : 0),
4360 removeFromWorkList(Op);
4369 /// InferAlignment - If we can infer some alignment information from this
4370 /// pointer, return it.
4371 static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) {
4372 // If this is a direct reference to a stack slot, use information about the
4373 // stack slot's alignment.
4374 int FrameIdx = 1 << 31;
4375 int64_t FrameOffset = 0;
4376 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) {
4377 FrameIdx = FI->getIndex();
4378 } else if (Ptr.getOpcode() == ISD::ADD &&
4379 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4380 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4381 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4382 FrameOffset = Ptr.getConstantOperandVal(1);
4385 if (FrameIdx != (1 << 31)) {
4386 // FIXME: Handle FI+CST.
4387 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo();
4388 if (MFI.isFixedObjectIndex(FrameIdx)) {
4389 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset;
4391 // The alignment of the frame index can be determined from its offset from
4392 // the incoming frame position. If the frame object is at offset 32 and
4393 // the stack is guaranteed to be 16-byte aligned, then we know that the
4394 // object is 16-byte aligned.
4395 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment();
4396 unsigned Align = MinAlign(ObjectOffset, StackAlign);
4398 // Finally, the frame object itself may have a known alignment. Factor
4399 // the alignment + offset into a new alignment. For example, if we know
4400 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a
4401 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte
4402 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc.
4403 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx),
4405 return std::max(Align, FIInfoAlign);
4412 SDValue DAGCombiner::visitLOAD(SDNode *N) {
4413 LoadSDNode *LD = cast<LoadSDNode>(N);
4414 SDValue Chain = LD->getChain();
4415 SDValue Ptr = LD->getBasePtr();
4417 // Try to infer better alignment information than the load already has.
4418 if (!Fast && LD->isUnindexed()) {
4419 if (unsigned Align = InferAlignment(Ptr, DAG)) {
4420 if (Align > LD->getAlignment())
4421 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0),
4422 Chain, Ptr, LD->getSrcValue(),
4423 LD->getSrcValueOffset(), LD->getMemoryVT(),
4424 LD->isVolatile(), Align);
4429 // If load is not volatile and there are no uses of the loaded value (and
4430 // the updated indexed value in case of indexed loads), change uses of the
4431 // chain value into uses of the chain input (i.e. delete the dead load).
4432 if (!LD->isVolatile()) {
4433 if (N->getValueType(1) == MVT::Other) {
4435 if (N->hasNUsesOfValue(0, 0)) {
4436 // It's not safe to use the two value CombineTo variant here. e.g.
4437 // v1, chain2 = load chain1, loc
4438 // v2, chain3 = load chain2, loc
4440 // Now we replace use of chain2 with chain1. This makes the second load
4441 // isomorphic to the one we are deleting, and thus makes this load live.
4442 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4443 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG));
4445 WorkListRemover DeadNodes(*this);
4446 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
4447 if (N->use_empty()) {
4448 removeFromWorkList(N);
4451 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4455 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
4456 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
4457 SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0));
4458 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4459 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG));
4460 DOUT << " and 2 other values\n";
4461 WorkListRemover DeadNodes(*this);
4462 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
4463 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
4464 DAG.getNode(ISD::UNDEF, N->getValueType(1)),
4466 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
4467 removeFromWorkList(N);
4469 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4474 // If this load is directly stored, replace the load value with the stored
4476 // TODO: Handle store large -> read small portion.
4477 // TODO: Handle TRUNCSTORE/LOADEXT
4478 if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
4479 !LD->isVolatile()) {
4480 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
4481 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
4482 if (PrevST->getBasePtr() == Ptr &&
4483 PrevST->getValue().getValueType() == N->getValueType(0))
4484 return CombineTo(N, Chain.getOperand(1), Chain);
4489 // Walk up chain skipping non-aliasing memory nodes.
4490 SDValue BetterChain = FindBetterChain(N, Chain);
4492 // If there is a better chain.
4493 if (Chain != BetterChain) {
4496 // Replace the chain to void dependency.
4497 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4498 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
4499 LD->getSrcValue(), LD->getSrcValueOffset(),
4500 LD->isVolatile(), LD->getAlignment());
4502 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
4503 LD->getValueType(0),
4504 BetterChain, Ptr, LD->getSrcValue(),
4505 LD->getSrcValueOffset(),
4508 LD->getAlignment());
4511 // Create token factor to keep old chain connected.
4512 SDValue Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
4513 Chain, ReplLoad.getValue(1));
4515 // Replace uses with load result and token factor. Don't add users
4517 return CombineTo(N, ReplLoad.getValue(0), Token, false);
4521 // Try transforming N to an indexed load.
4522 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4523 return SDValue(N, 0);
4529 SDValue DAGCombiner::visitSTORE(SDNode *N) {
4530 StoreSDNode *ST = cast<StoreSDNode>(N);
4531 SDValue Chain = ST->getChain();
4532 SDValue Value = ST->getValue();
4533 SDValue Ptr = ST->getBasePtr();
4535 // Try to infer better alignment information than the store already has.
4536 if (!Fast && ST->isUnindexed()) {
4537 if (unsigned Align = InferAlignment(Ptr, DAG)) {
4538 if (Align > ST->getAlignment())
4539 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(),
4540 ST->getSrcValueOffset(), ST->getMemoryVT(),
4541 ST->isVolatile(), Align);
4545 // If this is a store of a bit convert, store the input value if the
4546 // resultant store does not need a higher alignment than the original.
4547 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
4548 ST->isUnindexed()) {
4549 unsigned Align = ST->getAlignment();
4550 MVT SVT = Value.getOperand(0).getValueType();
4551 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
4552 getABITypeAlignment(SVT.getTypeForMVT());
4553 if (Align <= OrigAlign &&
4554 ((!AfterLegalize && !ST->isVolatile()) ||
4555 TLI.isOperationLegal(ISD::STORE, SVT)))
4556 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
4557 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign);
4560 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
4561 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
4562 // NOTE: If the original store is volatile, this transform must not increase
4563 // the number of stores. For example, on x86-32 an f64 can be stored in one
4564 // processor operation but an i64 (which is not legal) requires two. So the
4565 // transform should not be done in this case.
4566 if (Value.getOpcode() != ISD::TargetConstantFP) {
4568 switch (CFP->getValueType(0).getSimpleVT()) {
4569 default: assert(0 && "Unknown FP type");
4570 case MVT::f80: // We don't do this for these yet.
4575 if ((!AfterLegalize && !ST->isVolatile()) ||
4576 TLI.isOperationLegal(ISD::STORE, MVT::i32)) {
4577 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
4578 convertToAPInt().getZExtValue(), MVT::i32);
4579 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
4580 ST->getSrcValueOffset(), ST->isVolatile(),
4581 ST->getAlignment());
4585 if ((!AfterLegalize && !ST->isVolatile()) ||
4586 TLI.isOperationLegal(ISD::STORE, MVT::i64)) {
4587 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
4588 getZExtValue(), MVT::i64);
4589 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
4590 ST->getSrcValueOffset(), ST->isVolatile(),
4591 ST->getAlignment());
4592 } else if (!ST->isVolatile() &&
4593 TLI.isOperationLegal(ISD::STORE, MVT::i32)) {
4594 // Many FP stores are not made apparent until after legalize, e.g. for
4595 // argument passing. Since this is so common, custom legalize the
4596 // 64-bit integer store into two 32-bit stores.
4597 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue();
4598 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
4599 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
4600 if (TLI.isBigEndian()) std::swap(Lo, Hi);
4602 int SVOffset = ST->getSrcValueOffset();
4603 unsigned Alignment = ST->getAlignment();
4604 bool isVolatile = ST->isVolatile();
4606 SDValue St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
4607 ST->getSrcValueOffset(),
4608 isVolatile, ST->getAlignment());
4609 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4610 DAG.getConstant(4, Ptr.getValueType()));
4612 Alignment = MinAlign(Alignment, 4U);
4613 SDValue St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
4614 SVOffset, isVolatile, Alignment);
4615 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
4623 // Walk up chain skipping non-aliasing memory nodes.
4624 SDValue BetterChain = FindBetterChain(N, Chain);
4626 // If there is a better chain.
4627 if (Chain != BetterChain) {
4628 // Replace the chain to avoid dependency.
4630 if (ST->isTruncatingStore()) {
4631 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
4632 ST->getSrcValue(),ST->getSrcValueOffset(),
4634 ST->isVolatile(), ST->getAlignment());
4636 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
4637 ST->getSrcValue(), ST->getSrcValueOffset(),
4638 ST->isVolatile(), ST->getAlignment());
4641 // Create token to keep both nodes around.
4643 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
4645 // Don't add users to work list.
4646 return CombineTo(N, Token, false);
4650 // Try transforming N to an indexed store.
4651 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4652 return SDValue(N, 0);
4654 // FIXME: is there such a thing as a truncating indexed store?
4655 if (ST->isTruncatingStore() && ST->isUnindexed() &&
4656 Value.getValueType().isInteger()) {
4657 // See if we can simplify the input to this truncstore with knowledge that
4658 // only the low bits are being used. For example:
4659 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
4661 GetDemandedBits(Value,
4662 APInt::getLowBitsSet(Value.getValueSizeInBits(),
4663 ST->getMemoryVT().getSizeInBits()));
4664 AddToWorkList(Value.getNode());
4665 if (Shorter.getNode())
4666 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(),
4667 ST->getSrcValueOffset(), ST->getMemoryVT(),
4668 ST->isVolatile(), ST->getAlignment());
4670 // Otherwise, see if we can simplify the operation with
4671 // SimplifyDemandedBits, which only works if the value has a single use.
4672 if (SimplifyDemandedBits(Value,
4673 APInt::getLowBitsSet(
4674 Value.getValueSizeInBits(),
4675 ST->getMemoryVT().getSizeInBits())))
4676 return SDValue(N, 0);
4679 // If this is a load followed by a store to the same location, then the store
4681 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
4682 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
4683 ST->isUnindexed() && !ST->isVolatile() &&
4684 // There can't be any side effects between the load and store, such as
4686 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
4687 // The store is dead, remove it.
4692 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
4693 // truncating store. We can do this even if this is already a truncstore.
4694 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
4695 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
4696 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
4697 ST->getMemoryVT())) {
4698 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
4699 ST->getSrcValueOffset(), ST->getMemoryVT(),
4700 ST->isVolatile(), ST->getAlignment());
4706 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
4707 SDValue InVec = N->getOperand(0);
4708 SDValue InVal = N->getOperand(1);
4709 SDValue EltNo = N->getOperand(2);
4711 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
4712 // vector with the inserted element.
4713 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
4714 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4715 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), InVec.getNode()->op_end());
4716 if (Elt < Ops.size())
4718 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
4719 &Ops[0], Ops.size());
4725 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
4726 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
4727 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
4728 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
4730 // Perform only after legalization to ensure build_vector / vector_shuffle
4731 // optimizations have already been done.
4732 if (!AfterLegalize) return SDValue();
4734 SDValue InVec = N->getOperand(0);
4735 SDValue EltNo = N->getOperand(1);
4737 if (isa<ConstantSDNode>(EltNo)) {
4738 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
4739 bool NewLoad = false;
4740 MVT VT = InVec.getValueType();
4741 MVT EVT = VT.getVectorElementType();
4743 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
4744 MVT BCVT = InVec.getOperand(0).getValueType();
4745 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType()))
4747 InVec = InVec.getOperand(0);
4748 EVT = BCVT.getVectorElementType();
4752 LoadSDNode *LN0 = NULL;
4753 if (ISD::isNormalLoad(InVec.getNode()))
4754 LN0 = cast<LoadSDNode>(InVec);
4755 else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4756 InVec.getOperand(0).getValueType() == EVT &&
4757 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
4758 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
4759 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) {
4760 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
4762 // (load $addr+1*size)
4763 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2).
4764 getOperand(Elt))->getValue();
4765 unsigned NumElems = InVec.getOperand(2).getNumOperands();
4766 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
4767 if (InVec.getOpcode() == ISD::BIT_CONVERT)
4768 InVec = InVec.getOperand(0);
4769 if (ISD::isNormalLoad(InVec.getNode())) {
4770 LN0 = cast<LoadSDNode>(InVec);
4771 Elt = (Idx < NumElems) ? Idx : Idx - NumElems;
4774 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile())
4777 unsigned Align = LN0->getAlignment();
4779 // Check the resultant load doesn't need a higher alignment than the
4781 unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
4782 getABITypeAlignment(LVT.getTypeForMVT());
4783 if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT))
4788 SDValue NewPtr = LN0->getBasePtr();
4790 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
4791 MVT PtrType = NewPtr.getValueType();
4792 if (TLI.isBigEndian())
4793 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
4794 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
4795 DAG.getConstant(PtrOff, PtrType));
4797 return DAG.getLoad(LVT, LN0->getChain(), NewPtr,
4798 LN0->getSrcValue(), LN0->getSrcValueOffset(),
4799 LN0->isVolatile(), Align);
4805 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
4806 unsigned NumInScalars = N->getNumOperands();
4807 MVT VT = N->getValueType(0);
4808 unsigned NumElts = VT.getVectorNumElements();
4809 MVT EltType = VT.getVectorElementType();
4811 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
4812 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
4813 // at most two distinct vectors, turn this into a shuffle node.
4814 SDValue VecIn1, VecIn2;
4815 for (unsigned i = 0; i != NumInScalars; ++i) {
4816 // Ignore undef inputs.
4817 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4819 // If this input is something other than a EXTRACT_VECTOR_ELT with a
4820 // constant index, bail out.
4821 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4822 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
4823 VecIn1 = VecIn2 = SDValue(0, 0);
4827 // If the input vector type disagrees with the result of the build_vector,
4828 // we can't make a shuffle.
4829 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
4830 if (ExtractedFromVec.getValueType() != VT) {
4831 VecIn1 = VecIn2 = SDValue(0, 0);
4835 // Otherwise, remember this. We allow up to two distinct input vectors.
4836 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
4839 if (VecIn1.getNode() == 0) {
4840 VecIn1 = ExtractedFromVec;
4841 } else if (VecIn2.getNode() == 0) {
4842 VecIn2 = ExtractedFromVec;
4845 VecIn1 = VecIn2 = SDValue(0, 0);
4850 // If everything is good, we can make a shuffle operation.
4851 if (VecIn1.getNode()) {
4852 SmallVector<SDValue, 8> BuildVecIndices;
4853 for (unsigned i = 0; i != NumInScalars; ++i) {
4854 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
4855 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
4859 SDValue Extract = N->getOperand(i);
4861 // If extracting from the first vector, just use the index directly.
4862 if (Extract.getOperand(0) == VecIn1) {
4863 BuildVecIndices.push_back(Extract.getOperand(1));
4867 // Otherwise, use InIdx + VecSize
4868 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
4869 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars));
4872 // Add count and size info.
4873 MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts);
4875 // Return the new VECTOR_SHUFFLE node.
4878 if (VecIn2.getNode()) {
4881 // Use an undef build_vector as input for the second operand.
4882 std::vector<SDValue> UnOps(NumInScalars,
4883 DAG.getNode(ISD::UNDEF,
4885 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
4886 &UnOps[0], UnOps.size());
4887 AddToWorkList(Ops[1].getNode());
4889 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
4890 &BuildVecIndices[0], BuildVecIndices.size());
4891 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3);
4897 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
4898 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
4899 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
4900 // inputs come from at most two distinct vectors, turn this into a shuffle
4903 // If we only have one input vector, we don't need to do any concatenation.
4904 if (N->getNumOperands() == 1) {
4905 return N->getOperand(0);
4911 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
4912 SDValue ShufMask = N->getOperand(2);
4913 unsigned NumElts = ShufMask.getNumOperands();
4915 // If the shuffle mask is an identity operation on the LHS, return the LHS.
4916 bool isIdentity = true;
4917 for (unsigned i = 0; i != NumElts; ++i) {
4918 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4919 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
4924 if (isIdentity) return N->getOperand(0);
4926 // If the shuffle mask is an identity operation on the RHS, return the RHS.
4928 for (unsigned i = 0; i != NumElts; ++i) {
4929 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4930 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
4935 if (isIdentity) return N->getOperand(1);
4937 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
4939 bool isUnary = true;
4940 bool isSplat = true;
4942 unsigned BaseIdx = 0;
4943 for (unsigned i = 0; i != NumElts; ++i)
4944 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
4945 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
4946 int V = (Idx < NumElts) ? 0 : 1;
4960 SDValue N0 = N->getOperand(0);
4961 SDValue N1 = N->getOperand(1);
4962 // Normalize unary shuffle so the RHS is undef.
4963 if (isUnary && VecNum == 1)
4966 // If it is a splat, check if the argument vector is a build_vector with
4967 // all scalar elements the same.
4969 SDNode *V = N0.getNode();
4971 // If this is a bit convert that changes the element type of the vector but
4972 // not the number of vector elements, look through it. Be careful not to
4973 // look though conversions that change things like v4f32 to v2f64.
4974 if (V->getOpcode() == ISD::BIT_CONVERT) {
4975 SDValue ConvInput = V->getOperand(0);
4976 if (ConvInput.getValueType().isVector() &&
4977 ConvInput.getValueType().getVectorNumElements() == NumElts)
4978 V = ConvInput.getNode();
4981 if (V->getOpcode() == ISD::BUILD_VECTOR) {
4982 unsigned NumElems = V->getNumOperands();
4983 if (NumElems > BaseIdx) {
4985 bool AllSame = true;
4986 for (unsigned i = 0; i != NumElems; ++i) {
4987 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
4988 Base = V->getOperand(i);
4992 // Splat of <u, u, u, u>, return <u, u, u, u>
4993 if (!Base.getNode())
4995 for (unsigned i = 0; i != NumElems; ++i) {
4996 if (V->getOperand(i) != Base) {
5001 // Splat of <x, x, x, x>, return <x, x, x, x>
5008 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
5010 if (isUnary || N0 == N1) {
5011 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
5013 SmallVector<SDValue, 8> MappedOps;
5014 for (unsigned i = 0; i != NumElts; ++i) {
5015 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
5016 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
5017 MappedOps.push_back(ShufMask.getOperand(i));
5020 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
5021 MappedOps.push_back(DAG.getConstant(NewIdx,
5022 ShufMask.getOperand(i).getValueType()));
5025 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
5026 &MappedOps[0], MappedOps.size());
5027 AddToWorkList(ShufMask.getNode());
5028 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
5030 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
5037 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
5038 /// an AND to a vector_shuffle with the destination vector and a zero vector.
5039 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
5040 /// vector_shuffle V, Zero, <0, 4, 2, 4>
5041 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
5042 SDValue LHS = N->getOperand(0);
5043 SDValue RHS = N->getOperand(1);
5044 if (N->getOpcode() == ISD::AND) {
5045 if (RHS.getOpcode() == ISD::BIT_CONVERT)
5046 RHS = RHS.getOperand(0);
5047 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
5048 std::vector<SDValue> IdxOps;
5049 unsigned NumOps = RHS.getNumOperands();
5050 unsigned NumElts = NumOps;
5051 MVT EVT = RHS.getValueType().getVectorElementType();
5052 for (unsigned i = 0; i != NumElts; ++i) {
5053 SDValue Elt = RHS.getOperand(i);
5054 if (!isa<ConstantSDNode>(Elt))
5056 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
5057 IdxOps.push_back(DAG.getConstant(i, EVT));
5058 else if (cast<ConstantSDNode>(Elt)->isNullValue())
5059 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
5064 // Let's see if the target supports this vector_shuffle.
5065 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
5068 // Return the new VECTOR_SHUFFLE node.
5069 MVT VT = MVT::getVectorVT(EVT, NumElts);
5070 std::vector<SDValue> Ops;
5071 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
5073 AddToWorkList(LHS.getNode());
5074 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT));
5075 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
5076 &ZeroOps[0], ZeroOps.size()));
5077 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
5078 &IdxOps[0], IdxOps.size()));
5079 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT,
5080 &Ops[0], Ops.size());
5081 if (VT != N->getValueType(0))
5082 Result = DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Result);
5089 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
5090 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
5091 // After legalize, the target may be depending on adds and other
5092 // binary ops to provide legal ways to construct constants or other
5093 // things. Simplifying them may result in a loss of legality.
5094 if (AfterLegalize) return SDValue();
5096 MVT VT = N->getValueType(0);
5097 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
5099 MVT EltType = VT.getVectorElementType();
5100 SDValue LHS = N->getOperand(0);
5101 SDValue RHS = N->getOperand(1);
5102 SDValue Shuffle = XformToShuffleWithZero(N);
5103 if (Shuffle.getNode()) return Shuffle;
5105 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
5107 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
5108 RHS.getOpcode() == ISD::BUILD_VECTOR) {
5109 SmallVector<SDValue, 8> Ops;
5110 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
5111 SDValue LHSOp = LHS.getOperand(i);
5112 SDValue RHSOp = RHS.getOperand(i);
5113 // If these two elements can't be folded, bail out.
5114 if ((LHSOp.getOpcode() != ISD::UNDEF &&
5115 LHSOp.getOpcode() != ISD::Constant &&
5116 LHSOp.getOpcode() != ISD::ConstantFP) ||
5117 (RHSOp.getOpcode() != ISD::UNDEF &&
5118 RHSOp.getOpcode() != ISD::Constant &&
5119 RHSOp.getOpcode() != ISD::ConstantFP))
5121 // Can't fold divide by zero.
5122 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
5123 N->getOpcode() == ISD::FDIV) {
5124 if ((RHSOp.getOpcode() == ISD::Constant &&
5125 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
5126 (RHSOp.getOpcode() == ISD::ConstantFP &&
5127 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
5130 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp));
5131 AddToWorkList(Ops.back().getNode());
5132 assert((Ops.back().getOpcode() == ISD::UNDEF ||
5133 Ops.back().getOpcode() == ISD::Constant ||
5134 Ops.back().getOpcode() == ISD::ConstantFP) &&
5135 "Scalar binop didn't fold!");
5138 if (Ops.size() == LHS.getNumOperands()) {
5139 MVT VT = LHS.getValueType();
5140 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
5147 SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){
5148 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
5150 SDValue SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
5151 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5152 // If we got a simplified select_cc node back from SimplifySelectCC, then
5153 // break it down into a new SETCC node, and a new SELECT node, and then return
5154 // the SELECT node, since we were called with a SELECT node.
5155 if (SCC.getNode()) {
5156 // Check to see if we got a select_cc back (to turn into setcc/select).
5157 // Otherwise, just return whatever node we got back, like fabs.
5158 if (SCC.getOpcode() == ISD::SELECT_CC) {
5159 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
5160 SCC.getOperand(0), SCC.getOperand(1),
5162 AddToWorkList(SETCC.getNode());
5163 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
5164 SCC.getOperand(3), SETCC);
5171 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
5172 /// are the two values being selected between, see if we can simplify the
5173 /// select. Callers of this should assume that TheSelect is deleted if this
5174 /// returns true. As such, they should return the appropriate thing (e.g. the
5175 /// node) back to the top-level of the DAG combiner loop to avoid it being
5178 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
5181 // If this is a select from two identical things, try to pull the operation
5182 // through the select.
5183 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
5184 // If this is a load and the token chain is identical, replace the select
5185 // of two loads with a load through a select of the address to load from.
5186 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
5187 // constants have been dropped into the constant pool.
5188 if (LHS.getOpcode() == ISD::LOAD &&
5189 // Do not let this transformation reduce the number of volatile loads.
5190 !cast<LoadSDNode>(LHS)->isVolatile() &&
5191 !cast<LoadSDNode>(RHS)->isVolatile() &&
5192 // Token chains must be identical.
5193 LHS.getOperand(0) == RHS.getOperand(0)) {
5194 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
5195 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
5197 // If this is an EXTLOAD, the VT's must match.
5198 if (LLD->getMemoryVT() == RLD->getMemoryVT()) {
5199 // FIXME: this conflates two src values, discarding one. This is not
5200 // the right thing to do, but nothing uses srcvalues now. When they do,
5201 // turn SrcValue into a list of locations.
5203 if (TheSelect->getOpcode() == ISD::SELECT) {
5204 // Check that the condition doesn't reach either load. If so, folding
5205 // this will induce a cycle into the DAG.
5206 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5207 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) {
5208 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
5209 TheSelect->getOperand(0), LLD->getBasePtr(),
5213 // Check that the condition doesn't reach either load. If so, folding
5214 // this will induce a cycle into the DAG.
5215 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5216 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5217 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) &&
5218 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) {
5219 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
5220 TheSelect->getOperand(0),
5221 TheSelect->getOperand(1),
5222 LLD->getBasePtr(), RLD->getBasePtr(),
5223 TheSelect->getOperand(4));
5227 if (Addr.getNode()) {
5229 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
5230 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
5231 Addr,LLD->getSrcValue(),
5232 LLD->getSrcValueOffset(),
5234 LLD->getAlignment());
5236 Load = DAG.getExtLoad(LLD->getExtensionType(),
5237 TheSelect->getValueType(0),
5238 LLD->getChain(), Addr, LLD->getSrcValue(),
5239 LLD->getSrcValueOffset(),
5242 LLD->getAlignment());
5244 // Users of the select now use the result of the load.
5245 CombineTo(TheSelect, Load);
5247 // Users of the old loads now use the new load's chain. We know the
5248 // old-load value is dead now.
5249 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
5250 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
5260 SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
5261 SDValue N2, SDValue N3,
5262 ISD::CondCode CC, bool NotExtCompare) {
5264 MVT VT = N2.getValueType();
5265 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
5266 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
5267 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
5269 // Determine if the condition we're dealing with is constant
5270 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
5271 if (SCC.getNode()) AddToWorkList(SCC.getNode());
5272 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
5274 // fold select_cc true, x, y -> x
5275 if (SCCC && !SCCC->isNullValue())
5277 // fold select_cc false, x, y -> y
5278 if (SCCC && SCCC->isNullValue())
5281 // Check to see if we can simplify the select into an fabs node
5282 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
5283 // Allow either -0.0 or 0.0
5284 if (CFP->getValueAPF().isZero()) {
5285 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
5286 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
5287 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
5288 N2 == N3.getOperand(0))
5289 return DAG.getNode(ISD::FABS, VT, N0);
5291 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
5292 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
5293 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
5294 N2.getOperand(0) == N3)
5295 return DAG.getNode(ISD::FABS, VT, N3);
5299 // Check to see if we can perform the "gzip trick", transforming
5300 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
5301 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
5302 N0.getValueType().isInteger() &&
5303 N2.getValueType().isInteger() &&
5304 (N1C->isNullValue() || // (a < 0) ? b : 0
5305 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
5306 MVT XType = N0.getValueType();
5307 MVT AType = N2.getValueType();
5308 if (XType.bitsGE(AType)) {
5309 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
5310 // single-bit constant.
5311 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
5312 unsigned ShCtV = N2C->getAPIntValue().logBase2();
5313 ShCtV = XType.getSizeInBits()-ShCtV-1;
5314 SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
5315 SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
5316 AddToWorkList(Shift.getNode());
5317 if (XType.bitsGT(AType)) {
5318 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
5319 AddToWorkList(Shift.getNode());
5321 return DAG.getNode(ISD::AND, AType, Shift, N2);
5323 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0,
5324 DAG.getConstant(XType.getSizeInBits()-1,
5325 TLI.getShiftAmountTy()));
5326 AddToWorkList(Shift.getNode());
5327 if (XType.bitsGT(AType)) {
5328 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
5329 AddToWorkList(Shift.getNode());
5331 return DAG.getNode(ISD::AND, AType, Shift, N2);
5335 // fold select C, 16, 0 -> shl C, 4
5336 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
5337 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
5339 // If the caller doesn't want us to simplify this into a zext of a compare,
5341 if (NotExtCompare && N2C->getAPIntValue() == 1)
5344 // Get a SetCC of the condition
5345 // FIXME: Should probably make sure that setcc is legal if we ever have a
5346 // target where it isn't.
5348 // cast from setcc result type to select result type
5349 if (AfterLegalize) {
5350 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC);
5351 if (N2.getValueType().bitsLT(SCC.getValueType()))
5352 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
5354 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
5356 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
5357 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
5359 AddToWorkList(SCC.getNode());
5360 AddToWorkList(Temp.getNode());
5362 if (N2C->getAPIntValue() == 1)
5364 // shl setcc result by log2 n2c
5365 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
5366 DAG.getConstant(N2C->getAPIntValue().logBase2(),
5367 TLI.getShiftAmountTy()));
5370 // Check to see if this is the equivalent of setcc
5371 // FIXME: Turn all of these into setcc if setcc if setcc is legal
5372 // otherwise, go ahead with the folds.
5373 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
5374 MVT XType = N0.getValueType();
5375 if (!AfterLegalize ||
5376 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) {
5377 SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC);
5378 if (Res.getValueType() != VT)
5379 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
5383 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
5384 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
5386 TLI.isOperationLegal(ISD::CTLZ, XType))) {
5387 SDValue Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
5388 return DAG.getNode(ISD::SRL, XType, Ctlz,
5389 DAG.getConstant(Log2_32(XType.getSizeInBits()),
5390 TLI.getShiftAmountTy()));
5392 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
5393 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
5394 SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
5396 SDValue NotN0 = DAG.getNode(ISD::XOR, XType, N0,
5397 DAG.getConstant(~0ULL, XType));
5398 return DAG.getNode(ISD::SRL, XType,
5399 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
5400 DAG.getConstant(XType.getSizeInBits()-1,
5401 TLI.getShiftAmountTy()));
5403 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
5404 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
5405 SDValue Sign = DAG.getNode(ISD::SRL, XType, N0,
5406 DAG.getConstant(XType.getSizeInBits()-1,
5407 TLI.getShiftAmountTy()));
5408 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
5412 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
5413 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5414 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
5415 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
5416 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
5417 MVT XType = N0.getValueType();
5418 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0,
5419 DAG.getConstant(XType.getSizeInBits()-1,
5420 TLI.getShiftAmountTy()));
5421 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
5422 AddToWorkList(Shift.getNode());
5423 AddToWorkList(Add.getNode());
5424 return DAG.getNode(ISD::XOR, XType, Add, Shift);
5426 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
5427 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5428 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
5429 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
5430 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
5431 MVT XType = N0.getValueType();
5432 if (SubC->isNullValue() && XType.isInteger()) {
5433 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0,
5434 DAG.getConstant(XType.getSizeInBits()-1,
5435 TLI.getShiftAmountTy()));
5436 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
5437 AddToWorkList(Shift.getNode());
5438 AddToWorkList(Add.getNode());
5439 return DAG.getNode(ISD::XOR, XType, Add, Shift);
5447 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
5448 SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0,
5449 SDValue N1, ISD::CondCode Cond,
5450 bool foldBooleans) {
5451 TargetLowering::DAGCombinerInfo
5452 DagCombineInfo(DAG, !AfterLegalize, false, this);
5453 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
5456 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
5457 /// return a DAG expression to select that will generate the same value by
5458 /// multiplying by a magic number. See:
5459 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5460 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
5461 std::vector<SDNode*> Built;
5462 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
5464 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5470 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
5471 /// return a DAG expression to select that will generate the same value by
5472 /// multiplying by a magic number. See:
5473 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5474 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
5475 std::vector<SDNode*> Built;
5476 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
5478 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5484 /// FindBaseOffset - Return true if base is known not to alias with anything
5485 /// but itself. Provides base object and offset as results.
5486 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) {
5487 // Assume it is a primitive operation.
5488 Base = Ptr; Offset = 0;
5490 // If it's an adding a simple constant then integrate the offset.
5491 if (Base.getOpcode() == ISD::ADD) {
5492 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
5493 Base = Base.getOperand(0);
5494 Offset += C->getValue();
5498 // If it's any of the following then it can't alias with anything but itself.
5499 return isa<FrameIndexSDNode>(Base) ||
5500 isa<ConstantPoolSDNode>(Base) ||
5501 isa<GlobalAddressSDNode>(Base);
5504 /// isAlias - Return true if there is any possibility that the two addresses
5506 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
5507 const Value *SrcValue1, int SrcValueOffset1,
5508 SDValue Ptr2, int64_t Size2,
5509 const Value *SrcValue2, int SrcValueOffset2)
5511 // If they are the same then they must be aliases.
5512 if (Ptr1 == Ptr2) return true;
5514 // Gather base node and offset information.
5515 SDValue Base1, Base2;
5516 int64_t Offset1, Offset2;
5517 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
5518 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
5520 // If they have a same base address then...
5521 if (Base1 == Base2) {
5522 // Check to see if the addresses overlap.
5523 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
5526 // If we know both bases then they can't alias.
5527 if (KnownBase1 && KnownBase2) return false;
5529 if (CombinerGlobalAA) {
5530 // Use alias analysis information.
5531 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
5532 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
5533 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
5534 AliasAnalysis::AliasResult AAResult =
5535 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
5536 if (AAResult == AliasAnalysis::NoAlias)
5540 // Otherwise we have to assume they alias.
5544 /// FindAliasInfo - Extracts the relevant alias information from the memory
5545 /// node. Returns true if the operand was a load.
5546 bool DAGCombiner::FindAliasInfo(SDNode *N,
5547 SDValue &Ptr, int64_t &Size,
5548 const Value *&SrcValue, int &SrcValueOffset) {
5549 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5550 Ptr = LD->getBasePtr();
5551 Size = LD->getMemoryVT().getSizeInBits() >> 3;
5552 SrcValue = LD->getSrcValue();
5553 SrcValueOffset = LD->getSrcValueOffset();
5555 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5556 Ptr = ST->getBasePtr();
5557 Size = ST->getMemoryVT().getSizeInBits() >> 3;
5558 SrcValue = ST->getSrcValue();
5559 SrcValueOffset = ST->getSrcValueOffset();
5561 assert(0 && "FindAliasInfo expected a memory operand");
5567 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
5568 /// looking for aliasing nodes and adding them to the Aliases vector.
5569 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
5570 SmallVector<SDValue, 8> &Aliases) {
5571 SmallVector<SDValue, 8> Chains; // List of chains to visit.
5572 std::set<SDNode *> Visited; // Visited node set.
5574 // Get alias information for node.
5577 const Value *SrcValue;
5579 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
5582 Chains.push_back(OriginalChain);
5584 // Look at each chain and determine if it is an alias. If so, add it to the
5585 // aliases list. If not, then continue up the chain looking for the next
5587 while (!Chains.empty()) {
5588 SDValue Chain = Chains.back();
5591 // Don't bother if we've been before.
5592 if (Visited.find(Chain.getNode()) != Visited.end()) continue;
5593 Visited.insert(Chain.getNode());
5595 switch (Chain.getOpcode()) {
5596 case ISD::EntryToken:
5597 // Entry token is ideal chain operand, but handled in FindBetterChain.
5602 // Get alias information for Chain.
5605 const Value *OpSrcValue;
5606 int OpSrcValueOffset;
5607 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
5608 OpSrcValue, OpSrcValueOffset);
5610 // If chain is alias then stop here.
5611 if (!(IsLoad && IsOpLoad) &&
5612 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
5613 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
5614 Aliases.push_back(Chain);
5616 // Look further up the chain.
5617 Chains.push_back(Chain.getOperand(0));
5618 // Clean up old chain.
5619 AddToWorkList(Chain.getNode());
5624 case ISD::TokenFactor:
5625 // We have to check each of the operands of the token factor, so we queue
5626 // then up. Adding the operands to the queue (stack) in reverse order
5627 // maintains the original order and increases the likelihood that getNode
5628 // will find a matching token factor (CSE.)
5629 for (unsigned n = Chain.getNumOperands(); n;)
5630 Chains.push_back(Chain.getOperand(--n));
5631 // Eliminate the token factor if we can.
5632 AddToWorkList(Chain.getNode());
5636 // For all other instructions we will just have to take what we can get.
5637 Aliases.push_back(Chain);
5643 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
5644 /// for a better chain (aliasing node.)
5645 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
5646 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
5648 // Accumulate all the aliases to this node.
5649 GatherAllAliases(N, OldChain, Aliases);
5651 if (Aliases.size() == 0) {
5652 // If no operands then chain to entry token.
5653 return DAG.getEntryNode();
5654 } else if (Aliases.size() == 1) {
5655 // If a single operand then chain to it. We don't need to revisit it.
5659 // Construct a custom tailored token factor.
5660 SDValue NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5661 &Aliases[0], Aliases.size());
5663 // Make sure the old chain gets cleaned up.
5664 if (NewChain != OldChain) AddToWorkList(OldChain.getNode());
5669 // SelectionDAG::Combine - This is the entry point for the file.
5671 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA,
5673 /// run - This is the main entry point to this class.
5675 DAGCombiner(*this, AA, Fast).Run(RunningAfterLegalize);