1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/Target/TargetData.h"
28 #include "llvm/Target/TargetFrameInfo.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/ADT/SmallPtrSet.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
42 STATISTIC(NodesCombined , "Number of dag nodes combined");
43 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
44 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
45 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
49 CombinerAA("combiner-alias-analysis", cl::Hidden,
50 cl::desc("Turn on alias analysis during testing"));
53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
54 cl::desc("Include global information in alias analysis"));
56 //------------------------------ DAGCombiner ---------------------------------//
60 const TargetLowering &TLI;
62 CodeGenOpt::Level OptLevel;
66 // Worklist of all of the nodes that need to be simplified.
67 std::vector<SDNode*> WorkList;
69 // AA - Used for DAG load/store alias analysis.
72 /// AddUsersToWorkList - When an instruction is simplified, add all users of
73 /// the instruction to the work lists because they might get more simplified
76 void AddUsersToWorkList(SDNode *N) {
77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
82 /// visit - call the node-specific routine that knows how to fold each
83 /// particular type of node.
84 SDValue visit(SDNode *N);
87 /// AddToWorkList - Add to the work list making sure it's instance is at the
88 /// the back (next to be processed.)
89 void AddToWorkList(SDNode *N) {
90 removeFromWorkList(N);
91 WorkList.push_back(N);
94 /// removeFromWorkList - remove all instances of N from the worklist.
96 void removeFromWorkList(SDNode *N) {
97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
105 return CombineTo(N, &Res, 1, AddTo);
108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
110 SDValue To[] = { Res0, Res1 };
111 return CombineTo(N, To, 2, AddTo);
114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
118 /// SimplifyDemandedBits - Check the specified integer node value to see if
119 /// it can be simplified or if things it uses can be simplified by bit
120 /// propagation. If so, return true.
121 bool SimplifyDemandedBits(SDValue Op) {
122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
123 APInt Demanded = APInt::getAllOnesValue(BitWidth);
124 return SimplifyDemandedBits(Op, Demanded);
127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
129 bool CombineToPreIndexedLoadStore(SDNode *N);
130 bool CombineToPostIndexedLoadStore(SDNode *N);
132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
136 SDValue PromoteIntBinOp(SDValue Op);
137 SDValue PromoteIntShiftOp(SDValue Op);
138 SDValue PromoteExtend(SDValue Op);
139 bool PromoteLoad(SDValue Op);
141 /// combine - call the node-specific routine that knows how to fold each
142 /// particular type of node. If that doesn't do anything, try the
143 /// target-specific DAG combines.
144 SDValue combine(SDNode *N);
146 // Visitation implementation - Implement dag node combining for different
147 // node types. The semantics are as follows:
149 // SDValue.getNode() == 0 - No change was made
150 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
151 // otherwise - N should be replaced by the returned Operand.
153 SDValue visitTokenFactor(SDNode *N);
154 SDValue visitMERGE_VALUES(SDNode *N);
155 SDValue visitADD(SDNode *N);
156 SDValue visitSUB(SDNode *N);
157 SDValue visitADDC(SDNode *N);
158 SDValue visitADDE(SDNode *N);
159 SDValue visitMUL(SDNode *N);
160 SDValue visitSDIV(SDNode *N);
161 SDValue visitUDIV(SDNode *N);
162 SDValue visitSREM(SDNode *N);
163 SDValue visitUREM(SDNode *N);
164 SDValue visitMULHU(SDNode *N);
165 SDValue visitMULHS(SDNode *N);
166 SDValue visitSMUL_LOHI(SDNode *N);
167 SDValue visitUMUL_LOHI(SDNode *N);
168 SDValue visitSDIVREM(SDNode *N);
169 SDValue visitUDIVREM(SDNode *N);
170 SDValue visitAND(SDNode *N);
171 SDValue visitOR(SDNode *N);
172 SDValue visitXOR(SDNode *N);
173 SDValue SimplifyVBinOp(SDNode *N);
174 SDValue visitSHL(SDNode *N);
175 SDValue visitSRA(SDNode *N);
176 SDValue visitSRL(SDNode *N);
177 SDValue visitCTLZ(SDNode *N);
178 SDValue visitCTTZ(SDNode *N);
179 SDValue visitCTPOP(SDNode *N);
180 SDValue visitSELECT(SDNode *N);
181 SDValue visitSELECT_CC(SDNode *N);
182 SDValue visitSETCC(SDNode *N);
183 SDValue visitSIGN_EXTEND(SDNode *N);
184 SDValue visitZERO_EXTEND(SDNode *N);
185 SDValue visitANY_EXTEND(SDNode *N);
186 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
187 SDValue visitTRUNCATE(SDNode *N);
188 SDValue visitBITCAST(SDNode *N);
189 SDValue visitBUILD_PAIR(SDNode *N);
190 SDValue visitFADD(SDNode *N);
191 SDValue visitFSUB(SDNode *N);
192 SDValue visitFMUL(SDNode *N);
193 SDValue visitFDIV(SDNode *N);
194 SDValue visitFREM(SDNode *N);
195 SDValue visitFCOPYSIGN(SDNode *N);
196 SDValue visitSINT_TO_FP(SDNode *N);
197 SDValue visitUINT_TO_FP(SDNode *N);
198 SDValue visitFP_TO_SINT(SDNode *N);
199 SDValue visitFP_TO_UINT(SDNode *N);
200 SDValue visitFP_ROUND(SDNode *N);
201 SDValue visitFP_ROUND_INREG(SDNode *N);
202 SDValue visitFP_EXTEND(SDNode *N);
203 SDValue visitFNEG(SDNode *N);
204 SDValue visitFABS(SDNode *N);
205 SDValue visitBRCOND(SDNode *N);
206 SDValue visitBR_CC(SDNode *N);
207 SDValue visitLOAD(SDNode *N);
208 SDValue visitSTORE(SDNode *N);
209 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
210 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
211 SDValue visitBUILD_VECTOR(SDNode *N);
212 SDValue visitCONCAT_VECTORS(SDNode *N);
213 SDValue visitVECTOR_SHUFFLE(SDNode *N);
214 SDValue visitMEMBARRIER(SDNode *N);
216 SDValue XformToShuffleWithZero(SDNode *N);
217 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
219 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
221 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
222 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
223 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
224 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
225 SDValue N3, ISD::CondCode CC,
226 bool NotExtCompare = false);
227 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
228 DebugLoc DL, bool foldBooleans = true);
229 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
231 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
232 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
233 SDValue BuildSDIV(SDNode *N);
234 SDValue BuildUDIV(SDNode *N);
235 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
236 SDValue ReduceLoadWidth(SDNode *N);
237 SDValue ReduceLoadOpStoreWidth(SDNode *N);
239 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
241 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
242 /// looking for aliasing nodes and adding them to the Aliases vector.
243 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
244 SmallVector<SDValue, 8> &Aliases);
246 /// isAlias - Return true if there is any possibility that the two addresses
248 bool isAlias(SDValue Ptr1, int64_t Size1,
249 const Value *SrcValue1, int SrcValueOffset1,
250 unsigned SrcValueAlign1,
251 const MDNode *TBAAInfo1,
252 SDValue Ptr2, int64_t Size2,
253 const Value *SrcValue2, int SrcValueOffset2,
254 unsigned SrcValueAlign2,
255 const MDNode *TBAAInfo2) const;
257 /// FindAliasInfo - Extracts the relevant alias information from the memory
258 /// node. Returns true if the operand was a load.
259 bool FindAliasInfo(SDNode *N,
260 SDValue &Ptr, int64_t &Size,
261 const Value *&SrcValue, int &SrcValueOffset,
262 unsigned &SrcValueAlignment,
263 const MDNode *&TBAAInfo) const;
265 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
266 /// looking for a better chain (aliasing node.)
267 SDValue FindBetterChain(SDNode *N, SDValue Chain);
270 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
271 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted),
272 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
274 /// Run - runs the dag combiner on all nodes in the work list
275 void Run(CombineLevel AtLevel);
277 SelectionDAG &getDAG() const { return DAG; }
279 /// getShiftAmountTy - Returns a type large enough to hold any valid
280 /// shift amount - before type legalization these can be huge.
281 EVT getShiftAmountTy() {
282 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy();
285 /// isTypeLegal - This method returns true if we are running before type
286 /// legalization or if the specified VT is legal.
287 bool isTypeLegal(const EVT &VT) {
288 if (!LegalTypes) return true;
289 return TLI.isTypeLegal(VT);
296 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
297 /// nodes from the worklist.
298 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
301 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
303 virtual void NodeDeleted(SDNode *N, SDNode *E) {
304 DC.removeFromWorkList(N);
307 virtual void NodeUpdated(SDNode *N) {
313 //===----------------------------------------------------------------------===//
314 // TargetLowering::DAGCombinerInfo implementation
315 //===----------------------------------------------------------------------===//
317 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
318 ((DAGCombiner*)DC)->AddToWorkList(N);
321 SDValue TargetLowering::DAGCombinerInfo::
322 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
323 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
326 SDValue TargetLowering::DAGCombinerInfo::
327 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
328 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
332 SDValue TargetLowering::DAGCombinerInfo::
333 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
334 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
337 void TargetLowering::DAGCombinerInfo::
338 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
339 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
342 //===----------------------------------------------------------------------===//
344 //===----------------------------------------------------------------------===//
346 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
347 /// specified expression for the same cost as the expression itself, or 2 if we
348 /// can compute the negated form more cheaply than the expression itself.
349 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
350 unsigned Depth = 0) {
351 // No compile time optimizations on this type.
352 if (Op.getValueType() == MVT::ppcf128)
355 // fneg is removable even if it has multiple uses.
356 if (Op.getOpcode() == ISD::FNEG) return 2;
358 // Don't allow anything with multiple uses.
359 if (!Op.hasOneUse()) return 0;
361 // Don't recurse exponentially.
362 if (Depth > 6) return 0;
364 switch (Op.getOpcode()) {
365 default: return false;
366 case ISD::ConstantFP:
367 // Don't invert constant FP values after legalize. The negated constant
368 // isn't necessarily legal.
369 return LegalOperations ? 0 : 1;
371 // FIXME: determine better conditions for this xform.
372 if (!UnsafeFPMath) return 0;
374 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
375 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
377 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
378 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
380 // We can't turn -(A-B) into B-A when we honor signed zeros.
381 if (!UnsafeFPMath) return 0;
383 // fold (fneg (fsub A, B)) -> (fsub B, A)
388 if (HonorSignDependentRoundingFPMath()) return 0;
390 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
391 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
394 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
399 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
403 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
404 /// returns the newly negated expression.
405 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
406 bool LegalOperations, unsigned Depth = 0) {
407 // fneg is removable even if it has multiple uses.
408 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
410 // Don't allow anything with multiple uses.
411 assert(Op.hasOneUse() && "Unknown reuse!");
413 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
414 switch (Op.getOpcode()) {
415 default: llvm_unreachable("Unknown code");
416 case ISD::ConstantFP: {
417 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
419 return DAG.getConstantFP(V, Op.getValueType());
422 // FIXME: determine better conditions for this xform.
423 assert(UnsafeFPMath);
425 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
426 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
427 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
428 GetNegatedExpression(Op.getOperand(0), DAG,
429 LegalOperations, Depth+1),
431 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
432 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
433 GetNegatedExpression(Op.getOperand(1), DAG,
434 LegalOperations, Depth+1),
437 // We can't turn -(A-B) into B-A when we honor signed zeros.
438 assert(UnsafeFPMath);
440 // fold (fneg (fsub 0, B)) -> B
441 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
442 if (N0CFP->getValueAPF().isZero())
443 return Op.getOperand(1);
445 // fold (fneg (fsub A, B)) -> (fsub B, A)
446 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
447 Op.getOperand(1), Op.getOperand(0));
451 assert(!HonorSignDependentRoundingFPMath());
453 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
454 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
455 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
456 GetNegatedExpression(Op.getOperand(0), DAG,
457 LegalOperations, Depth+1),
460 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
461 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
463 GetNegatedExpression(Op.getOperand(1), DAG,
464 LegalOperations, Depth+1));
468 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
469 GetNegatedExpression(Op.getOperand(0), DAG,
470 LegalOperations, Depth+1));
472 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
473 GetNegatedExpression(Op.getOperand(0), DAG,
474 LegalOperations, Depth+1),
480 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
481 // that selects between the values 1 and 0, making it equivalent to a setcc.
482 // Also, set the incoming LHS, RHS, and CC references to the appropriate
483 // nodes based on the type of node we are checking. This simplifies life a
484 // bit for the callers.
485 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
487 if (N.getOpcode() == ISD::SETCC) {
488 LHS = N.getOperand(0);
489 RHS = N.getOperand(1);
490 CC = N.getOperand(2);
493 if (N.getOpcode() == ISD::SELECT_CC &&
494 N.getOperand(2).getOpcode() == ISD::Constant &&
495 N.getOperand(3).getOpcode() == ISD::Constant &&
496 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
497 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
498 LHS = N.getOperand(0);
499 RHS = N.getOperand(1);
500 CC = N.getOperand(4);
506 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
507 // one use. If this is true, it allows the users to invert the operation for
508 // free when it is profitable to do so.
509 static bool isOneUseSetCC(SDValue N) {
511 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
516 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
517 SDValue N0, SDValue N1) {
518 EVT VT = N0.getValueType();
519 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
520 if (isa<ConstantSDNode>(N1)) {
521 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
523 DAG.FoldConstantArithmetic(Opc, VT,
524 cast<ConstantSDNode>(N0.getOperand(1)),
525 cast<ConstantSDNode>(N1));
526 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
527 } else if (N0.hasOneUse()) {
528 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
529 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
530 N0.getOperand(0), N1);
531 AddToWorkList(OpNode.getNode());
532 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
536 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
537 if (isa<ConstantSDNode>(N0)) {
538 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
540 DAG.FoldConstantArithmetic(Opc, VT,
541 cast<ConstantSDNode>(N1.getOperand(1)),
542 cast<ConstantSDNode>(N0));
543 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
544 } else if (N1.hasOneUse()) {
545 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
546 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
547 N1.getOperand(0), N0);
548 AddToWorkList(OpNode.getNode());
549 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
556 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
558 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
560 DEBUG(dbgs() << "\nReplacing.1 ";
562 dbgs() << "\nWith: ";
563 To[0].getNode()->dump(&DAG);
564 dbgs() << " and " << NumTo-1 << " other values\n";
565 for (unsigned i = 0, e = NumTo; i != e; ++i)
566 assert((!To[i].getNode() ||
567 N->getValueType(i) == To[i].getValueType()) &&
568 "Cannot combine value to value of different type!"));
569 WorkListRemover DeadNodes(*this);
570 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
573 // Push the new nodes and any users onto the worklist
574 for (unsigned i = 0, e = NumTo; i != e; ++i) {
575 if (To[i].getNode()) {
576 AddToWorkList(To[i].getNode());
577 AddUsersToWorkList(To[i].getNode());
582 // Finally, if the node is now dead, remove it from the graph. The node
583 // may not be dead if the replacement process recursively simplified to
584 // something else needing this node.
585 if (N->use_empty()) {
586 // Nodes can be reintroduced into the worklist. Make sure we do not
587 // process a node that has been replaced.
588 removeFromWorkList(N);
590 // Finally, since the node is now dead, remove it from the graph.
593 return SDValue(N, 0);
597 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
598 // Replace all uses. If any nodes become isomorphic to other nodes and
599 // are deleted, make sure to remove them from our worklist.
600 WorkListRemover DeadNodes(*this);
601 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
603 // Push the new node and any (possibly new) users onto the worklist.
604 AddToWorkList(TLO.New.getNode());
605 AddUsersToWorkList(TLO.New.getNode());
607 // Finally, if the node is now dead, remove it from the graph. The node
608 // may not be dead if the replacement process recursively simplified to
609 // something else needing this node.
610 if (TLO.Old.getNode()->use_empty()) {
611 removeFromWorkList(TLO.Old.getNode());
613 // If the operands of this node are only used by the node, they will now
614 // be dead. Make sure to visit them first to delete dead nodes early.
615 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
616 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
617 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
619 DAG.DeleteNode(TLO.Old.getNode());
623 /// SimplifyDemandedBits - Check the specified integer node value to see if
624 /// it can be simplified or if things it uses can be simplified by bit
625 /// propagation. If so, return true.
626 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
627 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
628 APInt KnownZero, KnownOne;
629 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
633 AddToWorkList(Op.getNode());
635 // Replace the old value with the new one.
637 DEBUG(dbgs() << "\nReplacing.2 ";
638 TLO.Old.getNode()->dump(&DAG);
639 dbgs() << "\nWith: ";
640 TLO.New.getNode()->dump(&DAG);
643 CommitTargetLoweringOpt(TLO);
647 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
648 DebugLoc dl = Load->getDebugLoc();
649 EVT VT = Load->getValueType(0);
650 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
652 DEBUG(dbgs() << "\nReplacing.9 ";
654 dbgs() << "\nWith: ";
655 Trunc.getNode()->dump(&DAG);
657 WorkListRemover DeadNodes(*this);
658 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes);
659 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1),
661 removeFromWorkList(Load);
662 DAG.DeleteNode(Load);
663 AddToWorkList(Trunc.getNode());
666 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
668 DebugLoc dl = Op.getDebugLoc();
669 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
670 EVT MemVT = LD->getMemoryVT();
671 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
672 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
674 : LD->getExtensionType();
676 return DAG.getExtLoad(ExtType, PVT, dl,
677 LD->getChain(), LD->getBasePtr(),
678 LD->getPointerInfo(),
679 MemVT, LD->isVolatile(),
680 LD->isNonTemporal(), LD->getAlignment());
683 unsigned Opc = Op.getOpcode();
686 case ISD::AssertSext:
687 return DAG.getNode(ISD::AssertSext, dl, PVT,
688 SExtPromoteOperand(Op.getOperand(0), PVT),
690 case ISD::AssertZext:
691 return DAG.getNode(ISD::AssertZext, dl, PVT,
692 ZExtPromoteOperand(Op.getOperand(0), PVT),
694 case ISD::Constant: {
696 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
697 return DAG.getNode(ExtOpc, dl, PVT, Op);
701 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
703 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
706 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
707 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
709 EVT OldVT = Op.getValueType();
710 DebugLoc dl = Op.getDebugLoc();
711 bool Replace = false;
712 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
713 if (NewOp.getNode() == 0)
715 AddToWorkList(NewOp.getNode());
718 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
719 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
720 DAG.getValueType(OldVT));
723 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
724 EVT OldVT = Op.getValueType();
725 DebugLoc dl = Op.getDebugLoc();
726 bool Replace = false;
727 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
728 if (NewOp.getNode() == 0)
730 AddToWorkList(NewOp.getNode());
733 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
734 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
737 /// PromoteIntBinOp - Promote the specified integer binary operation if the
738 /// target indicates it is beneficial. e.g. On x86, it's usually better to
739 /// promote i16 operations to i32 since i16 instructions are longer.
740 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
741 if (!LegalOperations)
744 EVT VT = Op.getValueType();
745 if (VT.isVector() || !VT.isInteger())
748 // If operation type is 'undesirable', e.g. i16 on x86, consider
750 unsigned Opc = Op.getOpcode();
751 if (TLI.isTypeDesirableForOp(Opc, VT))
755 // Consult target whether it is a good idea to promote this operation and
756 // what's the right type to promote it to.
757 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
758 assert(PVT != VT && "Don't know what type to promote to!");
760 bool Replace0 = false;
761 SDValue N0 = Op.getOperand(0);
762 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
763 if (NN0.getNode() == 0)
766 bool Replace1 = false;
767 SDValue N1 = Op.getOperand(1);
772 NN1 = PromoteOperand(N1, PVT, Replace1);
773 if (NN1.getNode() == 0)
777 AddToWorkList(NN0.getNode());
779 AddToWorkList(NN1.getNode());
782 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
784 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
786 DEBUG(dbgs() << "\nPromoting ";
787 Op.getNode()->dump(&DAG));
788 DebugLoc dl = Op.getDebugLoc();
789 return DAG.getNode(ISD::TRUNCATE, dl, VT,
790 DAG.getNode(Opc, dl, PVT, NN0, NN1));
795 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
796 /// target indicates it is beneficial. e.g. On x86, it's usually better to
797 /// promote i16 operations to i32 since i16 instructions are longer.
798 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
799 if (!LegalOperations)
802 EVT VT = Op.getValueType();
803 if (VT.isVector() || !VT.isInteger())
806 // If operation type is 'undesirable', e.g. i16 on x86, consider
808 unsigned Opc = Op.getOpcode();
809 if (TLI.isTypeDesirableForOp(Opc, VT))
813 // Consult target whether it is a good idea to promote this operation and
814 // what's the right type to promote it to.
815 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
816 assert(PVT != VT && "Don't know what type to promote to!");
818 bool Replace = false;
819 SDValue N0 = Op.getOperand(0);
821 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
822 else if (Opc == ISD::SRL)
823 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
825 N0 = PromoteOperand(N0, PVT, Replace);
826 if (N0.getNode() == 0)
829 AddToWorkList(N0.getNode());
831 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
833 DEBUG(dbgs() << "\nPromoting ";
834 Op.getNode()->dump(&DAG));
835 DebugLoc dl = Op.getDebugLoc();
836 return DAG.getNode(ISD::TRUNCATE, dl, VT,
837 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
842 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
843 if (!LegalOperations)
846 EVT VT = Op.getValueType();
847 if (VT.isVector() || !VT.isInteger())
850 // If operation type is 'undesirable', e.g. i16 on x86, consider
852 unsigned Opc = Op.getOpcode();
853 if (TLI.isTypeDesirableForOp(Opc, VT))
857 // Consult target whether it is a good idea to promote this operation and
858 // what's the right type to promote it to.
859 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
860 assert(PVT != VT && "Don't know what type to promote to!");
861 // fold (aext (aext x)) -> (aext x)
862 // fold (aext (zext x)) -> (zext x)
863 // fold (aext (sext x)) -> (sext x)
864 DEBUG(dbgs() << "\nPromoting ";
865 Op.getNode()->dump(&DAG));
866 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
871 bool DAGCombiner::PromoteLoad(SDValue Op) {
872 if (!LegalOperations)
875 EVT VT = Op.getValueType();
876 if (VT.isVector() || !VT.isInteger())
879 // If operation type is 'undesirable', e.g. i16 on x86, consider
881 unsigned Opc = Op.getOpcode();
882 if (TLI.isTypeDesirableForOp(Opc, VT))
886 // Consult target whether it is a good idea to promote this operation and
887 // what's the right type to promote it to.
888 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
889 assert(PVT != VT && "Don't know what type to promote to!");
891 DebugLoc dl = Op.getDebugLoc();
892 SDNode *N = Op.getNode();
893 LoadSDNode *LD = cast<LoadSDNode>(N);
894 EVT MemVT = LD->getMemoryVT();
895 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
896 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
898 : LD->getExtensionType();
899 SDValue NewLD = DAG.getExtLoad(ExtType, PVT, dl,
900 LD->getChain(), LD->getBasePtr(),
901 LD->getPointerInfo(),
902 MemVT, LD->isVolatile(),
903 LD->isNonTemporal(), LD->getAlignment());
904 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
906 DEBUG(dbgs() << "\nPromoting ";
909 Result.getNode()->dump(&DAG);
911 WorkListRemover DeadNodes(*this);
912 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes);
913 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes);
914 removeFromWorkList(N);
916 AddToWorkList(Result.getNode());
923 //===----------------------------------------------------------------------===//
924 // Main DAG Combiner implementation
925 //===----------------------------------------------------------------------===//
927 void DAGCombiner::Run(CombineLevel AtLevel) {
928 // set the instance variables, so that the various visit routines may use it.
930 LegalOperations = Level >= NoIllegalOperations;
931 LegalTypes = Level >= NoIllegalTypes;
933 // Add all the dag nodes to the worklist.
934 WorkList.reserve(DAG.allnodes_size());
935 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
936 E = DAG.allnodes_end(); I != E; ++I)
937 WorkList.push_back(I);
939 // Create a dummy node (which is not added to allnodes), that adds a reference
940 // to the root node, preventing it from being deleted, and tracking any
941 // changes of the root.
942 HandleSDNode Dummy(DAG.getRoot());
944 // The root of the dag may dangle to deleted nodes until the dag combiner is
945 // done. Set it to null to avoid confusion.
946 DAG.setRoot(SDValue());
948 // while the worklist isn't empty, inspect the node on the end of it and
949 // try and combine it.
950 while (!WorkList.empty()) {
951 SDNode *N = WorkList.back();
954 // If N has no uses, it is dead. Make sure to revisit all N's operands once
955 // N is deleted from the DAG, since they too may now be dead or may have a
956 // reduced number of uses, allowing other xforms.
957 if (N->use_empty() && N != &Dummy) {
958 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
959 AddToWorkList(N->getOperand(i).getNode());
965 SDValue RV = combine(N);
967 if (RV.getNode() == 0)
972 // If we get back the same node we passed in, rather than a new node or
973 // zero, we know that the node must have defined multiple values and
974 // CombineTo was used. Since CombineTo takes care of the worklist
975 // mechanics for us, we have no work to do in this case.
976 if (RV.getNode() == N)
979 assert(N->getOpcode() != ISD::DELETED_NODE &&
980 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
981 "Node was deleted but visit returned new node!");
983 DEBUG(dbgs() << "\nReplacing.3 ";
985 dbgs() << "\nWith: ";
986 RV.getNode()->dump(&DAG);
988 WorkListRemover DeadNodes(*this);
989 if (N->getNumValues() == RV.getNode()->getNumValues())
990 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
992 assert(N->getValueType(0) == RV.getValueType() &&
993 N->getNumValues() == 1 && "Type mismatch");
995 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
998 // Push the new node and any users onto the worklist
999 AddToWorkList(RV.getNode());
1000 AddUsersToWorkList(RV.getNode());
1002 // Add any uses of the old node to the worklist in case this node is the
1003 // last one that uses them. They may become dead after this node is
1005 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1006 AddToWorkList(N->getOperand(i).getNode());
1008 // Finally, if the node is now dead, remove it from the graph. The node
1009 // may not be dead if the replacement process recursively simplified to
1010 // something else needing this node.
1011 if (N->use_empty()) {
1012 // Nodes can be reintroduced into the worklist. Make sure we do not
1013 // process a node that has been replaced.
1014 removeFromWorkList(N);
1016 // Finally, since the node is now dead, remove it from the graph.
1021 // If the root changed (e.g. it was a dead load, update the root).
1022 DAG.setRoot(Dummy.getValue());
1025 SDValue DAGCombiner::visit(SDNode *N) {
1026 switch (N->getOpcode()) {
1028 case ISD::TokenFactor: return visitTokenFactor(N);
1029 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1030 case ISD::ADD: return visitADD(N);
1031 case ISD::SUB: return visitSUB(N);
1032 case ISD::ADDC: return visitADDC(N);
1033 case ISD::ADDE: return visitADDE(N);
1034 case ISD::MUL: return visitMUL(N);
1035 case ISD::SDIV: return visitSDIV(N);
1036 case ISD::UDIV: return visitUDIV(N);
1037 case ISD::SREM: return visitSREM(N);
1038 case ISD::UREM: return visitUREM(N);
1039 case ISD::MULHU: return visitMULHU(N);
1040 case ISD::MULHS: return visitMULHS(N);
1041 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1042 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1043 case ISD::SDIVREM: return visitSDIVREM(N);
1044 case ISD::UDIVREM: return visitUDIVREM(N);
1045 case ISD::AND: return visitAND(N);
1046 case ISD::OR: return visitOR(N);
1047 case ISD::XOR: return visitXOR(N);
1048 case ISD::SHL: return visitSHL(N);
1049 case ISD::SRA: return visitSRA(N);
1050 case ISD::SRL: return visitSRL(N);
1051 case ISD::CTLZ: return visitCTLZ(N);
1052 case ISD::CTTZ: return visitCTTZ(N);
1053 case ISD::CTPOP: return visitCTPOP(N);
1054 case ISD::SELECT: return visitSELECT(N);
1055 case ISD::SELECT_CC: return visitSELECT_CC(N);
1056 case ISD::SETCC: return visitSETCC(N);
1057 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1058 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1059 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1060 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1061 case ISD::TRUNCATE: return visitTRUNCATE(N);
1062 case ISD::BITCAST: return visitBITCAST(N);
1063 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1064 case ISD::FADD: return visitFADD(N);
1065 case ISD::FSUB: return visitFSUB(N);
1066 case ISD::FMUL: return visitFMUL(N);
1067 case ISD::FDIV: return visitFDIV(N);
1068 case ISD::FREM: return visitFREM(N);
1069 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1070 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1071 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1072 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1073 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1074 case ISD::FP_ROUND: return visitFP_ROUND(N);
1075 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1076 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1077 case ISD::FNEG: return visitFNEG(N);
1078 case ISD::FABS: return visitFABS(N);
1079 case ISD::BRCOND: return visitBRCOND(N);
1080 case ISD::BR_CC: return visitBR_CC(N);
1081 case ISD::LOAD: return visitLOAD(N);
1082 case ISD::STORE: return visitSTORE(N);
1083 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1084 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1085 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1086 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1087 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1088 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1093 SDValue DAGCombiner::combine(SDNode *N) {
1094 SDValue RV = visit(N);
1096 // If nothing happened, try a target-specific DAG combine.
1097 if (RV.getNode() == 0) {
1098 assert(N->getOpcode() != ISD::DELETED_NODE &&
1099 "Node was deleted but visit returned NULL!");
1101 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1102 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1104 // Expose the DAG combiner to the target combiner impls.
1105 TargetLowering::DAGCombinerInfo
1106 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1108 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1112 // If nothing happened still, try promoting the operation.
1113 if (RV.getNode() == 0) {
1114 switch (N->getOpcode()) {
1122 RV = PromoteIntBinOp(SDValue(N, 0));
1127 RV = PromoteIntShiftOp(SDValue(N, 0));
1129 case ISD::SIGN_EXTEND:
1130 case ISD::ZERO_EXTEND:
1131 case ISD::ANY_EXTEND:
1132 RV = PromoteExtend(SDValue(N, 0));
1135 if (PromoteLoad(SDValue(N, 0)))
1141 // If N is a commutative binary node, try commuting it to enable more
1143 if (RV.getNode() == 0 &&
1144 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1145 N->getNumValues() == 1) {
1146 SDValue N0 = N->getOperand(0);
1147 SDValue N1 = N->getOperand(1);
1149 // Constant operands are canonicalized to RHS.
1150 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1151 SDValue Ops[] = { N1, N0 };
1152 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1155 return SDValue(CSENode, 0);
1162 /// getInputChainForNode - Given a node, return its input chain if it has one,
1163 /// otherwise return a null sd operand.
1164 static SDValue getInputChainForNode(SDNode *N) {
1165 if (unsigned NumOps = N->getNumOperands()) {
1166 if (N->getOperand(0).getValueType() == MVT::Other)
1167 return N->getOperand(0);
1168 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1169 return N->getOperand(NumOps-1);
1170 for (unsigned i = 1; i < NumOps-1; ++i)
1171 if (N->getOperand(i).getValueType() == MVT::Other)
1172 return N->getOperand(i);
1177 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1178 // If N has two operands, where one has an input chain equal to the other,
1179 // the 'other' chain is redundant.
1180 if (N->getNumOperands() == 2) {
1181 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1182 return N->getOperand(0);
1183 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1184 return N->getOperand(1);
1187 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1188 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1189 SmallPtrSet<SDNode*, 16> SeenOps;
1190 bool Changed = false; // If we should replace this token factor.
1192 // Start out with this token factor.
1195 // Iterate through token factors. The TFs grows when new token factors are
1197 for (unsigned i = 0; i < TFs.size(); ++i) {
1198 SDNode *TF = TFs[i];
1200 // Check each of the operands.
1201 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1202 SDValue Op = TF->getOperand(i);
1204 switch (Op.getOpcode()) {
1205 case ISD::EntryToken:
1206 // Entry tokens don't need to be added to the list. They are
1211 case ISD::TokenFactor:
1212 if (Op.hasOneUse() &&
1213 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1214 // Queue up for processing.
1215 TFs.push_back(Op.getNode());
1216 // Clean up in case the token factor is removed.
1217 AddToWorkList(Op.getNode());
1224 // Only add if it isn't already in the list.
1225 if (SeenOps.insert(Op.getNode()))
1236 // If we've change things around then replace token factor.
1239 // The entry token is the only possible outcome.
1240 Result = DAG.getEntryNode();
1242 // New and improved token factor.
1243 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1244 MVT::Other, &Ops[0], Ops.size());
1247 // Don't add users to work list.
1248 return CombineTo(N, Result, false);
1254 /// MERGE_VALUES can always be eliminated.
1255 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1256 WorkListRemover DeadNodes(*this);
1257 // Replacing results may cause a different MERGE_VALUES to suddenly
1258 // be CSE'd with N, and carry its uses with it. Iterate until no
1259 // uses remain, to ensure that the node can be safely deleted.
1261 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1262 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
1264 } while (!N->use_empty());
1265 removeFromWorkList(N);
1267 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1271 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1272 SelectionDAG &DAG) {
1273 EVT VT = N0.getValueType();
1274 SDValue N00 = N0.getOperand(0);
1275 SDValue N01 = N0.getOperand(1);
1276 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1278 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1279 isa<ConstantSDNode>(N00.getOperand(1))) {
1280 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1281 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1282 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1283 N00.getOperand(0), N01),
1284 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1285 N00.getOperand(1), N01));
1286 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1292 SDValue DAGCombiner::visitADD(SDNode *N) {
1293 SDValue N0 = N->getOperand(0);
1294 SDValue N1 = N->getOperand(1);
1295 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1296 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1297 EVT VT = N0.getValueType();
1300 if (VT.isVector()) {
1301 SDValue FoldedVOp = SimplifyVBinOp(N);
1302 if (FoldedVOp.getNode()) return FoldedVOp;
1305 // fold (add x, undef) -> undef
1306 if (N0.getOpcode() == ISD::UNDEF)
1308 if (N1.getOpcode() == ISD::UNDEF)
1310 // fold (add c1, c2) -> c1+c2
1312 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1313 // canonicalize constant to RHS
1315 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1316 // fold (add x, 0) -> x
1317 if (N1C && N1C->isNullValue())
1319 // fold (add Sym, c) -> Sym+c
1320 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1321 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1322 GA->getOpcode() == ISD::GlobalAddress)
1323 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1325 (uint64_t)N1C->getSExtValue());
1326 // fold ((c1-A)+c2) -> (c1+c2)-A
1327 if (N1C && N0.getOpcode() == ISD::SUB)
1328 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1329 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1330 DAG.getConstant(N1C->getAPIntValue()+
1331 N0C->getAPIntValue(), VT),
1334 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1335 if (RADD.getNode() != 0)
1337 // fold ((0-A) + B) -> B-A
1338 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1339 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1340 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1341 // fold (A + (0-B)) -> A-B
1342 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1343 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1344 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1345 // fold (A+(B-A)) -> B
1346 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1347 return N1.getOperand(0);
1348 // fold ((B-A)+A) -> B
1349 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1350 return N0.getOperand(0);
1351 // fold (A+(B-(A+C))) to (B-C)
1352 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1353 N0 == N1.getOperand(1).getOperand(0))
1354 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1355 N1.getOperand(1).getOperand(1));
1356 // fold (A+(B-(C+A))) to (B-C)
1357 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1358 N0 == N1.getOperand(1).getOperand(1))
1359 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1360 N1.getOperand(1).getOperand(0));
1361 // fold (A+((B-A)+or-C)) to (B+or-C)
1362 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1363 N1.getOperand(0).getOpcode() == ISD::SUB &&
1364 N0 == N1.getOperand(0).getOperand(1))
1365 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1366 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1368 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1369 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1370 SDValue N00 = N0.getOperand(0);
1371 SDValue N01 = N0.getOperand(1);
1372 SDValue N10 = N1.getOperand(0);
1373 SDValue N11 = N1.getOperand(1);
1375 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1376 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1377 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1378 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1381 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1382 return SDValue(N, 0);
1384 // fold (a+b) -> (a|b) iff a and b share no bits.
1385 if (VT.isInteger() && !VT.isVector()) {
1386 APInt LHSZero, LHSOne;
1387 APInt RHSZero, RHSOne;
1388 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1389 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1391 if (LHSZero.getBoolValue()) {
1392 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1394 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1395 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1396 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1397 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1398 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1402 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1403 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1404 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1405 if (Result.getNode()) return Result;
1407 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1408 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1409 if (Result.getNode()) return Result;
1412 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1413 if (N1.getOpcode() == ISD::SHL &&
1414 N1.getOperand(0).getOpcode() == ISD::SUB)
1415 if (ConstantSDNode *C =
1416 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1417 if (C->getAPIntValue() == 0)
1418 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1419 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1420 N1.getOperand(0).getOperand(1),
1422 if (N0.getOpcode() == ISD::SHL &&
1423 N0.getOperand(0).getOpcode() == ISD::SUB)
1424 if (ConstantSDNode *C =
1425 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1426 if (C->getAPIntValue() == 0)
1427 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1428 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1429 N0.getOperand(0).getOperand(1),
1432 if (N1.getOpcode() == ISD::AND) {
1433 SDValue AndOp0 = N1.getOperand(0);
1434 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1435 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1436 unsigned DestBits = VT.getScalarType().getSizeInBits();
1438 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1439 // and similar xforms where the inner op is either ~0 or 0.
1440 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1441 DebugLoc DL = N->getDebugLoc();
1442 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1449 SDValue DAGCombiner::visitADDC(SDNode *N) {
1450 SDValue N0 = N->getOperand(0);
1451 SDValue N1 = N->getOperand(1);
1452 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1453 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1454 EVT VT = N0.getValueType();
1456 // If the flag result is dead, turn this into an ADD.
1457 if (N->hasNUsesOfValue(0, 1))
1458 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1459 DAG.getNode(ISD::CARRY_FALSE,
1460 N->getDebugLoc(), MVT::Flag));
1462 // canonicalize constant to RHS.
1464 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1466 // fold (addc x, 0) -> x + no carry out
1467 if (N1C && N1C->isNullValue())
1468 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1469 N->getDebugLoc(), MVT::Flag));
1471 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1472 APInt LHSZero, LHSOne;
1473 APInt RHSZero, RHSOne;
1474 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1475 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1477 if (LHSZero.getBoolValue()) {
1478 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1480 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1481 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1482 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1483 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1484 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1485 DAG.getNode(ISD::CARRY_FALSE,
1486 N->getDebugLoc(), MVT::Flag));
1492 SDValue DAGCombiner::visitADDE(SDNode *N) {
1493 SDValue N0 = N->getOperand(0);
1494 SDValue N1 = N->getOperand(1);
1495 SDValue CarryIn = N->getOperand(2);
1496 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1497 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1499 // canonicalize constant to RHS
1501 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1504 // fold (adde x, y, false) -> (addc x, y)
1505 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1506 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1511 SDValue DAGCombiner::visitSUB(SDNode *N) {
1512 SDValue N0 = N->getOperand(0);
1513 SDValue N1 = N->getOperand(1);
1514 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1515 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1516 EVT VT = N0.getValueType();
1519 if (VT.isVector()) {
1520 SDValue FoldedVOp = SimplifyVBinOp(N);
1521 if (FoldedVOp.getNode()) return FoldedVOp;
1524 // fold (sub x, x) -> 0
1526 return DAG.getConstant(0, N->getValueType(0));
1527 // fold (sub c1, c2) -> c1-c2
1529 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1530 // fold (sub x, c) -> (add x, -c)
1532 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1533 DAG.getConstant(-N1C->getAPIntValue(), VT));
1534 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1535 if (N0C && N0C->isAllOnesValue())
1536 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1537 // fold (A+B)-A -> B
1538 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1539 return N0.getOperand(1);
1540 // fold (A+B)-B -> A
1541 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1542 return N0.getOperand(0);
1543 // fold ((A+(B+or-C))-B) -> A+or-C
1544 if (N0.getOpcode() == ISD::ADD &&
1545 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1546 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1547 N0.getOperand(1).getOperand(0) == N1)
1548 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1549 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1550 // fold ((A+(C+B))-B) -> A+C
1551 if (N0.getOpcode() == ISD::ADD &&
1552 N0.getOperand(1).getOpcode() == ISD::ADD &&
1553 N0.getOperand(1).getOperand(1) == N1)
1554 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1555 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1556 // fold ((A-(B-C))-C) -> A-B
1557 if (N0.getOpcode() == ISD::SUB &&
1558 N0.getOperand(1).getOpcode() == ISD::SUB &&
1559 N0.getOperand(1).getOperand(1) == N1)
1560 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1561 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1563 // If either operand of a sub is undef, the result is undef
1564 if (N0.getOpcode() == ISD::UNDEF)
1566 if (N1.getOpcode() == ISD::UNDEF)
1569 // If the relocation model supports it, consider symbol offsets.
1570 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1571 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1572 // fold (sub Sym, c) -> Sym-c
1573 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1574 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1576 (uint64_t)N1C->getSExtValue());
1577 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1578 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1579 if (GA->getGlobal() == GB->getGlobal())
1580 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1587 SDValue DAGCombiner::visitMUL(SDNode *N) {
1588 SDValue N0 = N->getOperand(0);
1589 SDValue N1 = N->getOperand(1);
1590 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1591 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1592 EVT VT = N0.getValueType();
1595 if (VT.isVector()) {
1596 SDValue FoldedVOp = SimplifyVBinOp(N);
1597 if (FoldedVOp.getNode()) return FoldedVOp;
1600 // fold (mul x, undef) -> 0
1601 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1602 return DAG.getConstant(0, VT);
1603 // fold (mul c1, c2) -> c1*c2
1605 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1606 // canonicalize constant to RHS
1608 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1609 // fold (mul x, 0) -> 0
1610 if (N1C && N1C->isNullValue())
1612 // fold (mul x, -1) -> 0-x
1613 if (N1C && N1C->isAllOnesValue())
1614 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1615 DAG.getConstant(0, VT), N0);
1616 // fold (mul x, (1 << c)) -> x << c
1617 if (N1C && N1C->getAPIntValue().isPowerOf2())
1618 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1619 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1620 getShiftAmountTy()));
1621 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1622 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1623 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1624 // FIXME: If the input is something that is easily negated (e.g. a
1625 // single-use add), we should put the negate there.
1626 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1627 DAG.getConstant(0, VT),
1628 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1629 DAG.getConstant(Log2Val, getShiftAmountTy())));
1631 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1632 if (N1C && N0.getOpcode() == ISD::SHL &&
1633 isa<ConstantSDNode>(N0.getOperand(1))) {
1634 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1635 N1, N0.getOperand(1));
1636 AddToWorkList(C3.getNode());
1637 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1638 N0.getOperand(0), C3);
1641 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1644 SDValue Sh(0,0), Y(0,0);
1645 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1646 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1647 N0.getNode()->hasOneUse()) {
1649 } else if (N1.getOpcode() == ISD::SHL &&
1650 isa<ConstantSDNode>(N1.getOperand(1)) &&
1651 N1.getNode()->hasOneUse()) {
1656 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1657 Sh.getOperand(0), Y);
1658 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1659 Mul, Sh.getOperand(1));
1663 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1664 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1665 isa<ConstantSDNode>(N0.getOperand(1)))
1666 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1667 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1668 N0.getOperand(0), N1),
1669 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1670 N0.getOperand(1), N1));
1673 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1674 if (RMUL.getNode() != 0)
1680 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1681 SDValue N0 = N->getOperand(0);
1682 SDValue N1 = N->getOperand(1);
1683 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1684 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1685 EVT VT = N->getValueType(0);
1688 if (VT.isVector()) {
1689 SDValue FoldedVOp = SimplifyVBinOp(N);
1690 if (FoldedVOp.getNode()) return FoldedVOp;
1693 // fold (sdiv c1, c2) -> c1/c2
1694 if (N0C && N1C && !N1C->isNullValue())
1695 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1696 // fold (sdiv X, 1) -> X
1697 if (N1C && N1C->getSExtValue() == 1LL)
1699 // fold (sdiv X, -1) -> 0-X
1700 if (N1C && N1C->isAllOnesValue())
1701 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1702 DAG.getConstant(0, VT), N0);
1703 // If we know the sign bits of both operands are zero, strength reduce to a
1704 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1705 if (!VT.isVector()) {
1706 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1707 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1710 // fold (sdiv X, pow2) -> simple ops after legalize
1711 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1712 (isPowerOf2_64(N1C->getSExtValue()) ||
1713 isPowerOf2_64(-N1C->getSExtValue()))) {
1714 // If dividing by powers of two is cheap, then don't perform the following
1716 if (TLI.isPow2DivCheap())
1719 int64_t pow2 = N1C->getSExtValue();
1720 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1721 unsigned lg2 = Log2_64(abs2);
1723 // Splat the sign bit into the register
1724 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1725 DAG.getConstant(VT.getSizeInBits()-1,
1726 getShiftAmountTy()));
1727 AddToWorkList(SGN.getNode());
1729 // Add (N0 < 0) ? abs2 - 1 : 0;
1730 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1731 DAG.getConstant(VT.getSizeInBits() - lg2,
1732 getShiftAmountTy()));
1733 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1734 AddToWorkList(SRL.getNode());
1735 AddToWorkList(ADD.getNode()); // Divide by pow2
1736 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1737 DAG.getConstant(lg2, getShiftAmountTy()));
1739 // If we're dividing by a positive value, we're done. Otherwise, we must
1740 // negate the result.
1744 AddToWorkList(SRA.getNode());
1745 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1746 DAG.getConstant(0, VT), SRA);
1749 // if integer divide is expensive and we satisfy the requirements, emit an
1750 // alternate sequence.
1751 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1752 !TLI.isIntDivCheap()) {
1753 SDValue Op = BuildSDIV(N);
1754 if (Op.getNode()) return Op;
1758 if (N0.getOpcode() == ISD::UNDEF)
1759 return DAG.getConstant(0, VT);
1760 // X / undef -> undef
1761 if (N1.getOpcode() == ISD::UNDEF)
1767 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1768 SDValue N0 = N->getOperand(0);
1769 SDValue N1 = N->getOperand(1);
1770 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1771 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1772 EVT VT = N->getValueType(0);
1775 if (VT.isVector()) {
1776 SDValue FoldedVOp = SimplifyVBinOp(N);
1777 if (FoldedVOp.getNode()) return FoldedVOp;
1780 // fold (udiv c1, c2) -> c1/c2
1781 if (N0C && N1C && !N1C->isNullValue())
1782 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1783 // fold (udiv x, (1 << c)) -> x >>u c
1784 if (N1C && N1C->getAPIntValue().isPowerOf2())
1785 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1786 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1787 getShiftAmountTy()));
1788 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1789 if (N1.getOpcode() == ISD::SHL) {
1790 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1791 if (SHC->getAPIntValue().isPowerOf2()) {
1792 EVT ADDVT = N1.getOperand(1).getValueType();
1793 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1795 DAG.getConstant(SHC->getAPIntValue()
1798 AddToWorkList(Add.getNode());
1799 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1803 // fold (udiv x, c) -> alternate
1804 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1805 SDValue Op = BuildUDIV(N);
1806 if (Op.getNode()) return Op;
1810 if (N0.getOpcode() == ISD::UNDEF)
1811 return DAG.getConstant(0, VT);
1812 // X / undef -> undef
1813 if (N1.getOpcode() == ISD::UNDEF)
1819 SDValue DAGCombiner::visitSREM(SDNode *N) {
1820 SDValue N0 = N->getOperand(0);
1821 SDValue N1 = N->getOperand(1);
1822 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1823 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1824 EVT VT = N->getValueType(0);
1826 // fold (srem c1, c2) -> c1%c2
1827 if (N0C && N1C && !N1C->isNullValue())
1828 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1829 // If we know the sign bits of both operands are zero, strength reduce to a
1830 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1831 if (!VT.isVector()) {
1832 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1833 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1836 // If X/C can be simplified by the division-by-constant logic, lower
1837 // X%C to the equivalent of X-X/C*C.
1838 if (N1C && !N1C->isNullValue()) {
1839 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1840 AddToWorkList(Div.getNode());
1841 SDValue OptimizedDiv = combine(Div.getNode());
1842 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1843 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1845 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1846 AddToWorkList(Mul.getNode());
1852 if (N0.getOpcode() == ISD::UNDEF)
1853 return DAG.getConstant(0, VT);
1854 // X % undef -> undef
1855 if (N1.getOpcode() == ISD::UNDEF)
1861 SDValue DAGCombiner::visitUREM(SDNode *N) {
1862 SDValue N0 = N->getOperand(0);
1863 SDValue N1 = N->getOperand(1);
1864 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1865 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1866 EVT VT = N->getValueType(0);
1868 // fold (urem c1, c2) -> c1%c2
1869 if (N0C && N1C && !N1C->isNullValue())
1870 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1871 // fold (urem x, pow2) -> (and x, pow2-1)
1872 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1873 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1874 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1875 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1876 if (N1.getOpcode() == ISD::SHL) {
1877 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1878 if (SHC->getAPIntValue().isPowerOf2()) {
1880 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1881 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1883 AddToWorkList(Add.getNode());
1884 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1889 // If X/C can be simplified by the division-by-constant logic, lower
1890 // X%C to the equivalent of X-X/C*C.
1891 if (N1C && !N1C->isNullValue()) {
1892 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1893 AddToWorkList(Div.getNode());
1894 SDValue OptimizedDiv = combine(Div.getNode());
1895 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1896 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1898 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1899 AddToWorkList(Mul.getNode());
1905 if (N0.getOpcode() == ISD::UNDEF)
1906 return DAG.getConstant(0, VT);
1907 // X % undef -> undef
1908 if (N1.getOpcode() == ISD::UNDEF)
1914 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1915 SDValue N0 = N->getOperand(0);
1916 SDValue N1 = N->getOperand(1);
1917 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1918 EVT VT = N->getValueType(0);
1919 DebugLoc DL = N->getDebugLoc();
1921 // fold (mulhs x, 0) -> 0
1922 if (N1C && N1C->isNullValue())
1924 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1925 if (N1C && N1C->getAPIntValue() == 1)
1926 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1927 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1928 getShiftAmountTy()));
1929 // fold (mulhs x, undef) -> 0
1930 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1931 return DAG.getConstant(0, VT);
1933 // If the type twice as wide is legal, transform the mulhs to a wider multiply
1935 if (VT.isSimple() && !VT.isVector()) {
1936 MVT Simple = VT.getSimpleVT();
1937 unsigned SimpleSize = Simple.getSizeInBits();
1938 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
1939 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
1940 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
1941 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
1942 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
1943 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
1944 DAG.getConstant(SimpleSize, getShiftAmountTy()));
1945 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
1952 SDValue DAGCombiner::visitMULHU(SDNode *N) {
1953 SDValue N0 = N->getOperand(0);
1954 SDValue N1 = N->getOperand(1);
1955 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1956 EVT VT = N->getValueType(0);
1957 DebugLoc DL = N->getDebugLoc();
1959 // fold (mulhu x, 0) -> 0
1960 if (N1C && N1C->isNullValue())
1962 // fold (mulhu x, 1) -> 0
1963 if (N1C && N1C->getAPIntValue() == 1)
1964 return DAG.getConstant(0, N0.getValueType());
1965 // fold (mulhu x, undef) -> 0
1966 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1967 return DAG.getConstant(0, VT);
1969 // If the type twice as wide is legal, transform the mulhu to a wider multiply
1971 if (VT.isSimple() && !VT.isVector()) {
1972 MVT Simple = VT.getSimpleVT();
1973 unsigned SimpleSize = Simple.getSizeInBits();
1974 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
1975 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
1976 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
1977 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
1978 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
1979 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
1980 DAG.getConstant(SimpleSize, getShiftAmountTy()));
1981 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
1988 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1989 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1990 /// that are being performed. Return true if a simplification was made.
1992 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
1994 // If the high half is not needed, just compute the low half.
1995 bool HiExists = N->hasAnyUseOfValue(1);
1997 (!LegalOperations ||
1998 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1999 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2000 N->op_begin(), N->getNumOperands());
2001 return CombineTo(N, Res, Res);
2004 // If the low half is not needed, just compute the high half.
2005 bool LoExists = N->hasAnyUseOfValue(0);
2007 (!LegalOperations ||
2008 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2009 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2010 N->op_begin(), N->getNumOperands());
2011 return CombineTo(N, Res, Res);
2014 // If both halves are used, return as it is.
2015 if (LoExists && HiExists)
2018 // If the two computed results can be simplified separately, separate them.
2020 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2021 N->op_begin(), N->getNumOperands());
2022 AddToWorkList(Lo.getNode());
2023 SDValue LoOpt = combine(Lo.getNode());
2024 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2025 (!LegalOperations ||
2026 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2027 return CombineTo(N, LoOpt, LoOpt);
2031 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2032 N->op_begin(), N->getNumOperands());
2033 AddToWorkList(Hi.getNode());
2034 SDValue HiOpt = combine(Hi.getNode());
2035 if (HiOpt.getNode() && HiOpt != Hi &&
2036 (!LegalOperations ||
2037 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2038 return CombineTo(N, HiOpt, HiOpt);
2044 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2045 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2046 if (Res.getNode()) return Res;
2048 EVT VT = N->getValueType(0);
2049 DebugLoc DL = N->getDebugLoc();
2051 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2053 if (VT.isSimple() && !VT.isVector()) {
2054 MVT Simple = VT.getSimpleVT();
2055 unsigned SimpleSize = Simple.getSizeInBits();
2056 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2057 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2058 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2059 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2060 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2061 // Compute the high part as N1.
2062 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2063 DAG.getConstant(SimpleSize, getShiftAmountTy()));
2064 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2065 // Compute the low part as N0.
2066 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2067 return CombineTo(N, Lo, Hi);
2074 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2075 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2076 if (Res.getNode()) return Res;
2078 EVT VT = N->getValueType(0);
2079 DebugLoc DL = N->getDebugLoc();
2081 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2083 if (VT.isSimple() && !VT.isVector()) {
2084 MVT Simple = VT.getSimpleVT();
2085 unsigned SimpleSize = Simple.getSizeInBits();
2086 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2087 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2088 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2089 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2090 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2091 // Compute the high part as N1.
2092 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2093 DAG.getConstant(SimpleSize, getShiftAmountTy()));
2094 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2095 // Compute the low part as N0.
2096 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2097 return CombineTo(N, Lo, Hi);
2104 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2105 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2106 if (Res.getNode()) return Res;
2111 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2112 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2113 if (Res.getNode()) return Res;
2118 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2119 /// two operands of the same opcode, try to simplify it.
2120 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2121 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2122 EVT VT = N0.getValueType();
2123 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2125 // Bail early if none of these transforms apply.
2126 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2128 // For each of OP in AND/OR/XOR:
2129 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2130 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2131 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2132 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2134 // do not sink logical op inside of a vector extend, since it may combine
2136 EVT Op0VT = N0.getOperand(0).getValueType();
2137 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2138 N0.getOpcode() == ISD::SIGN_EXTEND ||
2139 // Avoid infinite looping with PromoteIntBinOp.
2140 (N0.getOpcode() == ISD::ANY_EXTEND &&
2141 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2142 (N0.getOpcode() == ISD::TRUNCATE &&
2143 (!TLI.isZExtFree(VT, Op0VT) ||
2144 !TLI.isTruncateFree(Op0VT, VT)) &&
2145 TLI.isTypeLegal(Op0VT))) &&
2147 Op0VT == N1.getOperand(0).getValueType() &&
2148 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2149 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2150 N0.getOperand(0).getValueType(),
2151 N0.getOperand(0), N1.getOperand(0));
2152 AddToWorkList(ORNode.getNode());
2153 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2156 // For each of OP in SHL/SRL/SRA/AND...
2157 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2158 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2159 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2160 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2161 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2162 N0.getOperand(1) == N1.getOperand(1)) {
2163 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2164 N0.getOperand(0).getValueType(),
2165 N0.getOperand(0), N1.getOperand(0));
2166 AddToWorkList(ORNode.getNode());
2167 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2168 ORNode, N0.getOperand(1));
2174 SDValue DAGCombiner::visitAND(SDNode *N) {
2175 SDValue N0 = N->getOperand(0);
2176 SDValue N1 = N->getOperand(1);
2177 SDValue LL, LR, RL, RR, CC0, CC1;
2178 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2179 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2180 EVT VT = N1.getValueType();
2181 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2184 if (VT.isVector()) {
2185 SDValue FoldedVOp = SimplifyVBinOp(N);
2186 if (FoldedVOp.getNode()) return FoldedVOp;
2189 // fold (and x, undef) -> 0
2190 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2191 return DAG.getConstant(0, VT);
2192 // fold (and c1, c2) -> c1&c2
2194 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2195 // canonicalize constant to RHS
2197 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2198 // fold (and x, -1) -> x
2199 if (N1C && N1C->isAllOnesValue())
2201 // if (and x, c) is known to be zero, return 0
2202 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2203 APInt::getAllOnesValue(BitWidth)))
2204 return DAG.getConstant(0, VT);
2206 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2207 if (RAND.getNode() != 0)
2209 // fold (and (or x, C), D) -> D if (C & D) == D
2210 if (N1C && N0.getOpcode() == ISD::OR)
2211 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2212 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2214 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2215 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2216 SDValue N0Op0 = N0.getOperand(0);
2217 APInt Mask = ~N1C->getAPIntValue();
2218 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2219 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2220 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2221 N0.getValueType(), N0Op0);
2223 // Replace uses of the AND with uses of the Zero extend node.
2226 // We actually want to replace all uses of the any_extend with the
2227 // zero_extend, to avoid duplicating things. This will later cause this
2228 // AND to be folded.
2229 CombineTo(N0.getNode(), Zext);
2230 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2233 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2234 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2235 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2236 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2238 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2239 LL.getValueType().isInteger()) {
2240 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2241 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2242 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2243 LR.getValueType(), LL, RL);
2244 AddToWorkList(ORNode.getNode());
2245 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2247 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2248 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2249 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2250 LR.getValueType(), LL, RL);
2251 AddToWorkList(ANDNode.getNode());
2252 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2254 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2255 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2256 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2257 LR.getValueType(), LL, RL);
2258 AddToWorkList(ORNode.getNode());
2259 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2262 // canonicalize equivalent to ll == rl
2263 if (LL == RR && LR == RL) {
2264 Op1 = ISD::getSetCCSwappedOperands(Op1);
2267 if (LL == RL && LR == RR) {
2268 bool isInteger = LL.getValueType().isInteger();
2269 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2270 if (Result != ISD::SETCC_INVALID &&
2271 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2272 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2277 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2278 if (N0.getOpcode() == N1.getOpcode()) {
2279 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2280 if (Tmp.getNode()) return Tmp;
2283 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2284 // fold (and (sra)) -> (and (srl)) when possible.
2285 if (!VT.isVector() &&
2286 SimplifyDemandedBits(SDValue(N, 0)))
2287 return SDValue(N, 0);
2289 // fold (zext_inreg (extload x)) -> (zextload x)
2290 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2291 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2292 EVT MemVT = LN0->getMemoryVT();
2293 // If we zero all the possible extended bits, then we can turn this into
2294 // a zextload if we are running before legalize or the operation is legal.
2295 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2296 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2297 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2298 ((!LegalOperations && !LN0->isVolatile()) ||
2299 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2300 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getDebugLoc(),
2301 LN0->getChain(), LN0->getBasePtr(),
2302 LN0->getPointerInfo(), MemVT,
2303 LN0->isVolatile(), LN0->isNonTemporal(),
2304 LN0->getAlignment());
2306 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2307 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2310 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2311 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2313 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2314 EVT MemVT = LN0->getMemoryVT();
2315 // If we zero all the possible extended bits, then we can turn this into
2316 // a zextload if we are running before legalize or the operation is legal.
2317 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2318 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2319 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2320 ((!LegalOperations && !LN0->isVolatile()) ||
2321 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2322 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getDebugLoc(),
2324 LN0->getBasePtr(), LN0->getPointerInfo(),
2326 LN0->isVolatile(), LN0->isNonTemporal(),
2327 LN0->getAlignment());
2329 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2330 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2334 // fold (and (load x), 255) -> (zextload x, i8)
2335 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2336 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2337 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2338 (N0.getOpcode() == ISD::ANY_EXTEND &&
2339 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2340 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2341 LoadSDNode *LN0 = HasAnyExt
2342 ? cast<LoadSDNode>(N0.getOperand(0))
2343 : cast<LoadSDNode>(N0);
2344 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2345 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2346 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2347 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2348 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2349 EVT LoadedVT = LN0->getMemoryVT();
2351 if (ExtVT == LoadedVT &&
2352 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2353 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2356 DAG.getExtLoad(ISD::ZEXTLOAD, LoadResultTy, LN0->getDebugLoc(),
2357 LN0->getChain(), LN0->getBasePtr(),
2358 LN0->getPointerInfo(),
2359 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2360 LN0->getAlignment());
2362 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2363 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2366 // Do not change the width of a volatile load.
2367 // Do not generate loads of non-round integer types since these can
2368 // be expensive (and would be wrong if the type is not byte sized).
2369 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2370 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2371 EVT PtrType = LN0->getOperand(1).getValueType();
2373 unsigned Alignment = LN0->getAlignment();
2374 SDValue NewPtr = LN0->getBasePtr();
2376 // For big endian targets, we need to add an offset to the pointer
2377 // to load the correct bytes. For little endian systems, we merely
2378 // need to read fewer bytes from the same pointer.
2379 if (TLI.isBigEndian()) {
2380 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2381 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2382 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2383 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2384 NewPtr, DAG.getConstant(PtrOff, PtrType));
2385 Alignment = MinAlign(Alignment, PtrOff);
2388 AddToWorkList(NewPtr.getNode());
2390 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2392 DAG.getExtLoad(ISD::ZEXTLOAD, LoadResultTy, LN0->getDebugLoc(),
2393 LN0->getChain(), NewPtr,
2394 LN0->getPointerInfo(),
2395 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2398 CombineTo(LN0, Load, Load.getValue(1));
2399 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2408 SDValue DAGCombiner::visitOR(SDNode *N) {
2409 SDValue N0 = N->getOperand(0);
2410 SDValue N1 = N->getOperand(1);
2411 SDValue LL, LR, RL, RR, CC0, CC1;
2412 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2413 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2414 EVT VT = N1.getValueType();
2417 if (VT.isVector()) {
2418 SDValue FoldedVOp = SimplifyVBinOp(N);
2419 if (FoldedVOp.getNode()) return FoldedVOp;
2422 // fold (or x, undef) -> -1
2423 if (!LegalOperations &&
2424 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
2425 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
2426 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
2428 // fold (or c1, c2) -> c1|c2
2430 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
2431 // canonicalize constant to RHS
2433 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2434 // fold (or x, 0) -> x
2435 if (N1C && N1C->isNullValue())
2437 // fold (or x, -1) -> -1
2438 if (N1C && N1C->isAllOnesValue())
2440 // fold (or x, c) -> c iff (x & ~c) == 0
2441 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2444 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2445 if (ROR.getNode() != 0)
2447 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2448 // iff (c1 & c2) == 0.
2449 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2450 isa<ConstantSDNode>(N0.getOperand(1))) {
2451 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2452 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
2453 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2454 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2455 N0.getOperand(0), N1),
2456 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2458 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2459 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2460 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2461 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2463 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2464 LL.getValueType().isInteger()) {
2465 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2466 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2467 if (cast<ConstantSDNode>(LR)->isNullValue() &&
2468 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2469 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2470 LR.getValueType(), LL, RL);
2471 AddToWorkList(ORNode.getNode());
2472 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2474 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2475 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
2476 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2477 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2478 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2479 LR.getValueType(), LL, RL);
2480 AddToWorkList(ANDNode.getNode());
2481 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2484 // canonicalize equivalent to ll == rl
2485 if (LL == RR && LR == RL) {
2486 Op1 = ISD::getSetCCSwappedOperands(Op1);
2489 if (LL == RL && LR == RR) {
2490 bool isInteger = LL.getValueType().isInteger();
2491 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2492 if (Result != ISD::SETCC_INVALID &&
2493 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2494 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2499 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2500 if (N0.getOpcode() == N1.getOpcode()) {
2501 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2502 if (Tmp.getNode()) return Tmp;
2505 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2506 if (N0.getOpcode() == ISD::AND &&
2507 N1.getOpcode() == ISD::AND &&
2508 N0.getOperand(1).getOpcode() == ISD::Constant &&
2509 N1.getOperand(1).getOpcode() == ISD::Constant &&
2510 // Don't increase # computations.
2511 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2512 // We can only do this xform if we know that bits from X that are set in C2
2513 // but not in C1 are already zero. Likewise for Y.
2514 const APInt &LHSMask =
2515 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2516 const APInt &RHSMask =
2517 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2519 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2520 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2521 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2522 N0.getOperand(0), N1.getOperand(0));
2523 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2524 DAG.getConstant(LHSMask | RHSMask, VT));
2528 // See if this is some rotate idiom.
2529 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2530 return SDValue(Rot, 0);
2532 // Simplify the operands using demanded-bits information.
2533 if (!VT.isVector() &&
2534 SimplifyDemandedBits(SDValue(N, 0)))
2535 return SDValue(N, 0);
2540 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2541 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2542 if (Op.getOpcode() == ISD::AND) {
2543 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2544 Mask = Op.getOperand(1);
2545 Op = Op.getOperand(0);
2551 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2559 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2560 // idioms for rotate, and if the target supports rotation instructions, generate
2562 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2563 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2564 EVT VT = LHS.getValueType();
2565 if (!TLI.isTypeLegal(VT)) return 0;
2567 // The target must have at least one rotate flavor.
2568 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2569 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2570 if (!HasROTL && !HasROTR) return 0;
2572 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2573 SDValue LHSShift; // The shift.
2574 SDValue LHSMask; // AND value if any.
2575 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2576 return 0; // Not part of a rotate.
2578 SDValue RHSShift; // The shift.
2579 SDValue RHSMask; // AND value if any.
2580 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2581 return 0; // Not part of a rotate.
2583 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2584 return 0; // Not shifting the same value.
2586 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2587 return 0; // Shifts must disagree.
2589 // Canonicalize shl to left side in a shl/srl pair.
2590 if (RHSShift.getOpcode() == ISD::SHL) {
2591 std::swap(LHS, RHS);
2592 std::swap(LHSShift, RHSShift);
2593 std::swap(LHSMask , RHSMask );
2596 unsigned OpSizeInBits = VT.getSizeInBits();
2597 SDValue LHSShiftArg = LHSShift.getOperand(0);
2598 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2599 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2601 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2602 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2603 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2604 RHSShiftAmt.getOpcode() == ISD::Constant) {
2605 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2606 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2607 if ((LShVal + RShVal) != OpSizeInBits)
2612 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2614 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2616 // If there is an AND of either shifted operand, apply it to the result.
2617 if (LHSMask.getNode() || RHSMask.getNode()) {
2618 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2620 if (LHSMask.getNode()) {
2621 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2622 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2624 if (RHSMask.getNode()) {
2625 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2626 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2629 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2632 return Rot.getNode();
2635 // If there is a mask here, and we have a variable shift, we can't be sure
2636 // that we're masking out the right stuff.
2637 if (LHSMask.getNode() || RHSMask.getNode())
2640 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2641 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2642 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2643 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2644 if (ConstantSDNode *SUBC =
2645 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2646 if (SUBC->getAPIntValue() == OpSizeInBits) {
2648 return DAG.getNode(ISD::ROTL, DL, VT,
2649 LHSShiftArg, LHSShiftAmt).getNode();
2651 return DAG.getNode(ISD::ROTR, DL, VT,
2652 LHSShiftArg, RHSShiftAmt).getNode();
2657 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2658 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2659 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2660 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2661 if (ConstantSDNode *SUBC =
2662 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2663 if (SUBC->getAPIntValue() == OpSizeInBits) {
2665 return DAG.getNode(ISD::ROTR, DL, VT,
2666 LHSShiftArg, RHSShiftAmt).getNode();
2668 return DAG.getNode(ISD::ROTL, DL, VT,
2669 LHSShiftArg, LHSShiftAmt).getNode();
2674 // Look for sign/zext/any-extended or truncate cases:
2675 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2676 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2677 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2678 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
2679 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2680 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2681 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2682 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
2683 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
2684 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
2685 if (RExtOp0.getOpcode() == ISD::SUB &&
2686 RExtOp0.getOperand(1) == LExtOp0) {
2687 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2689 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2690 // (rotr x, (sub 32, y))
2691 if (ConstantSDNode *SUBC =
2692 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2693 if (SUBC->getAPIntValue() == OpSizeInBits) {
2694 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
2696 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
2699 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2700 RExtOp0 == LExtOp0.getOperand(1)) {
2701 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2703 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2704 // (rotl x, (sub 32, y))
2705 if (ConstantSDNode *SUBC =
2706 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2707 if (SUBC->getAPIntValue() == OpSizeInBits) {
2708 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
2710 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
2719 SDValue DAGCombiner::visitXOR(SDNode *N) {
2720 SDValue N0 = N->getOperand(0);
2721 SDValue N1 = N->getOperand(1);
2722 SDValue LHS, RHS, CC;
2723 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2724 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2725 EVT VT = N0.getValueType();
2728 if (VT.isVector()) {
2729 SDValue FoldedVOp = SimplifyVBinOp(N);
2730 if (FoldedVOp.getNode()) return FoldedVOp;
2733 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
2734 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
2735 return DAG.getConstant(0, VT);
2736 // fold (xor x, undef) -> undef
2737 if (N0.getOpcode() == ISD::UNDEF)
2739 if (N1.getOpcode() == ISD::UNDEF)
2741 // fold (xor c1, c2) -> c1^c2
2743 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
2744 // canonicalize constant to RHS
2746 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
2747 // fold (xor x, 0) -> x
2748 if (N1C && N1C->isNullValue())
2751 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
2752 if (RXOR.getNode() != 0)
2755 // fold !(x cc y) -> (x !cc y)
2756 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2757 bool isInt = LHS.getValueType().isInteger();
2758 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2761 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
2762 switch (N0.getOpcode()) {
2764 llvm_unreachable("Unhandled SetCC Equivalent!");
2766 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
2767 case ISD::SELECT_CC:
2768 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
2769 N0.getOperand(3), NotCC);
2774 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2775 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2776 N0.getNode()->hasOneUse() &&
2777 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2778 SDValue V = N0.getOperand(0);
2779 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
2780 DAG.getConstant(1, V.getValueType()));
2781 AddToWorkList(V.getNode());
2782 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
2785 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
2786 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2787 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2788 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2789 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2790 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2791 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2792 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2793 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2794 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2797 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
2798 if (N1C && N1C->isAllOnesValue() &&
2799 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2800 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2801 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2802 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2803 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2804 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2805 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2806 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2809 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
2810 if (N1C && N0.getOpcode() == ISD::XOR) {
2811 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2812 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2814 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
2815 DAG.getConstant(N1C->getAPIntValue() ^
2816 N00C->getAPIntValue(), VT));
2818 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
2819 DAG.getConstant(N1C->getAPIntValue() ^
2820 N01C->getAPIntValue(), VT));
2822 // fold (xor x, x) -> 0
2824 if (!VT.isVector()) {
2825 return DAG.getConstant(0, VT);
2826 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){
2827 // Produce a vector of zeros.
2828 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
2829 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
2830 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
2831 &Ops[0], Ops.size());
2835 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2836 if (N0.getOpcode() == N1.getOpcode()) {
2837 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2838 if (Tmp.getNode()) return Tmp;
2841 // Simplify the expression using non-local knowledge.
2842 if (!VT.isVector() &&
2843 SimplifyDemandedBits(SDValue(N, 0)))
2844 return SDValue(N, 0);
2849 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2850 /// the shift amount is a constant.
2851 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2852 SDNode *LHS = N->getOperand(0).getNode();
2853 if (!LHS->hasOneUse()) return SDValue();
2855 // We want to pull some binops through shifts, so that we have (and (shift))
2856 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2857 // thing happens with address calculations, so it's important to canonicalize
2859 bool HighBitSet = false; // Can we transform this if the high bit is set?
2861 switch (LHS->getOpcode()) {
2862 default: return SDValue();
2865 HighBitSet = false; // We can only transform sra if the high bit is clear.
2868 HighBitSet = true; // We can only transform sra if the high bit is set.
2871 if (N->getOpcode() != ISD::SHL)
2872 return SDValue(); // only shl(add) not sr[al](add).
2873 HighBitSet = false; // We can only transform sra if the high bit is clear.
2877 // We require the RHS of the binop to be a constant as well.
2878 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2879 if (!BinOpCst) return SDValue();
2881 // FIXME: disable this unless the input to the binop is a shift by a constant.
2882 // If it is not a shift, it pessimizes some common cases like:
2884 // void foo(int *X, int i) { X[i & 1235] = 1; }
2885 // int bar(int *X, int i) { return X[i & 255]; }
2886 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
2887 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2888 BinOpLHSVal->getOpcode() != ISD::SRA &&
2889 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2890 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2893 EVT VT = N->getValueType(0);
2895 // If this is a signed shift right, and the high bit is modified by the
2896 // logical operation, do not perform the transformation. The highBitSet
2897 // boolean indicates the value of the high bit of the constant which would
2898 // cause it to be modified for this operation.
2899 if (N->getOpcode() == ISD::SRA) {
2900 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
2901 if (BinOpRHSSignSet != HighBitSet)
2905 // Fold the constants, shifting the binop RHS by the shift amount.
2906 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
2908 LHS->getOperand(1), N->getOperand(1));
2910 // Create the new shift.
2911 SDValue NewShift = DAG.getNode(N->getOpcode(),
2912 LHS->getOperand(0).getDebugLoc(),
2913 VT, LHS->getOperand(0), N->getOperand(1));
2915 // Create the new binop.
2916 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
2919 SDValue DAGCombiner::visitSHL(SDNode *N) {
2920 SDValue N0 = N->getOperand(0);
2921 SDValue N1 = N->getOperand(1);
2922 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2923 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2924 EVT VT = N0.getValueType();
2925 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
2927 // fold (shl c1, c2) -> c1<<c2
2929 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
2930 // fold (shl 0, x) -> 0
2931 if (N0C && N0C->isNullValue())
2933 // fold (shl x, c >= size(x)) -> undef
2934 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2935 return DAG.getUNDEF(VT);
2936 // fold (shl x, 0) -> x
2937 if (N1C && N1C->isNullValue())
2939 // if (shl x, c) is known to be zero, return 0
2940 if (DAG.MaskedValueIsZero(SDValue(N, 0),
2941 APInt::getAllOnesValue(OpSizeInBits)))
2942 return DAG.getConstant(0, VT);
2943 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
2944 if (N1.getOpcode() == ISD::TRUNCATE &&
2945 N1.getOperand(0).getOpcode() == ISD::AND &&
2946 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2947 SDValue N101 = N1.getOperand(0).getOperand(1);
2948 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2949 EVT TruncVT = N1.getValueType();
2950 SDValue N100 = N1.getOperand(0).getOperand(0);
2951 APInt TruncC = N101C->getAPIntValue();
2952 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
2953 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
2954 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
2955 DAG.getNode(ISD::TRUNCATE,
2958 DAG.getConstant(TruncC, TruncVT)));
2962 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2963 return SDValue(N, 0);
2965 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
2966 if (N1C && N0.getOpcode() == ISD::SHL &&
2967 N0.getOperand(1).getOpcode() == ISD::Constant) {
2968 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2969 uint64_t c2 = N1C->getZExtValue();
2970 if (c1 + c2 > OpSizeInBits)
2971 return DAG.getConstant(0, VT);
2972 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
2973 DAG.getConstant(c1 + c2, N1.getValueType()));
2975 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
2976 // (srl (and x, (shl -1, c1)), (sub c1, c2))
2977 if (N1C && N0.getOpcode() == ISD::SRL &&
2978 N0.getOperand(1).getOpcode() == ISD::Constant) {
2979 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2980 if (c1 < VT.getSizeInBits()) {
2981 uint64_t c2 = N1C->getZExtValue();
2982 SDValue HiBitsMask =
2983 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
2984 VT.getSizeInBits() - c1),
2986 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT,
2990 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask,
2991 DAG.getConstant(c2-c1, N1.getValueType()));
2993 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask,
2994 DAG.getConstant(c1-c2, N1.getValueType()));
2997 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
2998 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
2999 SDValue HiBitsMask =
3000 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3001 VT.getSizeInBits() -
3002 N1C->getZExtValue()),
3004 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3009 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3010 if (NewSHL.getNode())
3017 SDValue DAGCombiner::visitSRA(SDNode *N) {
3018 SDValue N0 = N->getOperand(0);
3019 SDValue N1 = N->getOperand(1);
3020 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3021 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3022 EVT VT = N0.getValueType();
3023 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3025 // fold (sra c1, c2) -> (sra c1, c2)
3027 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3028 // fold (sra 0, x) -> 0
3029 if (N0C && N0C->isNullValue())
3031 // fold (sra -1, x) -> -1
3032 if (N0C && N0C->isAllOnesValue())
3034 // fold (sra x, (setge c, size(x))) -> undef
3035 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3036 return DAG.getUNDEF(VT);
3037 // fold (sra x, 0) -> x
3038 if (N1C && N1C->isNullValue())
3040 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3042 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3043 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3044 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3046 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3047 ExtVT, VT.getVectorNumElements());
3048 if ((!LegalOperations ||
3049 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3050 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3051 N0.getOperand(0), DAG.getValueType(ExtVT));
3054 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3055 if (N1C && N0.getOpcode() == ISD::SRA) {
3056 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3057 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3058 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3059 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3060 DAG.getConstant(Sum, N1C->getValueType(0)));
3064 // fold (sra (shl X, m), (sub result_size, n))
3065 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3066 // result_size - n != m.
3067 // If truncate is free for the target sext(shl) is likely to result in better
3069 if (N0.getOpcode() == ISD::SHL) {
3070 // Get the two constanst of the shifts, CN0 = m, CN = n.
3071 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3073 // Determine what the truncate's result bitsize and type would be.
3075 EVT::getIntegerVT(*DAG.getContext(),
3076 OpSizeInBits - N1C->getZExtValue());
3077 // Determine the residual right-shift amount.
3078 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3080 // If the shift is not a no-op (in which case this should be just a sign
3081 // extend already), the truncated to type is legal, sign_extend is legal
3082 // on that type, and the truncate to that type is both legal and free,
3083 // perform the transform.
3084 if ((ShiftAmt > 0) &&
3085 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3086 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3087 TLI.isTruncateFree(VT, TruncVT)) {
3089 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy());
3090 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3091 N0.getOperand(0), Amt);
3092 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3094 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3095 N->getValueType(0), Trunc);
3100 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3101 if (N1.getOpcode() == ISD::TRUNCATE &&
3102 N1.getOperand(0).getOpcode() == ISD::AND &&
3103 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3104 SDValue N101 = N1.getOperand(0).getOperand(1);
3105 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3106 EVT TruncVT = N1.getValueType();
3107 SDValue N100 = N1.getOperand(0).getOperand(0);
3108 APInt TruncC = N101C->getAPIntValue();
3109 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3110 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3111 DAG.getNode(ISD::AND, N->getDebugLoc(),
3113 DAG.getNode(ISD::TRUNCATE,
3116 DAG.getConstant(TruncC, TruncVT)));
3120 // Simplify, based on bits shifted out of the LHS.
3121 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3122 return SDValue(N, 0);
3125 // If the sign bit is known to be zero, switch this to a SRL.
3126 if (DAG.SignBitIsZero(N0))
3127 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3130 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3131 if (NewSRA.getNode())
3138 SDValue DAGCombiner::visitSRL(SDNode *N) {
3139 SDValue N0 = N->getOperand(0);
3140 SDValue N1 = N->getOperand(1);
3141 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3142 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3143 EVT VT = N0.getValueType();
3144 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3146 // fold (srl c1, c2) -> c1 >>u c2
3148 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3149 // fold (srl 0, x) -> 0
3150 if (N0C && N0C->isNullValue())
3152 // fold (srl x, c >= size(x)) -> undef
3153 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3154 return DAG.getUNDEF(VT);
3155 // fold (srl x, 0) -> x
3156 if (N1C && N1C->isNullValue())
3158 // if (srl x, c) is known to be zero, return 0
3159 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3160 APInt::getAllOnesValue(OpSizeInBits)))
3161 return DAG.getConstant(0, VT);
3163 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3164 if (N1C && N0.getOpcode() == ISD::SRL &&
3165 N0.getOperand(1).getOpcode() == ISD::Constant) {
3166 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3167 uint64_t c2 = N1C->getZExtValue();
3168 if (c1 + c2 > OpSizeInBits)
3169 return DAG.getConstant(0, VT);
3170 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3171 DAG.getConstant(c1 + c2, N1.getValueType()));
3174 // fold (srl (shl x, c), c) -> (and x, cst2)
3175 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3176 N0.getValueSizeInBits() <= 64) {
3177 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3178 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3179 DAG.getConstant(~0ULL >> ShAmt, VT));
3183 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3184 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3185 // Shifting in all undef bits?
3186 EVT SmallVT = N0.getOperand(0).getValueType();
3187 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3188 return DAG.getUNDEF(VT);
3190 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3191 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3192 N0.getOperand(0), N1);
3193 AddToWorkList(SmallShift.getNode());
3194 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3198 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3199 // bit, which is unmodified by sra.
3200 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3201 if (N0.getOpcode() == ISD::SRA)
3202 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3205 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3206 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3207 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3208 APInt KnownZero, KnownOne;
3209 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
3210 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
3212 // If any of the input bits are KnownOne, then the input couldn't be all
3213 // zeros, thus the result of the srl will always be zero.
3214 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3216 // If all of the bits input the to ctlz node are known to be zero, then
3217 // the result of the ctlz is "32" and the result of the shift is one.
3218 APInt UnknownBits = ~KnownZero & Mask;
3219 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3221 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3222 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3223 // Okay, we know that only that the single bit specified by UnknownBits
3224 // could be set on input to the CTLZ node. If this bit is set, the SRL
3225 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3226 // to an SRL/XOR pair, which is likely to simplify more.
3227 unsigned ShAmt = UnknownBits.countTrailingZeros();
3228 SDValue Op = N0.getOperand(0);
3231 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3232 DAG.getConstant(ShAmt, getShiftAmountTy()));
3233 AddToWorkList(Op.getNode());
3236 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3237 Op, DAG.getConstant(1, VT));
3241 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3242 if (N1.getOpcode() == ISD::TRUNCATE &&
3243 N1.getOperand(0).getOpcode() == ISD::AND &&
3244 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3245 SDValue N101 = N1.getOperand(0).getOperand(1);
3246 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3247 EVT TruncVT = N1.getValueType();
3248 SDValue N100 = N1.getOperand(0).getOperand(0);
3249 APInt TruncC = N101C->getAPIntValue();
3250 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3251 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3252 DAG.getNode(ISD::AND, N->getDebugLoc(),
3254 DAG.getNode(ISD::TRUNCATE,
3257 DAG.getConstant(TruncC, TruncVT)));
3261 // fold operands of srl based on knowledge that the low bits are not
3263 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3264 return SDValue(N, 0);
3267 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3268 if (NewSRL.getNode())
3272 // Attempt to convert a srl of a load into a narrower zero-extending load.
3273 SDValue NarrowLoad = ReduceLoadWidth(N);
3274 if (NarrowLoad.getNode())
3277 // Here is a common situation. We want to optimize:
3280 // %b = and i32 %a, 2
3281 // %c = srl i32 %b, 1
3282 // brcond i32 %c ...
3288 // %c = setcc eq %b, 0
3291 // However when after the source operand of SRL is optimized into AND, the SRL
3292 // itself may not be optimized further. Look for it and add the BRCOND into
3294 if (N->hasOneUse()) {
3295 SDNode *Use = *N->use_begin();
3296 if (Use->getOpcode() == ISD::BRCOND)
3298 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3299 // Also look pass the truncate.
3300 Use = *Use->use_begin();
3301 if (Use->getOpcode() == ISD::BRCOND)
3309 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
3310 SDValue N0 = N->getOperand(0);
3311 EVT VT = N->getValueType(0);
3313 // fold (ctlz c1) -> c2
3314 if (isa<ConstantSDNode>(N0))
3315 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3319 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
3320 SDValue N0 = N->getOperand(0);
3321 EVT VT = N->getValueType(0);
3323 // fold (cttz c1) -> c2
3324 if (isa<ConstantSDNode>(N0))
3325 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
3329 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
3330 SDValue N0 = N->getOperand(0);
3331 EVT VT = N->getValueType(0);
3333 // fold (ctpop c1) -> c2
3334 if (isa<ConstantSDNode>(N0))
3335 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
3339 SDValue DAGCombiner::visitSELECT(SDNode *N) {
3340 SDValue N0 = N->getOperand(0);
3341 SDValue N1 = N->getOperand(1);
3342 SDValue N2 = N->getOperand(2);
3343 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3344 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3345 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
3346 EVT VT = N->getValueType(0);
3347 EVT VT0 = N0.getValueType();
3349 // fold (select C, X, X) -> X
3352 // fold (select true, X, Y) -> X
3353 if (N0C && !N0C->isNullValue())
3355 // fold (select false, X, Y) -> Y
3356 if (N0C && N0C->isNullValue())
3358 // fold (select C, 1, X) -> (or C, X)
3359 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
3360 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3361 // fold (select C, 0, 1) -> (xor C, 1)
3362 if (VT.isInteger() &&
3365 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
3366 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
3369 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
3370 N0, DAG.getConstant(1, VT0));
3371 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
3372 N0, DAG.getConstant(1, VT0));
3373 AddToWorkList(XORNode.getNode());
3375 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
3376 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
3378 // fold (select C, 0, X) -> (and (not C), X)
3379 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
3380 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3381 AddToWorkList(NOTNode.getNode());
3382 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
3384 // fold (select C, X, 1) -> (or (not C), X)
3385 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
3386 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3387 AddToWorkList(NOTNode.getNode());
3388 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
3390 // fold (select C, X, 0) -> (and C, X)
3391 if (VT == MVT::i1 && N2C && N2C->isNullValue())
3392 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3393 // fold (select X, X, Y) -> (or X, Y)
3394 // fold (select X, 1, Y) -> (or X, Y)
3395 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
3396 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3397 // fold (select X, Y, X) -> (and X, Y)
3398 // fold (select X, Y, 0) -> (and X, Y)
3399 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
3400 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3402 // If we can fold this based on the true/false value, do so.
3403 if (SimplifySelectOps(N, N1, N2))
3404 return SDValue(N, 0); // Don't revisit N.
3406 // fold selects based on a setcc into other things, such as min/max/abs
3407 if (N0.getOpcode() == ISD::SETCC) {
3409 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
3410 // having to say they don't support SELECT_CC on every type the DAG knows
3411 // about, since there is no way to mark an opcode illegal at all value types
3412 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
3413 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
3414 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
3415 N0.getOperand(0), N0.getOperand(1),
3416 N1, N2, N0.getOperand(2));
3417 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
3423 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
3424 SDValue N0 = N->getOperand(0);
3425 SDValue N1 = N->getOperand(1);
3426 SDValue N2 = N->getOperand(2);
3427 SDValue N3 = N->getOperand(3);
3428 SDValue N4 = N->getOperand(4);
3429 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
3431 // fold select_cc lhs, rhs, x, x, cc -> x
3435 // Determine if the condition we're dealing with is constant
3436 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
3437 N0, N1, CC, N->getDebugLoc(), false);
3438 if (SCC.getNode()) AddToWorkList(SCC.getNode());
3440 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
3441 if (!SCCC->isNullValue())
3442 return N2; // cond always true -> true val
3444 return N3; // cond always false -> false val
3447 // Fold to a simpler select_cc
3448 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
3449 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
3450 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
3453 // If we can fold this based on the true/false value, do so.
3454 if (SimplifySelectOps(N, N2, N3))
3455 return SDValue(N, 0); // Don't revisit N.
3457 // fold select_cc into other things, such as min/max/abs
3458 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
3461 SDValue DAGCombiner::visitSETCC(SDNode *N) {
3462 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
3463 cast<CondCodeSDNode>(N->getOperand(2))->get(),
3467 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
3468 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
3469 // transformation. Returns true if extension are possible and the above
3470 // mentioned transformation is profitable.
3471 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
3473 SmallVector<SDNode*, 4> &ExtendNodes,
3474 const TargetLowering &TLI) {
3475 bool HasCopyToRegUses = false;
3476 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
3477 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3478 UE = N0.getNode()->use_end();
3483 if (UI.getUse().getResNo() != N0.getResNo())
3485 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
3486 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
3487 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
3488 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
3489 // Sign bits will be lost after a zext.
3492 for (unsigned i = 0; i != 2; ++i) {
3493 SDValue UseOp = User->getOperand(i);
3496 if (!isa<ConstantSDNode>(UseOp))
3501 ExtendNodes.push_back(User);
3504 // If truncates aren't free and there are users we can't
3505 // extend, it isn't worthwhile.
3508 // Remember if this value is live-out.
3509 if (User->getOpcode() == ISD::CopyToReg)
3510 HasCopyToRegUses = true;
3513 if (HasCopyToRegUses) {
3514 bool BothLiveOut = false;
3515 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3517 SDUse &Use = UI.getUse();
3518 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
3524 // Both unextended and extended values are live out. There had better be
3525 // a good reason for the transformation.
3526 return ExtendNodes.size();
3531 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
3532 SDValue N0 = N->getOperand(0);
3533 EVT VT = N->getValueType(0);
3535 // fold (sext c1) -> c1
3536 if (isa<ConstantSDNode>(N0))
3537 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
3539 // fold (sext (sext x)) -> (sext x)
3540 // fold (sext (aext x)) -> (sext x)
3541 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3542 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
3545 if (N0.getOpcode() == ISD::TRUNCATE) {
3546 // fold (sext (truncate (load x))) -> (sext (smaller load x))
3547 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
3548 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3549 if (NarrowLoad.getNode()) {
3550 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3551 if (NarrowLoad.getNode() != N0.getNode()) {
3552 CombineTo(N0.getNode(), NarrowLoad);
3553 // CombineTo deleted the truncate, if needed, but not what's under it.
3556 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3559 // See if the value being truncated is already sign extended. If so, just
3560 // eliminate the trunc/sext pair.
3561 SDValue Op = N0.getOperand(0);
3562 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
3563 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
3564 unsigned DestBits = VT.getScalarType().getSizeInBits();
3565 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
3567 if (OpBits == DestBits) {
3568 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
3569 // bits, it is already ready.
3570 if (NumSignBits > DestBits-MidBits)
3572 } else if (OpBits < DestBits) {
3573 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
3574 // bits, just sext from i32.
3575 if (NumSignBits > OpBits-MidBits)
3576 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
3578 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
3579 // bits, just truncate to i32.
3580 if (NumSignBits > OpBits-MidBits)
3581 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3584 // fold (sext (truncate x)) -> (sextinreg x).
3585 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
3586 N0.getValueType())) {
3587 if (OpBits < DestBits)
3588 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
3589 else if (OpBits > DestBits)
3590 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
3591 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
3592 DAG.getValueType(N0.getValueType()));
3596 // fold (sext (load x)) -> (sext (truncate (sextload x)))
3597 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3598 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3599 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
3600 bool DoXform = true;
3601 SmallVector<SDNode*, 4> SetCCs;
3602 if (!N0.hasOneUse())
3603 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
3605 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3606 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
3608 LN0->getBasePtr(), LN0->getPointerInfo(),
3610 LN0->isVolatile(), LN0->isNonTemporal(),
3611 LN0->getAlignment());
3612 CombineTo(N, ExtLoad);
3613 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3614 N0.getValueType(), ExtLoad);
3615 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3617 // Extend SetCC uses if necessary.
3618 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3619 SDNode *SetCC = SetCCs[i];
3620 SmallVector<SDValue, 4> Ops;
3622 for (unsigned j = 0; j != 2; ++j) {
3623 SDValue SOp = SetCC->getOperand(j);
3625 Ops.push_back(ExtLoad);
3627 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND,
3628 N->getDebugLoc(), VT, SOp));
3631 Ops.push_back(SetCC->getOperand(2));
3632 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3633 SetCC->getValueType(0),
3634 &Ops[0], Ops.size()));
3637 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3641 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
3642 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
3643 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3644 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3645 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3646 EVT MemVT = LN0->getMemoryVT();
3647 if ((!LegalOperations && !LN0->isVolatile()) ||
3648 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
3649 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
3651 LN0->getBasePtr(), LN0->getPointerInfo(),
3653 LN0->isVolatile(), LN0->isNonTemporal(),
3654 LN0->getAlignment());
3655 CombineTo(N, ExtLoad);
3656 CombineTo(N0.getNode(),
3657 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3658 N0.getValueType(), ExtLoad),
3659 ExtLoad.getValue(1));
3660 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3664 if (N0.getOpcode() == ISD::SETCC) {
3665 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
3666 // Only do this before legalize for now.
3667 if (VT.isVector() && !LegalOperations) {
3668 EVT N0VT = N0.getOperand(0).getValueType();
3669 // We know that the # elements of the results is the same as the
3670 // # elements of the compare (and the # elements of the compare result
3671 // for that matter). Check to see that they are the same size. If so,
3672 // we know that the element size of the sext'd result matches the
3673 // element size of the compare operands.
3674 if (VT.getSizeInBits() == N0VT.getSizeInBits())
3675 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3677 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3678 // If the desired elements are smaller or larger than the source
3679 // elements we can use a matching integer vector type and then
3680 // truncate/sign extend
3682 EVT MatchingElementType =
3683 EVT::getIntegerVT(*DAG.getContext(),
3684 N0VT.getScalarType().getSizeInBits());
3685 EVT MatchingVectorType =
3686 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
3687 N0VT.getVectorNumElements());
3689 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
3691 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3692 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
3696 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
3697 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
3699 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
3701 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3702 NegOne, DAG.getConstant(0, VT),
3703 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3704 if (SCC.getNode()) return SCC;
3705 if (!LegalOperations ||
3706 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
3707 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
3708 DAG.getSetCC(N->getDebugLoc(),
3709 TLI.getSetCCResultType(VT),
3710 N0.getOperand(0), N0.getOperand(1),
3711 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
3712 NegOne, DAG.getConstant(0, VT));
3715 // fold (sext x) -> (zext x) if the sign bit is known zero.
3716 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
3717 DAG.SignBitIsZero(N0))
3718 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3723 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
3724 SDValue N0 = N->getOperand(0);
3725 EVT VT = N->getValueType(0);
3727 // fold (zext c1) -> c1
3728 if (isa<ConstantSDNode>(N0))
3729 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3730 // fold (zext (zext x)) -> (zext x)
3731 // fold (zext (aext x)) -> (zext x)
3732 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3733 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
3736 // fold (zext (truncate (load x))) -> (zext (smaller load x))
3737 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
3738 if (N0.getOpcode() == ISD::TRUNCATE) {
3739 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3740 if (NarrowLoad.getNode()) {
3741 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3742 if (NarrowLoad.getNode() != N0.getNode()) {
3743 CombineTo(N0.getNode(), NarrowLoad);
3744 // CombineTo deleted the truncate, if needed, but not what's under it.
3747 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3751 // fold (zext (truncate x)) -> (and x, mask)
3752 if (N0.getOpcode() == ISD::TRUNCATE &&
3753 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
3755 // fold (zext (truncate (load x))) -> (zext (smaller load x))
3756 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
3757 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3758 if (NarrowLoad.getNode()) {
3759 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3760 if (NarrowLoad.getNode() != N0.getNode()) {
3761 CombineTo(N0.getNode(), NarrowLoad);
3762 // CombineTo deleted the truncate, if needed, but not what's under it.
3765 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3768 SDValue Op = N0.getOperand(0);
3769 if (Op.getValueType().bitsLT(VT)) {
3770 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
3771 } else if (Op.getValueType().bitsGT(VT)) {
3772 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3774 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
3775 N0.getValueType().getScalarType());
3778 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
3779 // if either of the casts is not free.
3780 if (N0.getOpcode() == ISD::AND &&
3781 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3782 N0.getOperand(1).getOpcode() == ISD::Constant &&
3783 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3784 N0.getValueType()) ||
3785 !TLI.isZExtFree(N0.getValueType(), VT))) {
3786 SDValue X = N0.getOperand(0).getOperand(0);
3787 if (X.getValueType().bitsLT(VT)) {
3788 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
3789 } else if (X.getValueType().bitsGT(VT)) {
3790 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3792 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3793 Mask = Mask.zext(VT.getSizeInBits());
3794 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3795 X, DAG.getConstant(Mask, VT));
3798 // fold (zext (load x)) -> (zext (truncate (zextload x)))
3799 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3800 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3801 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
3802 bool DoXform = true;
3803 SmallVector<SDNode*, 4> SetCCs;
3804 if (!N0.hasOneUse())
3805 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
3807 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3808 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N->getDebugLoc(),
3810 LN0->getBasePtr(), LN0->getPointerInfo(),
3812 LN0->isVolatile(), LN0->isNonTemporal(),
3813 LN0->getAlignment());
3814 CombineTo(N, ExtLoad);
3815 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3816 N0.getValueType(), ExtLoad);
3817 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3819 // Extend SetCC uses if necessary.
3820 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3821 SDNode *SetCC = SetCCs[i];
3822 SmallVector<SDValue, 4> Ops;
3824 for (unsigned j = 0; j != 2; ++j) {
3825 SDValue SOp = SetCC->getOperand(j);
3827 Ops.push_back(ExtLoad);
3829 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND,
3830 N->getDebugLoc(), VT, SOp));
3833 Ops.push_back(SetCC->getOperand(2));
3834 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3835 SetCC->getValueType(0),
3836 &Ops[0], Ops.size()));
3839 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3843 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
3844 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
3845 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3846 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3847 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3848 EVT MemVT = LN0->getMemoryVT();
3849 if ((!LegalOperations && !LN0->isVolatile()) ||
3850 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
3851 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N->getDebugLoc(),
3853 LN0->getBasePtr(), LN0->getPointerInfo(),
3855 LN0->isVolatile(), LN0->isNonTemporal(),
3856 LN0->getAlignment());
3857 CombineTo(N, ExtLoad);
3858 CombineTo(N0.getNode(),
3859 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
3861 ExtLoad.getValue(1));
3862 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3866 if (N0.getOpcode() == ISD::SETCC) {
3867 if (!LegalOperations && VT.isVector()) {
3868 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
3869 // Only do this before legalize for now.
3870 EVT N0VT = N0.getOperand(0).getValueType();
3871 EVT EltVT = VT.getVectorElementType();
3872 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
3873 DAG.getConstant(1, EltVT));
3874 if (VT.getSizeInBits() == N0VT.getSizeInBits()) {
3875 // We know that the # elements of the results is the same as the
3876 // # elements of the compare (and the # elements of the compare result
3877 // for that matter). Check to see that they are the same size. If so,
3878 // we know that the element size of the sext'd result matches the
3879 // element size of the compare operands.
3880 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3881 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3883 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
3884 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
3885 &OneOps[0], OneOps.size()));
3887 // If the desired elements are smaller or larger than the source
3888 // elements we can use a matching integer vector type and then
3889 // truncate/sign extend
3890 EVT MatchingElementType =
3891 EVT::getIntegerVT(*DAG.getContext(),
3892 N0VT.getScalarType().getSizeInBits());
3893 EVT MatchingVectorType =
3894 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
3895 N0VT.getVectorNumElements());
3897 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
3899 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3900 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3901 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
3902 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
3903 &OneOps[0], OneOps.size()));
3907 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3909 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3910 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3911 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3912 if (SCC.getNode()) return SCC;
3915 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
3916 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
3917 isa<ConstantSDNode>(N0.getOperand(1)) &&
3918 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
3920 if (N0.getOpcode() == ISD::SHL) {
3921 // If the original shl may be shifting out bits, do not perform this
3923 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3924 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() -
3925 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits();
3926 if (ShAmt > KnownZeroBits)
3929 DebugLoc dl = N->getDebugLoc();
3930 return DAG.getNode(N0.getOpcode(), dl, VT,
3931 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)),
3932 DAG.getNode(ISD::ZERO_EXTEND, dl,
3933 N0.getOperand(1).getValueType(),
3940 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
3941 SDValue N0 = N->getOperand(0);
3942 EVT VT = N->getValueType(0);
3944 // fold (aext c1) -> c1
3945 if (isa<ConstantSDNode>(N0))
3946 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
3947 // fold (aext (aext x)) -> (aext x)
3948 // fold (aext (zext x)) -> (zext x)
3949 // fold (aext (sext x)) -> (sext x)
3950 if (N0.getOpcode() == ISD::ANY_EXTEND ||
3951 N0.getOpcode() == ISD::ZERO_EXTEND ||
3952 N0.getOpcode() == ISD::SIGN_EXTEND)
3953 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
3955 // fold (aext (truncate (load x))) -> (aext (smaller load x))
3956 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
3957 if (N0.getOpcode() == ISD::TRUNCATE) {
3958 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3959 if (NarrowLoad.getNode()) {
3960 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3961 if (NarrowLoad.getNode() != N0.getNode()) {
3962 CombineTo(N0.getNode(), NarrowLoad);
3963 // CombineTo deleted the truncate, if needed, but not what's under it.
3966 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3970 // fold (aext (truncate x))
3971 if (N0.getOpcode() == ISD::TRUNCATE) {
3972 SDValue TruncOp = N0.getOperand(0);
3973 if (TruncOp.getValueType() == VT)
3974 return TruncOp; // x iff x size == zext size.
3975 if (TruncOp.getValueType().bitsGT(VT))
3976 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
3977 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
3980 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
3981 // if the trunc is not free.
3982 if (N0.getOpcode() == ISD::AND &&
3983 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3984 N0.getOperand(1).getOpcode() == ISD::Constant &&
3985 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3986 N0.getValueType())) {
3987 SDValue X = N0.getOperand(0).getOperand(0);
3988 if (X.getValueType().bitsLT(VT)) {
3989 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
3990 } else if (X.getValueType().bitsGT(VT)) {
3991 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
3993 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3994 Mask = Mask.zext(VT.getSizeInBits());
3995 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3996 X, DAG.getConstant(Mask, VT));
3999 // fold (aext (load x)) -> (aext (truncate (extload x)))
4000 if (ISD::isNON_EXTLoad(N0.getNode()) &&
4001 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4002 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4003 bool DoXform = true;
4004 SmallVector<SDNode*, 4> SetCCs;
4005 if (!N0.hasOneUse())
4006 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4008 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4009 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N->getDebugLoc(),
4011 LN0->getBasePtr(), LN0->getPointerInfo(),
4013 LN0->isVolatile(), LN0->isNonTemporal(),
4014 LN0->getAlignment());
4015 CombineTo(N, ExtLoad);
4016 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4017 N0.getValueType(), ExtLoad);
4018 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4020 // Extend SetCC uses if necessary.
4021 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
4022 SDNode *SetCC = SetCCs[i];
4023 SmallVector<SDValue, 4> Ops;
4025 for (unsigned j = 0; j != 2; ++j) {
4026 SDValue SOp = SetCC->getOperand(j);
4028 Ops.push_back(ExtLoad);
4030 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND,
4031 N->getDebugLoc(), VT, SOp));
4034 Ops.push_back(SetCC->getOperand(2));
4035 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
4036 SetCC->getValueType(0),
4037 &Ops[0], Ops.size()));
4040 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4044 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
4045 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4046 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
4047 if (N0.getOpcode() == ISD::LOAD &&
4048 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4050 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4051 EVT MemVT = LN0->getMemoryVT();
4052 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
4054 LN0->getChain(), LN0->getBasePtr(),
4055 LN0->getPointerInfo(), MemVT,
4056 LN0->isVolatile(), LN0->isNonTemporal(),
4057 LN0->getAlignment());
4058 CombineTo(N, ExtLoad);
4059 CombineTo(N0.getNode(),
4060 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4061 N0.getValueType(), ExtLoad),
4062 ExtLoad.getValue(1));
4063 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4066 if (N0.getOpcode() == ISD::SETCC) {
4067 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
4068 // Only do this before legalize for now.
4069 if (VT.isVector() && !LegalOperations) {
4070 EVT N0VT = N0.getOperand(0).getValueType();
4071 // We know that the # elements of the results is the same as the
4072 // # elements of the compare (and the # elements of the compare result
4073 // for that matter). Check to see that they are the same size. If so,
4074 // we know that the element size of the sext'd result matches the
4075 // element size of the compare operands.
4076 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4077 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4079 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4080 // If the desired elements are smaller or larger than the source
4081 // elements we can use a matching integer vector type and then
4082 // truncate/sign extend
4084 EVT MatchingElementType =
4085 EVT::getIntegerVT(*DAG.getContext(),
4086 N0VT.getScalarType().getSizeInBits());
4087 EVT MatchingVectorType =
4088 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4089 N0VT.getVectorNumElements());
4091 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4093 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4094 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4098 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4100 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4101 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4102 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4110 /// GetDemandedBits - See if the specified operand can be simplified with the
4111 /// knowledge that only the bits specified by Mask are used. If so, return the
4112 /// simpler operand, otherwise return a null SDValue.
4113 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4114 switch (V.getOpcode()) {
4118 // If the LHS or RHS don't contribute bits to the or, drop them.
4119 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4120 return V.getOperand(1);
4121 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4122 return V.getOperand(0);
4125 // Only look at single-use SRLs.
4126 if (!V.getNode()->hasOneUse())
4128 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4129 // See if we can recursively simplify the LHS.
4130 unsigned Amt = RHSC->getZExtValue();
4132 // Watch out for shift count overflow though.
4133 if (Amt >= Mask.getBitWidth()) break;
4134 APInt NewMask = Mask << Amt;
4135 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4136 if (SimplifyLHS.getNode())
4137 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4138 SimplifyLHS, V.getOperand(1));
4144 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
4145 /// bits and then truncated to a narrower type and where N is a multiple
4146 /// of number of bits of the narrower type, transform it to a narrower load
4147 /// from address + N / num of bits of new type. If the result is to be
4148 /// extended, also fold the extension to form a extending load.
4149 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
4150 unsigned Opc = N->getOpcode();
4152 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4153 SDValue N0 = N->getOperand(0);
4154 EVT VT = N->getValueType(0);
4157 // This transformation isn't valid for vector loads.
4161 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4163 if (Opc == ISD::SIGN_EXTEND_INREG) {
4164 ExtType = ISD::SEXTLOAD;
4165 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4166 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT))
4168 } else if (Opc == ISD::SRL) {
4169 // Annother special-case: SRL is basically zero-extending a narrower
4171 ExtType = ISD::ZEXTLOAD;
4173 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4174 if (!N01) return SDValue();
4175 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
4176 VT.getSizeInBits() - N01->getZExtValue());
4179 unsigned EVTBits = ExtVT.getSizeInBits();
4181 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) {
4182 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4183 ShAmt = N01->getZExtValue();
4184 // Is the shift amount a multiple of size of VT?
4185 if ((ShAmt & (EVTBits-1)) == 0) {
4186 N0 = N0.getOperand(0);
4187 // Is the load width a multiple of size of VT?
4188 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
4192 // If the shift amount is larger than the input type then we're not
4193 // accessing any of the loaded bytes. If the load was a zextload/extload
4194 // then the result of the shift+trunc is zero/undef (handled elsewhere).
4195 // If the load was a sextload then the result is a splat of the sign bit
4196 // of the extended byte. This is not worth optimizing for.
4197 if (ShAmt >= VT.getSizeInBits())
4203 // If the load is shifted left (and the result isn't shifted back right),
4204 // we can fold the truncate through the shift.
4205 unsigned ShLeftAmt = 0;
4206 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
4208 TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
4209 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4210 ShLeftAmt = N01->getZExtValue();
4211 N0 = N0.getOperand(0);
4215 // Do not generate loads of non-round integer types since these can
4216 // be expensive (and would be wrong if the type is not byte sized).
4217 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() &&
4218 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() >= EVTBits &&
4219 // Do not change the width of a volatile load.
4220 !cast<LoadSDNode>(N0)->isVolatile()) {
4221 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4222 EVT PtrType = N0.getOperand(1).getValueType();
4224 // For big endian targets, we need to adjust the offset to the pointer to
4225 // load the correct bytes.
4226 if (TLI.isBigEndian()) {
4227 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
4228 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
4229 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
4232 uint64_t PtrOff = ShAmt / 8;
4233 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
4234 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
4235 PtrType, LN0->getBasePtr(),
4236 DAG.getConstant(PtrOff, PtrType));
4237 AddToWorkList(NewPtr.getNode());
4239 SDValue Load = (ExtType == ISD::NON_EXTLOAD)
4240 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
4241 LN0->getPointerInfo().getWithOffset(PtrOff),
4242 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign)
4243 : DAG.getExtLoad(ExtType, VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
4244 LN0->getPointerInfo().getWithOffset(PtrOff),
4245 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
4248 // Replace the old load's chain with the new load's chain.
4249 WorkListRemover DeadNodes(*this);
4250 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
4253 // Shift the result left, if we've swallowed a left shift.
4254 SDValue Result = Load;
4255 if (ShLeftAmt != 0) {
4256 EVT ShImmTy = getShiftAmountTy();
4257 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
4259 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
4260 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
4263 // Return the new loaded value.
4270 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
4271 SDValue N0 = N->getOperand(0);
4272 SDValue N1 = N->getOperand(1);
4273 EVT VT = N->getValueType(0);
4274 EVT EVT = cast<VTSDNode>(N1)->getVT();
4275 unsigned VTBits = VT.getScalarType().getSizeInBits();
4276 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
4278 // fold (sext_in_reg c1) -> c1
4279 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
4280 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
4282 // If the input is already sign extended, just drop the extension.
4283 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
4286 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
4287 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4288 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
4289 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
4290 N0.getOperand(0), N1);
4293 // fold (sext_in_reg (sext x)) -> (sext x)
4294 // fold (sext_in_reg (aext x)) -> (sext x)
4295 // if x is small enough.
4296 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
4297 SDValue N00 = N0.getOperand(0);
4298 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
4299 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
4300 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
4303 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
4304 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
4305 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
4307 // fold operands of sext_in_reg based on knowledge that the top bits are not
4309 if (SimplifyDemandedBits(SDValue(N, 0)))
4310 return SDValue(N, 0);
4312 // fold (sext_in_reg (load x)) -> (smaller sextload x)
4313 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
4314 SDValue NarrowLoad = ReduceLoadWidth(N);
4315 if (NarrowLoad.getNode())
4318 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
4319 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
4320 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
4321 if (N0.getOpcode() == ISD::SRL) {
4322 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
4323 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
4324 // We can turn this into an SRA iff the input to the SRL is already sign
4326 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
4327 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
4328 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
4329 N0.getOperand(0), N0.getOperand(1));
4333 // fold (sext_inreg (extload x)) -> (sextload x)
4334 if (ISD::isEXTLoad(N0.getNode()) &&
4335 ISD::isUNINDEXEDLoad(N0.getNode()) &&
4336 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4337 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4338 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4339 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4340 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
4342 LN0->getBasePtr(), LN0->getPointerInfo(),
4344 LN0->isVolatile(), LN0->isNonTemporal(),
4345 LN0->getAlignment());
4346 CombineTo(N, ExtLoad);
4347 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4348 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4350 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
4351 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4353 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4354 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4355 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4356 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4357 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(),
4359 LN0->getBasePtr(), LN0->getPointerInfo(),
4361 LN0->isVolatile(), LN0->isNonTemporal(),
4362 LN0->getAlignment());
4363 CombineTo(N, ExtLoad);
4364 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4365 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4370 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
4371 SDValue N0 = N->getOperand(0);
4372 EVT VT = N->getValueType(0);
4375 if (N0.getValueType() == N->getValueType(0))
4377 // fold (truncate c1) -> c1
4378 if (isa<ConstantSDNode>(N0))
4379 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
4380 // fold (truncate (truncate x)) -> (truncate x)
4381 if (N0.getOpcode() == ISD::TRUNCATE)
4382 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4383 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
4384 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
4385 N0.getOpcode() == ISD::SIGN_EXTEND ||
4386 N0.getOpcode() == ISD::ANY_EXTEND) {
4387 if (N0.getOperand(0).getValueType().bitsLT(VT))
4388 // if the source is smaller than the dest, we still need an extend
4389 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4391 else if (N0.getOperand(0).getValueType().bitsGT(VT))
4392 // if the source is larger than the dest, than we just need the truncate
4393 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4395 // if the source and dest are the same type, we can drop both the extend
4396 // and the truncate.
4397 return N0.getOperand(0);
4400 // See if we can simplify the input to this truncate through knowledge that
4401 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
4404 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
4405 VT.getSizeInBits()));
4406 if (Shorter.getNode())
4407 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
4409 // fold (truncate (load x)) -> (smaller load x)
4410 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
4411 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
4412 SDValue Reduced = ReduceLoadWidth(N);
4413 if (Reduced.getNode())
4417 // Simplify the operands using demanded-bits information.
4418 if (!VT.isVector() &&
4419 SimplifyDemandedBits(SDValue(N, 0)))
4420 return SDValue(N, 0);
4425 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
4426 SDValue Elt = N->getOperand(i);
4427 if (Elt.getOpcode() != ISD::MERGE_VALUES)
4428 return Elt.getNode();
4429 return Elt.getOperand(Elt.getResNo()).getNode();
4432 /// CombineConsecutiveLoads - build_pair (load, load) -> load
4433 /// if load locations are consecutive.
4434 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
4435 assert(N->getOpcode() == ISD::BUILD_PAIR);
4437 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
4438 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
4439 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
4440 LD1->getPointerInfo().getAddrSpace() !=
4441 LD2->getPointerInfo().getAddrSpace())
4443 EVT LD1VT = LD1->getValueType(0);
4445 if (ISD::isNON_EXTLoad(LD2) &&
4447 // If both are volatile this would reduce the number of volatile loads.
4448 // If one is volatile it might be ok, but play conservative and bail out.
4449 !LD1->isVolatile() &&
4450 !LD2->isVolatile() &&
4451 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
4452 unsigned Align = LD1->getAlignment();
4453 unsigned NewAlign = TLI.getTargetData()->
4454 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4456 if (NewAlign <= Align &&
4457 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
4458 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
4459 LD1->getBasePtr(), LD1->getPointerInfo(),
4460 false, false, Align);
4466 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
4467 SDValue N0 = N->getOperand(0);
4468 EVT VT = N->getValueType(0);
4470 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
4471 // Only do this before legalize, since afterward the target may be depending
4472 // on the bitconvert.
4473 // First check to see if this is all constant.
4475 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
4477 bool isSimple = true;
4478 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
4479 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
4480 N0.getOperand(i).getOpcode() != ISD::Constant &&
4481 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
4486 EVT DestEltVT = N->getValueType(0).getVectorElementType();
4487 assert(!DestEltVT.isVector() &&
4488 "Element type of vector ValueType must not be vector!");
4490 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
4493 // If the input is a constant, let getNode fold it.
4494 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
4495 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
4496 if (Res.getNode() != N) {
4497 if (!LegalOperations ||
4498 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
4501 // Folding it resulted in an illegal node, and it's too late to
4502 // do that. Clean up the old node and forego the transformation.
4503 // Ideally this won't happen very often, because instcombine
4504 // and the earlier dagcombine runs (where illegal nodes are
4505 // permitted) should have folded most of them already.
4506 DAG.DeleteNode(Res.getNode());
4510 // (conv (conv x, t1), t2) -> (conv x, t2)
4511 if (N0.getOpcode() == ISD::BITCAST)
4512 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
4515 // fold (conv (load x)) -> (load (conv*)x)
4516 // If the resultant load doesn't need a higher alignment than the original!
4517 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
4518 // Do not change the width of a volatile load.
4519 !cast<LoadSDNode>(N0)->isVolatile() &&
4520 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
4521 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4522 unsigned Align = TLI.getTargetData()->
4523 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4524 unsigned OrigAlign = LN0->getAlignment();
4526 if (Align <= OrigAlign) {
4527 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
4528 LN0->getBasePtr(), LN0->getPointerInfo(),
4529 LN0->isVolatile(), LN0->isNonTemporal(),
4532 CombineTo(N0.getNode(),
4533 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
4534 N0.getValueType(), Load),
4540 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
4541 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
4542 // This often reduces constant pool loads.
4543 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
4544 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
4545 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
4547 AddToWorkList(NewConv.getNode());
4549 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
4550 if (N0.getOpcode() == ISD::FNEG)
4551 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
4552 NewConv, DAG.getConstant(SignBit, VT));
4553 assert(N0.getOpcode() == ISD::FABS);
4554 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4555 NewConv, DAG.getConstant(~SignBit, VT));
4558 // fold (bitconvert (fcopysign cst, x)) ->
4559 // (or (and (bitconvert x), sign), (and cst, (not sign)))
4560 // Note that we don't handle (copysign x, cst) because this can always be
4561 // folded to an fneg or fabs.
4562 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
4563 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
4564 VT.isInteger() && !VT.isVector()) {
4565 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
4566 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
4567 if (isTypeLegal(IntXVT)) {
4568 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
4569 IntXVT, N0.getOperand(1));
4570 AddToWorkList(X.getNode());
4572 // If X has a different width than the result/lhs, sext it or truncate it.
4573 unsigned VTWidth = VT.getSizeInBits();
4574 if (OrigXWidth < VTWidth) {
4575 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
4576 AddToWorkList(X.getNode());
4577 } else if (OrigXWidth > VTWidth) {
4578 // To get the sign bit in the right place, we have to shift it right
4579 // before truncating.
4580 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
4581 X.getValueType(), X,
4582 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
4583 AddToWorkList(X.getNode());
4584 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4585 AddToWorkList(X.getNode());
4588 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
4589 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
4590 X, DAG.getConstant(SignBit, VT));
4591 AddToWorkList(X.getNode());
4593 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
4594 VT, N0.getOperand(0));
4595 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
4596 Cst, DAG.getConstant(~SignBit, VT));
4597 AddToWorkList(Cst.getNode());
4599 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
4603 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
4604 if (N0.getOpcode() == ISD::BUILD_PAIR) {
4605 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
4606 if (CombineLD.getNode())
4613 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
4614 EVT VT = N->getValueType(0);
4615 return CombineConsecutiveLoads(N, VT);
4618 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
4619 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
4620 /// destination element value type.
4621 SDValue DAGCombiner::
4622 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
4623 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
4625 // If this is already the right type, we're done.
4626 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
4628 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
4629 unsigned DstBitSize = DstEltVT.getSizeInBits();
4631 // If this is a conversion of N elements of one type to N elements of another
4632 // type, convert each element. This handles FP<->INT cases.
4633 if (SrcBitSize == DstBitSize) {
4634 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4635 BV->getValueType(0).getVectorNumElements());
4637 // Due to the FP element handling below calling this routine recursively,
4638 // we can end up with a scalar-to-vector node here.
4639 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
4640 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
4641 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
4642 DstEltVT, BV->getOperand(0)));
4644 SmallVector<SDValue, 8> Ops;
4645 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4646 SDValue Op = BV->getOperand(i);
4647 // If the vector element type is not legal, the BUILD_VECTOR operands
4648 // are promoted and implicitly truncated. Make that explicit here.
4649 if (Op.getValueType() != SrcEltVT)
4650 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
4651 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
4653 AddToWorkList(Ops.back().getNode());
4655 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4656 &Ops[0], Ops.size());
4659 // Otherwise, we're growing or shrinking the elements. To avoid having to
4660 // handle annoying details of growing/shrinking FP values, we convert them to
4662 if (SrcEltVT.isFloatingPoint()) {
4663 // Convert the input float vector to a int vector where the elements are the
4665 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
4666 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
4667 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
4671 // Now we know the input is an integer vector. If the output is a FP type,
4672 // convert to integer first, then to FP of the right size.
4673 if (DstEltVT.isFloatingPoint()) {
4674 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
4675 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
4676 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
4678 // Next, convert to FP elements of the same size.
4679 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
4682 // Okay, we know the src/dst types are both integers of differing types.
4683 // Handling growing first.
4684 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
4685 if (SrcBitSize < DstBitSize) {
4686 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
4688 SmallVector<SDValue, 8> Ops;
4689 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
4690 i += NumInputsPerOutput) {
4691 bool isLE = TLI.isLittleEndian();
4692 APInt NewBits = APInt(DstBitSize, 0);
4693 bool EltIsUndef = true;
4694 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
4695 // Shift the previously computed bits over.
4696 NewBits <<= SrcBitSize;
4697 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
4698 if (Op.getOpcode() == ISD::UNDEF) continue;
4701 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
4702 zextOrTrunc(SrcBitSize).zext(DstBitSize);
4706 Ops.push_back(DAG.getUNDEF(DstEltVT));
4708 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
4711 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
4712 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4713 &Ops[0], Ops.size());
4716 // Finally, this must be the case where we are shrinking elements: each input
4717 // turns into multiple outputs.
4718 bool isS2V = ISD::isScalarToVector(BV);
4719 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
4720 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4721 NumOutputsPerInput*BV->getNumOperands());
4722 SmallVector<SDValue, 8> Ops;
4724 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4725 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
4726 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
4727 Ops.push_back(DAG.getUNDEF(DstEltVT));
4731 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
4732 getAPIntValue().zextOrTrunc(SrcBitSize);
4734 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
4735 APInt ThisVal = OpVal.trunc(DstBitSize);
4736 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
4737 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
4738 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
4739 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
4741 OpVal = OpVal.lshr(DstBitSize);
4744 // For big endian targets, swap the order of the pieces of each element.
4745 if (TLI.isBigEndian())
4746 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
4749 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4750 &Ops[0], Ops.size());
4753 SDValue DAGCombiner::visitFADD(SDNode *N) {
4754 SDValue N0 = N->getOperand(0);
4755 SDValue N1 = N->getOperand(1);
4756 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4757 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4758 EVT VT = N->getValueType(0);
4761 if (VT.isVector()) {
4762 SDValue FoldedVOp = SimplifyVBinOp(N);
4763 if (FoldedVOp.getNode()) return FoldedVOp;
4766 // fold (fadd c1, c2) -> (fadd c1, c2)
4767 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4768 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
4769 // canonicalize constant to RHS
4770 if (N0CFP && !N1CFP)
4771 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
4772 // fold (fadd A, 0) -> A
4773 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4775 // fold (fadd A, (fneg B)) -> (fsub A, B)
4776 if (isNegatibleForFree(N1, LegalOperations) == 2)
4777 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
4778 GetNegatedExpression(N1, DAG, LegalOperations));
4779 // fold (fadd (fneg A), B) -> (fsub B, A)
4780 if (isNegatibleForFree(N0, LegalOperations) == 2)
4781 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
4782 GetNegatedExpression(N0, DAG, LegalOperations));
4784 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
4785 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
4786 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4787 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
4788 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
4789 N0.getOperand(1), N1));
4794 SDValue DAGCombiner::visitFSUB(SDNode *N) {
4795 SDValue N0 = N->getOperand(0);
4796 SDValue N1 = N->getOperand(1);
4797 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4798 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4799 EVT VT = N->getValueType(0);
4802 if (VT.isVector()) {
4803 SDValue FoldedVOp = SimplifyVBinOp(N);
4804 if (FoldedVOp.getNode()) return FoldedVOp;
4807 // fold (fsub c1, c2) -> c1-c2
4808 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4809 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
4810 // fold (fsub A, 0) -> A
4811 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4813 // fold (fsub 0, B) -> -B
4814 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
4815 if (isNegatibleForFree(N1, LegalOperations))
4816 return GetNegatedExpression(N1, DAG, LegalOperations);
4817 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4818 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
4820 // fold (fsub A, (fneg B)) -> (fadd A, B)
4821 if (isNegatibleForFree(N1, LegalOperations))
4822 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
4823 GetNegatedExpression(N1, DAG, LegalOperations));
4828 SDValue DAGCombiner::visitFMUL(SDNode *N) {
4829 SDValue N0 = N->getOperand(0);
4830 SDValue N1 = N->getOperand(1);
4831 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4832 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4833 EVT VT = N->getValueType(0);
4836 if (VT.isVector()) {
4837 SDValue FoldedVOp = SimplifyVBinOp(N);
4838 if (FoldedVOp.getNode()) return FoldedVOp;
4841 // fold (fmul c1, c2) -> c1*c2
4842 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4843 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
4844 // canonicalize constant to RHS
4845 if (N0CFP && !N1CFP)
4846 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
4847 // fold (fmul A, 0) -> 0
4848 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4850 // fold (fmul A, 0) -> 0, vector edition.
4851 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
4853 // fold (fmul X, 2.0) -> (fadd X, X)
4854 if (N1CFP && N1CFP->isExactlyValue(+2.0))
4855 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
4856 // fold (fmul X, -1.0) -> (fneg X)
4857 if (N1CFP && N1CFP->isExactlyValue(-1.0))
4858 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4859 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
4861 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
4862 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4863 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4864 // Both can be negated for free, check to see if at least one is cheaper
4866 if (LHSNeg == 2 || RHSNeg == 2)
4867 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4868 GetNegatedExpression(N0, DAG, LegalOperations),
4869 GetNegatedExpression(N1, DAG, LegalOperations));
4873 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
4874 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
4875 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4876 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
4877 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4878 N0.getOperand(1), N1));
4883 SDValue DAGCombiner::visitFDIV(SDNode *N) {
4884 SDValue N0 = N->getOperand(0);
4885 SDValue N1 = N->getOperand(1);
4886 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4887 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4888 EVT VT = N->getValueType(0);
4891 if (VT.isVector()) {
4892 SDValue FoldedVOp = SimplifyVBinOp(N);
4893 if (FoldedVOp.getNode()) return FoldedVOp;
4896 // fold (fdiv c1, c2) -> c1/c2
4897 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4898 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
4901 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
4902 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4903 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4904 // Both can be negated for free, check to see if at least one is cheaper
4906 if (LHSNeg == 2 || RHSNeg == 2)
4907 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
4908 GetNegatedExpression(N0, DAG, LegalOperations),
4909 GetNegatedExpression(N1, DAG, LegalOperations));
4916 SDValue DAGCombiner::visitFREM(SDNode *N) {
4917 SDValue N0 = N->getOperand(0);
4918 SDValue N1 = N->getOperand(1);
4919 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4920 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4921 EVT VT = N->getValueType(0);
4923 // fold (frem c1, c2) -> fmod(c1,c2)
4924 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4925 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
4930 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
4931 SDValue N0 = N->getOperand(0);
4932 SDValue N1 = N->getOperand(1);
4933 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4934 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4935 EVT VT = N->getValueType(0);
4937 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
4938 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
4941 const APFloat& V = N1CFP->getValueAPF();
4942 // copysign(x, c1) -> fabs(x) iff ispos(c1)
4943 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
4944 if (!V.isNegative()) {
4945 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
4946 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4948 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4949 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
4950 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
4954 // copysign(fabs(x), y) -> copysign(x, y)
4955 // copysign(fneg(x), y) -> copysign(x, y)
4956 // copysign(copysign(x,z), y) -> copysign(x, y)
4957 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
4958 N0.getOpcode() == ISD::FCOPYSIGN)
4959 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4960 N0.getOperand(0), N1);
4962 // copysign(x, abs(y)) -> abs(x)
4963 if (N1.getOpcode() == ISD::FABS)
4964 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4966 // copysign(x, copysign(y,z)) -> copysign(x, z)
4967 if (N1.getOpcode() == ISD::FCOPYSIGN)
4968 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4969 N0, N1.getOperand(1));
4971 // copysign(x, fp_extend(y)) -> copysign(x, y)
4972 // copysign(x, fp_round(y)) -> copysign(x, y)
4973 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
4974 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4975 N0, N1.getOperand(0));
4980 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
4981 SDValue N0 = N->getOperand(0);
4982 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4983 EVT VT = N->getValueType(0);
4984 EVT OpVT = N0.getValueType();
4986 // fold (sint_to_fp c1) -> c1fp
4987 if (N0C && OpVT != MVT::ppcf128)
4988 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4990 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
4991 // but UINT_TO_FP is legal on this target, try to convert.
4992 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
4993 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
4994 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
4995 if (DAG.SignBitIsZero(N0))
4996 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5002 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
5003 SDValue N0 = N->getOperand(0);
5004 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5005 EVT VT = N->getValueType(0);
5006 EVT OpVT = N0.getValueType();
5008 // fold (uint_to_fp c1) -> c1fp
5009 if (N0C && OpVT != MVT::ppcf128)
5010 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5012 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
5013 // but SINT_TO_FP is legal on this target, try to convert.
5014 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
5015 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
5016 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
5017 if (DAG.SignBitIsZero(N0))
5018 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5024 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
5025 SDValue N0 = N->getOperand(0);
5026 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5027 EVT VT = N->getValueType(0);
5029 // fold (fp_to_sint c1fp) -> c1
5031 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
5036 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
5037 SDValue N0 = N->getOperand(0);
5038 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5039 EVT VT = N->getValueType(0);
5041 // fold (fp_to_uint c1fp) -> c1
5042 if (N0CFP && VT != MVT::ppcf128)
5043 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
5048 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
5049 SDValue N0 = N->getOperand(0);
5050 SDValue N1 = N->getOperand(1);
5051 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5052 EVT VT = N->getValueType(0);
5054 // fold (fp_round c1fp) -> c1fp
5055 if (N0CFP && N0.getValueType() != MVT::ppcf128)
5056 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
5058 // fold (fp_round (fp_extend x)) -> x
5059 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
5060 return N0.getOperand(0);
5062 // fold (fp_round (fp_round x)) -> (fp_round x)
5063 if (N0.getOpcode() == ISD::FP_ROUND) {
5064 // This is a value preserving truncation if both round's are.
5065 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
5066 N0.getNode()->getConstantOperandVal(1) == 1;
5067 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
5068 DAG.getIntPtrConstant(IsTrunc));
5071 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
5072 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
5073 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
5074 N0.getOperand(0), N1);
5075 AddToWorkList(Tmp.getNode());
5076 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5077 Tmp, N0.getOperand(1));
5083 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
5084 SDValue N0 = N->getOperand(0);
5085 EVT VT = N->getValueType(0);
5086 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5087 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5089 // fold (fp_round_inreg c1fp) -> c1fp
5090 if (N0CFP && isTypeLegal(EVT)) {
5091 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
5092 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
5098 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
5099 SDValue N0 = N->getOperand(0);
5100 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5101 EVT VT = N->getValueType(0);
5103 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
5104 if (N->hasOneUse() &&
5105 N->use_begin()->getOpcode() == ISD::FP_ROUND)
5108 // fold (fp_extend c1fp) -> c1fp
5109 if (N0CFP && VT != MVT::ppcf128)
5110 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
5112 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
5114 if (N0.getOpcode() == ISD::FP_ROUND
5115 && N0.getNode()->getConstantOperandVal(1) == 1) {
5116 SDValue In = N0.getOperand(0);
5117 if (In.getValueType() == VT) return In;
5118 if (VT.bitsLT(In.getValueType()))
5119 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
5120 In, N0.getOperand(1));
5121 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
5124 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
5125 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
5126 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5127 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
5128 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5129 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N->getDebugLoc(),
5131 LN0->getBasePtr(), LN0->getPointerInfo(),
5133 LN0->isVolatile(), LN0->isNonTemporal(),
5134 LN0->getAlignment());
5135 CombineTo(N, ExtLoad);
5136 CombineTo(N0.getNode(),
5137 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
5138 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
5139 ExtLoad.getValue(1));
5140 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5146 SDValue DAGCombiner::visitFNEG(SDNode *N) {
5147 SDValue N0 = N->getOperand(0);
5148 EVT VT = N->getValueType(0);
5150 if (isNegatibleForFree(N0, LegalOperations))
5151 return GetNegatedExpression(N0, DAG, LegalOperations);
5153 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
5154 // constant pool values.
5155 if (N0.getOpcode() == ISD::BITCAST &&
5157 N0.getNode()->hasOneUse() &&
5158 N0.getOperand(0).getValueType().isInteger()) {
5159 SDValue Int = N0.getOperand(0);
5160 EVT IntVT = Int.getValueType();
5161 if (IntVT.isInteger() && !IntVT.isVector()) {
5162 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
5163 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5164 AddToWorkList(Int.getNode());
5165 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5173 SDValue DAGCombiner::visitFABS(SDNode *N) {
5174 SDValue N0 = N->getOperand(0);
5175 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5176 EVT VT = N->getValueType(0);
5178 // fold (fabs c1) -> fabs(c1)
5179 if (N0CFP && VT != MVT::ppcf128)
5180 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5181 // fold (fabs (fabs x)) -> (fabs x)
5182 if (N0.getOpcode() == ISD::FABS)
5183 return N->getOperand(0);
5184 // fold (fabs (fneg x)) -> (fabs x)
5185 // fold (fabs (fcopysign x, y)) -> (fabs x)
5186 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
5187 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
5189 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
5190 // constant pool values.
5191 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
5192 N0.getOperand(0).getValueType().isInteger() &&
5193 !N0.getOperand(0).getValueType().isVector()) {
5194 SDValue Int = N0.getOperand(0);
5195 EVT IntVT = Int.getValueType();
5196 if (IntVT.isInteger() && !IntVT.isVector()) {
5197 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
5198 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5199 AddToWorkList(Int.getNode());
5200 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5201 N->getValueType(0), Int);
5208 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
5209 SDValue Chain = N->getOperand(0);
5210 SDValue N1 = N->getOperand(1);
5211 SDValue N2 = N->getOperand(2);
5213 // If N is a constant we could fold this into a fallthrough or unconditional
5214 // branch. However that doesn't happen very often in normal code, because
5215 // Instcombine/SimplifyCFG should have handled the available opportunities.
5216 // If we did this folding here, it would be necessary to update the
5217 // MachineBasicBlock CFG, which is awkward.
5219 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
5221 if (N1.getOpcode() == ISD::SETCC &&
5222 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
5223 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5224 Chain, N1.getOperand(2),
5225 N1.getOperand(0), N1.getOperand(1), N2);
5228 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
5229 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
5230 (N1.getOperand(0).hasOneUse() &&
5231 N1.getOperand(0).getOpcode() == ISD::SRL))) {
5233 if (N1.getOpcode() == ISD::TRUNCATE) {
5234 // Look pass the truncate.
5235 Trunc = N1.getNode();
5236 N1 = N1.getOperand(0);
5239 // Match this pattern so that we can generate simpler code:
5242 // %b = and i32 %a, 2
5243 // %c = srl i32 %b, 1
5244 // brcond i32 %c ...
5249 // %b = and i32 %a, 2
5250 // %c = setcc eq %b, 0
5253 // This applies only when the AND constant value has one bit set and the
5254 // SRL constant is equal to the log2 of the AND constant. The back-end is
5255 // smart enough to convert the result into a TEST/JMP sequence.
5256 SDValue Op0 = N1.getOperand(0);
5257 SDValue Op1 = N1.getOperand(1);
5259 if (Op0.getOpcode() == ISD::AND &&
5260 Op1.getOpcode() == ISD::Constant) {
5261 SDValue AndOp1 = Op0.getOperand(1);
5263 if (AndOp1.getOpcode() == ISD::Constant) {
5264 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
5266 if (AndConst.isPowerOf2() &&
5267 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
5269 DAG.getSetCC(N->getDebugLoc(),
5270 TLI.getSetCCResultType(Op0.getValueType()),
5271 Op0, DAG.getConstant(0, Op0.getValueType()),
5274 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5275 MVT::Other, Chain, SetCC, N2);
5276 // Don't add the new BRCond into the worklist or else SimplifySelectCC
5277 // will convert it back to (X & C1) >> C2.
5278 CombineTo(N, NewBRCond, false);
5279 // Truncate is dead.
5281 removeFromWorkList(Trunc);
5282 DAG.DeleteNode(Trunc);
5284 // Replace the uses of SRL with SETCC
5285 WorkListRemover DeadNodes(*this);
5286 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5287 removeFromWorkList(N1.getNode());
5288 DAG.DeleteNode(N1.getNode());
5289 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5295 // Restore N1 if the above transformation doesn't match.
5296 N1 = N->getOperand(1);
5299 // Transform br(xor(x, y)) -> br(x != y)
5300 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
5301 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
5302 SDNode *TheXor = N1.getNode();
5303 SDValue Op0 = TheXor->getOperand(0);
5304 SDValue Op1 = TheXor->getOperand(1);
5305 if (Op0.getOpcode() == Op1.getOpcode()) {
5306 // Avoid missing important xor optimizations.
5307 SDValue Tmp = visitXOR(TheXor);
5308 if (Tmp.getNode() && Tmp.getNode() != TheXor) {
5309 DEBUG(dbgs() << "\nReplacing.8 ";
5311 dbgs() << "\nWith: ";
5312 Tmp.getNode()->dump(&DAG);
5314 WorkListRemover DeadNodes(*this);
5315 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes);
5316 removeFromWorkList(TheXor);
5317 DAG.DeleteNode(TheXor);
5318 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5319 MVT::Other, Chain, Tmp, N2);
5323 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
5325 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
5326 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
5327 Op0.getOpcode() == ISD::XOR) {
5328 TheXor = Op0.getNode();
5332 EVT SetCCVT = N1.getValueType();
5334 SetCCVT = TLI.getSetCCResultType(SetCCVT);
5335 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
5338 Equal ? ISD::SETEQ : ISD::SETNE);
5339 // Replace the uses of XOR with SETCC
5340 WorkListRemover DeadNodes(*this);
5341 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5342 removeFromWorkList(N1.getNode());
5343 DAG.DeleteNode(N1.getNode());
5344 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5345 MVT::Other, Chain, SetCC, N2);
5352 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
5354 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
5355 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
5356 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
5358 // If N is a constant we could fold this into a fallthrough or unconditional
5359 // branch. However that doesn't happen very often in normal code, because
5360 // Instcombine/SimplifyCFG should have handled the available opportunities.
5361 // If we did this folding here, it would be necessary to update the
5362 // MachineBasicBlock CFG, which is awkward.
5364 // Use SimplifySetCC to simplify SETCC's.
5365 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
5366 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
5368 if (Simp.getNode()) AddToWorkList(Simp.getNode());
5370 // fold to a simpler setcc
5371 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
5372 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5373 N->getOperand(0), Simp.getOperand(2),
5374 Simp.getOperand(0), Simp.getOperand(1),
5380 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
5381 /// pre-indexed load / store when the base pointer is an add or subtract
5382 /// and it has other uses besides the load / store. After the
5383 /// transformation, the new indexed load / store has effectively folded
5384 /// the add / subtract in and all of its other uses are redirected to the
5385 /// new load / store.
5386 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
5387 if (!LegalOperations)
5393 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5394 if (LD->isIndexed())
5396 VT = LD->getMemoryVT();
5397 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
5398 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
5400 Ptr = LD->getBasePtr();
5401 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5402 if (ST->isIndexed())
5404 VT = ST->getMemoryVT();
5405 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
5406 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
5408 Ptr = ST->getBasePtr();
5414 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
5415 // out. There is no reason to make this a preinc/predec.
5416 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
5417 Ptr.getNode()->hasOneUse())
5420 // Ask the target to do addressing mode selection.
5423 ISD::MemIndexedMode AM = ISD::UNINDEXED;
5424 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
5426 // Don't create a indexed load / store with zero offset.
5427 if (isa<ConstantSDNode>(Offset) &&
5428 cast<ConstantSDNode>(Offset)->isNullValue())
5431 // Try turning it into a pre-indexed load / store except when:
5432 // 1) The new base ptr is a frame index.
5433 // 2) If N is a store and the new base ptr is either the same as or is a
5434 // predecessor of the value being stored.
5435 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
5436 // that would create a cycle.
5437 // 4) All uses are load / store ops that use it as old base ptr.
5439 // Check #1. Preinc'ing a frame index would require copying the stack pointer
5440 // (plus the implicit offset) to a register to preinc anyway.
5441 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5446 SDValue Val = cast<StoreSDNode>(N)->getValue();
5447 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
5451 // Now check for #3 and #4.
5452 bool RealUse = false;
5453 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
5454 E = Ptr.getNode()->use_end(); I != E; ++I) {
5458 if (Use->isPredecessorOf(N))
5461 if (!((Use->getOpcode() == ISD::LOAD &&
5462 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
5463 (Use->getOpcode() == ISD::STORE &&
5464 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
5473 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5474 BasePtr, Offset, AM);
5476 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5477 BasePtr, Offset, AM);
5480 DEBUG(dbgs() << "\nReplacing.4 ";
5482 dbgs() << "\nWith: ";
5483 Result.getNode()->dump(&DAG);
5485 WorkListRemover DeadNodes(*this);
5487 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5489 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5492 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5496 // Finally, since the node is now dead, remove it from the graph.
5499 // Replace the uses of Ptr with uses of the updated base value.
5500 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
5502 removeFromWorkList(Ptr.getNode());
5503 DAG.DeleteNode(Ptr.getNode());
5508 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
5509 /// add / sub of the base pointer node into a post-indexed load / store.
5510 /// The transformation folded the add / subtract into the new indexed
5511 /// load / store effectively and all of its uses are redirected to the
5512 /// new load / store.
5513 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
5514 if (!LegalOperations)
5520 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5521 if (LD->isIndexed())
5523 VT = LD->getMemoryVT();
5524 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
5525 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
5527 Ptr = LD->getBasePtr();
5528 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5529 if (ST->isIndexed())
5531 VT = ST->getMemoryVT();
5532 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
5533 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
5535 Ptr = ST->getBasePtr();
5541 if (Ptr.getNode()->hasOneUse())
5544 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
5545 E = Ptr.getNode()->use_end(); I != E; ++I) {
5548 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
5553 ISD::MemIndexedMode AM = ISD::UNINDEXED;
5554 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
5555 // Don't create a indexed load / store with zero offset.
5556 if (isa<ConstantSDNode>(Offset) &&
5557 cast<ConstantSDNode>(Offset)->isNullValue())
5560 // Try turning it into a post-indexed load / store except when
5561 // 1) All uses are load / store ops that use it as base ptr.
5562 // 2) Op must be independent of N, i.e. Op is neither a predecessor
5563 // nor a successor of N. Otherwise, if Op is folded that would
5566 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5570 bool TryNext = false;
5571 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
5572 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
5574 if (Use == Ptr.getNode())
5577 // If all the uses are load / store addresses, then don't do the
5579 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
5580 bool RealUse = false;
5581 for (SDNode::use_iterator III = Use->use_begin(),
5582 EEE = Use->use_end(); III != EEE; ++III) {
5583 SDNode *UseUse = *III;
5584 if (!((UseUse->getOpcode() == ISD::LOAD &&
5585 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
5586 (UseUse->getOpcode() == ISD::STORE &&
5587 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
5602 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
5603 SDValue Result = isLoad
5604 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5605 BasePtr, Offset, AM)
5606 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5607 BasePtr, Offset, AM);
5610 DEBUG(dbgs() << "\nReplacing.5 ";
5612 dbgs() << "\nWith: ";
5613 Result.getNode()->dump(&DAG);
5615 WorkListRemover DeadNodes(*this);
5617 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5619 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5622 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5626 // Finally, since the node is now dead, remove it from the graph.
5629 // Replace the uses of Use with uses of the updated base value.
5630 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
5631 Result.getValue(isLoad ? 1 : 0),
5633 removeFromWorkList(Op);
5643 SDValue DAGCombiner::visitLOAD(SDNode *N) {
5644 LoadSDNode *LD = cast<LoadSDNode>(N);
5645 SDValue Chain = LD->getChain();
5646 SDValue Ptr = LD->getBasePtr();
5648 // If load is not volatile and there are no uses of the loaded value (and
5649 // the updated indexed value in case of indexed loads), change uses of the
5650 // chain value into uses of the chain input (i.e. delete the dead load).
5651 if (!LD->isVolatile()) {
5652 if (N->getValueType(1) == MVT::Other) {
5654 if (N->hasNUsesOfValue(0, 0)) {
5655 // It's not safe to use the two value CombineTo variant here. e.g.
5656 // v1, chain2 = load chain1, loc
5657 // v2, chain3 = load chain2, loc
5659 // Now we replace use of chain2 with chain1. This makes the second load
5660 // isomorphic to the one we are deleting, and thus makes this load live.
5661 DEBUG(dbgs() << "\nReplacing.6 ";
5663 dbgs() << "\nWith chain: ";
5664 Chain.getNode()->dump(&DAG);
5666 WorkListRemover DeadNodes(*this);
5667 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
5669 if (N->use_empty()) {
5670 removeFromWorkList(N);
5674 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5678 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
5679 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
5680 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
5681 DEBUG(dbgs() << "\nReplacing.7 ";
5683 dbgs() << "\nWith: ";
5684 Undef.getNode()->dump(&DAG);
5685 dbgs() << " and 2 other values\n");
5686 WorkListRemover DeadNodes(*this);
5687 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
5688 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
5689 DAG.getUNDEF(N->getValueType(1)),
5691 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
5692 removeFromWorkList(N);
5694 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5699 // If this load is directly stored, replace the load value with the stored
5701 // TODO: Handle store large -> read small portion.
5702 // TODO: Handle TRUNCSTORE/LOADEXT
5703 if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
5704 !LD->isVolatile()) {
5705 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
5706 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
5707 if (PrevST->getBasePtr() == Ptr &&
5708 PrevST->getValue().getValueType() == N->getValueType(0))
5709 return CombineTo(N, Chain.getOperand(1), Chain);
5713 // Try to infer better alignment information than the load already has.
5714 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
5715 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
5716 if (Align > LD->getAlignment())
5717 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0),
5719 Chain, Ptr, LD->getPointerInfo(),
5721 LD->isVolatile(), LD->isNonTemporal(), Align);
5726 // Walk up chain skipping non-aliasing memory nodes.
5727 SDValue BetterChain = FindBetterChain(N, Chain);
5729 // If there is a better chain.
5730 if (Chain != BetterChain) {
5733 // Replace the chain to void dependency.
5734 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
5735 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
5736 BetterChain, Ptr, LD->getPointerInfo(),
5737 LD->isVolatile(), LD->isNonTemporal(),
5738 LD->getAlignment());
5740 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0),
5742 BetterChain, Ptr, LD->getPointerInfo(),
5745 LD->isNonTemporal(),
5746 LD->getAlignment());
5749 // Create token factor to keep old chain connected.
5750 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5751 MVT::Other, Chain, ReplLoad.getValue(1));
5753 // Make sure the new and old chains are cleaned up.
5754 AddToWorkList(Token.getNode());
5756 // Replace uses with load result and token factor. Don't add users
5758 return CombineTo(N, ReplLoad.getValue(0), Token, false);
5762 // Try transforming N to an indexed load.
5763 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5764 return SDValue(N, 0);
5769 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
5770 /// load is having specific bytes cleared out. If so, return the byte size
5771 /// being masked out and the shift amount.
5772 static std::pair<unsigned, unsigned>
5773 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
5774 std::pair<unsigned, unsigned> Result(0, 0);
5776 // Check for the structure we're looking for.
5777 if (V->getOpcode() != ISD::AND ||
5778 !isa<ConstantSDNode>(V->getOperand(1)) ||
5779 !ISD::isNormalLoad(V->getOperand(0).getNode()))
5782 // Check the chain and pointer.
5783 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
5784 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
5786 // The store should be chained directly to the load or be an operand of a
5788 if (LD == Chain.getNode())
5790 else if (Chain->getOpcode() != ISD::TokenFactor)
5791 return Result; // Fail.
5794 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
5795 if (Chain->getOperand(i).getNode() == LD) {
5799 if (!isOk) return Result;
5802 // This only handles simple types.
5803 if (V.getValueType() != MVT::i16 &&
5804 V.getValueType() != MVT::i32 &&
5805 V.getValueType() != MVT::i64)
5808 // Check the constant mask. Invert it so that the bits being masked out are
5809 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
5810 // follow the sign bit for uniformity.
5811 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
5812 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
5813 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
5814 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
5815 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
5816 if (NotMaskLZ == 64) return Result; // All zero mask.
5818 // See if we have a continuous run of bits. If so, we have 0*1+0*
5819 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
5822 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
5823 if (V.getValueType() != MVT::i64 && NotMaskLZ)
5824 NotMaskLZ -= 64-V.getValueSizeInBits();
5826 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
5827 switch (MaskedBytes) {
5831 default: return Result; // All one mask, or 5-byte mask.
5834 // Verify that the first bit starts at a multiple of mask so that the access
5835 // is aligned the same as the access width.
5836 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
5838 Result.first = MaskedBytes;
5839 Result.second = NotMaskTZ/8;
5844 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
5845 /// provides a value as specified by MaskInfo. If so, replace the specified
5846 /// store with a narrower store of truncated IVal.
5848 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
5849 SDValue IVal, StoreSDNode *St,
5851 unsigned NumBytes = MaskInfo.first;
5852 unsigned ByteShift = MaskInfo.second;
5853 SelectionDAG &DAG = DC->getDAG();
5855 // Check to see if IVal is all zeros in the part being masked in by the 'or'
5856 // that uses this. If not, this is not a replacement.
5857 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
5858 ByteShift*8, (ByteShift+NumBytes)*8);
5859 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
5861 // Check that it is legal on the target to do this. It is legal if the new
5862 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
5864 MVT VT = MVT::getIntegerVT(NumBytes*8);
5865 if (!DC->isTypeLegal(VT))
5868 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
5869 // shifted by ByteShift and truncated down to NumBytes.
5871 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
5872 DAG.getConstant(ByteShift*8, DC->getShiftAmountTy()));
5874 // Figure out the offset for the store and the alignment of the access.
5876 unsigned NewAlign = St->getAlignment();
5878 if (DAG.getTargetLoweringInfo().isLittleEndian())
5879 StOffset = ByteShift;
5881 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
5883 SDValue Ptr = St->getBasePtr();
5885 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
5886 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
5887 NewAlign = MinAlign(NewAlign, StOffset);
5890 // Truncate down to the new size.
5891 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
5894 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
5895 St->getPointerInfo().getWithOffset(StOffset),
5896 false, false, NewAlign).getNode();
5900 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
5901 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
5902 /// of the loaded bits, try narrowing the load and store if it would end up
5903 /// being a win for performance or code size.
5904 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
5905 StoreSDNode *ST = cast<StoreSDNode>(N);
5906 if (ST->isVolatile())
5909 SDValue Chain = ST->getChain();
5910 SDValue Value = ST->getValue();
5911 SDValue Ptr = ST->getBasePtr();
5912 EVT VT = Value.getValueType();
5914 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
5917 unsigned Opc = Value.getOpcode();
5919 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
5920 // is a byte mask indicating a consecutive number of bytes, check to see if
5921 // Y is known to provide just those bytes. If so, we try to replace the
5922 // load + replace + store sequence with a single (narrower) store, which makes
5924 if (Opc == ISD::OR) {
5925 std::pair<unsigned, unsigned> MaskedLoad;
5926 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
5927 if (MaskedLoad.first)
5928 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
5929 Value.getOperand(1), ST,this))
5930 return SDValue(NewST, 0);
5932 // Or is commutative, so try swapping X and Y.
5933 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
5934 if (MaskedLoad.first)
5935 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
5936 Value.getOperand(0), ST,this))
5937 return SDValue(NewST, 0);
5940 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
5941 Value.getOperand(1).getOpcode() != ISD::Constant)
5944 SDValue N0 = Value.getOperand(0);
5945 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
5946 Chain == SDValue(N0.getNode(), 1)) {
5947 LoadSDNode *LD = cast<LoadSDNode>(N0);
5948 if (LD->getBasePtr() != Ptr ||
5949 LD->getPointerInfo().getAddrSpace() !=
5950 ST->getPointerInfo().getAddrSpace())
5953 // Find the type to narrow it the load / op / store to.
5954 SDValue N1 = Value.getOperand(1);
5955 unsigned BitWidth = N1.getValueSizeInBits();
5956 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
5957 if (Opc == ISD::AND)
5958 Imm ^= APInt::getAllOnesValue(BitWidth);
5959 if (Imm == 0 || Imm.isAllOnesValue())
5961 unsigned ShAmt = Imm.countTrailingZeros();
5962 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
5963 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
5964 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
5965 while (NewBW < BitWidth &&
5966 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
5967 TLI.isNarrowingProfitable(VT, NewVT))) {
5968 NewBW = NextPowerOf2(NewBW);
5969 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
5971 if (NewBW >= BitWidth)
5974 // If the lsb changed does not start at the type bitwidth boundary,
5975 // start at the previous one.
5977 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
5978 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
5979 if ((Imm & Mask) == Imm) {
5980 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
5981 if (Opc == ISD::AND)
5982 NewImm ^= APInt::getAllOnesValue(NewBW);
5983 uint64_t PtrOff = ShAmt / 8;
5984 // For big endian targets, we need to adjust the offset to the pointer to
5985 // load the correct bytes.
5986 if (TLI.isBigEndian())
5987 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
5989 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
5990 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
5991 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy))
5994 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
5995 Ptr.getValueType(), Ptr,
5996 DAG.getConstant(PtrOff, Ptr.getValueType()));
5997 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
5998 LD->getChain(), NewPtr,
5999 LD->getPointerInfo().getWithOffset(PtrOff),
6000 LD->isVolatile(), LD->isNonTemporal(),
6002 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
6003 DAG.getConstant(NewImm, NewVT));
6004 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
6006 ST->getPointerInfo().getWithOffset(PtrOff),
6007 false, false, NewAlign);
6009 AddToWorkList(NewPtr.getNode());
6010 AddToWorkList(NewLD.getNode());
6011 AddToWorkList(NewVal.getNode());
6012 WorkListRemover DeadNodes(*this);
6013 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
6023 SDValue DAGCombiner::visitSTORE(SDNode *N) {
6024 StoreSDNode *ST = cast<StoreSDNode>(N);
6025 SDValue Chain = ST->getChain();
6026 SDValue Value = ST->getValue();
6027 SDValue Ptr = ST->getBasePtr();
6029 // If this is a store of a bit convert, store the input value if the
6030 // resultant store does not need a higher alignment than the original.
6031 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
6032 ST->isUnindexed()) {
6033 unsigned OrigAlign = ST->getAlignment();
6034 EVT SVT = Value.getOperand(0).getValueType();
6035 unsigned Align = TLI.getTargetData()->
6036 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
6037 if (Align <= OrigAlign &&
6038 ((!LegalOperations && !ST->isVolatile()) ||
6039 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
6040 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6041 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6042 ST->isNonTemporal(), OrigAlign);
6045 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
6046 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
6047 // NOTE: If the original store is volatile, this transform must not increase
6048 // the number of stores. For example, on x86-32 an f64 can be stored in one
6049 // processor operation but an i64 (which is not legal) requires two. So the
6050 // transform should not be done in this case.
6051 if (Value.getOpcode() != ISD::TargetConstantFP) {
6053 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
6054 default: llvm_unreachable("Unknown FP type");
6055 case MVT::f80: // We don't do this for these yet.
6060 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
6061 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6062 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
6063 bitcastToAPInt().getZExtValue(), MVT::i32);
6064 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6065 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6066 ST->isNonTemporal(), ST->getAlignment());
6070 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
6071 !ST->isVolatile()) ||
6072 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
6073 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
6074 getZExtValue(), MVT::i64);
6075 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6076 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6077 ST->isNonTemporal(), ST->getAlignment());
6078 } else if (!ST->isVolatile() &&
6079 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6080 // Many FP stores are not made apparent until after legalize, e.g. for
6081 // argument passing. Since this is so common, custom legalize the
6082 // 64-bit integer store into two 32-bit stores.
6083 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
6084 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
6085 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
6086 if (TLI.isBigEndian()) std::swap(Lo, Hi);
6088 unsigned Alignment = ST->getAlignment();
6089 bool isVolatile = ST->isVolatile();
6090 bool isNonTemporal = ST->isNonTemporal();
6092 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
6093 Ptr, ST->getPointerInfo(),
6094 isVolatile, isNonTemporal,
6095 ST->getAlignment());
6096 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
6097 DAG.getConstant(4, Ptr.getValueType()));
6098 Alignment = MinAlign(Alignment, 4U);
6099 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
6100 Ptr, ST->getPointerInfo().getWithOffset(4),
6101 isVolatile, isNonTemporal,
6103 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
6112 // Try to infer better alignment information than the store already has.
6113 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
6114 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
6115 if (Align > ST->getAlignment())
6116 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
6117 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6118 ST->isVolatile(), ST->isNonTemporal(), Align);
6123 // Walk up chain skipping non-aliasing memory nodes.
6124 SDValue BetterChain = FindBetterChain(N, Chain);
6126 // If there is a better chain.
6127 if (Chain != BetterChain) {
6130 // Replace the chain to avoid dependency.
6131 if (ST->isTruncatingStore()) {
6132 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6133 ST->getPointerInfo(),
6134 ST->getMemoryVT(), ST->isVolatile(),
6135 ST->isNonTemporal(), ST->getAlignment());
6137 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6138 ST->getPointerInfo(),
6139 ST->isVolatile(), ST->isNonTemporal(),
6140 ST->getAlignment());
6143 // Create token to keep both nodes around.
6144 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6145 MVT::Other, Chain, ReplStore);
6147 // Make sure the new and old chains are cleaned up.
6148 AddToWorkList(Token.getNode());
6150 // Don't add users to work list.
6151 return CombineTo(N, Token, false);
6155 // Try transforming N to an indexed store.
6156 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6157 return SDValue(N, 0);
6159 // FIXME: is there such a thing as a truncating indexed store?
6160 if (ST->isTruncatingStore() && ST->isUnindexed() &&
6161 Value.getValueType().isInteger()) {
6162 // See if we can simplify the input to this truncstore with knowledge that
6163 // only the low bits are being used. For example:
6164 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
6166 GetDemandedBits(Value,
6167 APInt::getLowBitsSet(Value.getValueSizeInBits(),
6168 ST->getMemoryVT().getSizeInBits()));
6169 AddToWorkList(Value.getNode());
6170 if (Shorter.getNode())
6171 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
6172 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6173 ST->isVolatile(), ST->isNonTemporal(),
6174 ST->getAlignment());
6176 // Otherwise, see if we can simplify the operation with
6177 // SimplifyDemandedBits, which only works if the value has a single use.
6178 if (SimplifyDemandedBits(Value,
6179 APInt::getLowBitsSet(
6180 Value.getValueType().getScalarType().getSizeInBits(),
6181 ST->getMemoryVT().getScalarType().getSizeInBits())))
6182 return SDValue(N, 0);
6185 // If this is a load followed by a store to the same location, then the store
6187 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
6188 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
6189 ST->isUnindexed() && !ST->isVolatile() &&
6190 // There can't be any side effects between the load and store, such as
6192 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
6193 // The store is dead, remove it.
6198 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
6199 // truncating store. We can do this even if this is already a truncstore.
6200 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
6201 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
6202 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
6203 ST->getMemoryVT())) {
6204 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6205 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6206 ST->isVolatile(), ST->isNonTemporal(),
6207 ST->getAlignment());
6210 return ReduceLoadOpStoreWidth(N);
6213 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
6214 SDValue InVec = N->getOperand(0);
6215 SDValue InVal = N->getOperand(1);
6216 SDValue EltNo = N->getOperand(2);
6218 // If the inserted element is an UNDEF, just use the input vector.
6219 if (InVal.getOpcode() == ISD::UNDEF)
6222 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
6223 // vector with the inserted element.
6224 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
6225 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6226 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
6227 InVec.getNode()->op_end());
6228 if (Elt < Ops.size())
6230 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6231 InVec.getValueType(), &Ops[0], Ops.size());
6233 // If the invec is an UNDEF and if EltNo is a constant, create a new
6234 // BUILD_VECTOR with undef elements and the inserted element.
6235 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF &&
6236 isa<ConstantSDNode>(EltNo)) {
6237 EVT VT = InVec.getValueType();
6238 EVT EltVT = VT.getVectorElementType();
6239 unsigned NElts = VT.getVectorNumElements();
6240 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT));
6242 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6243 if (Elt < Ops.size())
6245 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6246 InVec.getValueType(), &Ops[0], Ops.size());
6251 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
6252 // (vextract (scalar_to_vector val, 0) -> val
6253 SDValue InVec = N->getOperand(0);
6255 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
6256 // Check if the result type doesn't match the inserted element type. A
6257 // SCALAR_TO_VECTOR may truncate the inserted element and the
6258 // EXTRACT_VECTOR_ELT may widen the extracted vector.
6259 SDValue InOp = InVec.getOperand(0);
6260 EVT NVT = N->getValueType(0);
6261 if (InOp.getValueType() != NVT) {
6262 assert(InOp.getValueType().isInteger() && NVT.isInteger());
6263 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
6268 // Perform only after legalization to ensure build_vector / vector_shuffle
6269 // optimizations have already been done.
6270 if (!LegalOperations) return SDValue();
6272 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
6273 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
6274 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
6275 SDValue EltNo = N->getOperand(1);
6277 if (isa<ConstantSDNode>(EltNo)) {
6278 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6279 bool NewLoad = false;
6280 bool BCNumEltsChanged = false;
6281 EVT VT = InVec.getValueType();
6282 EVT ExtVT = VT.getVectorElementType();
6285 if (InVec.getOpcode() == ISD::BITCAST) {
6286 EVT BCVT = InVec.getOperand(0).getValueType();
6287 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
6289 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
6290 BCNumEltsChanged = true;
6291 InVec = InVec.getOperand(0);
6292 ExtVT = BCVT.getVectorElementType();
6296 LoadSDNode *LN0 = NULL;
6297 const ShuffleVectorSDNode *SVN = NULL;
6298 if (ISD::isNormalLoad(InVec.getNode())) {
6299 LN0 = cast<LoadSDNode>(InVec);
6300 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6301 InVec.getOperand(0).getValueType() == ExtVT &&
6302 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
6303 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
6304 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
6305 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
6307 // (load $addr+1*size)
6309 // If the bit convert changed the number of elements, it is unsafe
6310 // to examine the mask.
6311 if (BCNumEltsChanged)
6314 // Select the input vector, guarding against out of range extract vector.
6315 unsigned NumElems = VT.getVectorNumElements();
6316 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
6317 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
6319 if (InVec.getOpcode() == ISD::BITCAST)
6320 InVec = InVec.getOperand(0);
6321 if (ISD::isNormalLoad(InVec.getNode())) {
6322 LN0 = cast<LoadSDNode>(InVec);
6323 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
6327 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile())
6330 // If Idx was -1 above, Elt is going to be -1, so just return undef.
6332 return DAG.getUNDEF(LN0->getBasePtr().getValueType());
6334 unsigned Align = LN0->getAlignment();
6336 // Check the resultant load doesn't need a higher alignment than the
6340 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
6342 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
6348 SDValue NewPtr = LN0->getBasePtr();
6349 unsigned PtrOff = 0;
6352 PtrOff = LVT.getSizeInBits() * Elt / 8;
6353 EVT PtrType = NewPtr.getValueType();
6354 if (TLI.isBigEndian())
6355 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
6356 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
6357 DAG.getConstant(PtrOff, PtrType));
6360 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
6361 LN0->getPointerInfo().getWithOffset(PtrOff),
6362 LN0->isVolatile(), LN0->isNonTemporal(), Align);
6368 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
6369 unsigned NumInScalars = N->getNumOperands();
6370 EVT VT = N->getValueType(0);
6372 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
6373 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
6374 // at most two distinct vectors, turn this into a shuffle node.
6375 SDValue VecIn1, VecIn2;
6376 for (unsigned i = 0; i != NumInScalars; ++i) {
6377 // Ignore undef inputs.
6378 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6380 // If this input is something other than a EXTRACT_VECTOR_ELT with a
6381 // constant index, bail out.
6382 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6383 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
6384 VecIn1 = VecIn2 = SDValue(0, 0);
6388 // If the input vector type disagrees with the result of the build_vector,
6389 // we can't make a shuffle.
6390 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
6391 if (ExtractedFromVec.getValueType() != VT) {
6392 VecIn1 = VecIn2 = SDValue(0, 0);
6396 // Otherwise, remember this. We allow up to two distinct input vectors.
6397 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
6400 if (VecIn1.getNode() == 0) {
6401 VecIn1 = ExtractedFromVec;
6402 } else if (VecIn2.getNode() == 0) {
6403 VecIn2 = ExtractedFromVec;
6406 VecIn1 = VecIn2 = SDValue(0, 0);
6411 // If everything is good, we can make a shuffle operation.
6412 if (VecIn1.getNode()) {
6413 SmallVector<int, 8> Mask;
6414 for (unsigned i = 0; i != NumInScalars; ++i) {
6415 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
6420 // If extracting from the first vector, just use the index directly.
6421 SDValue Extract = N->getOperand(i);
6422 SDValue ExtVal = Extract.getOperand(1);
6423 if (Extract.getOperand(0) == VecIn1) {
6424 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
6425 if (ExtIndex > VT.getVectorNumElements())
6428 Mask.push_back(ExtIndex);
6432 // Otherwise, use InIdx + VecSize
6433 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
6434 Mask.push_back(Idx+NumInScalars);
6437 // Add count and size info.
6438 if (!isTypeLegal(VT))
6441 // Return the new VECTOR_SHUFFLE node.
6444 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6445 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
6451 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
6452 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
6453 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
6454 // inputs come from at most two distinct vectors, turn this into a shuffle
6457 // If we only have one input vector, we don't need to do any concatenation.
6458 if (N->getNumOperands() == 1)
6459 return N->getOperand(0);
6464 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
6465 EVT VT = N->getValueType(0);
6466 unsigned NumElts = VT.getVectorNumElements();
6468 SDValue N0 = N->getOperand(0);
6470 assert(N0.getValueType().getVectorNumElements() == NumElts &&
6471 "Vector shuffle must be normalized in DAG");
6473 // FIXME: implement canonicalizations from DAG.getVectorShuffle()
6475 // If it is a splat, check if the argument vector is another splat or a
6476 // build_vector with all scalar elements the same.
6477 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
6478 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
6479 SDNode *V = N0.getNode();
6481 // If this is a bit convert that changes the element type of the vector but
6482 // not the number of vector elements, look through it. Be careful not to
6483 // look though conversions that change things like v4f32 to v2f64.
6484 if (V->getOpcode() == ISD::BITCAST) {
6485 SDValue ConvInput = V->getOperand(0);
6486 if (ConvInput.getValueType().isVector() &&
6487 ConvInput.getValueType().getVectorNumElements() == NumElts)
6488 V = ConvInput.getNode();
6491 if (V->getOpcode() == ISD::BUILD_VECTOR) {
6492 assert(V->getNumOperands() == NumElts &&
6493 "BUILD_VECTOR has wrong number of operands");
6495 bool AllSame = true;
6496 for (unsigned i = 0; i != NumElts; ++i) {
6497 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
6498 Base = V->getOperand(i);
6502 // Splat of <u, u, u, u>, return <u, u, u, u>
6503 if (!Base.getNode())
6505 for (unsigned i = 0; i != NumElts; ++i) {
6506 if (V->getOperand(i) != Base) {
6511 // Splat of <x, x, x, x>, return <x, x, x, x>
6519 SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
6520 if (!TLI.getShouldFoldAtomicFences())
6523 SDValue atomic = N->getOperand(0);
6524 switch (atomic.getOpcode()) {
6525 case ISD::ATOMIC_CMP_SWAP:
6526 case ISD::ATOMIC_SWAP:
6527 case ISD::ATOMIC_LOAD_ADD:
6528 case ISD::ATOMIC_LOAD_SUB:
6529 case ISD::ATOMIC_LOAD_AND:
6530 case ISD::ATOMIC_LOAD_OR:
6531 case ISD::ATOMIC_LOAD_XOR:
6532 case ISD::ATOMIC_LOAD_NAND:
6533 case ISD::ATOMIC_LOAD_MIN:
6534 case ISD::ATOMIC_LOAD_MAX:
6535 case ISD::ATOMIC_LOAD_UMIN:
6536 case ISD::ATOMIC_LOAD_UMAX:
6542 SDValue fence = atomic.getOperand(0);
6543 if (fence.getOpcode() != ISD::MEMBARRIER)
6546 switch (atomic.getOpcode()) {
6547 case ISD::ATOMIC_CMP_SWAP:
6548 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
6549 fence.getOperand(0),
6550 atomic.getOperand(1), atomic.getOperand(2),
6551 atomic.getOperand(3)), atomic.getResNo());
6552 case ISD::ATOMIC_SWAP:
6553 case ISD::ATOMIC_LOAD_ADD:
6554 case ISD::ATOMIC_LOAD_SUB:
6555 case ISD::ATOMIC_LOAD_AND:
6556 case ISD::ATOMIC_LOAD_OR:
6557 case ISD::ATOMIC_LOAD_XOR:
6558 case ISD::ATOMIC_LOAD_NAND:
6559 case ISD::ATOMIC_LOAD_MIN:
6560 case ISD::ATOMIC_LOAD_MAX:
6561 case ISD::ATOMIC_LOAD_UMIN:
6562 case ISD::ATOMIC_LOAD_UMAX:
6563 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
6564 fence.getOperand(0),
6565 atomic.getOperand(1), atomic.getOperand(2)),
6572 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
6573 /// an AND to a vector_shuffle with the destination vector and a zero vector.
6574 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
6575 /// vector_shuffle V, Zero, <0, 4, 2, 4>
6576 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
6577 EVT VT = N->getValueType(0);
6578 DebugLoc dl = N->getDebugLoc();
6579 SDValue LHS = N->getOperand(0);
6580 SDValue RHS = N->getOperand(1);
6581 if (N->getOpcode() == ISD::AND) {
6582 if (RHS.getOpcode() == ISD::BITCAST)
6583 RHS = RHS.getOperand(0);
6584 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
6585 SmallVector<int, 8> Indices;
6586 unsigned NumElts = RHS.getNumOperands();
6587 for (unsigned i = 0; i != NumElts; ++i) {
6588 SDValue Elt = RHS.getOperand(i);
6589 if (!isa<ConstantSDNode>(Elt))
6591 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
6592 Indices.push_back(i);
6593 else if (cast<ConstantSDNode>(Elt)->isNullValue())
6594 Indices.push_back(NumElts);
6599 // Let's see if the target supports this vector_shuffle.
6600 EVT RVT = RHS.getValueType();
6601 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
6604 // Return the new VECTOR_SHUFFLE node.
6605 EVT EltVT = RVT.getVectorElementType();
6606 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
6607 DAG.getConstant(0, EltVT));
6608 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6609 RVT, &ZeroOps[0], ZeroOps.size());
6610 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
6611 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
6612 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
6619 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
6620 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
6621 // After legalize, the target may be depending on adds and other
6622 // binary ops to provide legal ways to construct constants or other
6623 // things. Simplifying them may result in a loss of legality.
6624 if (LegalOperations) return SDValue();
6626 EVT VT = N->getValueType(0);
6627 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
6629 EVT EltType = VT.getVectorElementType();
6630 SDValue LHS = N->getOperand(0);
6631 SDValue RHS = N->getOperand(1);
6632 SDValue Shuffle = XformToShuffleWithZero(N);
6633 if (Shuffle.getNode()) return Shuffle;
6635 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
6637 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
6638 RHS.getOpcode() == ISD::BUILD_VECTOR) {
6639 SmallVector<SDValue, 8> Ops;
6640 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
6641 SDValue LHSOp = LHS.getOperand(i);
6642 SDValue RHSOp = RHS.getOperand(i);
6643 // If these two elements can't be folded, bail out.
6644 if ((LHSOp.getOpcode() != ISD::UNDEF &&
6645 LHSOp.getOpcode() != ISD::Constant &&
6646 LHSOp.getOpcode() != ISD::ConstantFP) ||
6647 (RHSOp.getOpcode() != ISD::UNDEF &&
6648 RHSOp.getOpcode() != ISD::Constant &&
6649 RHSOp.getOpcode() != ISD::ConstantFP))
6652 // Can't fold divide by zero.
6653 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
6654 N->getOpcode() == ISD::FDIV) {
6655 if ((RHSOp.getOpcode() == ISD::Constant &&
6656 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
6657 (RHSOp.getOpcode() == ISD::ConstantFP &&
6658 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
6662 // If the vector element type is not legal, the BUILD_VECTOR operands
6663 // are promoted and implicitly truncated. Make that explicit here.
6664 if (LHSOp.getValueType() != EltType)
6665 LHSOp = DAG.getNode(ISD::TRUNCATE, LHS.getDebugLoc(), EltType, LHSOp);
6666 if (RHSOp.getValueType() != EltType)
6667 RHSOp = DAG.getNode(ISD::TRUNCATE, RHS.getDebugLoc(), EltType, RHSOp);
6669 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), EltType,
6671 if (FoldOp.getOpcode() != ISD::UNDEF &&
6672 FoldOp.getOpcode() != ISD::Constant &&
6673 FoldOp.getOpcode() != ISD::ConstantFP)
6675 Ops.push_back(FoldOp);
6676 AddToWorkList(FoldOp.getNode());
6679 if (Ops.size() == LHS.getNumOperands()) {
6680 EVT VT = LHS.getValueType();
6681 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
6682 &Ops[0], Ops.size());
6689 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
6690 SDValue N1, SDValue N2){
6691 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
6693 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
6694 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6696 // If we got a simplified select_cc node back from SimplifySelectCC, then
6697 // break it down into a new SETCC node, and a new SELECT node, and then return
6698 // the SELECT node, since we were called with a SELECT node.
6699 if (SCC.getNode()) {
6700 // Check to see if we got a select_cc back (to turn into setcc/select).
6701 // Otherwise, just return whatever node we got back, like fabs.
6702 if (SCC.getOpcode() == ISD::SELECT_CC) {
6703 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
6705 SCC.getOperand(0), SCC.getOperand(1),
6707 AddToWorkList(SETCC.getNode());
6708 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
6709 SCC.getOperand(2), SCC.getOperand(3), SETCC);
6717 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
6718 /// are the two values being selected between, see if we can simplify the
6719 /// select. Callers of this should assume that TheSelect is deleted if this
6720 /// returns true. As such, they should return the appropriate thing (e.g. the
6721 /// node) back to the top-level of the DAG combiner loop to avoid it being
6723 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
6726 // If this is a select from two identical things, try to pull the operation
6727 // through the select.
6728 if (LHS.getOpcode() != RHS.getOpcode() ||
6729 !LHS.hasOneUse() || !RHS.hasOneUse())
6732 // If this is a load and the token chain is identical, replace the select
6733 // of two loads with a load through a select of the address to load from.
6734 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
6735 // constants have been dropped into the constant pool.
6736 if (LHS.getOpcode() == ISD::LOAD) {
6737 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
6738 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
6740 // Token chains must be identical.
6741 if (LHS.getOperand(0) != RHS.getOperand(0) ||
6742 // Do not let this transformation reduce the number of volatile loads.
6743 LLD->isVolatile() || RLD->isVolatile() ||
6744 // If this is an EXTLOAD, the VT's must match.
6745 LLD->getMemoryVT() != RLD->getMemoryVT() ||
6746 // If this is an EXTLOAD, the kind of extension must match.
6747 (LLD->getExtensionType() != RLD->getExtensionType() &&
6748 // The only exception is if one of the extensions is anyext.
6749 LLD->getExtensionType() != ISD::EXTLOAD &&
6750 RLD->getExtensionType() != ISD::EXTLOAD) ||
6751 // FIXME: this discards src value information. This is
6752 // over-conservative. It would be beneficial to be able to remember
6753 // both potential memory locations. Since we are discarding
6754 // src value info, don't do the transformation if the memory
6755 // locations are not in the default address space.
6756 LLD->getPointerInfo().getAddrSpace() != 0 ||
6757 RLD->getPointerInfo().getAddrSpace() != 0)
6760 // Check that the select condition doesn't reach either load. If so,
6761 // folding this will induce a cycle into the DAG. If not, this is safe to
6762 // xform, so create a select of the addresses.
6764 if (TheSelect->getOpcode() == ISD::SELECT) {
6765 SDNode *CondNode = TheSelect->getOperand(0).getNode();
6766 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
6767 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
6769 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
6770 LLD->getBasePtr().getValueType(),
6771 TheSelect->getOperand(0), LLD->getBasePtr(),
6773 } else { // Otherwise SELECT_CC
6774 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
6775 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
6777 if ((LLD->hasAnyUseOfValue(1) &&
6778 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
6779 (LLD->hasAnyUseOfValue(1) &&
6780 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))))
6783 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
6784 LLD->getBasePtr().getValueType(),
6785 TheSelect->getOperand(0),
6786 TheSelect->getOperand(1),
6787 LLD->getBasePtr(), RLD->getBasePtr(),
6788 TheSelect->getOperand(4));
6792 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
6793 Load = DAG.getLoad(TheSelect->getValueType(0),
6794 TheSelect->getDebugLoc(),
6795 // FIXME: Discards pointer info.
6796 LLD->getChain(), Addr, MachinePointerInfo(),
6797 LLD->isVolatile(), LLD->isNonTemporal(),
6798 LLD->getAlignment());
6800 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
6801 RLD->getExtensionType() : LLD->getExtensionType(),
6802 TheSelect->getValueType(0),
6803 TheSelect->getDebugLoc(),
6804 // FIXME: Discards pointer info.
6805 LLD->getChain(), Addr, MachinePointerInfo(),
6806 LLD->getMemoryVT(), LLD->isVolatile(),
6807 LLD->isNonTemporal(), LLD->getAlignment());
6810 // Users of the select now use the result of the load.
6811 CombineTo(TheSelect, Load);
6813 // Users of the old loads now use the new load's chain. We know the
6814 // old-load value is dead now.
6815 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
6816 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
6823 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
6824 /// where 'cond' is the comparison specified by CC.
6825 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
6826 SDValue N2, SDValue N3,
6827 ISD::CondCode CC, bool NotExtCompare) {
6828 // (x ? y : y) -> y.
6829 if (N2 == N3) return N2;
6831 EVT VT = N2.getValueType();
6832 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
6833 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
6834 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
6836 // Determine if the condition we're dealing with is constant
6837 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
6838 N0, N1, CC, DL, false);
6839 if (SCC.getNode()) AddToWorkList(SCC.getNode());
6840 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
6842 // fold select_cc true, x, y -> x
6843 if (SCCC && !SCCC->isNullValue())
6845 // fold select_cc false, x, y -> y
6846 if (SCCC && SCCC->isNullValue())
6849 // Check to see if we can simplify the select into an fabs node
6850 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
6851 // Allow either -0.0 or 0.0
6852 if (CFP->getValueAPF().isZero()) {
6853 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
6854 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
6855 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
6856 N2 == N3.getOperand(0))
6857 return DAG.getNode(ISD::FABS, DL, VT, N0);
6859 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
6860 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
6861 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
6862 N2.getOperand(0) == N3)
6863 return DAG.getNode(ISD::FABS, DL, VT, N3);
6867 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
6868 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
6869 // in it. This is a win when the constant is not otherwise available because
6870 // it replaces two constant pool loads with one. We only do this if the FP
6871 // type is known to be legal, because if it isn't, then we are before legalize
6872 // types an we want the other legalization to happen first (e.g. to avoid
6873 // messing with soft float) and if the ConstantFP is not legal, because if
6874 // it is legal, we may not need to store the FP constant in a constant pool.
6875 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
6876 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
6877 if (TLI.isTypeLegal(N2.getValueType()) &&
6878 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
6879 TargetLowering::Legal) &&
6880 // If both constants have multiple uses, then we won't need to do an
6881 // extra load, they are likely around in registers for other users.
6882 (TV->hasOneUse() || FV->hasOneUse())) {
6883 Constant *Elts[] = {
6884 const_cast<ConstantFP*>(FV->getConstantFPValue()),
6885 const_cast<ConstantFP*>(TV->getConstantFPValue())
6887 const Type *FPTy = Elts[0]->getType();
6888 const TargetData &TD = *TLI.getTargetData();
6890 // Create a ConstantArray of the two constants.
6891 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2);
6892 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
6893 TD.getPrefTypeAlignment(FPTy));
6894 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6896 // Get the offsets to the 0 and 1 element of the array so that we can
6897 // select between them.
6898 SDValue Zero = DAG.getIntPtrConstant(0);
6899 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
6900 SDValue One = DAG.getIntPtrConstant(EltSize);
6902 SDValue Cond = DAG.getSetCC(DL,
6903 TLI.getSetCCResultType(N0.getValueType()),
6905 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
6907 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
6909 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
6910 MachinePointerInfo::getConstantPool(), false,
6916 // Check to see if we can perform the "gzip trick", transforming
6917 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
6918 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
6919 N0.getValueType().isInteger() &&
6920 N2.getValueType().isInteger() &&
6921 (N1C->isNullValue() || // (a < 0) ? b : 0
6922 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
6923 EVT XType = N0.getValueType();
6924 EVT AType = N2.getValueType();
6925 if (XType.bitsGE(AType)) {
6926 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
6927 // single-bit constant.
6928 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
6929 unsigned ShCtV = N2C->getAPIntValue().logBase2();
6930 ShCtV = XType.getSizeInBits()-ShCtV-1;
6931 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy());
6932 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
6934 AddToWorkList(Shift.getNode());
6936 if (XType.bitsGT(AType)) {
6937 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
6938 AddToWorkList(Shift.getNode());
6941 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
6944 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
6946 DAG.getConstant(XType.getSizeInBits()-1,
6947 getShiftAmountTy()));
6948 AddToWorkList(Shift.getNode());
6950 if (XType.bitsGT(AType)) {
6951 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
6952 AddToWorkList(Shift.getNode());
6955 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
6959 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
6960 // where y is has a single bit set.
6961 // A plaintext description would be, we can turn the SELECT_CC into an AND
6962 // when the condition can be materialized as an all-ones register. Any
6963 // single bit-test can be materialized as an all-ones register with
6964 // shift-left and shift-right-arith.
6965 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
6966 N0->getValueType(0) == VT &&
6967 N1C && N1C->isNullValue() &&
6968 N2C && N2C->isNullValue()) {
6969 SDValue AndLHS = N0->getOperand(0);
6970 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
6971 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
6972 // Shift the tested bit over the sign bit.
6973 APInt AndMask = ConstAndRHS->getAPIntValue();
6975 DAG.getConstant(AndMask.countLeadingZeros(), getShiftAmountTy());
6976 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
6978 // Now arithmetic right shift it all the way over, so the result is either
6979 // all-ones, or zero.
6981 DAG.getConstant(AndMask.getBitWidth()-1, getShiftAmountTy());
6982 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
6984 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
6988 // fold select C, 16, 0 -> shl C, 4
6989 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
6990 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
6992 // If the caller doesn't want us to simplify this into a zext of a compare,
6994 if (NotExtCompare && N2C->getAPIntValue() == 1)
6997 // Get a SetCC of the condition
6998 // FIXME: Should probably make sure that setcc is legal if we ever have a
6999 // target where it isn't.
7001 // cast from setcc result type to select result type
7003 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
7005 if (N2.getValueType().bitsLT(SCC.getValueType()))
7006 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
7008 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
7009 N2.getValueType(), SCC);
7011 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
7012 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
7013 N2.getValueType(), SCC);
7016 AddToWorkList(SCC.getNode());
7017 AddToWorkList(Temp.getNode());
7019 if (N2C->getAPIntValue() == 1)
7022 // shl setcc result by log2 n2c
7023 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
7024 DAG.getConstant(N2C->getAPIntValue().logBase2(),
7025 getShiftAmountTy()));
7028 // Check to see if this is the equivalent of setcc
7029 // FIXME: Turn all of these into setcc if setcc if setcc is legal
7030 // otherwise, go ahead with the folds.
7031 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
7032 EVT XType = N0.getValueType();
7033 if (!LegalOperations ||
7034 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
7035 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
7036 if (Res.getValueType() != VT)
7037 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
7041 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
7042 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
7043 (!LegalOperations ||
7044 TLI.isOperationLegal(ISD::CTLZ, XType))) {
7045 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
7046 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
7047 DAG.getConstant(Log2_32(XType.getSizeInBits()),
7048 getShiftAmountTy()));
7050 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
7051 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
7052 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
7053 XType, DAG.getConstant(0, XType), N0);
7054 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
7055 return DAG.getNode(ISD::SRL, DL, XType,
7056 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
7057 DAG.getConstant(XType.getSizeInBits()-1,
7058 getShiftAmountTy()));
7060 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
7061 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
7062 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
7063 DAG.getConstant(XType.getSizeInBits()-1,
7064 getShiftAmountTy()));
7065 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
7069 // Check to see if this is an integer abs.
7070 // select_cc setg[te] X, 0, X, -X ->
7071 // select_cc setgt X, -1, X, -X ->
7072 // select_cc setl[te] X, 0, -X, X ->
7073 // select_cc setlt X, 1, -X, X ->
7074 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
7076 ConstantSDNode *SubC = NULL;
7077 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
7078 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
7079 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
7080 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
7081 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
7082 (N1C->isOne() && CC == ISD::SETLT)) &&
7083 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
7084 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
7086 EVT XType = N0.getValueType();
7087 if (SubC && SubC->isNullValue() && XType.isInteger()) {
7088 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
7090 DAG.getConstant(XType.getSizeInBits()-1,
7091 getShiftAmountTy()));
7092 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
7094 AddToWorkList(Shift.getNode());
7095 AddToWorkList(Add.getNode());
7096 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
7103 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
7104 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
7105 SDValue N1, ISD::CondCode Cond,
7106 DebugLoc DL, bool foldBooleans) {
7107 TargetLowering::DAGCombinerInfo
7108 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
7109 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
7112 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
7113 /// return a DAG expression to select that will generate the same value by
7114 /// multiplying by a magic number. See:
7115 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
7116 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
7117 std::vector<SDNode*> Built;
7118 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
7120 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
7126 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
7127 /// return a DAG expression to select that will generate the same value by
7128 /// multiplying by a magic number. See:
7129 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
7130 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
7131 std::vector<SDNode*> Built;
7132 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
7134 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
7140 /// FindBaseOffset - Return true if base is a frame index, which is known not
7141 // to alias with anything but itself. Provides base object and offset as
7143 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
7144 const GlobalValue *&GV, void *&CV) {
7145 // Assume it is a primitive operation.
7146 Base = Ptr; Offset = 0; GV = 0; CV = 0;
7148 // If it's an adding a simple constant then integrate the offset.
7149 if (Base.getOpcode() == ISD::ADD) {
7150 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
7151 Base = Base.getOperand(0);
7152 Offset += C->getZExtValue();
7156 // Return the underlying GlobalValue, and update the Offset. Return false
7157 // for GlobalAddressSDNode since the same GlobalAddress may be represented
7158 // by multiple nodes with different offsets.
7159 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
7160 GV = G->getGlobal();
7161 Offset += G->getOffset();
7165 // Return the underlying Constant value, and update the Offset. Return false
7166 // for ConstantSDNodes since the same constant pool entry may be represented
7167 // by multiple nodes with different offsets.
7168 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
7169 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
7170 : (void *)C->getConstVal();
7171 Offset += C->getOffset();
7174 // If it's any of the following then it can't alias with anything but itself.
7175 return isa<FrameIndexSDNode>(Base);
7178 /// isAlias - Return true if there is any possibility that the two addresses
7180 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
7181 const Value *SrcValue1, int SrcValueOffset1,
7182 unsigned SrcValueAlign1,
7183 const MDNode *TBAAInfo1,
7184 SDValue Ptr2, int64_t Size2,
7185 const Value *SrcValue2, int SrcValueOffset2,
7186 unsigned SrcValueAlign2,
7187 const MDNode *TBAAInfo2) const {
7188 // If they are the same then they must be aliases.
7189 if (Ptr1 == Ptr2) return true;
7191 // Gather base node and offset information.
7192 SDValue Base1, Base2;
7193 int64_t Offset1, Offset2;
7194 const GlobalValue *GV1, *GV2;
7196 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
7197 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
7199 // If they have a same base address then check to see if they overlap.
7200 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
7201 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
7203 // It is possible for different frame indices to alias each other, mostly
7204 // when tail call optimization reuses return address slots for arguments.
7205 // To catch this case, look up the actual index of frame indices to compute
7206 // the real alias relationship.
7207 if (isFrameIndex1 && isFrameIndex2) {
7208 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7209 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
7210 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
7211 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
7214 // Otherwise, if we know what the bases are, and they aren't identical, then
7215 // we know they cannot alias.
7216 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
7219 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
7220 // compared to the size and offset of the access, we may be able to prove they
7221 // do not alias. This check is conservative for now to catch cases created by
7222 // splitting vector types.
7223 if ((SrcValueAlign1 == SrcValueAlign2) &&
7224 (SrcValueOffset1 != SrcValueOffset2) &&
7225 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
7226 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
7227 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
7229 // There is no overlap between these relatively aligned accesses of similar
7230 // size, return no alias.
7231 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
7235 if (CombinerGlobalAA) {
7236 // Use alias analysis information.
7237 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
7238 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
7239 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
7240 AliasAnalysis::AliasResult AAResult =
7241 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
7242 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
7243 if (AAResult == AliasAnalysis::NoAlias)
7247 // Otherwise we have to assume they alias.
7251 /// FindAliasInfo - Extracts the relevant alias information from the memory
7252 /// node. Returns true if the operand was a load.
7253 bool DAGCombiner::FindAliasInfo(SDNode *N,
7254 SDValue &Ptr, int64_t &Size,
7255 const Value *&SrcValue,
7256 int &SrcValueOffset,
7257 unsigned &SrcValueAlign,
7258 const MDNode *&TBAAInfo) const {
7259 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7260 Ptr = LD->getBasePtr();
7261 Size = LD->getMemoryVT().getSizeInBits() >> 3;
7262 SrcValue = LD->getSrcValue();
7263 SrcValueOffset = LD->getSrcValueOffset();
7264 SrcValueAlign = LD->getOriginalAlignment();
7265 TBAAInfo = LD->getTBAAInfo();
7267 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7268 Ptr = ST->getBasePtr();
7269 Size = ST->getMemoryVT().getSizeInBits() >> 3;
7270 SrcValue = ST->getSrcValue();
7271 SrcValueOffset = ST->getSrcValueOffset();
7272 SrcValueAlign = ST->getOriginalAlignment();
7273 TBAAInfo = ST->getTBAAInfo();
7275 llvm_unreachable("FindAliasInfo expected a memory operand");
7281 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
7282 /// looking for aliasing nodes and adding them to the Aliases vector.
7283 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
7284 SmallVector<SDValue, 8> &Aliases) {
7285 SmallVector<SDValue, 8> Chains; // List of chains to visit.
7286 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
7288 // Get alias information for node.
7291 const Value *SrcValue;
7293 unsigned SrcValueAlign;
7294 const MDNode *SrcTBAAInfo;
7295 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
7296 SrcValueAlign, SrcTBAAInfo);
7299 Chains.push_back(OriginalChain);
7302 // Look at each chain and determine if it is an alias. If so, add it to the
7303 // aliases list. If not, then continue up the chain looking for the next
7305 while (!Chains.empty()) {
7306 SDValue Chain = Chains.back();
7309 // For TokenFactor nodes, look at each operand and only continue up the
7310 // chain until we find two aliases. If we've seen two aliases, assume we'll
7311 // find more and revert to original chain since the xform is unlikely to be
7314 // FIXME: The depth check could be made to return the last non-aliasing
7315 // chain we found before we hit a tokenfactor rather than the original
7317 if (Depth > 6 || Aliases.size() == 2) {
7319 Aliases.push_back(OriginalChain);
7323 // Don't bother if we've been before.
7324 if (!Visited.insert(Chain.getNode()))
7327 switch (Chain.getOpcode()) {
7328 case ISD::EntryToken:
7329 // Entry token is ideal chain operand, but handled in FindBetterChain.
7334 // Get alias information for Chain.
7337 const Value *OpSrcValue;
7338 int OpSrcValueOffset;
7339 unsigned OpSrcValueAlign;
7340 const MDNode *OpSrcTBAAInfo;
7341 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
7342 OpSrcValue, OpSrcValueOffset,
7346 // If chain is alias then stop here.
7347 if (!(IsLoad && IsOpLoad) &&
7348 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
7350 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
7351 OpSrcValueAlign, OpSrcTBAAInfo)) {
7352 Aliases.push_back(Chain);
7354 // Look further up the chain.
7355 Chains.push_back(Chain.getOperand(0));
7361 case ISD::TokenFactor:
7362 // We have to check each of the operands of the token factor for "small"
7363 // token factors, so we queue them up. Adding the operands to the queue
7364 // (stack) in reverse order maintains the original order and increases the
7365 // likelihood that getNode will find a matching token factor (CSE.)
7366 if (Chain.getNumOperands() > 16) {
7367 Aliases.push_back(Chain);
7370 for (unsigned n = Chain.getNumOperands(); n;)
7371 Chains.push_back(Chain.getOperand(--n));
7376 // For all other instructions we will just have to take what we can get.
7377 Aliases.push_back(Chain);
7383 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
7384 /// for a better chain (aliasing node.)
7385 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
7386 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
7388 // Accumulate all the aliases to this node.
7389 GatherAllAliases(N, OldChain, Aliases);
7391 if (Aliases.size() == 0) {
7392 // If no operands then chain to entry token.
7393 return DAG.getEntryNode();
7394 } else if (Aliases.size() == 1) {
7395 // If a single operand then chain to it. We don't need to revisit it.
7399 // Construct a custom tailored token factor.
7400 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
7401 &Aliases[0], Aliases.size());
7404 // SelectionDAG::Combine - This is the entry point for the file.
7406 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
7407 CodeGenOpt::Level OptLevel) {
7408 /// run - This is the main entry point to this class.
7410 DAGCombiner(*this, AA, OptLevel).Run(Level);