1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/Target/TargetData.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/ADT/SmallPtrSet.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
41 STATISTIC(NodesCombined , "Number of dag nodes combined");
42 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
43 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
44 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
45 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
49 CombinerAA("combiner-alias-analysis", cl::Hidden,
50 cl::desc("Turn on alias analysis during testing"));
53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
54 cl::desc("Include global information in alias analysis"));
56 //------------------------------ DAGCombiner ---------------------------------//
60 const TargetLowering &TLI;
62 CodeGenOpt::Level OptLevel;
66 // Worklist of all of the nodes that need to be simplified.
67 std::vector<SDNode*> WorkList;
69 // AA - Used for DAG load/store alias analysis.
72 /// AddUsersToWorkList - When an instruction is simplified, add all users of
73 /// the instruction to the work lists because they might get more simplified
76 void AddUsersToWorkList(SDNode *N) {
77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
82 /// visit - call the node-specific routine that knows how to fold each
83 /// particular type of node.
84 SDValue visit(SDNode *N);
87 /// AddToWorkList - Add to the work list making sure it's instance is at the
88 /// the back (next to be processed.)
89 void AddToWorkList(SDNode *N) {
90 removeFromWorkList(N);
91 WorkList.push_back(N);
94 /// removeFromWorkList - remove all instances of N from the worklist.
96 void removeFromWorkList(SDNode *N) {
97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
105 return CombineTo(N, &Res, 1, AddTo);
108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
110 SDValue To[] = { Res0, Res1 };
111 return CombineTo(N, To, 2, AddTo);
114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
118 /// SimplifyDemandedBits - Check the specified integer node value to see if
119 /// it can be simplified or if things it uses can be simplified by bit
120 /// propagation. If so, return true.
121 bool SimplifyDemandedBits(SDValue Op) {
122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
123 APInt Demanded = APInt::getAllOnesValue(BitWidth);
124 return SimplifyDemandedBits(Op, Demanded);
127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
129 bool CombineToPreIndexedLoadStore(SDNode *N);
130 bool CombineToPostIndexedLoadStore(SDNode *N);
132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
136 SDValue PromoteIntBinOp(SDValue Op);
137 SDValue PromoteIntShiftOp(SDValue Op);
138 SDValue PromoteExtend(SDValue Op);
139 bool PromoteLoad(SDValue Op);
141 /// combine - call the node-specific routine that knows how to fold each
142 /// particular type of node. If that doesn't do anything, try the
143 /// target-specific DAG combines.
144 SDValue combine(SDNode *N);
146 // Visitation implementation - Implement dag node combining for different
147 // node types. The semantics are as follows:
149 // SDValue.getNode() == 0 - No change was made
150 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
151 // otherwise - N should be replaced by the returned Operand.
153 SDValue visitTokenFactor(SDNode *N);
154 SDValue visitMERGE_VALUES(SDNode *N);
155 SDValue visitADD(SDNode *N);
156 SDValue visitSUB(SDNode *N);
157 SDValue visitADDC(SDNode *N);
158 SDValue visitADDE(SDNode *N);
159 SDValue visitMUL(SDNode *N);
160 SDValue visitSDIV(SDNode *N);
161 SDValue visitUDIV(SDNode *N);
162 SDValue visitSREM(SDNode *N);
163 SDValue visitUREM(SDNode *N);
164 SDValue visitMULHU(SDNode *N);
165 SDValue visitMULHS(SDNode *N);
166 SDValue visitSMUL_LOHI(SDNode *N);
167 SDValue visitUMUL_LOHI(SDNode *N);
168 SDValue visitSDIVREM(SDNode *N);
169 SDValue visitUDIVREM(SDNode *N);
170 SDValue visitAND(SDNode *N);
171 SDValue visitOR(SDNode *N);
172 SDValue visitXOR(SDNode *N);
173 SDValue SimplifyVBinOp(SDNode *N);
174 SDValue visitSHL(SDNode *N);
175 SDValue visitSRA(SDNode *N);
176 SDValue visitSRL(SDNode *N);
177 SDValue visitCTLZ(SDNode *N);
178 SDValue visitCTTZ(SDNode *N);
179 SDValue visitCTPOP(SDNode *N);
180 SDValue visitSELECT(SDNode *N);
181 SDValue visitSELECT_CC(SDNode *N);
182 SDValue visitSETCC(SDNode *N);
183 SDValue visitSIGN_EXTEND(SDNode *N);
184 SDValue visitZERO_EXTEND(SDNode *N);
185 SDValue visitANY_EXTEND(SDNode *N);
186 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
187 SDValue visitTRUNCATE(SDNode *N);
188 SDValue visitBITCAST(SDNode *N);
189 SDValue visitBUILD_PAIR(SDNode *N);
190 SDValue visitFADD(SDNode *N);
191 SDValue visitFSUB(SDNode *N);
192 SDValue visitFMUL(SDNode *N);
193 SDValue visitFDIV(SDNode *N);
194 SDValue visitFREM(SDNode *N);
195 SDValue visitFCOPYSIGN(SDNode *N);
196 SDValue visitSINT_TO_FP(SDNode *N);
197 SDValue visitUINT_TO_FP(SDNode *N);
198 SDValue visitFP_TO_SINT(SDNode *N);
199 SDValue visitFP_TO_UINT(SDNode *N);
200 SDValue visitFP_ROUND(SDNode *N);
201 SDValue visitFP_ROUND_INREG(SDNode *N);
202 SDValue visitFP_EXTEND(SDNode *N);
203 SDValue visitFNEG(SDNode *N);
204 SDValue visitFABS(SDNode *N);
205 SDValue visitBRCOND(SDNode *N);
206 SDValue visitBR_CC(SDNode *N);
207 SDValue visitLOAD(SDNode *N);
208 SDValue visitSTORE(SDNode *N);
209 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
210 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
211 SDValue visitBUILD_VECTOR(SDNode *N);
212 SDValue visitCONCAT_VECTORS(SDNode *N);
213 SDValue visitVECTOR_SHUFFLE(SDNode *N);
214 SDValue visitMEMBARRIER(SDNode *N);
216 SDValue XformToShuffleWithZero(SDNode *N);
217 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
219 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
221 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
222 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
223 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
224 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
225 SDValue N3, ISD::CondCode CC,
226 bool NotExtCompare = false);
227 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
228 DebugLoc DL, bool foldBooleans = true);
229 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
231 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
232 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
233 SDValue BuildSDIV(SDNode *N);
234 SDValue BuildUDIV(SDNode *N);
235 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
236 SDValue ReduceLoadWidth(SDNode *N);
237 SDValue ReduceLoadOpStoreWidth(SDNode *N);
238 SDValue TransformFPLoadStorePair(SDNode *N);
240 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
242 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
243 /// looking for aliasing nodes and adding them to the Aliases vector.
244 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
245 SmallVector<SDValue, 8> &Aliases);
247 /// isAlias - Return true if there is any possibility that the two addresses
249 bool isAlias(SDValue Ptr1, int64_t Size1,
250 const Value *SrcValue1, int SrcValueOffset1,
251 unsigned SrcValueAlign1,
252 const MDNode *TBAAInfo1,
253 SDValue Ptr2, int64_t Size2,
254 const Value *SrcValue2, int SrcValueOffset2,
255 unsigned SrcValueAlign2,
256 const MDNode *TBAAInfo2) const;
258 /// FindAliasInfo - Extracts the relevant alias information from the memory
259 /// node. Returns true if the operand was a load.
260 bool FindAliasInfo(SDNode *N,
261 SDValue &Ptr, int64_t &Size,
262 const Value *&SrcValue, int &SrcValueOffset,
263 unsigned &SrcValueAlignment,
264 const MDNode *&TBAAInfo) const;
266 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
267 /// looking for a better chain (aliasing node.)
268 SDValue FindBetterChain(SDNode *N, SDValue Chain);
271 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
272 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted),
273 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
275 /// Run - runs the dag combiner on all nodes in the work list
276 void Run(CombineLevel AtLevel);
278 SelectionDAG &getDAG() const { return DAG; }
280 /// getShiftAmountTy - Returns a type large enough to hold any valid
281 /// shift amount - before type legalization these can be huge.
282 EVT getShiftAmountTy(EVT LHSTy) {
283 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy();
286 /// isTypeLegal - This method returns true if we are running before type
287 /// legalization or if the specified VT is legal.
288 bool isTypeLegal(const EVT &VT) {
289 if (!LegalTypes) return true;
290 return TLI.isTypeLegal(VT);
297 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
298 /// nodes from the worklist.
299 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
302 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
304 virtual void NodeDeleted(SDNode *N, SDNode *E) {
305 DC.removeFromWorkList(N);
308 virtual void NodeUpdated(SDNode *N) {
314 //===----------------------------------------------------------------------===//
315 // TargetLowering::DAGCombinerInfo implementation
316 //===----------------------------------------------------------------------===//
318 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
319 ((DAGCombiner*)DC)->AddToWorkList(N);
322 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
323 ((DAGCombiner*)DC)->removeFromWorkList(N);
326 SDValue TargetLowering::DAGCombinerInfo::
327 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
328 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
331 SDValue TargetLowering::DAGCombinerInfo::
332 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
333 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
337 SDValue TargetLowering::DAGCombinerInfo::
338 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
339 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
342 void TargetLowering::DAGCombinerInfo::
343 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
344 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
347 //===----------------------------------------------------------------------===//
349 //===----------------------------------------------------------------------===//
351 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
352 /// specified expression for the same cost as the expression itself, or 2 if we
353 /// can compute the negated form more cheaply than the expression itself.
354 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
355 unsigned Depth = 0) {
356 // No compile time optimizations on this type.
357 if (Op.getValueType() == MVT::ppcf128)
360 // fneg is removable even if it has multiple uses.
361 if (Op.getOpcode() == ISD::FNEG) return 2;
363 // Don't allow anything with multiple uses.
364 if (!Op.hasOneUse()) return 0;
366 // Don't recurse exponentially.
367 if (Depth > 6) return 0;
369 switch (Op.getOpcode()) {
370 default: return false;
371 case ISD::ConstantFP:
372 // Don't invert constant FP values after legalize. The negated constant
373 // isn't necessarily legal.
374 return LegalOperations ? 0 : 1;
376 // FIXME: determine better conditions for this xform.
377 if (!UnsafeFPMath) return 0;
379 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
380 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
382 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
383 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
385 // We can't turn -(A-B) into B-A when we honor signed zeros.
386 if (!UnsafeFPMath) return 0;
388 // fold (fneg (fsub A, B)) -> (fsub B, A)
393 if (HonorSignDependentRoundingFPMath()) return 0;
395 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
396 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
399 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
404 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
408 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
409 /// returns the newly negated expression.
410 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
411 bool LegalOperations, unsigned Depth = 0) {
412 // fneg is removable even if it has multiple uses.
413 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
415 // Don't allow anything with multiple uses.
416 assert(Op.hasOneUse() && "Unknown reuse!");
418 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
419 switch (Op.getOpcode()) {
420 default: llvm_unreachable("Unknown code");
421 case ISD::ConstantFP: {
422 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
424 return DAG.getConstantFP(V, Op.getValueType());
427 // FIXME: determine better conditions for this xform.
428 assert(UnsafeFPMath);
430 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
431 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
432 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
433 GetNegatedExpression(Op.getOperand(0), DAG,
434 LegalOperations, Depth+1),
436 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
437 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
438 GetNegatedExpression(Op.getOperand(1), DAG,
439 LegalOperations, Depth+1),
442 // We can't turn -(A-B) into B-A when we honor signed zeros.
443 assert(UnsafeFPMath);
445 // fold (fneg (fsub 0, B)) -> B
446 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
447 if (N0CFP->getValueAPF().isZero())
448 return Op.getOperand(1);
450 // fold (fneg (fsub A, B)) -> (fsub B, A)
451 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
452 Op.getOperand(1), Op.getOperand(0));
456 assert(!HonorSignDependentRoundingFPMath());
458 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
459 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
460 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
461 GetNegatedExpression(Op.getOperand(0), DAG,
462 LegalOperations, Depth+1),
465 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
466 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
468 GetNegatedExpression(Op.getOperand(1), DAG,
469 LegalOperations, Depth+1));
473 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
474 GetNegatedExpression(Op.getOperand(0), DAG,
475 LegalOperations, Depth+1));
477 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
478 GetNegatedExpression(Op.getOperand(0), DAG,
479 LegalOperations, Depth+1),
485 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
486 // that selects between the values 1 and 0, making it equivalent to a setcc.
487 // Also, set the incoming LHS, RHS, and CC references to the appropriate
488 // nodes based on the type of node we are checking. This simplifies life a
489 // bit for the callers.
490 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
492 if (N.getOpcode() == ISD::SETCC) {
493 LHS = N.getOperand(0);
494 RHS = N.getOperand(1);
495 CC = N.getOperand(2);
498 if (N.getOpcode() == ISD::SELECT_CC &&
499 N.getOperand(2).getOpcode() == ISD::Constant &&
500 N.getOperand(3).getOpcode() == ISD::Constant &&
501 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
502 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
503 LHS = N.getOperand(0);
504 RHS = N.getOperand(1);
505 CC = N.getOperand(4);
511 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
512 // one use. If this is true, it allows the users to invert the operation for
513 // free when it is profitable to do so.
514 static bool isOneUseSetCC(SDValue N) {
516 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
521 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
522 SDValue N0, SDValue N1) {
523 EVT VT = N0.getValueType();
524 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
525 if (isa<ConstantSDNode>(N1)) {
526 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
528 DAG.FoldConstantArithmetic(Opc, VT,
529 cast<ConstantSDNode>(N0.getOperand(1)),
530 cast<ConstantSDNode>(N1));
531 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
532 } else if (N0.hasOneUse()) {
533 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
534 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
535 N0.getOperand(0), N1);
536 AddToWorkList(OpNode.getNode());
537 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
541 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
542 if (isa<ConstantSDNode>(N0)) {
543 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
545 DAG.FoldConstantArithmetic(Opc, VT,
546 cast<ConstantSDNode>(N1.getOperand(1)),
547 cast<ConstantSDNode>(N0));
548 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
549 } else if (N1.hasOneUse()) {
550 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
551 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
552 N1.getOperand(0), N0);
553 AddToWorkList(OpNode.getNode());
554 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
561 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
563 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
565 DEBUG(dbgs() << "\nReplacing.1 ";
567 dbgs() << "\nWith: ";
568 To[0].getNode()->dump(&DAG);
569 dbgs() << " and " << NumTo-1 << " other values\n";
570 for (unsigned i = 0, e = NumTo; i != e; ++i)
571 assert((!To[i].getNode() ||
572 N->getValueType(i) == To[i].getValueType()) &&
573 "Cannot combine value to value of different type!"));
574 WorkListRemover DeadNodes(*this);
575 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
578 // Push the new nodes and any users onto the worklist
579 for (unsigned i = 0, e = NumTo; i != e; ++i) {
580 if (To[i].getNode()) {
581 AddToWorkList(To[i].getNode());
582 AddUsersToWorkList(To[i].getNode());
587 // Finally, if the node is now dead, remove it from the graph. The node
588 // may not be dead if the replacement process recursively simplified to
589 // something else needing this node.
590 if (N->use_empty()) {
591 // Nodes can be reintroduced into the worklist. Make sure we do not
592 // process a node that has been replaced.
593 removeFromWorkList(N);
595 // Finally, since the node is now dead, remove it from the graph.
598 return SDValue(N, 0);
602 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
603 // Replace all uses. If any nodes become isomorphic to other nodes and
604 // are deleted, make sure to remove them from our worklist.
605 WorkListRemover DeadNodes(*this);
606 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
608 // Push the new node and any (possibly new) users onto the worklist.
609 AddToWorkList(TLO.New.getNode());
610 AddUsersToWorkList(TLO.New.getNode());
612 // Finally, if the node is now dead, remove it from the graph. The node
613 // may not be dead if the replacement process recursively simplified to
614 // something else needing this node.
615 if (TLO.Old.getNode()->use_empty()) {
616 removeFromWorkList(TLO.Old.getNode());
618 // If the operands of this node are only used by the node, they will now
619 // be dead. Make sure to visit them first to delete dead nodes early.
620 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
621 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
622 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
624 DAG.DeleteNode(TLO.Old.getNode());
628 /// SimplifyDemandedBits - Check the specified integer node value to see if
629 /// it can be simplified or if things it uses can be simplified by bit
630 /// propagation. If so, return true.
631 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
632 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
633 APInt KnownZero, KnownOne;
634 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
638 AddToWorkList(Op.getNode());
640 // Replace the old value with the new one.
642 DEBUG(dbgs() << "\nReplacing.2 ";
643 TLO.Old.getNode()->dump(&DAG);
644 dbgs() << "\nWith: ";
645 TLO.New.getNode()->dump(&DAG);
648 CommitTargetLoweringOpt(TLO);
652 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
653 DebugLoc dl = Load->getDebugLoc();
654 EVT VT = Load->getValueType(0);
655 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
657 DEBUG(dbgs() << "\nReplacing.9 ";
659 dbgs() << "\nWith: ";
660 Trunc.getNode()->dump(&DAG);
662 WorkListRemover DeadNodes(*this);
663 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes);
664 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1),
666 removeFromWorkList(Load);
667 DAG.DeleteNode(Load);
668 AddToWorkList(Trunc.getNode());
671 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
673 DebugLoc dl = Op.getDebugLoc();
674 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
675 EVT MemVT = LD->getMemoryVT();
676 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
677 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
679 : LD->getExtensionType();
681 return DAG.getExtLoad(ExtType, dl, PVT,
682 LD->getChain(), LD->getBasePtr(),
683 LD->getPointerInfo(),
684 MemVT, LD->isVolatile(),
685 LD->isNonTemporal(), LD->getAlignment());
688 unsigned Opc = Op.getOpcode();
691 case ISD::AssertSext:
692 return DAG.getNode(ISD::AssertSext, dl, PVT,
693 SExtPromoteOperand(Op.getOperand(0), PVT),
695 case ISD::AssertZext:
696 return DAG.getNode(ISD::AssertZext, dl, PVT,
697 ZExtPromoteOperand(Op.getOperand(0), PVT),
699 case ISD::Constant: {
701 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
702 return DAG.getNode(ExtOpc, dl, PVT, Op);
706 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
708 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
711 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
712 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
714 EVT OldVT = Op.getValueType();
715 DebugLoc dl = Op.getDebugLoc();
716 bool Replace = false;
717 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
718 if (NewOp.getNode() == 0)
720 AddToWorkList(NewOp.getNode());
723 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
724 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
725 DAG.getValueType(OldVT));
728 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
729 EVT OldVT = Op.getValueType();
730 DebugLoc dl = Op.getDebugLoc();
731 bool Replace = false;
732 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
733 if (NewOp.getNode() == 0)
735 AddToWorkList(NewOp.getNode());
738 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
739 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
742 /// PromoteIntBinOp - Promote the specified integer binary operation if the
743 /// target indicates it is beneficial. e.g. On x86, it's usually better to
744 /// promote i16 operations to i32 since i16 instructions are longer.
745 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
746 if (!LegalOperations)
749 EVT VT = Op.getValueType();
750 if (VT.isVector() || !VT.isInteger())
753 // If operation type is 'undesirable', e.g. i16 on x86, consider
755 unsigned Opc = Op.getOpcode();
756 if (TLI.isTypeDesirableForOp(Opc, VT))
760 // Consult target whether it is a good idea to promote this operation and
761 // what's the right type to promote it to.
762 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
763 assert(PVT != VT && "Don't know what type to promote to!");
765 bool Replace0 = false;
766 SDValue N0 = Op.getOperand(0);
767 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
768 if (NN0.getNode() == 0)
771 bool Replace1 = false;
772 SDValue N1 = Op.getOperand(1);
777 NN1 = PromoteOperand(N1, PVT, Replace1);
778 if (NN1.getNode() == 0)
782 AddToWorkList(NN0.getNode());
784 AddToWorkList(NN1.getNode());
787 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
789 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
791 DEBUG(dbgs() << "\nPromoting ";
792 Op.getNode()->dump(&DAG));
793 DebugLoc dl = Op.getDebugLoc();
794 return DAG.getNode(ISD::TRUNCATE, dl, VT,
795 DAG.getNode(Opc, dl, PVT, NN0, NN1));
800 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
801 /// target indicates it is beneficial. e.g. On x86, it's usually better to
802 /// promote i16 operations to i32 since i16 instructions are longer.
803 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
804 if (!LegalOperations)
807 EVT VT = Op.getValueType();
808 if (VT.isVector() || !VT.isInteger())
811 // If operation type is 'undesirable', e.g. i16 on x86, consider
813 unsigned Opc = Op.getOpcode();
814 if (TLI.isTypeDesirableForOp(Opc, VT))
818 // Consult target whether it is a good idea to promote this operation and
819 // what's the right type to promote it to.
820 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
821 assert(PVT != VT && "Don't know what type to promote to!");
823 bool Replace = false;
824 SDValue N0 = Op.getOperand(0);
826 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
827 else if (Opc == ISD::SRL)
828 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
830 N0 = PromoteOperand(N0, PVT, Replace);
831 if (N0.getNode() == 0)
834 AddToWorkList(N0.getNode());
836 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
838 DEBUG(dbgs() << "\nPromoting ";
839 Op.getNode()->dump(&DAG));
840 DebugLoc dl = Op.getDebugLoc();
841 return DAG.getNode(ISD::TRUNCATE, dl, VT,
842 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
847 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
848 if (!LegalOperations)
851 EVT VT = Op.getValueType();
852 if (VT.isVector() || !VT.isInteger())
855 // If operation type is 'undesirable', e.g. i16 on x86, consider
857 unsigned Opc = Op.getOpcode();
858 if (TLI.isTypeDesirableForOp(Opc, VT))
862 // Consult target whether it is a good idea to promote this operation and
863 // what's the right type to promote it to.
864 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
865 assert(PVT != VT && "Don't know what type to promote to!");
866 // fold (aext (aext x)) -> (aext x)
867 // fold (aext (zext x)) -> (zext x)
868 // fold (aext (sext x)) -> (sext x)
869 DEBUG(dbgs() << "\nPromoting ";
870 Op.getNode()->dump(&DAG));
871 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
876 bool DAGCombiner::PromoteLoad(SDValue Op) {
877 if (!LegalOperations)
880 EVT VT = Op.getValueType();
881 if (VT.isVector() || !VT.isInteger())
884 // If operation type is 'undesirable', e.g. i16 on x86, consider
886 unsigned Opc = Op.getOpcode();
887 if (TLI.isTypeDesirableForOp(Opc, VT))
891 // Consult target whether it is a good idea to promote this operation and
892 // what's the right type to promote it to.
893 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
894 assert(PVT != VT && "Don't know what type to promote to!");
896 DebugLoc dl = Op.getDebugLoc();
897 SDNode *N = Op.getNode();
898 LoadSDNode *LD = cast<LoadSDNode>(N);
899 EVT MemVT = LD->getMemoryVT();
900 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
901 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
903 : LD->getExtensionType();
904 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
905 LD->getChain(), LD->getBasePtr(),
906 LD->getPointerInfo(),
907 MemVT, LD->isVolatile(),
908 LD->isNonTemporal(), LD->getAlignment());
909 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
911 DEBUG(dbgs() << "\nPromoting ";
914 Result.getNode()->dump(&DAG);
916 WorkListRemover DeadNodes(*this);
917 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes);
918 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes);
919 removeFromWorkList(N);
921 AddToWorkList(Result.getNode());
928 //===----------------------------------------------------------------------===//
929 // Main DAG Combiner implementation
930 //===----------------------------------------------------------------------===//
932 void DAGCombiner::Run(CombineLevel AtLevel) {
933 // set the instance variables, so that the various visit routines may use it.
935 LegalOperations = Level >= NoIllegalOperations;
936 LegalTypes = Level >= NoIllegalTypes;
938 // Add all the dag nodes to the worklist.
939 WorkList.reserve(DAG.allnodes_size());
940 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
941 E = DAG.allnodes_end(); I != E; ++I)
942 WorkList.push_back(I);
944 // Create a dummy node (which is not added to allnodes), that adds a reference
945 // to the root node, preventing it from being deleted, and tracking any
946 // changes of the root.
947 HandleSDNode Dummy(DAG.getRoot());
949 // The root of the dag may dangle to deleted nodes until the dag combiner is
950 // done. Set it to null to avoid confusion.
951 DAG.setRoot(SDValue());
953 // while the worklist isn't empty, inspect the node on the end of it and
954 // try and combine it.
955 while (!WorkList.empty()) {
956 SDNode *N = WorkList.back();
959 // If N has no uses, it is dead. Make sure to revisit all N's operands once
960 // N is deleted from the DAG, since they too may now be dead or may have a
961 // reduced number of uses, allowing other xforms.
962 if (N->use_empty() && N != &Dummy) {
963 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
964 AddToWorkList(N->getOperand(i).getNode());
970 SDValue RV = combine(N);
972 if (RV.getNode() == 0)
977 // If we get back the same node we passed in, rather than a new node or
978 // zero, we know that the node must have defined multiple values and
979 // CombineTo was used. Since CombineTo takes care of the worklist
980 // mechanics for us, we have no work to do in this case.
981 if (RV.getNode() == N)
984 assert(N->getOpcode() != ISD::DELETED_NODE &&
985 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
986 "Node was deleted but visit returned new node!");
988 DEBUG(dbgs() << "\nReplacing.3 ";
990 dbgs() << "\nWith: ";
991 RV.getNode()->dump(&DAG);
993 WorkListRemover DeadNodes(*this);
994 if (N->getNumValues() == RV.getNode()->getNumValues())
995 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
997 assert(N->getValueType(0) == RV.getValueType() &&
998 N->getNumValues() == 1 && "Type mismatch");
1000 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
1003 // Push the new node and any users onto the worklist
1004 AddToWorkList(RV.getNode());
1005 AddUsersToWorkList(RV.getNode());
1007 // Add any uses of the old node to the worklist in case this node is the
1008 // last one that uses them. They may become dead after this node is
1010 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1011 AddToWorkList(N->getOperand(i).getNode());
1013 // Finally, if the node is now dead, remove it from the graph. The node
1014 // may not be dead if the replacement process recursively simplified to
1015 // something else needing this node.
1016 if (N->use_empty()) {
1017 // Nodes can be reintroduced into the worklist. Make sure we do not
1018 // process a node that has been replaced.
1019 removeFromWorkList(N);
1021 // Finally, since the node is now dead, remove it from the graph.
1026 // If the root changed (e.g. it was a dead load, update the root).
1027 DAG.setRoot(Dummy.getValue());
1030 SDValue DAGCombiner::visit(SDNode *N) {
1031 switch (N->getOpcode()) {
1033 case ISD::TokenFactor: return visitTokenFactor(N);
1034 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1035 case ISD::ADD: return visitADD(N);
1036 case ISD::SUB: return visitSUB(N);
1037 case ISD::ADDC: return visitADDC(N);
1038 case ISD::ADDE: return visitADDE(N);
1039 case ISD::MUL: return visitMUL(N);
1040 case ISD::SDIV: return visitSDIV(N);
1041 case ISD::UDIV: return visitUDIV(N);
1042 case ISD::SREM: return visitSREM(N);
1043 case ISD::UREM: return visitUREM(N);
1044 case ISD::MULHU: return visitMULHU(N);
1045 case ISD::MULHS: return visitMULHS(N);
1046 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1047 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1048 case ISD::SDIVREM: return visitSDIVREM(N);
1049 case ISD::UDIVREM: return visitUDIVREM(N);
1050 case ISD::AND: return visitAND(N);
1051 case ISD::OR: return visitOR(N);
1052 case ISD::XOR: return visitXOR(N);
1053 case ISD::SHL: return visitSHL(N);
1054 case ISD::SRA: return visitSRA(N);
1055 case ISD::SRL: return visitSRL(N);
1056 case ISD::CTLZ: return visitCTLZ(N);
1057 case ISD::CTTZ: return visitCTTZ(N);
1058 case ISD::CTPOP: return visitCTPOP(N);
1059 case ISD::SELECT: return visitSELECT(N);
1060 case ISD::SELECT_CC: return visitSELECT_CC(N);
1061 case ISD::SETCC: return visitSETCC(N);
1062 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1063 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1064 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1065 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1066 case ISD::TRUNCATE: return visitTRUNCATE(N);
1067 case ISD::BITCAST: return visitBITCAST(N);
1068 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1069 case ISD::FADD: return visitFADD(N);
1070 case ISD::FSUB: return visitFSUB(N);
1071 case ISD::FMUL: return visitFMUL(N);
1072 case ISD::FDIV: return visitFDIV(N);
1073 case ISD::FREM: return visitFREM(N);
1074 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1075 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1076 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1077 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1078 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1079 case ISD::FP_ROUND: return visitFP_ROUND(N);
1080 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1081 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1082 case ISD::FNEG: return visitFNEG(N);
1083 case ISD::FABS: return visitFABS(N);
1084 case ISD::BRCOND: return visitBRCOND(N);
1085 case ISD::BR_CC: return visitBR_CC(N);
1086 case ISD::LOAD: return visitLOAD(N);
1087 case ISD::STORE: return visitSTORE(N);
1088 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1089 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1090 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1091 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1092 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1093 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1098 SDValue DAGCombiner::combine(SDNode *N) {
1099 SDValue RV = visit(N);
1101 // If nothing happened, try a target-specific DAG combine.
1102 if (RV.getNode() == 0) {
1103 assert(N->getOpcode() != ISD::DELETED_NODE &&
1104 "Node was deleted but visit returned NULL!");
1106 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1107 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1109 // Expose the DAG combiner to the target combiner impls.
1110 TargetLowering::DAGCombinerInfo
1111 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1113 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1117 // If nothing happened still, try promoting the operation.
1118 if (RV.getNode() == 0) {
1119 switch (N->getOpcode()) {
1127 RV = PromoteIntBinOp(SDValue(N, 0));
1132 RV = PromoteIntShiftOp(SDValue(N, 0));
1134 case ISD::SIGN_EXTEND:
1135 case ISD::ZERO_EXTEND:
1136 case ISD::ANY_EXTEND:
1137 RV = PromoteExtend(SDValue(N, 0));
1140 if (PromoteLoad(SDValue(N, 0)))
1146 // If N is a commutative binary node, try commuting it to enable more
1148 if (RV.getNode() == 0 &&
1149 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1150 N->getNumValues() == 1) {
1151 SDValue N0 = N->getOperand(0);
1152 SDValue N1 = N->getOperand(1);
1154 // Constant operands are canonicalized to RHS.
1155 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1156 SDValue Ops[] = { N1, N0 };
1157 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1160 return SDValue(CSENode, 0);
1167 /// getInputChainForNode - Given a node, return its input chain if it has one,
1168 /// otherwise return a null sd operand.
1169 static SDValue getInputChainForNode(SDNode *N) {
1170 if (unsigned NumOps = N->getNumOperands()) {
1171 if (N->getOperand(0).getValueType() == MVT::Other)
1172 return N->getOperand(0);
1173 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1174 return N->getOperand(NumOps-1);
1175 for (unsigned i = 1; i < NumOps-1; ++i)
1176 if (N->getOperand(i).getValueType() == MVT::Other)
1177 return N->getOperand(i);
1182 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1183 // If N has two operands, where one has an input chain equal to the other,
1184 // the 'other' chain is redundant.
1185 if (N->getNumOperands() == 2) {
1186 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1187 return N->getOperand(0);
1188 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1189 return N->getOperand(1);
1192 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1193 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1194 SmallPtrSet<SDNode*, 16> SeenOps;
1195 bool Changed = false; // If we should replace this token factor.
1197 // Start out with this token factor.
1200 // Iterate through token factors. The TFs grows when new token factors are
1202 for (unsigned i = 0; i < TFs.size(); ++i) {
1203 SDNode *TF = TFs[i];
1205 // Check each of the operands.
1206 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1207 SDValue Op = TF->getOperand(i);
1209 switch (Op.getOpcode()) {
1210 case ISD::EntryToken:
1211 // Entry tokens don't need to be added to the list. They are
1216 case ISD::TokenFactor:
1217 if (Op.hasOneUse() &&
1218 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1219 // Queue up for processing.
1220 TFs.push_back(Op.getNode());
1221 // Clean up in case the token factor is removed.
1222 AddToWorkList(Op.getNode());
1229 // Only add if it isn't already in the list.
1230 if (SeenOps.insert(Op.getNode()))
1241 // If we've change things around then replace token factor.
1244 // The entry token is the only possible outcome.
1245 Result = DAG.getEntryNode();
1247 // New and improved token factor.
1248 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1249 MVT::Other, &Ops[0], Ops.size());
1252 // Don't add users to work list.
1253 return CombineTo(N, Result, false);
1259 /// MERGE_VALUES can always be eliminated.
1260 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1261 WorkListRemover DeadNodes(*this);
1262 // Replacing results may cause a different MERGE_VALUES to suddenly
1263 // be CSE'd with N, and carry its uses with it. Iterate until no
1264 // uses remain, to ensure that the node can be safely deleted.
1266 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1267 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
1269 } while (!N->use_empty());
1270 removeFromWorkList(N);
1272 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1276 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1277 SelectionDAG &DAG) {
1278 EVT VT = N0.getValueType();
1279 SDValue N00 = N0.getOperand(0);
1280 SDValue N01 = N0.getOperand(1);
1281 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1283 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1284 isa<ConstantSDNode>(N00.getOperand(1))) {
1285 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1286 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1287 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1288 N00.getOperand(0), N01),
1289 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1290 N00.getOperand(1), N01));
1291 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1297 /// isCarryMaterialization - Returns true if V is an ADDE node that is known to
1298 /// return 0 or 1 depending on the carry flag.
1299 static bool isCarryMaterialization(SDValue V) {
1300 if (V.getOpcode() != ISD::ADDE)
1303 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(0));
1304 return C && C->isNullValue() && V.getOperand(0) == V.getOperand(1);
1307 SDValue DAGCombiner::visitADD(SDNode *N) {
1308 SDValue N0 = N->getOperand(0);
1309 SDValue N1 = N->getOperand(1);
1310 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1311 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1312 EVT VT = N0.getValueType();
1315 if (VT.isVector()) {
1316 SDValue FoldedVOp = SimplifyVBinOp(N);
1317 if (FoldedVOp.getNode()) return FoldedVOp;
1320 // fold (add x, undef) -> undef
1321 if (N0.getOpcode() == ISD::UNDEF)
1323 if (N1.getOpcode() == ISD::UNDEF)
1325 // fold (add c1, c2) -> c1+c2
1327 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1328 // canonicalize constant to RHS
1330 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1331 // fold (add x, 0) -> x
1332 if (N1C && N1C->isNullValue())
1334 // fold (add Sym, c) -> Sym+c
1335 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1336 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1337 GA->getOpcode() == ISD::GlobalAddress)
1338 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1340 (uint64_t)N1C->getSExtValue());
1341 // fold ((c1-A)+c2) -> (c1+c2)-A
1342 if (N1C && N0.getOpcode() == ISD::SUB)
1343 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1344 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1345 DAG.getConstant(N1C->getAPIntValue()+
1346 N0C->getAPIntValue(), VT),
1349 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1350 if (RADD.getNode() != 0)
1352 // fold ((0-A) + B) -> B-A
1353 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1354 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1355 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1356 // fold (A + (0-B)) -> A-B
1357 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1358 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1359 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1360 // fold (A+(B-A)) -> B
1361 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1362 return N1.getOperand(0);
1363 // fold ((B-A)+A) -> B
1364 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1365 return N0.getOperand(0);
1366 // fold (A+(B-(A+C))) to (B-C)
1367 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1368 N0 == N1.getOperand(1).getOperand(0))
1369 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1370 N1.getOperand(1).getOperand(1));
1371 // fold (A+(B-(C+A))) to (B-C)
1372 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1373 N0 == N1.getOperand(1).getOperand(1))
1374 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1375 N1.getOperand(1).getOperand(0));
1376 // fold (A+((B-A)+or-C)) to (B+or-C)
1377 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1378 N1.getOperand(0).getOpcode() == ISD::SUB &&
1379 N0 == N1.getOperand(0).getOperand(1))
1380 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1381 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1383 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1384 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1385 SDValue N00 = N0.getOperand(0);
1386 SDValue N01 = N0.getOperand(1);
1387 SDValue N10 = N1.getOperand(0);
1388 SDValue N11 = N1.getOperand(1);
1390 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1391 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1392 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1393 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1396 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1397 return SDValue(N, 0);
1399 // fold (a+b) -> (a|b) iff a and b share no bits.
1400 if (VT.isInteger() && !VT.isVector()) {
1401 APInt LHSZero, LHSOne;
1402 APInt RHSZero, RHSOne;
1403 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1404 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1406 if (LHSZero.getBoolValue()) {
1407 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1409 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1410 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1411 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1412 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1413 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1417 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1418 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1419 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1420 if (Result.getNode()) return Result;
1422 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1423 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1424 if (Result.getNode()) return Result;
1427 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1428 if (N1.getOpcode() == ISD::SHL &&
1429 N1.getOperand(0).getOpcode() == ISD::SUB)
1430 if (ConstantSDNode *C =
1431 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1432 if (C->getAPIntValue() == 0)
1433 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1434 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1435 N1.getOperand(0).getOperand(1),
1437 if (N0.getOpcode() == ISD::SHL &&
1438 N0.getOperand(0).getOpcode() == ISD::SUB)
1439 if (ConstantSDNode *C =
1440 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1441 if (C->getAPIntValue() == 0)
1442 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1443 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1444 N0.getOperand(0).getOperand(1),
1447 if (N1.getOpcode() == ISD::AND) {
1448 SDValue AndOp0 = N1.getOperand(0);
1449 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1450 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1451 unsigned DestBits = VT.getScalarType().getSizeInBits();
1453 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1454 // and similar xforms where the inner op is either ~0 or 0.
1455 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1456 DebugLoc DL = N->getDebugLoc();
1457 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1461 // add (sext i1), X -> sub X, (zext i1)
1462 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1463 N0.getOperand(0).getValueType() == MVT::i1 &&
1464 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1465 DebugLoc DL = N->getDebugLoc();
1466 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1467 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1470 // add (adde 0, 0, glue), X -> adde X, 0, glue
1471 if (N0->hasOneUse() && isCarryMaterialization(N0))
1472 return DAG.getNode(ISD::ADDE, N->getDebugLoc(),
1473 DAG.getVTList(VT, MVT::Glue), N1, N0.getOperand(0),
1476 // add X, (adde 0, 0, glue) -> adde X, 0, glue
1477 if (N1->hasOneUse() && isCarryMaterialization(N1))
1478 return DAG.getNode(ISD::ADDE, N->getDebugLoc(),
1479 DAG.getVTList(VT, MVT::Glue), N0, N1.getOperand(0),
1485 SDValue DAGCombiner::visitADDC(SDNode *N) {
1486 SDValue N0 = N->getOperand(0);
1487 SDValue N1 = N->getOperand(1);
1488 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1489 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1490 EVT VT = N0.getValueType();
1492 // If the flag result is dead, turn this into an ADD.
1493 if (N->hasNUsesOfValue(0, 1))
1494 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1495 DAG.getNode(ISD::CARRY_FALSE,
1496 N->getDebugLoc(), MVT::Glue));
1498 // canonicalize constant to RHS.
1500 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1502 // fold (addc x, 0) -> x + no carry out
1503 if (N1C && N1C->isNullValue())
1504 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1505 N->getDebugLoc(), MVT::Glue));
1507 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1508 APInt LHSZero, LHSOne;
1509 APInt RHSZero, RHSOne;
1510 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1511 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1513 if (LHSZero.getBoolValue()) {
1514 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1516 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1517 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1518 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1519 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1520 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1521 DAG.getNode(ISD::CARRY_FALSE,
1522 N->getDebugLoc(), MVT::Glue));
1525 // addc (adde 0, 0, glue), X -> adde X, 0, glue
1526 if (N0->hasOneUse() && isCarryMaterialization(N0))
1527 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N1,
1528 DAG.getConstant(0, VT), N0.getOperand(2));
1530 // addc X, (adde 0, 0, glue) -> adde X, 0, glue
1531 if (N1->hasOneUse() && isCarryMaterialization(N1))
1532 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N0,
1533 DAG.getConstant(0, VT), N1.getOperand(2));
1538 SDValue DAGCombiner::visitADDE(SDNode *N) {
1539 SDValue N0 = N->getOperand(0);
1540 SDValue N1 = N->getOperand(1);
1541 SDValue CarryIn = N->getOperand(2);
1542 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1543 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1545 // If both operands are null we know that carry out will always be false.
1546 if (N0C && N0C->isNullValue() && N0 == N1)
1547 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), DAG.getNode(ISD::CARRY_FALSE,
1551 // canonicalize constant to RHS
1553 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1556 // fold (adde x, y, false) -> (addc x, y)
1557 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1558 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1563 // Since it may not be valid to emit a fold to zero for vector initializers
1564 // check if we can before folding.
1565 static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT,
1566 SelectionDAG &DAG, bool LegalOperations) {
1567 if (!VT.isVector()) {
1568 return DAG.getConstant(0, VT);
1569 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1570 // Produce a vector of zeros.
1571 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
1572 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
1573 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
1574 &Ops[0], Ops.size());
1579 SDValue DAGCombiner::visitSUB(SDNode *N) {
1580 SDValue N0 = N->getOperand(0);
1581 SDValue N1 = N->getOperand(1);
1582 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1583 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1584 EVT VT = N0.getValueType();
1587 if (VT.isVector()) {
1588 SDValue FoldedVOp = SimplifyVBinOp(N);
1589 if (FoldedVOp.getNode()) return FoldedVOp;
1592 // fold (sub x, x) -> 0
1593 // FIXME: Refactor this and xor and other similar operations together.
1595 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
1596 // fold (sub c1, c2) -> c1-c2
1598 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1599 // fold (sub x, c) -> (add x, -c)
1601 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1602 DAG.getConstant(-N1C->getAPIntValue(), VT));
1603 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1604 if (N0C && N0C->isAllOnesValue())
1605 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1606 // fold A-(A-B) -> B
1607 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1608 return N1.getOperand(1);
1609 // fold (A+B)-A -> B
1610 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1611 return N0.getOperand(1);
1612 // fold (A+B)-B -> A
1613 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1614 return N0.getOperand(0);
1615 // fold ((A+(B+or-C))-B) -> A+or-C
1616 if (N0.getOpcode() == ISD::ADD &&
1617 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1618 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1619 N0.getOperand(1).getOperand(0) == N1)
1620 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1621 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1622 // fold ((A+(C+B))-B) -> A+C
1623 if (N0.getOpcode() == ISD::ADD &&
1624 N0.getOperand(1).getOpcode() == ISD::ADD &&
1625 N0.getOperand(1).getOperand(1) == N1)
1626 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1627 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1628 // fold ((A-(B-C))-C) -> A-B
1629 if (N0.getOpcode() == ISD::SUB &&
1630 N0.getOperand(1).getOpcode() == ISD::SUB &&
1631 N0.getOperand(1).getOperand(1) == N1)
1632 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1633 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1635 // If either operand of a sub is undef, the result is undef
1636 if (N0.getOpcode() == ISD::UNDEF)
1638 if (N1.getOpcode() == ISD::UNDEF)
1641 // If the relocation model supports it, consider symbol offsets.
1642 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1643 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1644 // fold (sub Sym, c) -> Sym-c
1645 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1646 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1648 (uint64_t)N1C->getSExtValue());
1649 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1650 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1651 if (GA->getGlobal() == GB->getGlobal())
1652 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1659 SDValue DAGCombiner::visitMUL(SDNode *N) {
1660 SDValue N0 = N->getOperand(0);
1661 SDValue N1 = N->getOperand(1);
1662 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1663 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1664 EVT VT = N0.getValueType();
1667 if (VT.isVector()) {
1668 SDValue FoldedVOp = SimplifyVBinOp(N);
1669 if (FoldedVOp.getNode()) return FoldedVOp;
1672 // fold (mul x, undef) -> 0
1673 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1674 return DAG.getConstant(0, VT);
1675 // fold (mul c1, c2) -> c1*c2
1677 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1678 // canonicalize constant to RHS
1680 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1681 // fold (mul x, 0) -> 0
1682 if (N1C && N1C->isNullValue())
1684 // fold (mul x, -1) -> 0-x
1685 if (N1C && N1C->isAllOnesValue())
1686 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1687 DAG.getConstant(0, VT), N0);
1688 // fold (mul x, (1 << c)) -> x << c
1689 if (N1C && N1C->getAPIntValue().isPowerOf2())
1690 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1691 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1692 getShiftAmountTy(N0.getValueType())));
1693 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1694 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1695 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1696 // FIXME: If the input is something that is easily negated (e.g. a
1697 // single-use add), we should put the negate there.
1698 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1699 DAG.getConstant(0, VT),
1700 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1701 DAG.getConstant(Log2Val,
1702 getShiftAmountTy(N0.getValueType()))));
1704 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1705 if (N1C && N0.getOpcode() == ISD::SHL &&
1706 isa<ConstantSDNode>(N0.getOperand(1))) {
1707 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1708 N1, N0.getOperand(1));
1709 AddToWorkList(C3.getNode());
1710 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1711 N0.getOperand(0), C3);
1714 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1717 SDValue Sh(0,0), Y(0,0);
1718 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1719 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1720 N0.getNode()->hasOneUse()) {
1722 } else if (N1.getOpcode() == ISD::SHL &&
1723 isa<ConstantSDNode>(N1.getOperand(1)) &&
1724 N1.getNode()->hasOneUse()) {
1729 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1730 Sh.getOperand(0), Y);
1731 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1732 Mul, Sh.getOperand(1));
1736 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1737 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1738 isa<ConstantSDNode>(N0.getOperand(1)))
1739 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1740 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1741 N0.getOperand(0), N1),
1742 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1743 N0.getOperand(1), N1));
1746 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1747 if (RMUL.getNode() != 0)
1753 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1754 SDValue N0 = N->getOperand(0);
1755 SDValue N1 = N->getOperand(1);
1756 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1757 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1758 EVT VT = N->getValueType(0);
1761 if (VT.isVector()) {
1762 SDValue FoldedVOp = SimplifyVBinOp(N);
1763 if (FoldedVOp.getNode()) return FoldedVOp;
1766 // fold (sdiv c1, c2) -> c1/c2
1767 if (N0C && N1C && !N1C->isNullValue())
1768 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1769 // fold (sdiv X, 1) -> X
1770 if (N1C && N1C->getSExtValue() == 1LL)
1772 // fold (sdiv X, -1) -> 0-X
1773 if (N1C && N1C->isAllOnesValue())
1774 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1775 DAG.getConstant(0, VT), N0);
1776 // If we know the sign bits of both operands are zero, strength reduce to a
1777 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1778 if (!VT.isVector()) {
1779 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1780 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1783 // fold (sdiv X, pow2) -> simple ops after legalize
1784 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1785 (isPowerOf2_64(N1C->getSExtValue()) ||
1786 isPowerOf2_64(-N1C->getSExtValue()))) {
1787 // If dividing by powers of two is cheap, then don't perform the following
1789 if (TLI.isPow2DivCheap())
1792 int64_t pow2 = N1C->getSExtValue();
1793 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1794 unsigned lg2 = Log2_64(abs2);
1796 // Splat the sign bit into the register
1797 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1798 DAG.getConstant(VT.getSizeInBits()-1,
1799 getShiftAmountTy(N0.getValueType())));
1800 AddToWorkList(SGN.getNode());
1802 // Add (N0 < 0) ? abs2 - 1 : 0;
1803 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1804 DAG.getConstant(VT.getSizeInBits() - lg2,
1805 getShiftAmountTy(SGN.getValueType())));
1806 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1807 AddToWorkList(SRL.getNode());
1808 AddToWorkList(ADD.getNode()); // Divide by pow2
1809 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1810 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1812 // If we're dividing by a positive value, we're done. Otherwise, we must
1813 // negate the result.
1817 AddToWorkList(SRA.getNode());
1818 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1819 DAG.getConstant(0, VT), SRA);
1822 // if integer divide is expensive and we satisfy the requirements, emit an
1823 // alternate sequence.
1824 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1825 !TLI.isIntDivCheap()) {
1826 SDValue Op = BuildSDIV(N);
1827 if (Op.getNode()) return Op;
1831 if (N0.getOpcode() == ISD::UNDEF)
1832 return DAG.getConstant(0, VT);
1833 // X / undef -> undef
1834 if (N1.getOpcode() == ISD::UNDEF)
1840 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1841 SDValue N0 = N->getOperand(0);
1842 SDValue N1 = N->getOperand(1);
1843 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1844 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1845 EVT VT = N->getValueType(0);
1848 if (VT.isVector()) {
1849 SDValue FoldedVOp = SimplifyVBinOp(N);
1850 if (FoldedVOp.getNode()) return FoldedVOp;
1853 // fold (udiv c1, c2) -> c1/c2
1854 if (N0C && N1C && !N1C->isNullValue())
1855 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1856 // fold (udiv x, (1 << c)) -> x >>u c
1857 if (N1C && N1C->getAPIntValue().isPowerOf2())
1858 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1859 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1860 getShiftAmountTy(N0.getValueType())));
1861 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1862 if (N1.getOpcode() == ISD::SHL) {
1863 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1864 if (SHC->getAPIntValue().isPowerOf2()) {
1865 EVT ADDVT = N1.getOperand(1).getValueType();
1866 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1868 DAG.getConstant(SHC->getAPIntValue()
1871 AddToWorkList(Add.getNode());
1872 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1876 // fold (udiv x, c) -> alternate
1877 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1878 SDValue Op = BuildUDIV(N);
1879 if (Op.getNode()) return Op;
1883 if (N0.getOpcode() == ISD::UNDEF)
1884 return DAG.getConstant(0, VT);
1885 // X / undef -> undef
1886 if (N1.getOpcode() == ISD::UNDEF)
1892 SDValue DAGCombiner::visitSREM(SDNode *N) {
1893 SDValue N0 = N->getOperand(0);
1894 SDValue N1 = N->getOperand(1);
1895 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1896 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1897 EVT VT = N->getValueType(0);
1899 // fold (srem c1, c2) -> c1%c2
1900 if (N0C && N1C && !N1C->isNullValue())
1901 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1902 // If we know the sign bits of both operands are zero, strength reduce to a
1903 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1904 if (!VT.isVector()) {
1905 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1906 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1909 // If X/C can be simplified by the division-by-constant logic, lower
1910 // X%C to the equivalent of X-X/C*C.
1911 if (N1C && !N1C->isNullValue()) {
1912 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1913 AddToWorkList(Div.getNode());
1914 SDValue OptimizedDiv = combine(Div.getNode());
1915 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1916 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1918 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1919 AddToWorkList(Mul.getNode());
1925 if (N0.getOpcode() == ISD::UNDEF)
1926 return DAG.getConstant(0, VT);
1927 // X % undef -> undef
1928 if (N1.getOpcode() == ISD::UNDEF)
1934 SDValue DAGCombiner::visitUREM(SDNode *N) {
1935 SDValue N0 = N->getOperand(0);
1936 SDValue N1 = N->getOperand(1);
1937 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1938 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1939 EVT VT = N->getValueType(0);
1941 // fold (urem c1, c2) -> c1%c2
1942 if (N0C && N1C && !N1C->isNullValue())
1943 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1944 // fold (urem x, pow2) -> (and x, pow2-1)
1945 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1946 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1947 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1948 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1949 if (N1.getOpcode() == ISD::SHL) {
1950 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1951 if (SHC->getAPIntValue().isPowerOf2()) {
1953 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1954 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1956 AddToWorkList(Add.getNode());
1957 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1962 // If X/C can be simplified by the division-by-constant logic, lower
1963 // X%C to the equivalent of X-X/C*C.
1964 if (N1C && !N1C->isNullValue()) {
1965 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1966 AddToWorkList(Div.getNode());
1967 SDValue OptimizedDiv = combine(Div.getNode());
1968 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1969 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1971 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1972 AddToWorkList(Mul.getNode());
1978 if (N0.getOpcode() == ISD::UNDEF)
1979 return DAG.getConstant(0, VT);
1980 // X % undef -> undef
1981 if (N1.getOpcode() == ISD::UNDEF)
1987 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1988 SDValue N0 = N->getOperand(0);
1989 SDValue N1 = N->getOperand(1);
1990 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1991 EVT VT = N->getValueType(0);
1992 DebugLoc DL = N->getDebugLoc();
1994 // fold (mulhs x, 0) -> 0
1995 if (N1C && N1C->isNullValue())
1997 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1998 if (N1C && N1C->getAPIntValue() == 1)
1999 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
2000 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2001 getShiftAmountTy(N0.getValueType())));
2002 // fold (mulhs x, undef) -> 0
2003 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2004 return DAG.getConstant(0, VT);
2006 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2008 if (VT.isSimple() && !VT.isVector()) {
2009 MVT Simple = VT.getSimpleVT();
2010 unsigned SimpleSize = Simple.getSizeInBits();
2011 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2012 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2013 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2014 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2015 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2016 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2017 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2018 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2025 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2026 SDValue N0 = N->getOperand(0);
2027 SDValue N1 = N->getOperand(1);
2028 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2029 EVT VT = N->getValueType(0);
2030 DebugLoc DL = N->getDebugLoc();
2032 // fold (mulhu x, 0) -> 0
2033 if (N1C && N1C->isNullValue())
2035 // fold (mulhu x, 1) -> 0
2036 if (N1C && N1C->getAPIntValue() == 1)
2037 return DAG.getConstant(0, N0.getValueType());
2038 // fold (mulhu x, undef) -> 0
2039 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2040 return DAG.getConstant(0, VT);
2042 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2044 if (VT.isSimple() && !VT.isVector()) {
2045 MVT Simple = VT.getSimpleVT();
2046 unsigned SimpleSize = Simple.getSizeInBits();
2047 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2048 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2049 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2050 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2051 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2052 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2053 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2054 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2061 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2062 /// compute two values. LoOp and HiOp give the opcodes for the two computations
2063 /// that are being performed. Return true if a simplification was made.
2065 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2067 // If the high half is not needed, just compute the low half.
2068 bool HiExists = N->hasAnyUseOfValue(1);
2070 (!LegalOperations ||
2071 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2072 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2073 N->op_begin(), N->getNumOperands());
2074 return CombineTo(N, Res, Res);
2077 // If the low half is not needed, just compute the high half.
2078 bool LoExists = N->hasAnyUseOfValue(0);
2080 (!LegalOperations ||
2081 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2082 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2083 N->op_begin(), N->getNumOperands());
2084 return CombineTo(N, Res, Res);
2087 // If both halves are used, return as it is.
2088 if (LoExists && HiExists)
2091 // If the two computed results can be simplified separately, separate them.
2093 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2094 N->op_begin(), N->getNumOperands());
2095 AddToWorkList(Lo.getNode());
2096 SDValue LoOpt = combine(Lo.getNode());
2097 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2098 (!LegalOperations ||
2099 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2100 return CombineTo(N, LoOpt, LoOpt);
2104 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2105 N->op_begin(), N->getNumOperands());
2106 AddToWorkList(Hi.getNode());
2107 SDValue HiOpt = combine(Hi.getNode());
2108 if (HiOpt.getNode() && HiOpt != Hi &&
2109 (!LegalOperations ||
2110 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2111 return CombineTo(N, HiOpt, HiOpt);
2117 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2118 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2119 if (Res.getNode()) return Res;
2121 EVT VT = N->getValueType(0);
2122 DebugLoc DL = N->getDebugLoc();
2124 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2126 if (VT.isSimple() && !VT.isVector()) {
2127 MVT Simple = VT.getSimpleVT();
2128 unsigned SimpleSize = Simple.getSizeInBits();
2129 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2130 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2131 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2132 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2133 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2134 // Compute the high part as N1.
2135 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2136 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2137 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2138 // Compute the low part as N0.
2139 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2140 return CombineTo(N, Lo, Hi);
2147 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2148 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2149 if (Res.getNode()) return Res;
2151 EVT VT = N->getValueType(0);
2152 DebugLoc DL = N->getDebugLoc();
2154 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2156 if (VT.isSimple() && !VT.isVector()) {
2157 MVT Simple = VT.getSimpleVT();
2158 unsigned SimpleSize = Simple.getSizeInBits();
2159 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2160 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2161 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2162 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2163 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2164 // Compute the high part as N1.
2165 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2166 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2167 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2168 // Compute the low part as N0.
2169 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2170 return CombineTo(N, Lo, Hi);
2177 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2178 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2179 if (Res.getNode()) return Res;
2184 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2185 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2186 if (Res.getNode()) return Res;
2191 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2192 /// two operands of the same opcode, try to simplify it.
2193 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2194 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2195 EVT VT = N0.getValueType();
2196 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2198 // Bail early if none of these transforms apply.
2199 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2201 // For each of OP in AND/OR/XOR:
2202 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2203 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2204 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2205 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2207 // do not sink logical op inside of a vector extend, since it may combine
2209 EVT Op0VT = N0.getOperand(0).getValueType();
2210 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2211 N0.getOpcode() == ISD::SIGN_EXTEND ||
2212 // Avoid infinite looping with PromoteIntBinOp.
2213 (N0.getOpcode() == ISD::ANY_EXTEND &&
2214 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2215 (N0.getOpcode() == ISD::TRUNCATE &&
2216 (!TLI.isZExtFree(VT, Op0VT) ||
2217 !TLI.isTruncateFree(Op0VT, VT)) &&
2218 TLI.isTypeLegal(Op0VT))) &&
2220 Op0VT == N1.getOperand(0).getValueType() &&
2221 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2222 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2223 N0.getOperand(0).getValueType(),
2224 N0.getOperand(0), N1.getOperand(0));
2225 AddToWorkList(ORNode.getNode());
2226 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2229 // For each of OP in SHL/SRL/SRA/AND...
2230 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2231 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2232 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2233 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2234 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2235 N0.getOperand(1) == N1.getOperand(1)) {
2236 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2237 N0.getOperand(0).getValueType(),
2238 N0.getOperand(0), N1.getOperand(0));
2239 AddToWorkList(ORNode.getNode());
2240 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2241 ORNode, N0.getOperand(1));
2247 SDValue DAGCombiner::visitAND(SDNode *N) {
2248 SDValue N0 = N->getOperand(0);
2249 SDValue N1 = N->getOperand(1);
2250 SDValue LL, LR, RL, RR, CC0, CC1;
2251 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2252 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2253 EVT VT = N1.getValueType();
2254 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2257 if (VT.isVector()) {
2258 SDValue FoldedVOp = SimplifyVBinOp(N);
2259 if (FoldedVOp.getNode()) return FoldedVOp;
2262 // fold (and x, undef) -> 0
2263 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2264 return DAG.getConstant(0, VT);
2265 // fold (and c1, c2) -> c1&c2
2267 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2268 // canonicalize constant to RHS
2270 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2271 // fold (and x, -1) -> x
2272 if (N1C && N1C->isAllOnesValue())
2274 // if (and x, c) is known to be zero, return 0
2275 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2276 APInt::getAllOnesValue(BitWidth)))
2277 return DAG.getConstant(0, VT);
2279 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2280 if (RAND.getNode() != 0)
2282 // fold (and (or x, C), D) -> D if (C & D) == D
2283 if (N1C && N0.getOpcode() == ISD::OR)
2284 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2285 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2287 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2288 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2289 SDValue N0Op0 = N0.getOperand(0);
2290 APInt Mask = ~N1C->getAPIntValue();
2291 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2292 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2293 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2294 N0.getValueType(), N0Op0);
2296 // Replace uses of the AND with uses of the Zero extend node.
2299 // We actually want to replace all uses of the any_extend with the
2300 // zero_extend, to avoid duplicating things. This will later cause this
2301 // AND to be folded.
2302 CombineTo(N0.getNode(), Zext);
2303 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2306 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2307 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2308 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2309 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2311 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2312 LL.getValueType().isInteger()) {
2313 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2314 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2315 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2316 LR.getValueType(), LL, RL);
2317 AddToWorkList(ORNode.getNode());
2318 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2320 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2321 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2322 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2323 LR.getValueType(), LL, RL);
2324 AddToWorkList(ANDNode.getNode());
2325 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2327 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2328 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2329 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2330 LR.getValueType(), LL, RL);
2331 AddToWorkList(ORNode.getNode());
2332 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2335 // canonicalize equivalent to ll == rl
2336 if (LL == RR && LR == RL) {
2337 Op1 = ISD::getSetCCSwappedOperands(Op1);
2340 if (LL == RL && LR == RR) {
2341 bool isInteger = LL.getValueType().isInteger();
2342 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2343 if (Result != ISD::SETCC_INVALID &&
2344 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2345 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2350 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2351 if (N0.getOpcode() == N1.getOpcode()) {
2352 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2353 if (Tmp.getNode()) return Tmp;
2356 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2357 // fold (and (sra)) -> (and (srl)) when possible.
2358 if (!VT.isVector() &&
2359 SimplifyDemandedBits(SDValue(N, 0)))
2360 return SDValue(N, 0);
2362 // fold (zext_inreg (extload x)) -> (zextload x)
2363 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2364 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2365 EVT MemVT = LN0->getMemoryVT();
2366 // If we zero all the possible extended bits, then we can turn this into
2367 // a zextload if we are running before legalize or the operation is legal.
2368 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2369 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2370 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2371 ((!LegalOperations && !LN0->isVolatile()) ||
2372 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2373 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2374 LN0->getChain(), LN0->getBasePtr(),
2375 LN0->getPointerInfo(), MemVT,
2376 LN0->isVolatile(), LN0->isNonTemporal(),
2377 LN0->getAlignment());
2379 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2380 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2383 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2384 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2386 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2387 EVT MemVT = LN0->getMemoryVT();
2388 // If we zero all the possible extended bits, then we can turn this into
2389 // a zextload if we are running before legalize or the operation is legal.
2390 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2391 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2392 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2393 ((!LegalOperations && !LN0->isVolatile()) ||
2394 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2395 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2397 LN0->getBasePtr(), LN0->getPointerInfo(),
2399 LN0->isVolatile(), LN0->isNonTemporal(),
2400 LN0->getAlignment());
2402 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2403 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2407 // fold (and (load x), 255) -> (zextload x, i8)
2408 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2409 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2410 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2411 (N0.getOpcode() == ISD::ANY_EXTEND &&
2412 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2413 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2414 LoadSDNode *LN0 = HasAnyExt
2415 ? cast<LoadSDNode>(N0.getOperand(0))
2416 : cast<LoadSDNode>(N0);
2417 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2418 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2419 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2420 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2421 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2422 EVT LoadedVT = LN0->getMemoryVT();
2424 if (ExtVT == LoadedVT &&
2425 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2426 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2429 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2430 LN0->getChain(), LN0->getBasePtr(),
2431 LN0->getPointerInfo(),
2432 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2433 LN0->getAlignment());
2435 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2436 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2439 // Do not change the width of a volatile load.
2440 // Do not generate loads of non-round integer types since these can
2441 // be expensive (and would be wrong if the type is not byte sized).
2442 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2443 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2444 EVT PtrType = LN0->getOperand(1).getValueType();
2446 unsigned Alignment = LN0->getAlignment();
2447 SDValue NewPtr = LN0->getBasePtr();
2449 // For big endian targets, we need to add an offset to the pointer
2450 // to load the correct bytes. For little endian systems, we merely
2451 // need to read fewer bytes from the same pointer.
2452 if (TLI.isBigEndian()) {
2453 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2454 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2455 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2456 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2457 NewPtr, DAG.getConstant(PtrOff, PtrType));
2458 Alignment = MinAlign(Alignment, PtrOff);
2461 AddToWorkList(NewPtr.getNode());
2463 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2465 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2466 LN0->getChain(), NewPtr,
2467 LN0->getPointerInfo(),
2468 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2471 CombineTo(LN0, Load, Load.getValue(1));
2472 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2481 SDValue DAGCombiner::visitOR(SDNode *N) {
2482 SDValue N0 = N->getOperand(0);
2483 SDValue N1 = N->getOperand(1);
2484 SDValue LL, LR, RL, RR, CC0, CC1;
2485 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2486 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2487 EVT VT = N1.getValueType();
2490 if (VT.isVector()) {
2491 SDValue FoldedVOp = SimplifyVBinOp(N);
2492 if (FoldedVOp.getNode()) return FoldedVOp;
2495 // fold (or x, undef) -> -1
2496 if (!LegalOperations &&
2497 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
2498 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
2499 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
2501 // fold (or c1, c2) -> c1|c2
2503 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
2504 // canonicalize constant to RHS
2506 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2507 // fold (or x, 0) -> x
2508 if (N1C && N1C->isNullValue())
2510 // fold (or x, -1) -> -1
2511 if (N1C && N1C->isAllOnesValue())
2513 // fold (or x, c) -> c iff (x & ~c) == 0
2514 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2517 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2518 if (ROR.getNode() != 0)
2520 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2521 // iff (c1 & c2) == 0.
2522 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2523 isa<ConstantSDNode>(N0.getOperand(1))) {
2524 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2525 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
2526 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2527 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2528 N0.getOperand(0), N1),
2529 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2531 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2532 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2533 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2534 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2536 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2537 LL.getValueType().isInteger()) {
2538 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2539 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2540 if (cast<ConstantSDNode>(LR)->isNullValue() &&
2541 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2542 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2543 LR.getValueType(), LL, RL);
2544 AddToWorkList(ORNode.getNode());
2545 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2547 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2548 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
2549 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2550 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2551 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2552 LR.getValueType(), LL, RL);
2553 AddToWorkList(ANDNode.getNode());
2554 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2557 // canonicalize equivalent to ll == rl
2558 if (LL == RR && LR == RL) {
2559 Op1 = ISD::getSetCCSwappedOperands(Op1);
2562 if (LL == RL && LR == RR) {
2563 bool isInteger = LL.getValueType().isInteger();
2564 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2565 if (Result != ISD::SETCC_INVALID &&
2566 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2567 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2572 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2573 if (N0.getOpcode() == N1.getOpcode()) {
2574 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2575 if (Tmp.getNode()) return Tmp;
2578 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2579 if (N0.getOpcode() == ISD::AND &&
2580 N1.getOpcode() == ISD::AND &&
2581 N0.getOperand(1).getOpcode() == ISD::Constant &&
2582 N1.getOperand(1).getOpcode() == ISD::Constant &&
2583 // Don't increase # computations.
2584 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2585 // We can only do this xform if we know that bits from X that are set in C2
2586 // but not in C1 are already zero. Likewise for Y.
2587 const APInt &LHSMask =
2588 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2589 const APInt &RHSMask =
2590 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2592 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2593 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2594 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2595 N0.getOperand(0), N1.getOperand(0));
2596 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2597 DAG.getConstant(LHSMask | RHSMask, VT));
2601 // See if this is some rotate idiom.
2602 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2603 return SDValue(Rot, 0);
2605 // Simplify the operands using demanded-bits information.
2606 if (!VT.isVector() &&
2607 SimplifyDemandedBits(SDValue(N, 0)))
2608 return SDValue(N, 0);
2613 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2614 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2615 if (Op.getOpcode() == ISD::AND) {
2616 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2617 Mask = Op.getOperand(1);
2618 Op = Op.getOperand(0);
2624 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2632 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2633 // idioms for rotate, and if the target supports rotation instructions, generate
2635 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2636 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2637 EVT VT = LHS.getValueType();
2638 if (!TLI.isTypeLegal(VT)) return 0;
2640 // The target must have at least one rotate flavor.
2641 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2642 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2643 if (!HasROTL && !HasROTR) return 0;
2645 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2646 SDValue LHSShift; // The shift.
2647 SDValue LHSMask; // AND value if any.
2648 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2649 return 0; // Not part of a rotate.
2651 SDValue RHSShift; // The shift.
2652 SDValue RHSMask; // AND value if any.
2653 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2654 return 0; // Not part of a rotate.
2656 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2657 return 0; // Not shifting the same value.
2659 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2660 return 0; // Shifts must disagree.
2662 // Canonicalize shl to left side in a shl/srl pair.
2663 if (RHSShift.getOpcode() == ISD::SHL) {
2664 std::swap(LHS, RHS);
2665 std::swap(LHSShift, RHSShift);
2666 std::swap(LHSMask , RHSMask );
2669 unsigned OpSizeInBits = VT.getSizeInBits();
2670 SDValue LHSShiftArg = LHSShift.getOperand(0);
2671 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2672 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2674 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2675 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2676 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2677 RHSShiftAmt.getOpcode() == ISD::Constant) {
2678 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2679 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2680 if ((LShVal + RShVal) != OpSizeInBits)
2685 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2687 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2689 // If there is an AND of either shifted operand, apply it to the result.
2690 if (LHSMask.getNode() || RHSMask.getNode()) {
2691 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2693 if (LHSMask.getNode()) {
2694 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2695 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2697 if (RHSMask.getNode()) {
2698 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2699 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2702 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2705 return Rot.getNode();
2708 // If there is a mask here, and we have a variable shift, we can't be sure
2709 // that we're masking out the right stuff.
2710 if (LHSMask.getNode() || RHSMask.getNode())
2713 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2714 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2715 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2716 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2717 if (ConstantSDNode *SUBC =
2718 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2719 if (SUBC->getAPIntValue() == OpSizeInBits) {
2721 return DAG.getNode(ISD::ROTL, DL, VT,
2722 LHSShiftArg, LHSShiftAmt).getNode();
2724 return DAG.getNode(ISD::ROTR, DL, VT,
2725 LHSShiftArg, RHSShiftAmt).getNode();
2730 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2731 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2732 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2733 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2734 if (ConstantSDNode *SUBC =
2735 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2736 if (SUBC->getAPIntValue() == OpSizeInBits) {
2738 return DAG.getNode(ISD::ROTR, DL, VT,
2739 LHSShiftArg, RHSShiftAmt).getNode();
2741 return DAG.getNode(ISD::ROTL, DL, VT,
2742 LHSShiftArg, LHSShiftAmt).getNode();
2747 // Look for sign/zext/any-extended or truncate cases:
2748 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2749 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2750 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2751 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
2752 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2753 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2754 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2755 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
2756 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
2757 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
2758 if (RExtOp0.getOpcode() == ISD::SUB &&
2759 RExtOp0.getOperand(1) == LExtOp0) {
2760 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2762 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2763 // (rotr x, (sub 32, y))
2764 if (ConstantSDNode *SUBC =
2765 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2766 if (SUBC->getAPIntValue() == OpSizeInBits) {
2767 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
2769 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
2772 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2773 RExtOp0 == LExtOp0.getOperand(1)) {
2774 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2776 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2777 // (rotl x, (sub 32, y))
2778 if (ConstantSDNode *SUBC =
2779 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2780 if (SUBC->getAPIntValue() == OpSizeInBits) {
2781 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
2783 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
2792 SDValue DAGCombiner::visitXOR(SDNode *N) {
2793 SDValue N0 = N->getOperand(0);
2794 SDValue N1 = N->getOperand(1);
2795 SDValue LHS, RHS, CC;
2796 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2797 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2798 EVT VT = N0.getValueType();
2801 if (VT.isVector()) {
2802 SDValue FoldedVOp = SimplifyVBinOp(N);
2803 if (FoldedVOp.getNode()) return FoldedVOp;
2806 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
2807 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
2808 return DAG.getConstant(0, VT);
2809 // fold (xor x, undef) -> undef
2810 if (N0.getOpcode() == ISD::UNDEF)
2812 if (N1.getOpcode() == ISD::UNDEF)
2814 // fold (xor c1, c2) -> c1^c2
2816 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
2817 // canonicalize constant to RHS
2819 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
2820 // fold (xor x, 0) -> x
2821 if (N1C && N1C->isNullValue())
2824 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
2825 if (RXOR.getNode() != 0)
2828 // fold !(x cc y) -> (x !cc y)
2829 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2830 bool isInt = LHS.getValueType().isInteger();
2831 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2834 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
2835 switch (N0.getOpcode()) {
2837 llvm_unreachable("Unhandled SetCC Equivalent!");
2839 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
2840 case ISD::SELECT_CC:
2841 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
2842 N0.getOperand(3), NotCC);
2847 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2848 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2849 N0.getNode()->hasOneUse() &&
2850 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2851 SDValue V = N0.getOperand(0);
2852 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
2853 DAG.getConstant(1, V.getValueType()));
2854 AddToWorkList(V.getNode());
2855 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
2858 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
2859 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2860 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2861 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2862 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2863 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2864 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2865 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2866 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2867 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2870 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
2871 if (N1C && N1C->isAllOnesValue() &&
2872 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2873 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2874 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2875 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2876 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2877 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2878 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2879 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2882 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
2883 if (N1C && N0.getOpcode() == ISD::XOR) {
2884 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2885 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2887 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
2888 DAG.getConstant(N1C->getAPIntValue() ^
2889 N00C->getAPIntValue(), VT));
2891 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
2892 DAG.getConstant(N1C->getAPIntValue() ^
2893 N01C->getAPIntValue(), VT));
2895 // fold (xor x, x) -> 0
2897 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
2899 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2900 if (N0.getOpcode() == N1.getOpcode()) {
2901 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2902 if (Tmp.getNode()) return Tmp;
2905 // Simplify the expression using non-local knowledge.
2906 if (!VT.isVector() &&
2907 SimplifyDemandedBits(SDValue(N, 0)))
2908 return SDValue(N, 0);
2913 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2914 /// the shift amount is a constant.
2915 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2916 SDNode *LHS = N->getOperand(0).getNode();
2917 if (!LHS->hasOneUse()) return SDValue();
2919 // We want to pull some binops through shifts, so that we have (and (shift))
2920 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2921 // thing happens with address calculations, so it's important to canonicalize
2923 bool HighBitSet = false; // Can we transform this if the high bit is set?
2925 switch (LHS->getOpcode()) {
2926 default: return SDValue();
2929 HighBitSet = false; // We can only transform sra if the high bit is clear.
2932 HighBitSet = true; // We can only transform sra if the high bit is set.
2935 if (N->getOpcode() != ISD::SHL)
2936 return SDValue(); // only shl(add) not sr[al](add).
2937 HighBitSet = false; // We can only transform sra if the high bit is clear.
2941 // We require the RHS of the binop to be a constant as well.
2942 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2943 if (!BinOpCst) return SDValue();
2945 // FIXME: disable this unless the input to the binop is a shift by a constant.
2946 // If it is not a shift, it pessimizes some common cases like:
2948 // void foo(int *X, int i) { X[i & 1235] = 1; }
2949 // int bar(int *X, int i) { return X[i & 255]; }
2950 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
2951 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2952 BinOpLHSVal->getOpcode() != ISD::SRA &&
2953 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2954 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2957 EVT VT = N->getValueType(0);
2959 // If this is a signed shift right, and the high bit is modified by the
2960 // logical operation, do not perform the transformation. The highBitSet
2961 // boolean indicates the value of the high bit of the constant which would
2962 // cause it to be modified for this operation.
2963 if (N->getOpcode() == ISD::SRA) {
2964 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
2965 if (BinOpRHSSignSet != HighBitSet)
2969 // Fold the constants, shifting the binop RHS by the shift amount.
2970 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
2972 LHS->getOperand(1), N->getOperand(1));
2974 // Create the new shift.
2975 SDValue NewShift = DAG.getNode(N->getOpcode(),
2976 LHS->getOperand(0).getDebugLoc(),
2977 VT, LHS->getOperand(0), N->getOperand(1));
2979 // Create the new binop.
2980 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
2983 SDValue DAGCombiner::visitSHL(SDNode *N) {
2984 SDValue N0 = N->getOperand(0);
2985 SDValue N1 = N->getOperand(1);
2986 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2987 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2988 EVT VT = N0.getValueType();
2989 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
2991 // fold (shl c1, c2) -> c1<<c2
2993 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
2994 // fold (shl 0, x) -> 0
2995 if (N0C && N0C->isNullValue())
2997 // fold (shl x, c >= size(x)) -> undef
2998 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2999 return DAG.getUNDEF(VT);
3000 // fold (shl x, 0) -> x
3001 if (N1C && N1C->isNullValue())
3003 // if (shl x, c) is known to be zero, return 0
3004 if (DAG.MaskedValueIsZero(SDValue(N, 0),
3005 APInt::getAllOnesValue(OpSizeInBits)))
3006 return DAG.getConstant(0, VT);
3007 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
3008 if (N1.getOpcode() == ISD::TRUNCATE &&
3009 N1.getOperand(0).getOpcode() == ISD::AND &&
3010 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3011 SDValue N101 = N1.getOperand(0).getOperand(1);
3012 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3013 EVT TruncVT = N1.getValueType();
3014 SDValue N100 = N1.getOperand(0).getOperand(0);
3015 APInt TruncC = N101C->getAPIntValue();
3016 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3017 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
3018 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
3019 DAG.getNode(ISD::TRUNCATE,
3022 DAG.getConstant(TruncC, TruncVT)));
3026 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3027 return SDValue(N, 0);
3029 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
3030 if (N1C && N0.getOpcode() == ISD::SHL &&
3031 N0.getOperand(1).getOpcode() == ISD::Constant) {
3032 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3033 uint64_t c2 = N1C->getZExtValue();
3034 if (c1 + c2 >= OpSizeInBits)
3035 return DAG.getConstant(0, VT);
3036 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3037 DAG.getConstant(c1 + c2, N1.getValueType()));
3040 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
3041 // For this to be valid, the second form must not preserve any of the bits
3042 // that are shifted out by the inner shift in the first form. This means
3043 // the outer shift size must be >= the number of bits added by the ext.
3044 // As a corollary, we don't care what kind of ext it is.
3045 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3046 N0.getOpcode() == ISD::ANY_EXTEND ||
3047 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3048 N0.getOperand(0).getOpcode() == ISD::SHL &&
3049 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3051 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3052 uint64_t c2 = N1C->getZExtValue();
3053 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3054 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3055 if (c2 >= OpSizeInBits - InnerShiftSize) {
3056 if (c1 + c2 >= OpSizeInBits)
3057 return DAG.getConstant(0, VT);
3058 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
3059 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT,
3060 N0.getOperand(0)->getOperand(0)),
3061 DAG.getConstant(c1 + c2, N1.getValueType()));
3065 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
3066 // (srl (and x, (shl -1, c1)), (sub c1, c2))
3067 if (N1C && N0.getOpcode() == ISD::SRL &&
3068 N0.getOperand(1).getOpcode() == ISD::Constant) {
3069 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3070 if (c1 < VT.getSizeInBits()) {
3071 uint64_t c2 = N1C->getZExtValue();
3072 SDValue HiBitsMask =
3073 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3074 VT.getSizeInBits() - c1),
3076 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT,
3080 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask,
3081 DAG.getConstant(c2-c1, N1.getValueType()));
3083 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask,
3084 DAG.getConstant(c1-c2, N1.getValueType()));
3087 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
3088 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3089 SDValue HiBitsMask =
3090 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3091 VT.getSizeInBits() -
3092 N1C->getZExtValue()),
3094 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3099 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3100 if (NewSHL.getNode())
3107 SDValue DAGCombiner::visitSRA(SDNode *N) {
3108 SDValue N0 = N->getOperand(0);
3109 SDValue N1 = N->getOperand(1);
3110 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3111 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3112 EVT VT = N0.getValueType();
3113 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3115 // fold (sra c1, c2) -> (sra c1, c2)
3117 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3118 // fold (sra 0, x) -> 0
3119 if (N0C && N0C->isNullValue())
3121 // fold (sra -1, x) -> -1
3122 if (N0C && N0C->isAllOnesValue())
3124 // fold (sra x, (setge c, size(x))) -> undef
3125 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3126 return DAG.getUNDEF(VT);
3127 // fold (sra x, 0) -> x
3128 if (N1C && N1C->isNullValue())
3130 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3132 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3133 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3134 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3136 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3137 ExtVT, VT.getVectorNumElements());
3138 if ((!LegalOperations ||
3139 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3140 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3141 N0.getOperand(0), DAG.getValueType(ExtVT));
3144 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3145 if (N1C && N0.getOpcode() == ISD::SRA) {
3146 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3147 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3148 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3149 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3150 DAG.getConstant(Sum, N1C->getValueType(0)));
3154 // fold (sra (shl X, m), (sub result_size, n))
3155 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3156 // result_size - n != m.
3157 // If truncate is free for the target sext(shl) is likely to result in better
3159 if (N0.getOpcode() == ISD::SHL) {
3160 // Get the two constanst of the shifts, CN0 = m, CN = n.
3161 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3163 // Determine what the truncate's result bitsize and type would be.
3165 EVT::getIntegerVT(*DAG.getContext(),
3166 OpSizeInBits - N1C->getZExtValue());
3167 // Determine the residual right-shift amount.
3168 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3170 // If the shift is not a no-op (in which case this should be just a sign
3171 // extend already), the truncated to type is legal, sign_extend is legal
3172 // on that type, and the truncate to that type is both legal and free,
3173 // perform the transform.
3174 if ((ShiftAmt > 0) &&
3175 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3176 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3177 TLI.isTruncateFree(VT, TruncVT)) {
3179 SDValue Amt = DAG.getConstant(ShiftAmt,
3180 getShiftAmountTy(N0.getOperand(0).getValueType()));
3181 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3182 N0.getOperand(0), Amt);
3183 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3185 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3186 N->getValueType(0), Trunc);
3191 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3192 if (N1.getOpcode() == ISD::TRUNCATE &&
3193 N1.getOperand(0).getOpcode() == ISD::AND &&
3194 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3195 SDValue N101 = N1.getOperand(0).getOperand(1);
3196 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3197 EVT TruncVT = N1.getValueType();
3198 SDValue N100 = N1.getOperand(0).getOperand(0);
3199 APInt TruncC = N101C->getAPIntValue();
3200 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3201 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3202 DAG.getNode(ISD::AND, N->getDebugLoc(),
3204 DAG.getNode(ISD::TRUNCATE,
3207 DAG.getConstant(TruncC, TruncVT)));
3211 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2))
3212 // if c1 is equal to the number of bits the trunc removes
3213 if (N0.getOpcode() == ISD::TRUNCATE &&
3214 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3215 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3216 N0.getOperand(0).hasOneUse() &&
3217 N0.getOperand(0).getOperand(1).hasOneUse() &&
3218 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3219 EVT LargeVT = N0.getOperand(0).getValueType();
3220 ConstantSDNode *LargeShiftAmt =
3221 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3223 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits ==
3224 LargeShiftAmt->getZExtValue()) {
3226 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(),
3227 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3228 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT,
3229 N0.getOperand(0).getOperand(0), Amt);
3230 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA);
3234 // Simplify, based on bits shifted out of the LHS.
3235 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3236 return SDValue(N, 0);
3239 // If the sign bit is known to be zero, switch this to a SRL.
3240 if (DAG.SignBitIsZero(N0))
3241 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3244 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3245 if (NewSRA.getNode())
3252 SDValue DAGCombiner::visitSRL(SDNode *N) {
3253 SDValue N0 = N->getOperand(0);
3254 SDValue N1 = N->getOperand(1);
3255 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3256 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3257 EVT VT = N0.getValueType();
3258 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3260 // fold (srl c1, c2) -> c1 >>u c2
3262 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3263 // fold (srl 0, x) -> 0
3264 if (N0C && N0C->isNullValue())
3266 // fold (srl x, c >= size(x)) -> undef
3267 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3268 return DAG.getUNDEF(VT);
3269 // fold (srl x, 0) -> x
3270 if (N1C && N1C->isNullValue())
3272 // if (srl x, c) is known to be zero, return 0
3273 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3274 APInt::getAllOnesValue(OpSizeInBits)))
3275 return DAG.getConstant(0, VT);
3277 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3278 if (N1C && N0.getOpcode() == ISD::SRL &&
3279 N0.getOperand(1).getOpcode() == ISD::Constant) {
3280 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3281 uint64_t c2 = N1C->getZExtValue();
3282 if (c1 + c2 >= OpSizeInBits)
3283 return DAG.getConstant(0, VT);
3284 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3285 DAG.getConstant(c1 + c2, N1.getValueType()));
3288 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3289 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3290 N0.getOperand(0).getOpcode() == ISD::SRL &&
3291 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3293 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3294 uint64_t c2 = N1C->getZExtValue();
3295 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3296 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3297 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3298 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
3299 if (c1 + OpSizeInBits == InnerShiftSize) {
3300 if (c1 + c2 >= InnerShiftSize)
3301 return DAG.getConstant(0, VT);
3302 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
3303 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3304 N0.getOperand(0)->getOperand(0),
3305 DAG.getConstant(c1 + c2, ShiftCountVT)));
3309 // fold (srl (shl x, c), c) -> (and x, cst2)
3310 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3311 N0.getValueSizeInBits() <= 64) {
3312 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3313 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3314 DAG.getConstant(~0ULL >> ShAmt, VT));
3318 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3319 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3320 // Shifting in all undef bits?
3321 EVT SmallVT = N0.getOperand(0).getValueType();
3322 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3323 return DAG.getUNDEF(VT);
3325 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3326 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3327 N0.getOperand(0), N1);
3328 AddToWorkList(SmallShift.getNode());
3329 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3333 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3334 // bit, which is unmodified by sra.
3335 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3336 if (N0.getOpcode() == ISD::SRA)
3337 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3340 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3341 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3342 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3343 APInt KnownZero, KnownOne;
3344 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
3345 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
3347 // If any of the input bits are KnownOne, then the input couldn't be all
3348 // zeros, thus the result of the srl will always be zero.
3349 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3351 // If all of the bits input the to ctlz node are known to be zero, then
3352 // the result of the ctlz is "32" and the result of the shift is one.
3353 APInt UnknownBits = ~KnownZero & Mask;
3354 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3356 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3357 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3358 // Okay, we know that only that the single bit specified by UnknownBits
3359 // could be set on input to the CTLZ node. If this bit is set, the SRL
3360 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3361 // to an SRL/XOR pair, which is likely to simplify more.
3362 unsigned ShAmt = UnknownBits.countTrailingZeros();
3363 SDValue Op = N0.getOperand(0);
3366 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3367 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
3368 AddToWorkList(Op.getNode());
3371 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3372 Op, DAG.getConstant(1, VT));
3376 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3377 if (N1.getOpcode() == ISD::TRUNCATE &&
3378 N1.getOperand(0).getOpcode() == ISD::AND &&
3379 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3380 SDValue N101 = N1.getOperand(0).getOperand(1);
3381 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3382 EVT TruncVT = N1.getValueType();
3383 SDValue N100 = N1.getOperand(0).getOperand(0);
3384 APInt TruncC = N101C->getAPIntValue();
3385 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3386 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3387 DAG.getNode(ISD::AND, N->getDebugLoc(),
3389 DAG.getNode(ISD::TRUNCATE,
3392 DAG.getConstant(TruncC, TruncVT)));
3396 // fold operands of srl based on knowledge that the low bits are not
3398 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3399 return SDValue(N, 0);
3402 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3403 if (NewSRL.getNode())
3407 // Attempt to convert a srl of a load into a narrower zero-extending load.
3408 SDValue NarrowLoad = ReduceLoadWidth(N);
3409 if (NarrowLoad.getNode())
3412 // Here is a common situation. We want to optimize:
3415 // %b = and i32 %a, 2
3416 // %c = srl i32 %b, 1
3417 // brcond i32 %c ...
3423 // %c = setcc eq %b, 0
3426 // However when after the source operand of SRL is optimized into AND, the SRL
3427 // itself may not be optimized further. Look for it and add the BRCOND into
3429 if (N->hasOneUse()) {
3430 SDNode *Use = *N->use_begin();
3431 if (Use->getOpcode() == ISD::BRCOND)
3433 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3434 // Also look pass the truncate.
3435 Use = *Use->use_begin();
3436 if (Use->getOpcode() == ISD::BRCOND)
3444 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
3445 SDValue N0 = N->getOperand(0);
3446 EVT VT = N->getValueType(0);
3448 // fold (ctlz c1) -> c2
3449 if (isa<ConstantSDNode>(N0))
3450 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3454 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
3455 SDValue N0 = N->getOperand(0);
3456 EVT VT = N->getValueType(0);
3458 // fold (cttz c1) -> c2
3459 if (isa<ConstantSDNode>(N0))
3460 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
3464 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
3465 SDValue N0 = N->getOperand(0);
3466 EVT VT = N->getValueType(0);
3468 // fold (ctpop c1) -> c2
3469 if (isa<ConstantSDNode>(N0))
3470 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
3474 SDValue DAGCombiner::visitSELECT(SDNode *N) {
3475 SDValue N0 = N->getOperand(0);
3476 SDValue N1 = N->getOperand(1);
3477 SDValue N2 = N->getOperand(2);
3478 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3479 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3480 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
3481 EVT VT = N->getValueType(0);
3482 EVT VT0 = N0.getValueType();
3484 // fold (select C, X, X) -> X
3487 // fold (select true, X, Y) -> X
3488 if (N0C && !N0C->isNullValue())
3490 // fold (select false, X, Y) -> Y
3491 if (N0C && N0C->isNullValue())
3493 // fold (select C, 1, X) -> (or C, X)
3494 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
3495 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3496 // fold (select C, 0, 1) -> (xor C, 1)
3497 if (VT.isInteger() &&
3500 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
3501 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
3504 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
3505 N0, DAG.getConstant(1, VT0));
3506 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
3507 N0, DAG.getConstant(1, VT0));
3508 AddToWorkList(XORNode.getNode());
3510 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
3511 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
3513 // fold (select C, 0, X) -> (and (not C), X)
3514 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
3515 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3516 AddToWorkList(NOTNode.getNode());
3517 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
3519 // fold (select C, X, 1) -> (or (not C), X)
3520 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
3521 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3522 AddToWorkList(NOTNode.getNode());
3523 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
3525 // fold (select C, X, 0) -> (and C, X)
3526 if (VT == MVT::i1 && N2C && N2C->isNullValue())
3527 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3528 // fold (select X, X, Y) -> (or X, Y)
3529 // fold (select X, 1, Y) -> (or X, Y)
3530 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
3531 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3532 // fold (select X, Y, X) -> (and X, Y)
3533 // fold (select X, Y, 0) -> (and X, Y)
3534 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
3535 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3537 // If we can fold this based on the true/false value, do so.
3538 if (SimplifySelectOps(N, N1, N2))
3539 return SDValue(N, 0); // Don't revisit N.
3541 // fold selects based on a setcc into other things, such as min/max/abs
3542 if (N0.getOpcode() == ISD::SETCC) {
3544 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
3545 // having to say they don't support SELECT_CC on every type the DAG knows
3546 // about, since there is no way to mark an opcode illegal at all value types
3547 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
3548 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
3549 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
3550 N0.getOperand(0), N0.getOperand(1),
3551 N1, N2, N0.getOperand(2));
3552 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
3558 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
3559 SDValue N0 = N->getOperand(0);
3560 SDValue N1 = N->getOperand(1);
3561 SDValue N2 = N->getOperand(2);
3562 SDValue N3 = N->getOperand(3);
3563 SDValue N4 = N->getOperand(4);
3564 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
3566 // fold select_cc lhs, rhs, x, x, cc -> x
3570 // Determine if the condition we're dealing with is constant
3571 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
3572 N0, N1, CC, N->getDebugLoc(), false);
3573 if (SCC.getNode()) AddToWorkList(SCC.getNode());
3575 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
3576 if (!SCCC->isNullValue())
3577 return N2; // cond always true -> true val
3579 return N3; // cond always false -> false val
3582 // Fold to a simpler select_cc
3583 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
3584 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
3585 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
3588 // If we can fold this based on the true/false value, do so.
3589 if (SimplifySelectOps(N, N2, N3))
3590 return SDValue(N, 0); // Don't revisit N.
3592 // fold select_cc into other things, such as min/max/abs
3593 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
3596 SDValue DAGCombiner::visitSETCC(SDNode *N) {
3597 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
3598 cast<CondCodeSDNode>(N->getOperand(2))->get(),
3602 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
3603 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
3604 // transformation. Returns true if extension are possible and the above
3605 // mentioned transformation is profitable.
3606 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
3608 SmallVector<SDNode*, 4> &ExtendNodes,
3609 const TargetLowering &TLI) {
3610 bool HasCopyToRegUses = false;
3611 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
3612 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3613 UE = N0.getNode()->use_end();
3618 if (UI.getUse().getResNo() != N0.getResNo())
3620 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
3621 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
3622 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
3623 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
3624 // Sign bits will be lost after a zext.
3627 for (unsigned i = 0; i != 2; ++i) {
3628 SDValue UseOp = User->getOperand(i);
3631 if (!isa<ConstantSDNode>(UseOp))
3636 ExtendNodes.push_back(User);
3639 // If truncates aren't free and there are users we can't
3640 // extend, it isn't worthwhile.
3643 // Remember if this value is live-out.
3644 if (User->getOpcode() == ISD::CopyToReg)
3645 HasCopyToRegUses = true;
3648 if (HasCopyToRegUses) {
3649 bool BothLiveOut = false;
3650 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3652 SDUse &Use = UI.getUse();
3653 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
3659 // Both unextended and extended values are live out. There had better be
3660 // a good reason for the transformation.
3661 return ExtendNodes.size();
3666 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
3667 SDValue N0 = N->getOperand(0);
3668 EVT VT = N->getValueType(0);
3670 // fold (sext c1) -> c1
3671 if (isa<ConstantSDNode>(N0))
3672 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
3674 // fold (sext (sext x)) -> (sext x)
3675 // fold (sext (aext x)) -> (sext x)
3676 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3677 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
3680 if (N0.getOpcode() == ISD::TRUNCATE) {
3681 // fold (sext (truncate (load x))) -> (sext (smaller load x))
3682 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
3683 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3684 if (NarrowLoad.getNode()) {
3685 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3686 if (NarrowLoad.getNode() != N0.getNode()) {
3687 CombineTo(N0.getNode(), NarrowLoad);
3688 // CombineTo deleted the truncate, if needed, but not what's under it.
3691 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3694 // See if the value being truncated is already sign extended. If so, just
3695 // eliminate the trunc/sext pair.
3696 SDValue Op = N0.getOperand(0);
3697 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
3698 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
3699 unsigned DestBits = VT.getScalarType().getSizeInBits();
3700 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
3702 if (OpBits == DestBits) {
3703 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
3704 // bits, it is already ready.
3705 if (NumSignBits > DestBits-MidBits)
3707 } else if (OpBits < DestBits) {
3708 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
3709 // bits, just sext from i32.
3710 if (NumSignBits > OpBits-MidBits)
3711 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
3713 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
3714 // bits, just truncate to i32.
3715 if (NumSignBits > OpBits-MidBits)
3716 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3719 // fold (sext (truncate x)) -> (sextinreg x).
3720 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
3721 N0.getValueType())) {
3722 if (OpBits < DestBits)
3723 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
3724 else if (OpBits > DestBits)
3725 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
3726 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
3727 DAG.getValueType(N0.getValueType()));
3731 // fold (sext (load x)) -> (sext (truncate (sextload x)))
3732 // None of the supported targets knows how to perform load and sign extend
3733 // on vectors in one instruction. We only perform this transformation on
3735 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
3736 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3737 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
3738 bool DoXform = true;
3739 SmallVector<SDNode*, 4> SetCCs;
3740 if (!N0.hasOneUse())
3741 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
3743 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3744 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3746 LN0->getBasePtr(), LN0->getPointerInfo(),
3748 LN0->isVolatile(), LN0->isNonTemporal(),
3749 LN0->getAlignment());
3750 CombineTo(N, ExtLoad);
3751 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3752 N0.getValueType(), ExtLoad);
3753 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3755 // Extend SetCC uses if necessary.
3756 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3757 SDNode *SetCC = SetCCs[i];
3758 SmallVector<SDValue, 4> Ops;
3760 for (unsigned j = 0; j != 2; ++j) {
3761 SDValue SOp = SetCC->getOperand(j);
3763 Ops.push_back(ExtLoad);
3765 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND,
3766 N->getDebugLoc(), VT, SOp));
3769 Ops.push_back(SetCC->getOperand(2));
3770 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3771 SetCC->getValueType(0),
3772 &Ops[0], Ops.size()));
3775 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3779 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
3780 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
3781 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3782 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3783 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3784 EVT MemVT = LN0->getMemoryVT();
3785 if ((!LegalOperations && !LN0->isVolatile()) ||
3786 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
3787 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3789 LN0->getBasePtr(), LN0->getPointerInfo(),
3791 LN0->isVolatile(), LN0->isNonTemporal(),
3792 LN0->getAlignment());
3793 CombineTo(N, ExtLoad);
3794 CombineTo(N0.getNode(),
3795 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3796 N0.getValueType(), ExtLoad),
3797 ExtLoad.getValue(1));
3798 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3802 if (N0.getOpcode() == ISD::SETCC) {
3803 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
3804 // Only do this before legalize for now.
3805 if (VT.isVector() && !LegalOperations) {
3806 EVT N0VT = N0.getOperand(0).getValueType();
3807 // We know that the # elements of the results is the same as the
3808 // # elements of the compare (and the # elements of the compare result
3809 // for that matter). Check to see that they are the same size. If so,
3810 // we know that the element size of the sext'd result matches the
3811 // element size of the compare operands.
3812 if (VT.getSizeInBits() == N0VT.getSizeInBits())
3813 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3815 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3816 // If the desired elements are smaller or larger than the source
3817 // elements we can use a matching integer vector type and then
3818 // truncate/sign extend
3820 EVT MatchingElementType =
3821 EVT::getIntegerVT(*DAG.getContext(),
3822 N0VT.getScalarType().getSizeInBits());
3823 EVT MatchingVectorType =
3824 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
3825 N0VT.getVectorNumElements());
3827 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
3829 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3830 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
3834 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
3835 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
3837 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
3839 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3840 NegOne, DAG.getConstant(0, VT),
3841 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3842 if (SCC.getNode()) return SCC;
3843 if (!LegalOperations ||
3844 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
3845 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
3846 DAG.getSetCC(N->getDebugLoc(),
3847 TLI.getSetCCResultType(VT),
3848 N0.getOperand(0), N0.getOperand(1),
3849 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
3850 NegOne, DAG.getConstant(0, VT));
3853 // fold (sext x) -> (zext x) if the sign bit is known zero.
3854 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
3855 DAG.SignBitIsZero(N0))
3856 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3861 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
3862 SDValue N0 = N->getOperand(0);
3863 EVT VT = N->getValueType(0);
3865 // fold (zext c1) -> c1
3866 if (isa<ConstantSDNode>(N0))
3867 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3868 // fold (zext (zext x)) -> (zext x)
3869 // fold (zext (aext x)) -> (zext x)
3870 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3871 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
3874 // fold (zext (truncate (load x))) -> (zext (smaller load x))
3875 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
3876 if (N0.getOpcode() == ISD::TRUNCATE) {
3877 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3878 if (NarrowLoad.getNode()) {
3879 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3880 if (NarrowLoad.getNode() != N0.getNode()) {
3881 CombineTo(N0.getNode(), NarrowLoad);
3882 // CombineTo deleted the truncate, if needed, but not what's under it.
3885 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3889 // fold (zext (truncate x)) -> (and x, mask)
3890 if (N0.getOpcode() == ISD::TRUNCATE &&
3891 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
3893 // fold (zext (truncate (load x))) -> (zext (smaller load x))
3894 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
3895 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3896 if (NarrowLoad.getNode()) {
3897 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3898 if (NarrowLoad.getNode() != N0.getNode()) {
3899 CombineTo(N0.getNode(), NarrowLoad);
3900 // CombineTo deleted the truncate, if needed, but not what's under it.
3903 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3906 SDValue Op = N0.getOperand(0);
3907 if (Op.getValueType().bitsLT(VT)) {
3908 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
3909 } else if (Op.getValueType().bitsGT(VT)) {
3910 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3912 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
3913 N0.getValueType().getScalarType());
3916 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
3917 // if either of the casts is not free.
3918 if (N0.getOpcode() == ISD::AND &&
3919 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3920 N0.getOperand(1).getOpcode() == ISD::Constant &&
3921 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3922 N0.getValueType()) ||
3923 !TLI.isZExtFree(N0.getValueType(), VT))) {
3924 SDValue X = N0.getOperand(0).getOperand(0);
3925 if (X.getValueType().bitsLT(VT)) {
3926 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
3927 } else if (X.getValueType().bitsGT(VT)) {
3928 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3930 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3931 Mask = Mask.zext(VT.getSizeInBits());
3932 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3933 X, DAG.getConstant(Mask, VT));
3936 // fold (zext (load x)) -> (zext (truncate (zextload x)))
3937 // None of the supported targets knows how to perform load and vector_zext
3938 // on vectors in one instruction. We only perform this transformation on
3940 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
3941 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3942 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
3943 bool DoXform = true;
3944 SmallVector<SDNode*, 4> SetCCs;
3945 if (!N0.hasOneUse())
3946 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
3948 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3949 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3951 LN0->getBasePtr(), LN0->getPointerInfo(),
3953 LN0->isVolatile(), LN0->isNonTemporal(),
3954 LN0->getAlignment());
3955 CombineTo(N, ExtLoad);
3956 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3957 N0.getValueType(), ExtLoad);
3958 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3960 // Extend SetCC uses if necessary.
3961 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3962 SDNode *SetCC = SetCCs[i];
3963 SmallVector<SDValue, 4> Ops;
3965 for (unsigned j = 0; j != 2; ++j) {
3966 SDValue SOp = SetCC->getOperand(j);
3968 Ops.push_back(ExtLoad);
3970 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND,
3971 N->getDebugLoc(), VT, SOp));
3974 Ops.push_back(SetCC->getOperand(2));
3975 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3976 SetCC->getValueType(0),
3977 &Ops[0], Ops.size()));
3980 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3984 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
3985 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
3986 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3987 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3988 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3989 EVT MemVT = LN0->getMemoryVT();
3990 if ((!LegalOperations && !LN0->isVolatile()) ||
3991 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
3992 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3994 LN0->getBasePtr(), LN0->getPointerInfo(),
3996 LN0->isVolatile(), LN0->isNonTemporal(),
3997 LN0->getAlignment());
3998 CombineTo(N, ExtLoad);
3999 CombineTo(N0.getNode(),
4000 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
4002 ExtLoad.getValue(1));
4003 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4007 if (N0.getOpcode() == ISD::SETCC) {
4008 if (!LegalOperations && VT.isVector()) {
4009 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4010 // Only do this before legalize for now.
4011 EVT N0VT = N0.getOperand(0).getValueType();
4012 EVT EltVT = VT.getVectorElementType();
4013 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
4014 DAG.getConstant(1, EltVT));
4015 if (VT.getSizeInBits() == N0VT.getSizeInBits()) {
4016 // We know that the # elements of the results is the same as the
4017 // # elements of the compare (and the # elements of the compare result
4018 // for that matter). Check to see that they are the same size. If so,
4019 // we know that the element size of the sext'd result matches the
4020 // element size of the compare operands.
4021 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4022 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4024 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4025 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4026 &OneOps[0], OneOps.size()));
4028 // If the desired elements are smaller or larger than the source
4029 // elements we can use a matching integer vector type and then
4030 // truncate/sign extend
4031 EVT MatchingElementType =
4032 EVT::getIntegerVT(*DAG.getContext(),
4033 N0VT.getScalarType().getSizeInBits());
4034 EVT MatchingVectorType =
4035 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4036 N0VT.getVectorNumElements());
4038 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4040 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4041 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4042 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
4043 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4044 &OneOps[0], OneOps.size()));
4048 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4050 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4051 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4052 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4053 if (SCC.getNode()) return SCC;
4056 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
4057 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4058 isa<ConstantSDNode>(N0.getOperand(1)) &&
4059 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4061 SDValue ShAmt = N0.getOperand(1);
4062 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4063 if (N0.getOpcode() == ISD::SHL) {
4064 SDValue InnerZExt = N0.getOperand(0);
4065 // If the original shl may be shifting out bits, do not perform this
4067 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
4068 InnerZExt.getOperand(0).getValueType().getSizeInBits();
4069 if (ShAmtVal > KnownZeroBits)
4073 DebugLoc DL = N->getDebugLoc();
4075 // Ensure that the shift amount is wide enough for the shifted value.
4076 if (VT.getSizeInBits() >= 256)
4077 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
4079 return DAG.getNode(N0.getOpcode(), DL, VT,
4080 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4087 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
4088 SDValue N0 = N->getOperand(0);
4089 EVT VT = N->getValueType(0);
4091 // fold (aext c1) -> c1
4092 if (isa<ConstantSDNode>(N0))
4093 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
4094 // fold (aext (aext x)) -> (aext x)
4095 // fold (aext (zext x)) -> (zext x)
4096 // fold (aext (sext x)) -> (sext x)
4097 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4098 N0.getOpcode() == ISD::ZERO_EXTEND ||
4099 N0.getOpcode() == ISD::SIGN_EXTEND)
4100 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
4102 // fold (aext (truncate (load x))) -> (aext (smaller load x))
4103 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4104 if (N0.getOpcode() == ISD::TRUNCATE) {
4105 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4106 if (NarrowLoad.getNode()) {
4107 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4108 if (NarrowLoad.getNode() != N0.getNode()) {
4109 CombineTo(N0.getNode(), NarrowLoad);
4110 // CombineTo deleted the truncate, if needed, but not what's under it.
4113 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
4117 // fold (aext (truncate x))
4118 if (N0.getOpcode() == ISD::TRUNCATE) {
4119 SDValue TruncOp = N0.getOperand(0);
4120 if (TruncOp.getValueType() == VT)
4121 return TruncOp; // x iff x size == zext size.
4122 if (TruncOp.getValueType().bitsGT(VT))
4123 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
4124 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
4127 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
4128 // if the trunc is not free.
4129 if (N0.getOpcode() == ISD::AND &&
4130 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4131 N0.getOperand(1).getOpcode() == ISD::Constant &&
4132 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4133 N0.getValueType())) {
4134 SDValue X = N0.getOperand(0).getOperand(0);
4135 if (X.getValueType().bitsLT(VT)) {
4136 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
4137 } else if (X.getValueType().bitsGT(VT)) {
4138 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
4140 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4141 Mask = Mask.zext(VT.getSizeInBits());
4142 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4143 X, DAG.getConstant(Mask, VT));
4146 // fold (aext (load x)) -> (aext (truncate (extload x)))
4147 // None of the supported targets knows how to perform load and any_ext
4148 // on vectors in one instruction. We only perform this transformation on
4150 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4151 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4152 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4153 bool DoXform = true;
4154 SmallVector<SDNode*, 4> SetCCs;
4155 if (!N0.hasOneUse())
4156 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4158 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4159 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4161 LN0->getBasePtr(), LN0->getPointerInfo(),
4163 LN0->isVolatile(), LN0->isNonTemporal(),
4164 LN0->getAlignment());
4165 CombineTo(N, ExtLoad);
4166 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4167 N0.getValueType(), ExtLoad);
4168 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4170 // Extend SetCC uses if necessary.
4171 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
4172 SDNode *SetCC = SetCCs[i];
4173 SmallVector<SDValue, 4> Ops;
4175 for (unsigned j = 0; j != 2; ++j) {
4176 SDValue SOp = SetCC->getOperand(j);
4178 Ops.push_back(ExtLoad);
4180 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND,
4181 N->getDebugLoc(), VT, SOp));
4184 Ops.push_back(SetCC->getOperand(2));
4185 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
4186 SetCC->getValueType(0),
4187 &Ops[0], Ops.size()));
4190 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4194 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
4195 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4196 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
4197 if (N0.getOpcode() == ISD::LOAD &&
4198 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4200 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4201 EVT MemVT = LN0->getMemoryVT();
4202 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
4203 VT, LN0->getChain(), LN0->getBasePtr(),
4204 LN0->getPointerInfo(), MemVT,
4205 LN0->isVolatile(), LN0->isNonTemporal(),
4206 LN0->getAlignment());
4207 CombineTo(N, ExtLoad);
4208 CombineTo(N0.getNode(),
4209 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4210 N0.getValueType(), ExtLoad),
4211 ExtLoad.getValue(1));
4212 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4215 if (N0.getOpcode() == ISD::SETCC) {
4216 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
4217 // Only do this before legalize for now.
4218 if (VT.isVector() && !LegalOperations) {
4219 EVT N0VT = N0.getOperand(0).getValueType();
4220 // We know that the # elements of the results is the same as the
4221 // # elements of the compare (and the # elements of the compare result
4222 // for that matter). Check to see that they are the same size. If so,
4223 // we know that the element size of the sext'd result matches the
4224 // element size of the compare operands.
4225 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4226 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4228 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4229 // If the desired elements are smaller or larger than the source
4230 // elements we can use a matching integer vector type and then
4231 // truncate/sign extend
4233 EVT MatchingElementType =
4234 EVT::getIntegerVT(*DAG.getContext(),
4235 N0VT.getScalarType().getSizeInBits());
4236 EVT MatchingVectorType =
4237 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4238 N0VT.getVectorNumElements());
4240 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4242 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4243 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4247 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4249 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4250 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4251 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4259 /// GetDemandedBits - See if the specified operand can be simplified with the
4260 /// knowledge that only the bits specified by Mask are used. If so, return the
4261 /// simpler operand, otherwise return a null SDValue.
4262 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4263 switch (V.getOpcode()) {
4267 // If the LHS or RHS don't contribute bits to the or, drop them.
4268 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4269 return V.getOperand(1);
4270 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4271 return V.getOperand(0);
4274 // Only look at single-use SRLs.
4275 if (!V.getNode()->hasOneUse())
4277 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4278 // See if we can recursively simplify the LHS.
4279 unsigned Amt = RHSC->getZExtValue();
4281 // Watch out for shift count overflow though.
4282 if (Amt >= Mask.getBitWidth()) break;
4283 APInt NewMask = Mask << Amt;
4284 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4285 if (SimplifyLHS.getNode())
4286 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4287 SimplifyLHS, V.getOperand(1));
4293 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
4294 /// bits and then truncated to a narrower type and where N is a multiple
4295 /// of number of bits of the narrower type, transform it to a narrower load
4296 /// from address + N / num of bits of new type. If the result is to be
4297 /// extended, also fold the extension to form a extending load.
4298 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
4299 unsigned Opc = N->getOpcode();
4301 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4302 SDValue N0 = N->getOperand(0);
4303 EVT VT = N->getValueType(0);
4306 // This transformation isn't valid for vector loads.
4310 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4312 if (Opc == ISD::SIGN_EXTEND_INREG) {
4313 ExtType = ISD::SEXTLOAD;
4314 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4315 } else if (Opc == ISD::SRL) {
4316 // Another special-case: SRL is basically zero-extending a narrower value.
4317 ExtType = ISD::ZEXTLOAD;
4319 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4320 if (!N01) return SDValue();
4321 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
4322 VT.getSizeInBits() - N01->getZExtValue());
4324 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
4327 unsigned EVTBits = ExtVT.getSizeInBits();
4329 // Do not generate loads of non-round integer types since these can
4330 // be expensive (and would be wrong if the type is not byte sized).
4331 if (!ExtVT.isRound())
4335 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4336 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4337 ShAmt = N01->getZExtValue();
4338 // Is the shift amount a multiple of size of VT?
4339 if ((ShAmt & (EVTBits-1)) == 0) {
4340 N0 = N0.getOperand(0);
4341 // Is the load width a multiple of size of VT?
4342 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
4346 // At this point, we must have a load or else we can't do the transform.
4347 if (!isa<LoadSDNode>(N0)) return SDValue();
4349 // If the shift amount is larger than the input type then we're not
4350 // accessing any of the loaded bytes. If the load was a zextload/extload
4351 // then the result of the shift+trunc is zero/undef (handled elsewhere).
4352 // If the load was a sextload then the result is a splat of the sign bit
4353 // of the extended byte. This is not worth optimizing for.
4354 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
4359 // If the load is shifted left (and the result isn't shifted back right),
4360 // we can fold the truncate through the shift.
4361 unsigned ShLeftAmt = 0;
4362 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
4363 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
4364 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4365 ShLeftAmt = N01->getZExtValue();
4366 N0 = N0.getOperand(0);
4370 // If we haven't found a load, we can't narrow it. Don't transform one with
4371 // multiple uses, this would require adding a new load.
4372 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() ||
4373 // Don't change the width of a volatile load.
4374 cast<LoadSDNode>(N0)->isVolatile())
4377 // Verify that we are actually reducing a load width here.
4378 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits)
4381 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4382 EVT PtrType = N0.getOperand(1).getValueType();
4384 // For big endian targets, we need to adjust the offset to the pointer to
4385 // load the correct bytes.
4386 if (TLI.isBigEndian()) {
4387 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
4388 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
4389 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
4392 uint64_t PtrOff = ShAmt / 8;
4393 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
4394 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
4395 PtrType, LN0->getBasePtr(),
4396 DAG.getConstant(PtrOff, PtrType));
4397 AddToWorkList(NewPtr.getNode());
4400 if (ExtType == ISD::NON_EXTLOAD)
4401 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
4402 LN0->getPointerInfo().getWithOffset(PtrOff),
4403 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign);
4405 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr,
4406 LN0->getPointerInfo().getWithOffset(PtrOff),
4407 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
4410 // Replace the old load's chain with the new load's chain.
4411 WorkListRemover DeadNodes(*this);
4412 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
4415 // Shift the result left, if we've swallowed a left shift.
4416 SDValue Result = Load;
4417 if (ShLeftAmt != 0) {
4418 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
4419 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
4421 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
4422 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
4425 // Return the new loaded value.
4429 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
4430 SDValue N0 = N->getOperand(0);
4431 SDValue N1 = N->getOperand(1);
4432 EVT VT = N->getValueType(0);
4433 EVT EVT = cast<VTSDNode>(N1)->getVT();
4434 unsigned VTBits = VT.getScalarType().getSizeInBits();
4435 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
4437 // fold (sext_in_reg c1) -> c1
4438 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
4439 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
4441 // If the input is already sign extended, just drop the extension.
4442 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
4445 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
4446 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4447 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
4448 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
4449 N0.getOperand(0), N1);
4452 // fold (sext_in_reg (sext x)) -> (sext x)
4453 // fold (sext_in_reg (aext x)) -> (sext x)
4454 // if x is small enough.
4455 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
4456 SDValue N00 = N0.getOperand(0);
4457 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
4458 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
4459 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
4462 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
4463 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
4464 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
4466 // fold operands of sext_in_reg based on knowledge that the top bits are not
4468 if (SimplifyDemandedBits(SDValue(N, 0)))
4469 return SDValue(N, 0);
4471 // fold (sext_in_reg (load x)) -> (smaller sextload x)
4472 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
4473 SDValue NarrowLoad = ReduceLoadWidth(N);
4474 if (NarrowLoad.getNode())
4477 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
4478 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
4479 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
4480 if (N0.getOpcode() == ISD::SRL) {
4481 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
4482 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
4483 // We can turn this into an SRA iff the input to the SRL is already sign
4485 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
4486 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
4487 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
4488 N0.getOperand(0), N0.getOperand(1));
4492 // fold (sext_inreg (extload x)) -> (sextload x)
4493 if (ISD::isEXTLoad(N0.getNode()) &&
4494 ISD::isUNINDEXEDLoad(N0.getNode()) &&
4495 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4496 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4497 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4498 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4499 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4501 LN0->getBasePtr(), LN0->getPointerInfo(),
4503 LN0->isVolatile(), LN0->isNonTemporal(),
4504 LN0->getAlignment());
4505 CombineTo(N, ExtLoad);
4506 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4507 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4509 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
4510 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4512 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4513 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4514 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4515 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4516 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4518 LN0->getBasePtr(), LN0->getPointerInfo(),
4520 LN0->isVolatile(), LN0->isNonTemporal(),
4521 LN0->getAlignment());
4522 CombineTo(N, ExtLoad);
4523 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4524 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4529 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
4530 SDValue N0 = N->getOperand(0);
4531 EVT VT = N->getValueType(0);
4534 if (N0.getValueType() == N->getValueType(0))
4536 // fold (truncate c1) -> c1
4537 if (isa<ConstantSDNode>(N0))
4538 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
4539 // fold (truncate (truncate x)) -> (truncate x)
4540 if (N0.getOpcode() == ISD::TRUNCATE)
4541 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4542 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
4543 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
4544 N0.getOpcode() == ISD::SIGN_EXTEND ||
4545 N0.getOpcode() == ISD::ANY_EXTEND) {
4546 if (N0.getOperand(0).getValueType().bitsLT(VT))
4547 // if the source is smaller than the dest, we still need an extend
4548 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4550 else if (N0.getOperand(0).getValueType().bitsGT(VT))
4551 // if the source is larger than the dest, than we just need the truncate
4552 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4554 // if the source and dest are the same type, we can drop both the extend
4555 // and the truncate.
4556 return N0.getOperand(0);
4559 // See if we can simplify the input to this truncate through knowledge that
4560 // only the low bits are being used.
4561 // For example "trunc (or (shl x, 8), y)" // -> trunc y
4562 // Currently we only perform this optimization on scalars because vectors
4563 // may have different active low bits.
4564 if (!VT.isVector()) {
4566 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
4567 VT.getSizeInBits()));
4568 if (Shorter.getNode())
4569 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
4571 // fold (truncate (load x)) -> (smaller load x)
4572 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
4573 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
4574 SDValue Reduced = ReduceLoadWidth(N);
4575 if (Reduced.getNode())
4579 // Simplify the operands using demanded-bits information.
4580 if (!VT.isVector() &&
4581 SimplifyDemandedBits(SDValue(N, 0)))
4582 return SDValue(N, 0);
4587 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
4588 SDValue Elt = N->getOperand(i);
4589 if (Elt.getOpcode() != ISD::MERGE_VALUES)
4590 return Elt.getNode();
4591 return Elt.getOperand(Elt.getResNo()).getNode();
4594 /// CombineConsecutiveLoads - build_pair (load, load) -> load
4595 /// if load locations are consecutive.
4596 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
4597 assert(N->getOpcode() == ISD::BUILD_PAIR);
4599 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
4600 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
4601 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
4602 LD1->getPointerInfo().getAddrSpace() !=
4603 LD2->getPointerInfo().getAddrSpace())
4605 EVT LD1VT = LD1->getValueType(0);
4607 if (ISD::isNON_EXTLoad(LD2) &&
4609 // If both are volatile this would reduce the number of volatile loads.
4610 // If one is volatile it might be ok, but play conservative and bail out.
4611 !LD1->isVolatile() &&
4612 !LD2->isVolatile() &&
4613 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
4614 unsigned Align = LD1->getAlignment();
4615 unsigned NewAlign = TLI.getTargetData()->
4616 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4618 if (NewAlign <= Align &&
4619 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
4620 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
4621 LD1->getBasePtr(), LD1->getPointerInfo(),
4622 false, false, Align);
4628 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
4629 SDValue N0 = N->getOperand(0);
4630 EVT VT = N->getValueType(0);
4632 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
4633 // Only do this before legalize, since afterward the target may be depending
4634 // on the bitconvert.
4635 // First check to see if this is all constant.
4637 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
4639 bool isSimple = true;
4640 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
4641 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
4642 N0.getOperand(i).getOpcode() != ISD::Constant &&
4643 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
4648 EVT DestEltVT = N->getValueType(0).getVectorElementType();
4649 assert(!DestEltVT.isVector() &&
4650 "Element type of vector ValueType must not be vector!");
4652 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
4655 // If the input is a constant, let getNode fold it.
4656 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
4657 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
4658 if (Res.getNode() != N) {
4659 if (!LegalOperations ||
4660 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
4663 // Folding it resulted in an illegal node, and it's too late to
4664 // do that. Clean up the old node and forego the transformation.
4665 // Ideally this won't happen very often, because instcombine
4666 // and the earlier dagcombine runs (where illegal nodes are
4667 // permitted) should have folded most of them already.
4668 DAG.DeleteNode(Res.getNode());
4672 // (conv (conv x, t1), t2) -> (conv x, t2)
4673 if (N0.getOpcode() == ISD::BITCAST)
4674 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
4677 // fold (conv (load x)) -> (load (conv*)x)
4678 // If the resultant load doesn't need a higher alignment than the original!
4679 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
4680 // Do not change the width of a volatile load.
4681 !cast<LoadSDNode>(N0)->isVolatile() &&
4682 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
4683 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4684 unsigned Align = TLI.getTargetData()->
4685 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4686 unsigned OrigAlign = LN0->getAlignment();
4688 if (Align <= OrigAlign) {
4689 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
4690 LN0->getBasePtr(), LN0->getPointerInfo(),
4691 LN0->isVolatile(), LN0->isNonTemporal(),
4694 CombineTo(N0.getNode(),
4695 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
4696 N0.getValueType(), Load),
4702 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
4703 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
4704 // This often reduces constant pool loads.
4705 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
4706 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
4707 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
4709 AddToWorkList(NewConv.getNode());
4711 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
4712 if (N0.getOpcode() == ISD::FNEG)
4713 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
4714 NewConv, DAG.getConstant(SignBit, VT));
4715 assert(N0.getOpcode() == ISD::FABS);
4716 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4717 NewConv, DAG.getConstant(~SignBit, VT));
4720 // fold (bitconvert (fcopysign cst, x)) ->
4721 // (or (and (bitconvert x), sign), (and cst, (not sign)))
4722 // Note that we don't handle (copysign x, cst) because this can always be
4723 // folded to an fneg or fabs.
4724 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
4725 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
4726 VT.isInteger() && !VT.isVector()) {
4727 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
4728 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
4729 if (isTypeLegal(IntXVT)) {
4730 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
4731 IntXVT, N0.getOperand(1));
4732 AddToWorkList(X.getNode());
4734 // If X has a different width than the result/lhs, sext it or truncate it.
4735 unsigned VTWidth = VT.getSizeInBits();
4736 if (OrigXWidth < VTWidth) {
4737 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
4738 AddToWorkList(X.getNode());
4739 } else if (OrigXWidth > VTWidth) {
4740 // To get the sign bit in the right place, we have to shift it right
4741 // before truncating.
4742 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
4743 X.getValueType(), X,
4744 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
4745 AddToWorkList(X.getNode());
4746 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4747 AddToWorkList(X.getNode());
4750 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
4751 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
4752 X, DAG.getConstant(SignBit, VT));
4753 AddToWorkList(X.getNode());
4755 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
4756 VT, N0.getOperand(0));
4757 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
4758 Cst, DAG.getConstant(~SignBit, VT));
4759 AddToWorkList(Cst.getNode());
4761 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
4765 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
4766 if (N0.getOpcode() == ISD::BUILD_PAIR) {
4767 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
4768 if (CombineLD.getNode())
4775 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
4776 EVT VT = N->getValueType(0);
4777 return CombineConsecutiveLoads(N, VT);
4780 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
4781 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
4782 /// destination element value type.
4783 SDValue DAGCombiner::
4784 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
4785 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
4787 // If this is already the right type, we're done.
4788 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
4790 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
4791 unsigned DstBitSize = DstEltVT.getSizeInBits();
4793 // If this is a conversion of N elements of one type to N elements of another
4794 // type, convert each element. This handles FP<->INT cases.
4795 if (SrcBitSize == DstBitSize) {
4796 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4797 BV->getValueType(0).getVectorNumElements());
4799 // Due to the FP element handling below calling this routine recursively,
4800 // we can end up with a scalar-to-vector node here.
4801 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
4802 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
4803 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
4804 DstEltVT, BV->getOperand(0)));
4806 SmallVector<SDValue, 8> Ops;
4807 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4808 SDValue Op = BV->getOperand(i);
4809 // If the vector element type is not legal, the BUILD_VECTOR operands
4810 // are promoted and implicitly truncated. Make that explicit here.
4811 if (Op.getValueType() != SrcEltVT)
4812 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
4813 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
4815 AddToWorkList(Ops.back().getNode());
4817 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4818 &Ops[0], Ops.size());
4821 // Otherwise, we're growing or shrinking the elements. To avoid having to
4822 // handle annoying details of growing/shrinking FP values, we convert them to
4824 if (SrcEltVT.isFloatingPoint()) {
4825 // Convert the input float vector to a int vector where the elements are the
4827 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
4828 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
4829 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
4833 // Now we know the input is an integer vector. If the output is a FP type,
4834 // convert to integer first, then to FP of the right size.
4835 if (DstEltVT.isFloatingPoint()) {
4836 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
4837 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
4838 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
4840 // Next, convert to FP elements of the same size.
4841 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
4844 // Okay, we know the src/dst types are both integers of differing types.
4845 // Handling growing first.
4846 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
4847 if (SrcBitSize < DstBitSize) {
4848 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
4850 SmallVector<SDValue, 8> Ops;
4851 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
4852 i += NumInputsPerOutput) {
4853 bool isLE = TLI.isLittleEndian();
4854 APInt NewBits = APInt(DstBitSize, 0);
4855 bool EltIsUndef = true;
4856 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
4857 // Shift the previously computed bits over.
4858 NewBits <<= SrcBitSize;
4859 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
4860 if (Op.getOpcode() == ISD::UNDEF) continue;
4863 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
4864 zextOrTrunc(SrcBitSize).zext(DstBitSize);
4868 Ops.push_back(DAG.getUNDEF(DstEltVT));
4870 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
4873 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
4874 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4875 &Ops[0], Ops.size());
4878 // Finally, this must be the case where we are shrinking elements: each input
4879 // turns into multiple outputs.
4880 bool isS2V = ISD::isScalarToVector(BV);
4881 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
4882 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4883 NumOutputsPerInput*BV->getNumOperands());
4884 SmallVector<SDValue, 8> Ops;
4886 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4887 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
4888 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
4889 Ops.push_back(DAG.getUNDEF(DstEltVT));
4893 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
4894 getAPIntValue().zextOrTrunc(SrcBitSize);
4896 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
4897 APInt ThisVal = OpVal.trunc(DstBitSize);
4898 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
4899 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
4900 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
4901 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
4903 OpVal = OpVal.lshr(DstBitSize);
4906 // For big endian targets, swap the order of the pieces of each element.
4907 if (TLI.isBigEndian())
4908 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
4911 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4912 &Ops[0], Ops.size());
4915 SDValue DAGCombiner::visitFADD(SDNode *N) {
4916 SDValue N0 = N->getOperand(0);
4917 SDValue N1 = N->getOperand(1);
4918 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4919 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4920 EVT VT = N->getValueType(0);
4923 if (VT.isVector()) {
4924 SDValue FoldedVOp = SimplifyVBinOp(N);
4925 if (FoldedVOp.getNode()) return FoldedVOp;
4928 // fold (fadd c1, c2) -> (fadd c1, c2)
4929 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4930 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
4931 // canonicalize constant to RHS
4932 if (N0CFP && !N1CFP)
4933 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
4934 // fold (fadd A, 0) -> A
4935 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4937 // fold (fadd A, (fneg B)) -> (fsub A, B)
4938 if (isNegatibleForFree(N1, LegalOperations) == 2)
4939 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
4940 GetNegatedExpression(N1, DAG, LegalOperations));
4941 // fold (fadd (fneg A), B) -> (fsub B, A)
4942 if (isNegatibleForFree(N0, LegalOperations) == 2)
4943 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
4944 GetNegatedExpression(N0, DAG, LegalOperations));
4946 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
4947 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
4948 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4949 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
4950 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
4951 N0.getOperand(1), N1));
4956 SDValue DAGCombiner::visitFSUB(SDNode *N) {
4957 SDValue N0 = N->getOperand(0);
4958 SDValue N1 = N->getOperand(1);
4959 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4960 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4961 EVT VT = N->getValueType(0);
4964 if (VT.isVector()) {
4965 SDValue FoldedVOp = SimplifyVBinOp(N);
4966 if (FoldedVOp.getNode()) return FoldedVOp;
4969 // fold (fsub c1, c2) -> c1-c2
4970 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4971 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
4972 // fold (fsub A, 0) -> A
4973 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4975 // fold (fsub 0, B) -> -B
4976 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
4977 if (isNegatibleForFree(N1, LegalOperations))
4978 return GetNegatedExpression(N1, DAG, LegalOperations);
4979 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4980 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
4982 // fold (fsub A, (fneg B)) -> (fadd A, B)
4983 if (isNegatibleForFree(N1, LegalOperations))
4984 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
4985 GetNegatedExpression(N1, DAG, LegalOperations));
4990 SDValue DAGCombiner::visitFMUL(SDNode *N) {
4991 SDValue N0 = N->getOperand(0);
4992 SDValue N1 = N->getOperand(1);
4993 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4994 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4995 EVT VT = N->getValueType(0);
4998 if (VT.isVector()) {
4999 SDValue FoldedVOp = SimplifyVBinOp(N);
5000 if (FoldedVOp.getNode()) return FoldedVOp;
5003 // fold (fmul c1, c2) -> c1*c2
5004 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5005 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
5006 // canonicalize constant to RHS
5007 if (N0CFP && !N1CFP)
5008 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
5009 // fold (fmul A, 0) -> 0
5010 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
5012 // fold (fmul A, 0) -> 0, vector edition.
5013 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
5015 // fold (fmul X, 2.0) -> (fadd X, X)
5016 if (N1CFP && N1CFP->isExactlyValue(+2.0))
5017 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
5018 // fold (fmul X, -1.0) -> (fneg X)
5019 if (N1CFP && N1CFP->isExactlyValue(-1.0))
5020 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5021 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
5023 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
5024 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
5025 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
5026 // Both can be negated for free, check to see if at least one is cheaper
5028 if (LHSNeg == 2 || RHSNeg == 2)
5029 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5030 GetNegatedExpression(N0, DAG, LegalOperations),
5031 GetNegatedExpression(N1, DAG, LegalOperations));
5035 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
5036 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
5037 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
5038 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
5039 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5040 N0.getOperand(1), N1));
5045 SDValue DAGCombiner::visitFDIV(SDNode *N) {
5046 SDValue N0 = N->getOperand(0);
5047 SDValue N1 = N->getOperand(1);
5048 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5049 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5050 EVT VT = N->getValueType(0);
5053 if (VT.isVector()) {
5054 SDValue FoldedVOp = SimplifyVBinOp(N);
5055 if (FoldedVOp.getNode()) return FoldedVOp;
5058 // fold (fdiv c1, c2) -> c1/c2
5059 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5060 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
5063 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
5064 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
5065 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
5066 // Both can be negated for free, check to see if at least one is cheaper
5068 if (LHSNeg == 2 || RHSNeg == 2)
5069 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
5070 GetNegatedExpression(N0, DAG, LegalOperations),
5071 GetNegatedExpression(N1, DAG, LegalOperations));
5078 SDValue DAGCombiner::visitFREM(SDNode *N) {
5079 SDValue N0 = N->getOperand(0);
5080 SDValue N1 = N->getOperand(1);
5081 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5082 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5083 EVT VT = N->getValueType(0);
5085 // fold (frem c1, c2) -> fmod(c1,c2)
5086 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5087 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
5092 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
5093 SDValue N0 = N->getOperand(0);
5094 SDValue N1 = N->getOperand(1);
5095 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5096 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5097 EVT VT = N->getValueType(0);
5099 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
5100 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
5103 const APFloat& V = N1CFP->getValueAPF();
5104 // copysign(x, c1) -> fabs(x) iff ispos(c1)
5105 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
5106 if (!V.isNegative()) {
5107 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
5108 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5110 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5111 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
5112 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
5116 // copysign(fabs(x), y) -> copysign(x, y)
5117 // copysign(fneg(x), y) -> copysign(x, y)
5118 // copysign(copysign(x,z), y) -> copysign(x, y)
5119 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
5120 N0.getOpcode() == ISD::FCOPYSIGN)
5121 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5122 N0.getOperand(0), N1);
5124 // copysign(x, abs(y)) -> abs(x)
5125 if (N1.getOpcode() == ISD::FABS)
5126 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5128 // copysign(x, copysign(y,z)) -> copysign(x, z)
5129 if (N1.getOpcode() == ISD::FCOPYSIGN)
5130 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5131 N0, N1.getOperand(1));
5133 // copysign(x, fp_extend(y)) -> copysign(x, y)
5134 // copysign(x, fp_round(y)) -> copysign(x, y)
5135 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
5136 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5137 N0, N1.getOperand(0));
5142 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
5143 SDValue N0 = N->getOperand(0);
5144 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5145 EVT VT = N->getValueType(0);
5146 EVT OpVT = N0.getValueType();
5148 // fold (sint_to_fp c1) -> c1fp
5149 if (N0C && OpVT != MVT::ppcf128 &&
5150 // ...but only if the target supports immediate floating-point values
5151 (Level == llvm::Unrestricted || TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5152 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5154 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
5155 // but UINT_TO_FP is legal on this target, try to convert.
5156 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
5157 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
5158 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
5159 if (DAG.SignBitIsZero(N0))
5160 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5166 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
5167 SDValue N0 = N->getOperand(0);
5168 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5169 EVT VT = N->getValueType(0);
5170 EVT OpVT = N0.getValueType();
5172 // fold (uint_to_fp c1) -> c1fp
5173 if (N0C && OpVT != MVT::ppcf128 &&
5174 // ...but only if the target supports immediate floating-point values
5175 (Level == llvm::Unrestricted || TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5176 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5178 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
5179 // but SINT_TO_FP is legal on this target, try to convert.
5180 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
5181 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
5182 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
5183 if (DAG.SignBitIsZero(N0))
5184 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5190 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
5191 SDValue N0 = N->getOperand(0);
5192 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5193 EVT VT = N->getValueType(0);
5195 // fold (fp_to_sint c1fp) -> c1
5197 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
5202 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
5203 SDValue N0 = N->getOperand(0);
5204 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5205 EVT VT = N->getValueType(0);
5207 // fold (fp_to_uint c1fp) -> c1
5208 if (N0CFP && VT != MVT::ppcf128)
5209 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
5214 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
5215 SDValue N0 = N->getOperand(0);
5216 SDValue N1 = N->getOperand(1);
5217 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5218 EVT VT = N->getValueType(0);
5220 // fold (fp_round c1fp) -> c1fp
5221 if (N0CFP && N0.getValueType() != MVT::ppcf128)
5222 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
5224 // fold (fp_round (fp_extend x)) -> x
5225 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
5226 return N0.getOperand(0);
5228 // fold (fp_round (fp_round x)) -> (fp_round x)
5229 if (N0.getOpcode() == ISD::FP_ROUND) {
5230 // This is a value preserving truncation if both round's are.
5231 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
5232 N0.getNode()->getConstantOperandVal(1) == 1;
5233 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
5234 DAG.getIntPtrConstant(IsTrunc));
5237 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
5238 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
5239 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
5240 N0.getOperand(0), N1);
5241 AddToWorkList(Tmp.getNode());
5242 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5243 Tmp, N0.getOperand(1));
5249 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
5250 SDValue N0 = N->getOperand(0);
5251 EVT VT = N->getValueType(0);
5252 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5253 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5255 // fold (fp_round_inreg c1fp) -> c1fp
5256 if (N0CFP && isTypeLegal(EVT)) {
5257 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
5258 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
5264 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
5265 SDValue N0 = N->getOperand(0);
5266 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5267 EVT VT = N->getValueType(0);
5269 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
5270 if (N->hasOneUse() &&
5271 N->use_begin()->getOpcode() == ISD::FP_ROUND)
5274 // fold (fp_extend c1fp) -> c1fp
5275 if (N0CFP && VT != MVT::ppcf128)
5276 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
5278 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
5280 if (N0.getOpcode() == ISD::FP_ROUND
5281 && N0.getNode()->getConstantOperandVal(1) == 1) {
5282 SDValue In = N0.getOperand(0);
5283 if (In.getValueType() == VT) return In;
5284 if (VT.bitsLT(In.getValueType()))
5285 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
5286 In, N0.getOperand(1));
5287 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
5290 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
5291 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
5292 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5293 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
5294 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5295 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
5297 LN0->getBasePtr(), LN0->getPointerInfo(),
5299 LN0->isVolatile(), LN0->isNonTemporal(),
5300 LN0->getAlignment());
5301 CombineTo(N, ExtLoad);
5302 CombineTo(N0.getNode(),
5303 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
5304 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
5305 ExtLoad.getValue(1));
5306 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5312 SDValue DAGCombiner::visitFNEG(SDNode *N) {
5313 SDValue N0 = N->getOperand(0);
5314 EVT VT = N->getValueType(0);
5316 if (isNegatibleForFree(N0, LegalOperations))
5317 return GetNegatedExpression(N0, DAG, LegalOperations);
5319 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
5320 // constant pool values.
5321 if (N0.getOpcode() == ISD::BITCAST &&
5323 N0.getNode()->hasOneUse() &&
5324 N0.getOperand(0).getValueType().isInteger()) {
5325 SDValue Int = N0.getOperand(0);
5326 EVT IntVT = Int.getValueType();
5327 if (IntVT.isInteger() && !IntVT.isVector()) {
5328 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
5329 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5330 AddToWorkList(Int.getNode());
5331 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5339 SDValue DAGCombiner::visitFABS(SDNode *N) {
5340 SDValue N0 = N->getOperand(0);
5341 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5342 EVT VT = N->getValueType(0);
5344 // fold (fabs c1) -> fabs(c1)
5345 if (N0CFP && VT != MVT::ppcf128)
5346 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5347 // fold (fabs (fabs x)) -> (fabs x)
5348 if (N0.getOpcode() == ISD::FABS)
5349 return N->getOperand(0);
5350 // fold (fabs (fneg x)) -> (fabs x)
5351 // fold (fabs (fcopysign x, y)) -> (fabs x)
5352 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
5353 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
5355 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
5356 // constant pool values.
5357 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
5358 N0.getOperand(0).getValueType().isInteger() &&
5359 !N0.getOperand(0).getValueType().isVector()) {
5360 SDValue Int = N0.getOperand(0);
5361 EVT IntVT = Int.getValueType();
5362 if (IntVT.isInteger() && !IntVT.isVector()) {
5363 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
5364 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5365 AddToWorkList(Int.getNode());
5366 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5367 N->getValueType(0), Int);
5374 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
5375 SDValue Chain = N->getOperand(0);
5376 SDValue N1 = N->getOperand(1);
5377 SDValue N2 = N->getOperand(2);
5379 // If N is a constant we could fold this into a fallthrough or unconditional
5380 // branch. However that doesn't happen very often in normal code, because
5381 // Instcombine/SimplifyCFG should have handled the available opportunities.
5382 // If we did this folding here, it would be necessary to update the
5383 // MachineBasicBlock CFG, which is awkward.
5385 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
5387 if (N1.getOpcode() == ISD::SETCC &&
5388 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
5389 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5390 Chain, N1.getOperand(2),
5391 N1.getOperand(0), N1.getOperand(1), N2);
5394 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
5395 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
5396 (N1.getOperand(0).hasOneUse() &&
5397 N1.getOperand(0).getOpcode() == ISD::SRL))) {
5399 if (N1.getOpcode() == ISD::TRUNCATE) {
5400 // Look pass the truncate.
5401 Trunc = N1.getNode();
5402 N1 = N1.getOperand(0);
5405 // Match this pattern so that we can generate simpler code:
5408 // %b = and i32 %a, 2
5409 // %c = srl i32 %b, 1
5410 // brcond i32 %c ...
5415 // %b = and i32 %a, 2
5416 // %c = setcc eq %b, 0
5419 // This applies only when the AND constant value has one bit set and the
5420 // SRL constant is equal to the log2 of the AND constant. The back-end is
5421 // smart enough to convert the result into a TEST/JMP sequence.
5422 SDValue Op0 = N1.getOperand(0);
5423 SDValue Op1 = N1.getOperand(1);
5425 if (Op0.getOpcode() == ISD::AND &&
5426 Op1.getOpcode() == ISD::Constant) {
5427 SDValue AndOp1 = Op0.getOperand(1);
5429 if (AndOp1.getOpcode() == ISD::Constant) {
5430 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
5432 if (AndConst.isPowerOf2() &&
5433 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
5435 DAG.getSetCC(N->getDebugLoc(),
5436 TLI.getSetCCResultType(Op0.getValueType()),
5437 Op0, DAG.getConstant(0, Op0.getValueType()),
5440 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5441 MVT::Other, Chain, SetCC, N2);
5442 // Don't add the new BRCond into the worklist or else SimplifySelectCC
5443 // will convert it back to (X & C1) >> C2.
5444 CombineTo(N, NewBRCond, false);
5445 // Truncate is dead.
5447 removeFromWorkList(Trunc);
5448 DAG.DeleteNode(Trunc);
5450 // Replace the uses of SRL with SETCC
5451 WorkListRemover DeadNodes(*this);
5452 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5453 removeFromWorkList(N1.getNode());
5454 DAG.DeleteNode(N1.getNode());
5455 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5461 // Restore N1 if the above transformation doesn't match.
5462 N1 = N->getOperand(1);
5465 // Transform br(xor(x, y)) -> br(x != y)
5466 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
5467 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
5468 SDNode *TheXor = N1.getNode();
5469 SDValue Op0 = TheXor->getOperand(0);
5470 SDValue Op1 = TheXor->getOperand(1);
5471 if (Op0.getOpcode() == Op1.getOpcode()) {
5472 // Avoid missing important xor optimizations.
5473 SDValue Tmp = visitXOR(TheXor);
5474 if (Tmp.getNode() && Tmp.getNode() != TheXor) {
5475 DEBUG(dbgs() << "\nReplacing.8 ";
5477 dbgs() << "\nWith: ";
5478 Tmp.getNode()->dump(&DAG);
5480 WorkListRemover DeadNodes(*this);
5481 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes);
5482 removeFromWorkList(TheXor);
5483 DAG.DeleteNode(TheXor);
5484 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5485 MVT::Other, Chain, Tmp, N2);
5489 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
5491 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
5492 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
5493 Op0.getOpcode() == ISD::XOR) {
5494 TheXor = Op0.getNode();
5498 EVT SetCCVT = N1.getValueType();
5500 SetCCVT = TLI.getSetCCResultType(SetCCVT);
5501 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
5504 Equal ? ISD::SETEQ : ISD::SETNE);
5505 // Replace the uses of XOR with SETCC
5506 WorkListRemover DeadNodes(*this);
5507 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5508 removeFromWorkList(N1.getNode());
5509 DAG.DeleteNode(N1.getNode());
5510 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5511 MVT::Other, Chain, SetCC, N2);
5518 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
5520 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
5521 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
5522 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
5524 // If N is a constant we could fold this into a fallthrough or unconditional
5525 // branch. However that doesn't happen very often in normal code, because
5526 // Instcombine/SimplifyCFG should have handled the available opportunities.
5527 // If we did this folding here, it would be necessary to update the
5528 // MachineBasicBlock CFG, which is awkward.
5530 // Use SimplifySetCC to simplify SETCC's.
5531 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
5532 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
5534 if (Simp.getNode()) AddToWorkList(Simp.getNode());
5536 // fold to a simpler setcc
5537 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
5538 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5539 N->getOperand(0), Simp.getOperand(2),
5540 Simp.getOperand(0), Simp.getOperand(1),
5546 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
5547 /// pre-indexed load / store when the base pointer is an add or subtract
5548 /// and it has other uses besides the load / store. After the
5549 /// transformation, the new indexed load / store has effectively folded
5550 /// the add / subtract in and all of its other uses are redirected to the
5551 /// new load / store.
5552 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
5553 if (!LegalOperations)
5559 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5560 if (LD->isIndexed())
5562 VT = LD->getMemoryVT();
5563 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
5564 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
5566 Ptr = LD->getBasePtr();
5567 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5568 if (ST->isIndexed())
5570 VT = ST->getMemoryVT();
5571 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
5572 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
5574 Ptr = ST->getBasePtr();
5580 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
5581 // out. There is no reason to make this a preinc/predec.
5582 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
5583 Ptr.getNode()->hasOneUse())
5586 // Ask the target to do addressing mode selection.
5589 ISD::MemIndexedMode AM = ISD::UNINDEXED;
5590 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
5592 // Don't create a indexed load / store with zero offset.
5593 if (isa<ConstantSDNode>(Offset) &&
5594 cast<ConstantSDNode>(Offset)->isNullValue())
5597 // Try turning it into a pre-indexed load / store except when:
5598 // 1) The new base ptr is a frame index.
5599 // 2) If N is a store and the new base ptr is either the same as or is a
5600 // predecessor of the value being stored.
5601 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
5602 // that would create a cycle.
5603 // 4) All uses are load / store ops that use it as old base ptr.
5605 // Check #1. Preinc'ing a frame index would require copying the stack pointer
5606 // (plus the implicit offset) to a register to preinc anyway.
5607 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5612 SDValue Val = cast<StoreSDNode>(N)->getValue();
5613 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
5617 // Now check for #3 and #4.
5618 bool RealUse = false;
5619 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
5620 E = Ptr.getNode()->use_end(); I != E; ++I) {
5624 if (Use->isPredecessorOf(N))
5627 if (!((Use->getOpcode() == ISD::LOAD &&
5628 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
5629 (Use->getOpcode() == ISD::STORE &&
5630 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
5639 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5640 BasePtr, Offset, AM);
5642 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5643 BasePtr, Offset, AM);
5646 DEBUG(dbgs() << "\nReplacing.4 ";
5648 dbgs() << "\nWith: ";
5649 Result.getNode()->dump(&DAG);
5651 WorkListRemover DeadNodes(*this);
5653 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5655 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5658 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5662 // Finally, since the node is now dead, remove it from the graph.
5665 // Replace the uses of Ptr with uses of the updated base value.
5666 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
5668 removeFromWorkList(Ptr.getNode());
5669 DAG.DeleteNode(Ptr.getNode());
5674 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
5675 /// add / sub of the base pointer node into a post-indexed load / store.
5676 /// The transformation folded the add / subtract into the new indexed
5677 /// load / store effectively and all of its uses are redirected to the
5678 /// new load / store.
5679 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
5680 if (!LegalOperations)
5686 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5687 if (LD->isIndexed())
5689 VT = LD->getMemoryVT();
5690 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
5691 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
5693 Ptr = LD->getBasePtr();
5694 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5695 if (ST->isIndexed())
5697 VT = ST->getMemoryVT();
5698 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
5699 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
5701 Ptr = ST->getBasePtr();
5707 if (Ptr.getNode()->hasOneUse())
5710 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
5711 E = Ptr.getNode()->use_end(); I != E; ++I) {
5714 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
5719 ISD::MemIndexedMode AM = ISD::UNINDEXED;
5720 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
5721 // Don't create a indexed load / store with zero offset.
5722 if (isa<ConstantSDNode>(Offset) &&
5723 cast<ConstantSDNode>(Offset)->isNullValue())
5726 // Try turning it into a post-indexed load / store except when
5727 // 1) All uses are load / store ops that use it as base ptr.
5728 // 2) Op must be independent of N, i.e. Op is neither a predecessor
5729 // nor a successor of N. Otherwise, if Op is folded that would
5732 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5736 bool TryNext = false;
5737 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
5738 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
5740 if (Use == Ptr.getNode())
5743 // If all the uses are load / store addresses, then don't do the
5745 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
5746 bool RealUse = false;
5747 for (SDNode::use_iterator III = Use->use_begin(),
5748 EEE = Use->use_end(); III != EEE; ++III) {
5749 SDNode *UseUse = *III;
5750 if (!((UseUse->getOpcode() == ISD::LOAD &&
5751 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
5752 (UseUse->getOpcode() == ISD::STORE &&
5753 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
5768 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
5769 SDValue Result = isLoad
5770 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5771 BasePtr, Offset, AM)
5772 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5773 BasePtr, Offset, AM);
5776 DEBUG(dbgs() << "\nReplacing.5 ";
5778 dbgs() << "\nWith: ";
5779 Result.getNode()->dump(&DAG);
5781 WorkListRemover DeadNodes(*this);
5783 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5785 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5788 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5792 // Finally, since the node is now dead, remove it from the graph.
5795 // Replace the uses of Use with uses of the updated base value.
5796 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
5797 Result.getValue(isLoad ? 1 : 0),
5799 removeFromWorkList(Op);
5809 SDValue DAGCombiner::visitLOAD(SDNode *N) {
5810 LoadSDNode *LD = cast<LoadSDNode>(N);
5811 SDValue Chain = LD->getChain();
5812 SDValue Ptr = LD->getBasePtr();
5814 // If load is not volatile and there are no uses of the loaded value (and
5815 // the updated indexed value in case of indexed loads), change uses of the
5816 // chain value into uses of the chain input (i.e. delete the dead load).
5817 if (!LD->isVolatile()) {
5818 if (N->getValueType(1) == MVT::Other) {
5820 if (N->hasNUsesOfValue(0, 0)) {
5821 // It's not safe to use the two value CombineTo variant here. e.g.
5822 // v1, chain2 = load chain1, loc
5823 // v2, chain3 = load chain2, loc
5825 // Now we replace use of chain2 with chain1. This makes the second load
5826 // isomorphic to the one we are deleting, and thus makes this load live.
5827 DEBUG(dbgs() << "\nReplacing.6 ";
5829 dbgs() << "\nWith chain: ";
5830 Chain.getNode()->dump(&DAG);
5832 WorkListRemover DeadNodes(*this);
5833 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
5835 if (N->use_empty()) {
5836 removeFromWorkList(N);
5840 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5844 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
5845 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
5846 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
5847 DEBUG(dbgs() << "\nReplacing.7 ";
5849 dbgs() << "\nWith: ";
5850 Undef.getNode()->dump(&DAG);
5851 dbgs() << " and 2 other values\n");
5852 WorkListRemover DeadNodes(*this);
5853 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
5854 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
5855 DAG.getUNDEF(N->getValueType(1)),
5857 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
5858 removeFromWorkList(N);
5860 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5865 // If this load is directly stored, replace the load value with the stored
5867 // TODO: Handle store large -> read small portion.
5868 // TODO: Handle TRUNCSTORE/LOADEXT
5869 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
5870 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
5871 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
5872 if (PrevST->getBasePtr() == Ptr &&
5873 PrevST->getValue().getValueType() == N->getValueType(0))
5874 return CombineTo(N, Chain.getOperand(1), Chain);
5878 // Try to infer better alignment information than the load already has.
5879 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
5880 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
5881 if (Align > LD->getAlignment())
5882 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
5883 LD->getValueType(0),
5884 Chain, Ptr, LD->getPointerInfo(),
5886 LD->isVolatile(), LD->isNonTemporal(), Align);
5891 // Walk up chain skipping non-aliasing memory nodes.
5892 SDValue BetterChain = FindBetterChain(N, Chain);
5894 // If there is a better chain.
5895 if (Chain != BetterChain) {
5898 // Replace the chain to void dependency.
5899 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
5900 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
5901 BetterChain, Ptr, LD->getPointerInfo(),
5902 LD->isVolatile(), LD->isNonTemporal(),
5903 LD->getAlignment());
5905 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
5906 LD->getValueType(0),
5907 BetterChain, Ptr, LD->getPointerInfo(),
5910 LD->isNonTemporal(),
5911 LD->getAlignment());
5914 // Create token factor to keep old chain connected.
5915 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5916 MVT::Other, Chain, ReplLoad.getValue(1));
5918 // Make sure the new and old chains are cleaned up.
5919 AddToWorkList(Token.getNode());
5921 // Replace uses with load result and token factor. Don't add users
5923 return CombineTo(N, ReplLoad.getValue(0), Token, false);
5927 // Try transforming N to an indexed load.
5928 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5929 return SDValue(N, 0);
5934 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
5935 /// load is having specific bytes cleared out. If so, return the byte size
5936 /// being masked out and the shift amount.
5937 static std::pair<unsigned, unsigned>
5938 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
5939 std::pair<unsigned, unsigned> Result(0, 0);
5941 // Check for the structure we're looking for.
5942 if (V->getOpcode() != ISD::AND ||
5943 !isa<ConstantSDNode>(V->getOperand(1)) ||
5944 !ISD::isNormalLoad(V->getOperand(0).getNode()))
5947 // Check the chain and pointer.
5948 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
5949 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
5951 // The store should be chained directly to the load or be an operand of a
5953 if (LD == Chain.getNode())
5955 else if (Chain->getOpcode() != ISD::TokenFactor)
5956 return Result; // Fail.
5959 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
5960 if (Chain->getOperand(i).getNode() == LD) {
5964 if (!isOk) return Result;
5967 // This only handles simple types.
5968 if (V.getValueType() != MVT::i16 &&
5969 V.getValueType() != MVT::i32 &&
5970 V.getValueType() != MVT::i64)
5973 // Check the constant mask. Invert it so that the bits being masked out are
5974 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
5975 // follow the sign bit for uniformity.
5976 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
5977 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
5978 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
5979 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
5980 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
5981 if (NotMaskLZ == 64) return Result; // All zero mask.
5983 // See if we have a continuous run of bits. If so, we have 0*1+0*
5984 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
5987 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
5988 if (V.getValueType() != MVT::i64 && NotMaskLZ)
5989 NotMaskLZ -= 64-V.getValueSizeInBits();
5991 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
5992 switch (MaskedBytes) {
5996 default: return Result; // All one mask, or 5-byte mask.
5999 // Verify that the first bit starts at a multiple of mask so that the access
6000 // is aligned the same as the access width.
6001 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
6003 Result.first = MaskedBytes;
6004 Result.second = NotMaskTZ/8;
6009 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
6010 /// provides a value as specified by MaskInfo. If so, replace the specified
6011 /// store with a narrower store of truncated IVal.
6013 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
6014 SDValue IVal, StoreSDNode *St,
6016 unsigned NumBytes = MaskInfo.first;
6017 unsigned ByteShift = MaskInfo.second;
6018 SelectionDAG &DAG = DC->getDAG();
6020 // Check to see if IVal is all zeros in the part being masked in by the 'or'
6021 // that uses this. If not, this is not a replacement.
6022 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
6023 ByteShift*8, (ByteShift+NumBytes)*8);
6024 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
6026 // Check that it is legal on the target to do this. It is legal if the new
6027 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
6029 MVT VT = MVT::getIntegerVT(NumBytes*8);
6030 if (!DC->isTypeLegal(VT))
6033 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
6034 // shifted by ByteShift and truncated down to NumBytes.
6036 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
6037 DAG.getConstant(ByteShift*8,
6038 DC->getShiftAmountTy(IVal.getValueType())));
6040 // Figure out the offset for the store and the alignment of the access.
6042 unsigned NewAlign = St->getAlignment();
6044 if (DAG.getTargetLoweringInfo().isLittleEndian())
6045 StOffset = ByteShift;
6047 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
6049 SDValue Ptr = St->getBasePtr();
6051 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
6052 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
6053 NewAlign = MinAlign(NewAlign, StOffset);
6056 // Truncate down to the new size.
6057 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
6060 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
6061 St->getPointerInfo().getWithOffset(StOffset),
6062 false, false, NewAlign).getNode();
6066 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
6067 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
6068 /// of the loaded bits, try narrowing the load and store if it would end up
6069 /// being a win for performance or code size.
6070 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
6071 StoreSDNode *ST = cast<StoreSDNode>(N);
6072 if (ST->isVolatile())
6075 SDValue Chain = ST->getChain();
6076 SDValue Value = ST->getValue();
6077 SDValue Ptr = ST->getBasePtr();
6078 EVT VT = Value.getValueType();
6080 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
6083 unsigned Opc = Value.getOpcode();
6085 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
6086 // is a byte mask indicating a consecutive number of bytes, check to see if
6087 // Y is known to provide just those bytes. If so, we try to replace the
6088 // load + replace + store sequence with a single (narrower) store, which makes
6090 if (Opc == ISD::OR) {
6091 std::pair<unsigned, unsigned> MaskedLoad;
6092 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
6093 if (MaskedLoad.first)
6094 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6095 Value.getOperand(1), ST,this))
6096 return SDValue(NewST, 0);
6098 // Or is commutative, so try swapping X and Y.
6099 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
6100 if (MaskedLoad.first)
6101 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6102 Value.getOperand(0), ST,this))
6103 return SDValue(NewST, 0);
6106 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
6107 Value.getOperand(1).getOpcode() != ISD::Constant)
6110 SDValue N0 = Value.getOperand(0);
6111 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6112 Chain == SDValue(N0.getNode(), 1)) {
6113 LoadSDNode *LD = cast<LoadSDNode>(N0);
6114 if (LD->getBasePtr() != Ptr ||
6115 LD->getPointerInfo().getAddrSpace() !=
6116 ST->getPointerInfo().getAddrSpace())
6119 // Find the type to narrow it the load / op / store to.
6120 SDValue N1 = Value.getOperand(1);
6121 unsigned BitWidth = N1.getValueSizeInBits();
6122 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
6123 if (Opc == ISD::AND)
6124 Imm ^= APInt::getAllOnesValue(BitWidth);
6125 if (Imm == 0 || Imm.isAllOnesValue())
6127 unsigned ShAmt = Imm.countTrailingZeros();
6128 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
6129 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
6130 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6131 while (NewBW < BitWidth &&
6132 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
6133 TLI.isNarrowingProfitable(VT, NewVT))) {
6134 NewBW = NextPowerOf2(NewBW);
6135 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6137 if (NewBW >= BitWidth)
6140 // If the lsb changed does not start at the type bitwidth boundary,
6141 // start at the previous one.
6143 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
6144 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
6145 if ((Imm & Mask) == Imm) {
6146 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
6147 if (Opc == ISD::AND)
6148 NewImm ^= APInt::getAllOnesValue(NewBW);
6149 uint64_t PtrOff = ShAmt / 8;
6150 // For big endian targets, we need to adjust the offset to the pointer to
6151 // load the correct bytes.
6152 if (TLI.isBigEndian())
6153 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
6155 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
6156 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
6157 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy))
6160 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
6161 Ptr.getValueType(), Ptr,
6162 DAG.getConstant(PtrOff, Ptr.getValueType()));
6163 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
6164 LD->getChain(), NewPtr,
6165 LD->getPointerInfo().getWithOffset(PtrOff),
6166 LD->isVolatile(), LD->isNonTemporal(),
6168 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
6169 DAG.getConstant(NewImm, NewVT));
6170 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
6172 ST->getPointerInfo().getWithOffset(PtrOff),
6173 false, false, NewAlign);
6175 AddToWorkList(NewPtr.getNode());
6176 AddToWorkList(NewLD.getNode());
6177 AddToWorkList(NewVal.getNode());
6178 WorkListRemover DeadNodes(*this);
6179 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
6189 /// TransformFPLoadStorePair - For a given floating point load / store pair,
6190 /// if the load value isn't used by any other operations, then consider
6191 /// transforming the pair to integer load / store operations if the target
6192 /// deems the transformation profitable.
6193 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
6194 StoreSDNode *ST = cast<StoreSDNode>(N);
6195 SDValue Chain = ST->getChain();
6196 SDValue Value = ST->getValue();
6197 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
6198 Value.hasOneUse() &&
6199 Chain == SDValue(Value.getNode(), 1)) {
6200 LoadSDNode *LD = cast<LoadSDNode>(Value);
6201 EVT VT = LD->getMemoryVT();
6202 if (!VT.isFloatingPoint() ||
6203 VT != ST->getMemoryVT() ||
6204 LD->isNonTemporal() ||
6205 ST->isNonTemporal() ||
6206 LD->getPointerInfo().getAddrSpace() != 0 ||
6207 ST->getPointerInfo().getAddrSpace() != 0)
6210 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
6211 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
6212 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
6213 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
6214 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
6217 unsigned LDAlign = LD->getAlignment();
6218 unsigned STAlign = ST->getAlignment();
6219 const Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
6220 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy);
6221 if (LDAlign < ABIAlign || STAlign < ABIAlign)
6224 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(),
6225 LD->getChain(), LD->getBasePtr(),
6226 LD->getPointerInfo(),
6227 false, false, LDAlign);
6229 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(),
6230 NewLD, ST->getBasePtr(),
6231 ST->getPointerInfo(),
6232 false, false, STAlign);
6234 AddToWorkList(NewLD.getNode());
6235 AddToWorkList(NewST.getNode());
6236 WorkListRemover DeadNodes(*this);
6237 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1),
6246 SDValue DAGCombiner::visitSTORE(SDNode *N) {
6247 StoreSDNode *ST = cast<StoreSDNode>(N);
6248 SDValue Chain = ST->getChain();
6249 SDValue Value = ST->getValue();
6250 SDValue Ptr = ST->getBasePtr();
6252 // If this is a store of a bit convert, store the input value if the
6253 // resultant store does not need a higher alignment than the original.
6254 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
6255 ST->isUnindexed()) {
6256 unsigned OrigAlign = ST->getAlignment();
6257 EVT SVT = Value.getOperand(0).getValueType();
6258 unsigned Align = TLI.getTargetData()->
6259 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
6260 if (Align <= OrigAlign &&
6261 ((!LegalOperations && !ST->isVolatile()) ||
6262 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
6263 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6264 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6265 ST->isNonTemporal(), OrigAlign);
6268 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
6269 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
6270 // NOTE: If the original store is volatile, this transform must not increase
6271 // the number of stores. For example, on x86-32 an f64 can be stored in one
6272 // processor operation but an i64 (which is not legal) requires two. So the
6273 // transform should not be done in this case.
6274 if (Value.getOpcode() != ISD::TargetConstantFP) {
6276 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
6277 default: llvm_unreachable("Unknown FP type");
6278 case MVT::f80: // We don't do this for these yet.
6283 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
6284 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6285 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
6286 bitcastToAPInt().getZExtValue(), MVT::i32);
6287 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6288 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6289 ST->isNonTemporal(), ST->getAlignment());
6293 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
6294 !ST->isVolatile()) ||
6295 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
6296 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
6297 getZExtValue(), MVT::i64);
6298 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6299 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6300 ST->isNonTemporal(), ST->getAlignment());
6301 } else if (!ST->isVolatile() &&
6302 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6303 // Many FP stores are not made apparent until after legalize, e.g. for
6304 // argument passing. Since this is so common, custom legalize the
6305 // 64-bit integer store into two 32-bit stores.
6306 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
6307 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
6308 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
6309 if (TLI.isBigEndian()) std::swap(Lo, Hi);
6311 unsigned Alignment = ST->getAlignment();
6312 bool isVolatile = ST->isVolatile();
6313 bool isNonTemporal = ST->isNonTemporal();
6315 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
6316 Ptr, ST->getPointerInfo(),
6317 isVolatile, isNonTemporal,
6318 ST->getAlignment());
6319 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
6320 DAG.getConstant(4, Ptr.getValueType()));
6321 Alignment = MinAlign(Alignment, 4U);
6322 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
6323 Ptr, ST->getPointerInfo().getWithOffset(4),
6324 isVolatile, isNonTemporal,
6326 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
6335 // Try to infer better alignment information than the store already has.
6336 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
6337 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
6338 if (Align > ST->getAlignment())
6339 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
6340 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6341 ST->isVolatile(), ST->isNonTemporal(), Align);
6345 // Try transforming a pair floating point load / store ops to integer
6346 // load / store ops.
6347 SDValue NewST = TransformFPLoadStorePair(N);
6348 if (NewST.getNode())
6352 // Walk up chain skipping non-aliasing memory nodes.
6353 SDValue BetterChain = FindBetterChain(N, Chain);
6355 // If there is a better chain.
6356 if (Chain != BetterChain) {
6359 // Replace the chain to avoid dependency.
6360 if (ST->isTruncatingStore()) {
6361 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6362 ST->getPointerInfo(),
6363 ST->getMemoryVT(), ST->isVolatile(),
6364 ST->isNonTemporal(), ST->getAlignment());
6366 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6367 ST->getPointerInfo(),
6368 ST->isVolatile(), ST->isNonTemporal(),
6369 ST->getAlignment());
6372 // Create token to keep both nodes around.
6373 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6374 MVT::Other, Chain, ReplStore);
6376 // Make sure the new and old chains are cleaned up.
6377 AddToWorkList(Token.getNode());
6379 // Don't add users to work list.
6380 return CombineTo(N, Token, false);
6384 // Try transforming N to an indexed store.
6385 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6386 return SDValue(N, 0);
6388 // FIXME: is there such a thing as a truncating indexed store?
6389 if (ST->isTruncatingStore() && ST->isUnindexed() &&
6390 Value.getValueType().isInteger()) {
6391 // See if we can simplify the input to this truncstore with knowledge that
6392 // only the low bits are being used. For example:
6393 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
6395 GetDemandedBits(Value,
6396 APInt::getLowBitsSet(Value.getValueSizeInBits(),
6397 ST->getMemoryVT().getSizeInBits()));
6398 AddToWorkList(Value.getNode());
6399 if (Shorter.getNode())
6400 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
6401 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6402 ST->isVolatile(), ST->isNonTemporal(),
6403 ST->getAlignment());
6405 // Otherwise, see if we can simplify the operation with
6406 // SimplifyDemandedBits, which only works if the value has a single use.
6407 if (SimplifyDemandedBits(Value,
6408 APInt::getLowBitsSet(
6409 Value.getValueType().getScalarType().getSizeInBits(),
6410 ST->getMemoryVT().getScalarType().getSizeInBits())))
6411 return SDValue(N, 0);
6414 // If this is a load followed by a store to the same location, then the store
6416 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
6417 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
6418 ST->isUnindexed() && !ST->isVolatile() &&
6419 // There can't be any side effects between the load and store, such as
6421 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
6422 // The store is dead, remove it.
6427 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
6428 // truncating store. We can do this even if this is already a truncstore.
6429 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
6430 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
6431 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
6432 ST->getMemoryVT())) {
6433 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6434 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6435 ST->isVolatile(), ST->isNonTemporal(),
6436 ST->getAlignment());
6439 return ReduceLoadOpStoreWidth(N);
6442 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
6443 SDValue InVec = N->getOperand(0);
6444 SDValue InVal = N->getOperand(1);
6445 SDValue EltNo = N->getOperand(2);
6447 // If the inserted element is an UNDEF, just use the input vector.
6448 if (InVal.getOpcode() == ISD::UNDEF)
6451 EVT VT = InVec.getValueType();
6453 // If we can't generate a legal BUILD_VECTOR, exit
6454 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
6457 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
6458 // vector with the inserted element.
6459 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
6460 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6461 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
6462 InVec.getNode()->op_end());
6463 if (Elt < Ops.size())
6465 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6466 VT, &Ops[0], Ops.size());
6468 // If the invec is an UNDEF and if EltNo is a constant, create a new
6469 // BUILD_VECTOR with undef elements and the inserted element.
6470 if (InVec.getOpcode() == ISD::UNDEF &&
6471 isa<ConstantSDNode>(EltNo)) {
6472 EVT EltVT = VT.getVectorElementType();
6473 unsigned NElts = VT.getVectorNumElements();
6474 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT));
6476 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6477 if (Elt < Ops.size())
6479 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6480 VT, &Ops[0], Ops.size());
6485 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
6486 // (vextract (scalar_to_vector val, 0) -> val
6487 SDValue InVec = N->getOperand(0);
6489 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
6490 // Check if the result type doesn't match the inserted element type. A
6491 // SCALAR_TO_VECTOR may truncate the inserted element and the
6492 // EXTRACT_VECTOR_ELT may widen the extracted vector.
6493 SDValue InOp = InVec.getOperand(0);
6494 EVT NVT = N->getValueType(0);
6495 if (InOp.getValueType() != NVT) {
6496 assert(InOp.getValueType().isInteger() && NVT.isInteger());
6497 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
6502 // Perform only after legalization to ensure build_vector / vector_shuffle
6503 // optimizations have already been done.
6504 if (!LegalOperations) return SDValue();
6506 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
6507 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
6508 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
6509 SDValue EltNo = N->getOperand(1);
6511 if (isa<ConstantSDNode>(EltNo)) {
6512 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6513 bool NewLoad = false;
6514 bool BCNumEltsChanged = false;
6515 EVT VT = InVec.getValueType();
6516 EVT ExtVT = VT.getVectorElementType();
6519 if (InVec.getOpcode() == ISD::BITCAST) {
6520 EVT BCVT = InVec.getOperand(0).getValueType();
6521 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
6523 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
6524 BCNumEltsChanged = true;
6525 InVec = InVec.getOperand(0);
6526 ExtVT = BCVT.getVectorElementType();
6530 LoadSDNode *LN0 = NULL;
6531 const ShuffleVectorSDNode *SVN = NULL;
6532 if (ISD::isNormalLoad(InVec.getNode())) {
6533 LN0 = cast<LoadSDNode>(InVec);
6534 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6535 InVec.getOperand(0).getValueType() == ExtVT &&
6536 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
6537 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
6538 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
6539 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
6541 // (load $addr+1*size)
6543 // If the bit convert changed the number of elements, it is unsafe
6544 // to examine the mask.
6545 if (BCNumEltsChanged)
6548 // Select the input vector, guarding against out of range extract vector.
6549 unsigned NumElems = VT.getVectorNumElements();
6550 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
6551 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
6553 if (InVec.getOpcode() == ISD::BITCAST)
6554 InVec = InVec.getOperand(0);
6555 if (ISD::isNormalLoad(InVec.getNode())) {
6556 LN0 = cast<LoadSDNode>(InVec);
6557 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
6561 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile())
6564 // If Idx was -1 above, Elt is going to be -1, so just return undef.
6566 return DAG.getUNDEF(LN0->getBasePtr().getValueType());
6568 unsigned Align = LN0->getAlignment();
6570 // Check the resultant load doesn't need a higher alignment than the
6574 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
6576 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
6582 SDValue NewPtr = LN0->getBasePtr();
6583 unsigned PtrOff = 0;
6586 PtrOff = LVT.getSizeInBits() * Elt / 8;
6587 EVT PtrType = NewPtr.getValueType();
6588 if (TLI.isBigEndian())
6589 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
6590 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
6591 DAG.getConstant(PtrOff, PtrType));
6594 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
6595 LN0->getPointerInfo().getWithOffset(PtrOff),
6596 LN0->isVolatile(), LN0->isNonTemporal(), Align);
6602 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
6603 unsigned NumInScalars = N->getNumOperands();
6604 EVT VT = N->getValueType(0);
6606 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
6607 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
6608 // at most two distinct vectors, turn this into a shuffle node.
6609 SDValue VecIn1, VecIn2;
6610 for (unsigned i = 0; i != NumInScalars; ++i) {
6611 // Ignore undef inputs.
6612 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6614 // If this input is something other than a EXTRACT_VECTOR_ELT with a
6615 // constant index, bail out.
6616 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6617 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
6618 VecIn1 = VecIn2 = SDValue(0, 0);
6622 // If the input vector type disagrees with the result of the build_vector,
6623 // we can't make a shuffle.
6624 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
6625 if (ExtractedFromVec.getValueType() != VT) {
6626 VecIn1 = VecIn2 = SDValue(0, 0);
6630 // Otherwise, remember this. We allow up to two distinct input vectors.
6631 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
6634 if (VecIn1.getNode() == 0) {
6635 VecIn1 = ExtractedFromVec;
6636 } else if (VecIn2.getNode() == 0) {
6637 VecIn2 = ExtractedFromVec;
6640 VecIn1 = VecIn2 = SDValue(0, 0);
6645 // If everything is good, we can make a shuffle operation.
6646 if (VecIn1.getNode()) {
6647 SmallVector<int, 8> Mask;
6648 for (unsigned i = 0; i != NumInScalars; ++i) {
6649 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
6654 // If extracting from the first vector, just use the index directly.
6655 SDValue Extract = N->getOperand(i);
6656 SDValue ExtVal = Extract.getOperand(1);
6657 if (Extract.getOperand(0) == VecIn1) {
6658 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
6659 if (ExtIndex > VT.getVectorNumElements())
6662 Mask.push_back(ExtIndex);
6666 // Otherwise, use InIdx + VecSize
6667 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
6668 Mask.push_back(Idx+NumInScalars);
6671 // Add count and size info.
6672 if (!isTypeLegal(VT))
6675 // Return the new VECTOR_SHUFFLE node.
6678 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6679 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
6685 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
6686 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
6687 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
6688 // inputs come from at most two distinct vectors, turn this into a shuffle
6691 // If we only have one input vector, we don't need to do any concatenation.
6692 if (N->getNumOperands() == 1)
6693 return N->getOperand(0);
6698 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
6699 EVT VT = N->getValueType(0);
6700 unsigned NumElts = VT.getVectorNumElements();
6702 SDValue N0 = N->getOperand(0);
6704 assert(N0.getValueType().getVectorNumElements() == NumElts &&
6705 "Vector shuffle must be normalized in DAG");
6707 // FIXME: implement canonicalizations from DAG.getVectorShuffle()
6709 // If it is a splat, check if the argument vector is another splat or a
6710 // build_vector with all scalar elements the same.
6711 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
6712 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
6713 SDNode *V = N0.getNode();
6715 // If this is a bit convert that changes the element type of the vector but
6716 // not the number of vector elements, look through it. Be careful not to
6717 // look though conversions that change things like v4f32 to v2f64.
6718 if (V->getOpcode() == ISD::BITCAST) {
6719 SDValue ConvInput = V->getOperand(0);
6720 if (ConvInput.getValueType().isVector() &&
6721 ConvInput.getValueType().getVectorNumElements() == NumElts)
6722 V = ConvInput.getNode();
6725 if (V->getOpcode() == ISD::BUILD_VECTOR) {
6726 assert(V->getNumOperands() == NumElts &&
6727 "BUILD_VECTOR has wrong number of operands");
6729 bool AllSame = true;
6730 for (unsigned i = 0; i != NumElts; ++i) {
6731 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
6732 Base = V->getOperand(i);
6736 // Splat of <u, u, u, u>, return <u, u, u, u>
6737 if (!Base.getNode())
6739 for (unsigned i = 0; i != NumElts; ++i) {
6740 if (V->getOperand(i) != Base) {
6745 // Splat of <x, x, x, x>, return <x, x, x, x>
6753 SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
6754 if (!TLI.getShouldFoldAtomicFences())
6757 SDValue atomic = N->getOperand(0);
6758 switch (atomic.getOpcode()) {
6759 case ISD::ATOMIC_CMP_SWAP:
6760 case ISD::ATOMIC_SWAP:
6761 case ISD::ATOMIC_LOAD_ADD:
6762 case ISD::ATOMIC_LOAD_SUB:
6763 case ISD::ATOMIC_LOAD_AND:
6764 case ISD::ATOMIC_LOAD_OR:
6765 case ISD::ATOMIC_LOAD_XOR:
6766 case ISD::ATOMIC_LOAD_NAND:
6767 case ISD::ATOMIC_LOAD_MIN:
6768 case ISD::ATOMIC_LOAD_MAX:
6769 case ISD::ATOMIC_LOAD_UMIN:
6770 case ISD::ATOMIC_LOAD_UMAX:
6776 SDValue fence = atomic.getOperand(0);
6777 if (fence.getOpcode() != ISD::MEMBARRIER)
6780 switch (atomic.getOpcode()) {
6781 case ISD::ATOMIC_CMP_SWAP:
6782 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
6783 fence.getOperand(0),
6784 atomic.getOperand(1), atomic.getOperand(2),
6785 atomic.getOperand(3)), atomic.getResNo());
6786 case ISD::ATOMIC_SWAP:
6787 case ISD::ATOMIC_LOAD_ADD:
6788 case ISD::ATOMIC_LOAD_SUB:
6789 case ISD::ATOMIC_LOAD_AND:
6790 case ISD::ATOMIC_LOAD_OR:
6791 case ISD::ATOMIC_LOAD_XOR:
6792 case ISD::ATOMIC_LOAD_NAND:
6793 case ISD::ATOMIC_LOAD_MIN:
6794 case ISD::ATOMIC_LOAD_MAX:
6795 case ISD::ATOMIC_LOAD_UMIN:
6796 case ISD::ATOMIC_LOAD_UMAX:
6797 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
6798 fence.getOperand(0),
6799 atomic.getOperand(1), atomic.getOperand(2)),
6806 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
6807 /// an AND to a vector_shuffle with the destination vector and a zero vector.
6808 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
6809 /// vector_shuffle V, Zero, <0, 4, 2, 4>
6810 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
6811 EVT VT = N->getValueType(0);
6812 DebugLoc dl = N->getDebugLoc();
6813 SDValue LHS = N->getOperand(0);
6814 SDValue RHS = N->getOperand(1);
6815 if (N->getOpcode() == ISD::AND) {
6816 if (RHS.getOpcode() == ISD::BITCAST)
6817 RHS = RHS.getOperand(0);
6818 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
6819 SmallVector<int, 8> Indices;
6820 unsigned NumElts = RHS.getNumOperands();
6821 for (unsigned i = 0; i != NumElts; ++i) {
6822 SDValue Elt = RHS.getOperand(i);
6823 if (!isa<ConstantSDNode>(Elt))
6825 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
6826 Indices.push_back(i);
6827 else if (cast<ConstantSDNode>(Elt)->isNullValue())
6828 Indices.push_back(NumElts);
6833 // Let's see if the target supports this vector_shuffle.
6834 EVT RVT = RHS.getValueType();
6835 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
6838 // Return the new VECTOR_SHUFFLE node.
6839 EVT EltVT = RVT.getVectorElementType();
6840 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
6841 DAG.getConstant(0, EltVT));
6842 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6843 RVT, &ZeroOps[0], ZeroOps.size());
6844 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
6845 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
6846 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
6853 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
6854 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
6855 // After legalize, the target may be depending on adds and other
6856 // binary ops to provide legal ways to construct constants or other
6857 // things. Simplifying them may result in a loss of legality.
6858 if (LegalOperations) return SDValue();
6860 assert(N->getValueType(0).isVector() &&
6861 "SimplifyVBinOp only works on vectors!");
6863 SDValue LHS = N->getOperand(0);
6864 SDValue RHS = N->getOperand(1);
6865 SDValue Shuffle = XformToShuffleWithZero(N);
6866 if (Shuffle.getNode()) return Shuffle;
6868 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
6870 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
6871 RHS.getOpcode() == ISD::BUILD_VECTOR) {
6872 SmallVector<SDValue, 8> Ops;
6873 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
6874 SDValue LHSOp = LHS.getOperand(i);
6875 SDValue RHSOp = RHS.getOperand(i);
6876 // If these two elements can't be folded, bail out.
6877 if ((LHSOp.getOpcode() != ISD::UNDEF &&
6878 LHSOp.getOpcode() != ISD::Constant &&
6879 LHSOp.getOpcode() != ISD::ConstantFP) ||
6880 (RHSOp.getOpcode() != ISD::UNDEF &&
6881 RHSOp.getOpcode() != ISD::Constant &&
6882 RHSOp.getOpcode() != ISD::ConstantFP))
6885 // Can't fold divide by zero.
6886 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
6887 N->getOpcode() == ISD::FDIV) {
6888 if ((RHSOp.getOpcode() == ISD::Constant &&
6889 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
6890 (RHSOp.getOpcode() == ISD::ConstantFP &&
6891 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
6895 EVT VT = LHSOp.getValueType();
6896 assert(RHSOp.getValueType() == VT &&
6897 "SimplifyVBinOp with different BUILD_VECTOR element types");
6898 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT,
6900 if (FoldOp.getOpcode() != ISD::UNDEF &&
6901 FoldOp.getOpcode() != ISD::Constant &&
6902 FoldOp.getOpcode() != ISD::ConstantFP)
6904 Ops.push_back(FoldOp);
6905 AddToWorkList(FoldOp.getNode());
6908 if (Ops.size() == LHS.getNumOperands())
6909 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6910 LHS.getValueType(), &Ops[0], Ops.size());
6916 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
6917 SDValue N1, SDValue N2){
6918 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
6920 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
6921 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6923 // If we got a simplified select_cc node back from SimplifySelectCC, then
6924 // break it down into a new SETCC node, and a new SELECT node, and then return
6925 // the SELECT node, since we were called with a SELECT node.
6926 if (SCC.getNode()) {
6927 // Check to see if we got a select_cc back (to turn into setcc/select).
6928 // Otherwise, just return whatever node we got back, like fabs.
6929 if (SCC.getOpcode() == ISD::SELECT_CC) {
6930 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
6932 SCC.getOperand(0), SCC.getOperand(1),
6934 AddToWorkList(SETCC.getNode());
6935 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
6936 SCC.getOperand(2), SCC.getOperand(3), SETCC);
6944 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
6945 /// are the two values being selected between, see if we can simplify the
6946 /// select. Callers of this should assume that TheSelect is deleted if this
6947 /// returns true. As such, they should return the appropriate thing (e.g. the
6948 /// node) back to the top-level of the DAG combiner loop to avoid it being
6950 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
6953 // Cannot simplify select with vector condition
6954 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
6956 // If this is a select from two identical things, try to pull the operation
6957 // through the select.
6958 if (LHS.getOpcode() != RHS.getOpcode() ||
6959 !LHS.hasOneUse() || !RHS.hasOneUse())
6962 // If this is a load and the token chain is identical, replace the select
6963 // of two loads with a load through a select of the address to load from.
6964 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
6965 // constants have been dropped into the constant pool.
6966 if (LHS.getOpcode() == ISD::LOAD) {
6967 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
6968 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
6970 // Token chains must be identical.
6971 if (LHS.getOperand(0) != RHS.getOperand(0) ||
6972 // Do not let this transformation reduce the number of volatile loads.
6973 LLD->isVolatile() || RLD->isVolatile() ||
6974 // If this is an EXTLOAD, the VT's must match.
6975 LLD->getMemoryVT() != RLD->getMemoryVT() ||
6976 // If this is an EXTLOAD, the kind of extension must match.
6977 (LLD->getExtensionType() != RLD->getExtensionType() &&
6978 // The only exception is if one of the extensions is anyext.
6979 LLD->getExtensionType() != ISD::EXTLOAD &&
6980 RLD->getExtensionType() != ISD::EXTLOAD) ||
6981 // FIXME: this discards src value information. This is
6982 // over-conservative. It would be beneficial to be able to remember
6983 // both potential memory locations. Since we are discarding
6984 // src value info, don't do the transformation if the memory
6985 // locations are not in the default address space.
6986 LLD->getPointerInfo().getAddrSpace() != 0 ||
6987 RLD->getPointerInfo().getAddrSpace() != 0)
6990 // Check that the select condition doesn't reach either load. If so,
6991 // folding this will induce a cycle into the DAG. If not, this is safe to
6992 // xform, so create a select of the addresses.
6994 if (TheSelect->getOpcode() == ISD::SELECT) {
6995 SDNode *CondNode = TheSelect->getOperand(0).getNode();
6996 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
6997 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
6999 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
7000 LLD->getBasePtr().getValueType(),
7001 TheSelect->getOperand(0), LLD->getBasePtr(),
7003 } else { // Otherwise SELECT_CC
7004 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
7005 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
7007 if ((LLD->hasAnyUseOfValue(1) &&
7008 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
7009 (LLD->hasAnyUseOfValue(1) &&
7010 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))))
7013 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
7014 LLD->getBasePtr().getValueType(),
7015 TheSelect->getOperand(0),
7016 TheSelect->getOperand(1),
7017 LLD->getBasePtr(), RLD->getBasePtr(),
7018 TheSelect->getOperand(4));
7022 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
7023 Load = DAG.getLoad(TheSelect->getValueType(0),
7024 TheSelect->getDebugLoc(),
7025 // FIXME: Discards pointer info.
7026 LLD->getChain(), Addr, MachinePointerInfo(),
7027 LLD->isVolatile(), LLD->isNonTemporal(),
7028 LLD->getAlignment());
7030 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
7031 RLD->getExtensionType() : LLD->getExtensionType(),
7032 TheSelect->getDebugLoc(),
7033 TheSelect->getValueType(0),
7034 // FIXME: Discards pointer info.
7035 LLD->getChain(), Addr, MachinePointerInfo(),
7036 LLD->getMemoryVT(), LLD->isVolatile(),
7037 LLD->isNonTemporal(), LLD->getAlignment());
7040 // Users of the select now use the result of the load.
7041 CombineTo(TheSelect, Load);
7043 // Users of the old loads now use the new load's chain. We know the
7044 // old-load value is dead now.
7045 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
7046 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
7053 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
7054 /// where 'cond' is the comparison specified by CC.
7055 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
7056 SDValue N2, SDValue N3,
7057 ISD::CondCode CC, bool NotExtCompare) {
7058 // (x ? y : y) -> y.
7059 if (N2 == N3) return N2;
7061 EVT VT = N2.getValueType();
7062 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
7063 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
7064 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
7066 // Determine if the condition we're dealing with is constant
7067 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
7068 N0, N1, CC, DL, false);
7069 if (SCC.getNode()) AddToWorkList(SCC.getNode());
7070 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
7072 // fold select_cc true, x, y -> x
7073 if (SCCC && !SCCC->isNullValue())
7075 // fold select_cc false, x, y -> y
7076 if (SCCC && SCCC->isNullValue())
7079 // Check to see if we can simplify the select into an fabs node
7080 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
7081 // Allow either -0.0 or 0.0
7082 if (CFP->getValueAPF().isZero()) {
7083 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
7084 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
7085 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
7086 N2 == N3.getOperand(0))
7087 return DAG.getNode(ISD::FABS, DL, VT, N0);
7089 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
7090 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
7091 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
7092 N2.getOperand(0) == N3)
7093 return DAG.getNode(ISD::FABS, DL, VT, N3);
7097 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
7098 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
7099 // in it. This is a win when the constant is not otherwise available because
7100 // it replaces two constant pool loads with one. We only do this if the FP
7101 // type is known to be legal, because if it isn't, then we are before legalize
7102 // types an we want the other legalization to happen first (e.g. to avoid
7103 // messing with soft float) and if the ConstantFP is not legal, because if
7104 // it is legal, we may not need to store the FP constant in a constant pool.
7105 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
7106 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
7107 if (TLI.isTypeLegal(N2.getValueType()) &&
7108 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
7109 TargetLowering::Legal) &&
7110 // If both constants have multiple uses, then we won't need to do an
7111 // extra load, they are likely around in registers for other users.
7112 (TV->hasOneUse() || FV->hasOneUse())) {
7113 Constant *Elts[] = {
7114 const_cast<ConstantFP*>(FV->getConstantFPValue()),
7115 const_cast<ConstantFP*>(TV->getConstantFPValue())
7117 const Type *FPTy = Elts[0]->getType();
7118 const TargetData &TD = *TLI.getTargetData();
7120 // Create a ConstantArray of the two constants.
7121 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2);
7122 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
7123 TD.getPrefTypeAlignment(FPTy));
7124 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
7126 // Get the offsets to the 0 and 1 element of the array so that we can
7127 // select between them.
7128 SDValue Zero = DAG.getIntPtrConstant(0);
7129 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
7130 SDValue One = DAG.getIntPtrConstant(EltSize);
7132 SDValue Cond = DAG.getSetCC(DL,
7133 TLI.getSetCCResultType(N0.getValueType()),
7135 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
7137 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
7139 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
7140 MachinePointerInfo::getConstantPool(), false,
7146 // Check to see if we can perform the "gzip trick", transforming
7147 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
7148 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
7149 N0.getValueType().isInteger() &&
7150 N2.getValueType().isInteger() &&
7151 (N1C->isNullValue() || // (a < 0) ? b : 0
7152 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
7153 EVT XType = N0.getValueType();
7154 EVT AType = N2.getValueType();
7155 if (XType.bitsGE(AType)) {
7156 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
7157 // single-bit constant.
7158 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
7159 unsigned ShCtV = N2C->getAPIntValue().logBase2();
7160 ShCtV = XType.getSizeInBits()-ShCtV-1;
7161 SDValue ShCt = DAG.getConstant(ShCtV,
7162 getShiftAmountTy(N0.getValueType()));
7163 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
7165 AddToWorkList(Shift.getNode());
7167 if (XType.bitsGT(AType)) {
7168 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
7169 AddToWorkList(Shift.getNode());
7172 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
7175 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
7177 DAG.getConstant(XType.getSizeInBits()-1,
7178 getShiftAmountTy(N0.getValueType())));
7179 AddToWorkList(Shift.getNode());
7181 if (XType.bitsGT(AType)) {
7182 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
7183 AddToWorkList(Shift.getNode());
7186 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
7190 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
7191 // where y is has a single bit set.
7192 // A plaintext description would be, we can turn the SELECT_CC into an AND
7193 // when the condition can be materialized as an all-ones register. Any
7194 // single bit-test can be materialized as an all-ones register with
7195 // shift-left and shift-right-arith.
7196 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
7197 N0->getValueType(0) == VT &&
7198 N1C && N1C->isNullValue() &&
7199 N2C && N2C->isNullValue()) {
7200 SDValue AndLHS = N0->getOperand(0);
7201 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
7202 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
7203 // Shift the tested bit over the sign bit.
7204 APInt AndMask = ConstAndRHS->getAPIntValue();
7206 DAG.getConstant(AndMask.countLeadingZeros(),
7207 getShiftAmountTy(AndLHS.getValueType()));
7208 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
7210 // Now arithmetic right shift it all the way over, so the result is either
7211 // all-ones, or zero.
7213 DAG.getConstant(AndMask.getBitWidth()-1,
7214 getShiftAmountTy(Shl.getValueType()));
7215 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
7217 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
7221 // fold select C, 16, 0 -> shl C, 4
7222 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
7223 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
7225 // If the caller doesn't want us to simplify this into a zext of a compare,
7227 if (NotExtCompare && N2C->getAPIntValue() == 1)
7230 // Get a SetCC of the condition
7231 // FIXME: Should probably make sure that setcc is legal if we ever have a
7232 // target where it isn't.
7234 // cast from setcc result type to select result type
7236 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
7238 if (N2.getValueType().bitsLT(SCC.getValueType()))
7239 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
7241 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
7242 N2.getValueType(), SCC);
7244 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
7245 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
7246 N2.getValueType(), SCC);
7249 AddToWorkList(SCC.getNode());
7250 AddToWorkList(Temp.getNode());
7252 if (N2C->getAPIntValue() == 1)
7255 // shl setcc result by log2 n2c
7256 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
7257 DAG.getConstant(N2C->getAPIntValue().logBase2(),
7258 getShiftAmountTy(Temp.getValueType())));
7261 // Check to see if this is the equivalent of setcc
7262 // FIXME: Turn all of these into setcc if setcc if setcc is legal
7263 // otherwise, go ahead with the folds.
7264 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
7265 EVT XType = N0.getValueType();
7266 if (!LegalOperations ||
7267 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
7268 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
7269 if (Res.getValueType() != VT)
7270 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
7274 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
7275 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
7276 (!LegalOperations ||
7277 TLI.isOperationLegal(ISD::CTLZ, XType))) {
7278 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
7279 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
7280 DAG.getConstant(Log2_32(XType.getSizeInBits()),
7281 getShiftAmountTy(Ctlz.getValueType())));
7283 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
7284 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
7285 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
7286 XType, DAG.getConstant(0, XType), N0);
7287 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
7288 return DAG.getNode(ISD::SRL, DL, XType,
7289 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
7290 DAG.getConstant(XType.getSizeInBits()-1,
7291 getShiftAmountTy(XType)));
7293 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
7294 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
7295 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
7296 DAG.getConstant(XType.getSizeInBits()-1,
7297 getShiftAmountTy(N0.getValueType())));
7298 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
7302 // Check to see if this is an integer abs.
7303 // select_cc setg[te] X, 0, X, -X ->
7304 // select_cc setgt X, -1, X, -X ->
7305 // select_cc setl[te] X, 0, -X, X ->
7306 // select_cc setlt X, 1, -X, X ->
7307 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
7309 ConstantSDNode *SubC = NULL;
7310 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
7311 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
7312 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
7313 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
7314 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
7315 (N1C->isOne() && CC == ISD::SETLT)) &&
7316 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
7317 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
7319 EVT XType = N0.getValueType();
7320 if (SubC && SubC->isNullValue() && XType.isInteger()) {
7321 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
7323 DAG.getConstant(XType.getSizeInBits()-1,
7324 getShiftAmountTy(N0.getValueType())));
7325 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
7327 AddToWorkList(Shift.getNode());
7328 AddToWorkList(Add.getNode());
7329 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
7336 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
7337 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
7338 SDValue N1, ISD::CondCode Cond,
7339 DebugLoc DL, bool foldBooleans) {
7340 TargetLowering::DAGCombinerInfo
7341 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
7342 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
7345 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
7346 /// return a DAG expression to select that will generate the same value by
7347 /// multiplying by a magic number. See:
7348 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
7349 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
7350 std::vector<SDNode*> Built;
7351 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
7353 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
7359 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
7360 /// return a DAG expression to select that will generate the same value by
7361 /// multiplying by a magic number. See:
7362 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
7363 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
7364 std::vector<SDNode*> Built;
7365 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
7367 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
7373 /// FindBaseOffset - Return true if base is a frame index, which is known not
7374 // to alias with anything but itself. Provides base object and offset as
7376 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
7377 const GlobalValue *&GV, void *&CV) {
7378 // Assume it is a primitive operation.
7379 Base = Ptr; Offset = 0; GV = 0; CV = 0;
7381 // If it's an adding a simple constant then integrate the offset.
7382 if (Base.getOpcode() == ISD::ADD) {
7383 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
7384 Base = Base.getOperand(0);
7385 Offset += C->getZExtValue();
7389 // Return the underlying GlobalValue, and update the Offset. Return false
7390 // for GlobalAddressSDNode since the same GlobalAddress may be represented
7391 // by multiple nodes with different offsets.
7392 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
7393 GV = G->getGlobal();
7394 Offset += G->getOffset();
7398 // Return the underlying Constant value, and update the Offset. Return false
7399 // for ConstantSDNodes since the same constant pool entry may be represented
7400 // by multiple nodes with different offsets.
7401 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
7402 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
7403 : (void *)C->getConstVal();
7404 Offset += C->getOffset();
7407 // If it's any of the following then it can't alias with anything but itself.
7408 return isa<FrameIndexSDNode>(Base);
7411 /// isAlias - Return true if there is any possibility that the two addresses
7413 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
7414 const Value *SrcValue1, int SrcValueOffset1,
7415 unsigned SrcValueAlign1,
7416 const MDNode *TBAAInfo1,
7417 SDValue Ptr2, int64_t Size2,
7418 const Value *SrcValue2, int SrcValueOffset2,
7419 unsigned SrcValueAlign2,
7420 const MDNode *TBAAInfo2) const {
7421 // If they are the same then they must be aliases.
7422 if (Ptr1 == Ptr2) return true;
7424 // Gather base node and offset information.
7425 SDValue Base1, Base2;
7426 int64_t Offset1, Offset2;
7427 const GlobalValue *GV1, *GV2;
7429 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
7430 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
7432 // If they have a same base address then check to see if they overlap.
7433 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
7434 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
7436 // It is possible for different frame indices to alias each other, mostly
7437 // when tail call optimization reuses return address slots for arguments.
7438 // To catch this case, look up the actual index of frame indices to compute
7439 // the real alias relationship.
7440 if (isFrameIndex1 && isFrameIndex2) {
7441 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7442 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
7443 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
7444 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
7447 // Otherwise, if we know what the bases are, and they aren't identical, then
7448 // we know they cannot alias.
7449 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
7452 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
7453 // compared to the size and offset of the access, we may be able to prove they
7454 // do not alias. This check is conservative for now to catch cases created by
7455 // splitting vector types.
7456 if ((SrcValueAlign1 == SrcValueAlign2) &&
7457 (SrcValueOffset1 != SrcValueOffset2) &&
7458 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
7459 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
7460 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
7462 // There is no overlap between these relatively aligned accesses of similar
7463 // size, return no alias.
7464 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
7468 if (CombinerGlobalAA) {
7469 // Use alias analysis information.
7470 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
7471 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
7472 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
7473 AliasAnalysis::AliasResult AAResult =
7474 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
7475 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
7476 if (AAResult == AliasAnalysis::NoAlias)
7480 // Otherwise we have to assume they alias.
7484 /// FindAliasInfo - Extracts the relevant alias information from the memory
7485 /// node. Returns true if the operand was a load.
7486 bool DAGCombiner::FindAliasInfo(SDNode *N,
7487 SDValue &Ptr, int64_t &Size,
7488 const Value *&SrcValue,
7489 int &SrcValueOffset,
7490 unsigned &SrcValueAlign,
7491 const MDNode *&TBAAInfo) const {
7492 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7493 Ptr = LD->getBasePtr();
7494 Size = LD->getMemoryVT().getSizeInBits() >> 3;
7495 SrcValue = LD->getSrcValue();
7496 SrcValueOffset = LD->getSrcValueOffset();
7497 SrcValueAlign = LD->getOriginalAlignment();
7498 TBAAInfo = LD->getTBAAInfo();
7500 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7501 Ptr = ST->getBasePtr();
7502 Size = ST->getMemoryVT().getSizeInBits() >> 3;
7503 SrcValue = ST->getSrcValue();
7504 SrcValueOffset = ST->getSrcValueOffset();
7505 SrcValueAlign = ST->getOriginalAlignment();
7506 TBAAInfo = ST->getTBAAInfo();
7508 llvm_unreachable("FindAliasInfo expected a memory operand");
7514 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
7515 /// looking for aliasing nodes and adding them to the Aliases vector.
7516 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
7517 SmallVector<SDValue, 8> &Aliases) {
7518 SmallVector<SDValue, 8> Chains; // List of chains to visit.
7519 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
7521 // Get alias information for node.
7524 const Value *SrcValue;
7526 unsigned SrcValueAlign;
7527 const MDNode *SrcTBAAInfo;
7528 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
7529 SrcValueAlign, SrcTBAAInfo);
7532 Chains.push_back(OriginalChain);
7535 // Look at each chain and determine if it is an alias. If so, add it to the
7536 // aliases list. If not, then continue up the chain looking for the next
7538 while (!Chains.empty()) {
7539 SDValue Chain = Chains.back();
7542 // For TokenFactor nodes, look at each operand and only continue up the
7543 // chain until we find two aliases. If we've seen two aliases, assume we'll
7544 // find more and revert to original chain since the xform is unlikely to be
7547 // FIXME: The depth check could be made to return the last non-aliasing
7548 // chain we found before we hit a tokenfactor rather than the original
7550 if (Depth > 6 || Aliases.size() == 2) {
7552 Aliases.push_back(OriginalChain);
7556 // Don't bother if we've been before.
7557 if (!Visited.insert(Chain.getNode()))
7560 switch (Chain.getOpcode()) {
7561 case ISD::EntryToken:
7562 // Entry token is ideal chain operand, but handled in FindBetterChain.
7567 // Get alias information for Chain.
7570 const Value *OpSrcValue;
7571 int OpSrcValueOffset;
7572 unsigned OpSrcValueAlign;
7573 const MDNode *OpSrcTBAAInfo;
7574 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
7575 OpSrcValue, OpSrcValueOffset,
7579 // If chain is alias then stop here.
7580 if (!(IsLoad && IsOpLoad) &&
7581 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
7583 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
7584 OpSrcValueAlign, OpSrcTBAAInfo)) {
7585 Aliases.push_back(Chain);
7587 // Look further up the chain.
7588 Chains.push_back(Chain.getOperand(0));
7594 case ISD::TokenFactor:
7595 // We have to check each of the operands of the token factor for "small"
7596 // token factors, so we queue them up. Adding the operands to the queue
7597 // (stack) in reverse order maintains the original order and increases the
7598 // likelihood that getNode will find a matching token factor (CSE.)
7599 if (Chain.getNumOperands() > 16) {
7600 Aliases.push_back(Chain);
7603 for (unsigned n = Chain.getNumOperands(); n;)
7604 Chains.push_back(Chain.getOperand(--n));
7609 // For all other instructions we will just have to take what we can get.
7610 Aliases.push_back(Chain);
7616 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
7617 /// for a better chain (aliasing node.)
7618 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
7619 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
7621 // Accumulate all the aliases to this node.
7622 GatherAllAliases(N, OldChain, Aliases);
7624 if (Aliases.size() == 0) {
7625 // If no operands then chain to entry token.
7626 return DAG.getEntryNode();
7627 } else if (Aliases.size() == 1) {
7628 // If a single operand then chain to it. We don't need to revisit it.
7632 // Construct a custom tailored token factor.
7633 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
7634 &Aliases[0], Aliases.size());
7637 // SelectionDAG::Combine - This is the entry point for the file.
7639 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
7640 CodeGenOpt::Level OptLevel) {
7641 /// run - This is the main entry point to this class.
7643 DAGCombiner(*this, AA, OptLevel).Run(Level);