1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/DataLayout.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
40 STATISTIC(NodesCombined , "Number of dag nodes combined");
41 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
42 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
43 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
44 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
48 CombinerAA("combiner-alias-analysis", cl::Hidden,
49 cl::desc("Turn on alias analysis during testing"));
52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
53 cl::desc("Include global information in alias analysis"));
55 //------------------------------ DAGCombiner ---------------------------------//
59 const TargetLowering &TLI;
61 CodeGenOpt::Level OptLevel;
65 // Worklist of all of the nodes that need to be simplified.
67 // This has the semantics that when adding to the worklist,
68 // the item added must be next to be processed. It should
69 // also only appear once. The naive approach to this takes
72 // To reduce the insert/remove time to logarithmic, we use
73 // a set and a vector to maintain our worklist.
75 // The set contains the items on the worklist, but does not
76 // maintain the order they should be visited.
78 // The vector maintains the order nodes should be visited, but may
79 // contain duplicate or removed nodes. When choosing a node to
80 // visit, we pop off the order stack until we find an item that is
81 // also in the contents set. All operations are O(log N).
82 SmallPtrSet<SDNode*, 64> WorkListContents;
83 SmallVector<SDNode*, 64> WorkListOrder;
85 // AA - Used for DAG load/store alias analysis.
88 /// AddUsersToWorkList - When an instruction is simplified, add all users of
89 /// the instruction to the work lists because they might get more simplified
92 void AddUsersToWorkList(SDNode *N) {
93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
98 /// visit - call the node-specific routine that knows how to fold each
99 /// particular type of node.
100 SDValue visit(SDNode *N);
103 /// AddToWorkList - Add to the work list making sure its instance is at the
104 /// back (next to be processed.)
105 void AddToWorkList(SDNode *N) {
106 WorkListContents.insert(N);
107 WorkListOrder.push_back(N);
110 /// removeFromWorkList - remove all instances of N from the worklist.
112 void removeFromWorkList(SDNode *N) {
113 WorkListContents.erase(N);
116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
120 return CombineTo(N, &Res, 1, AddTo);
123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
125 SDValue To[] = { Res0, Res1 };
126 return CombineTo(N, To, 2, AddTo);
129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
133 /// SimplifyDemandedBits - Check the specified integer node value to see if
134 /// it can be simplified or if things it uses can be simplified by bit
135 /// propagation. If so, return true.
136 bool SimplifyDemandedBits(SDValue Op) {
137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
138 APInt Demanded = APInt::getAllOnesValue(BitWidth);
139 return SimplifyDemandedBits(Op, Demanded);
142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
144 bool CombineToPreIndexedLoadStore(SDNode *N);
145 bool CombineToPostIndexedLoadStore(SDNode *N);
147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
151 SDValue PromoteIntBinOp(SDValue Op);
152 SDValue PromoteIntShiftOp(SDValue Op);
153 SDValue PromoteExtend(SDValue Op);
154 bool PromoteLoad(SDValue Op);
156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
158 ISD::NodeType ExtType);
160 /// combine - call the node-specific routine that knows how to fold each
161 /// particular type of node. If that doesn't do anything, try the
162 /// target-specific DAG combines.
163 SDValue combine(SDNode *N);
165 // Visitation implementation - Implement dag node combining for different
166 // node types. The semantics are as follows:
168 // SDValue.getNode() == 0 - No change was made
169 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
170 // otherwise - N should be replaced by the returned Operand.
172 SDValue visitTokenFactor(SDNode *N);
173 SDValue visitMERGE_VALUES(SDNode *N);
174 SDValue visitADD(SDNode *N);
175 SDValue visitSUB(SDNode *N);
176 SDValue visitADDC(SDNode *N);
177 SDValue visitSUBC(SDNode *N);
178 SDValue visitADDE(SDNode *N);
179 SDValue visitSUBE(SDNode *N);
180 SDValue visitMUL(SDNode *N);
181 SDValue visitSDIV(SDNode *N);
182 SDValue visitUDIV(SDNode *N);
183 SDValue visitSREM(SDNode *N);
184 SDValue visitUREM(SDNode *N);
185 SDValue visitMULHU(SDNode *N);
186 SDValue visitMULHS(SDNode *N);
187 SDValue visitSMUL_LOHI(SDNode *N);
188 SDValue visitUMUL_LOHI(SDNode *N);
189 SDValue visitSMULO(SDNode *N);
190 SDValue visitUMULO(SDNode *N);
191 SDValue visitSDIVREM(SDNode *N);
192 SDValue visitUDIVREM(SDNode *N);
193 SDValue visitAND(SDNode *N);
194 SDValue visitOR(SDNode *N);
195 SDValue visitXOR(SDNode *N);
196 SDValue SimplifyVBinOp(SDNode *N);
197 SDValue SimplifyVUnaryOp(SDNode *N);
198 SDValue visitSHL(SDNode *N);
199 SDValue visitSRA(SDNode *N);
200 SDValue visitSRL(SDNode *N);
201 SDValue visitCTLZ(SDNode *N);
202 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
203 SDValue visitCTTZ(SDNode *N);
204 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
205 SDValue visitCTPOP(SDNode *N);
206 SDValue visitSELECT(SDNode *N);
207 SDValue visitSELECT_CC(SDNode *N);
208 SDValue visitSETCC(SDNode *N);
209 SDValue visitSIGN_EXTEND(SDNode *N);
210 SDValue visitZERO_EXTEND(SDNode *N);
211 SDValue visitANY_EXTEND(SDNode *N);
212 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
213 SDValue visitTRUNCATE(SDNode *N);
214 SDValue visitBITCAST(SDNode *N);
215 SDValue visitBUILD_PAIR(SDNode *N);
216 SDValue visitFADD(SDNode *N);
217 SDValue visitFSUB(SDNode *N);
218 SDValue visitFMUL(SDNode *N);
219 SDValue visitFMA(SDNode *N);
220 SDValue visitFDIV(SDNode *N);
221 SDValue visitFREM(SDNode *N);
222 SDValue visitFCOPYSIGN(SDNode *N);
223 SDValue visitSINT_TO_FP(SDNode *N);
224 SDValue visitUINT_TO_FP(SDNode *N);
225 SDValue visitFP_TO_SINT(SDNode *N);
226 SDValue visitFP_TO_UINT(SDNode *N);
227 SDValue visitFP_ROUND(SDNode *N);
228 SDValue visitFP_ROUND_INREG(SDNode *N);
229 SDValue visitFP_EXTEND(SDNode *N);
230 SDValue visitFNEG(SDNode *N);
231 SDValue visitFABS(SDNode *N);
232 SDValue visitFCEIL(SDNode *N);
233 SDValue visitFTRUNC(SDNode *N);
234 SDValue visitFFLOOR(SDNode *N);
235 SDValue visitBRCOND(SDNode *N);
236 SDValue visitBR_CC(SDNode *N);
237 SDValue visitLOAD(SDNode *N);
238 SDValue visitSTORE(SDNode *N);
239 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
240 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
241 SDValue visitBUILD_VECTOR(SDNode *N);
242 SDValue visitCONCAT_VECTORS(SDNode *N);
243 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
244 SDValue visitVECTOR_SHUFFLE(SDNode *N);
245 SDValue visitMEMBARRIER(SDNode *N);
247 SDValue XformToShuffleWithZero(SDNode *N);
248 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
250 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
252 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
253 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
254 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
255 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
256 SDValue N3, ISD::CondCode CC,
257 bool NotExtCompare = false);
258 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
259 DebugLoc DL, bool foldBooleans = true);
260 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
262 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
263 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
264 SDValue BuildSDIV(SDNode *N);
265 SDValue BuildUDIV(SDNode *N);
266 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
267 bool DemandHighBits = true);
268 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
269 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
270 SDValue ReduceLoadWidth(SDNode *N);
271 SDValue ReduceLoadOpStoreWidth(SDNode *N);
272 SDValue TransformFPLoadStorePair(SDNode *N);
274 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
276 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
277 /// looking for aliasing nodes and adding them to the Aliases vector.
278 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
279 SmallVector<SDValue, 8> &Aliases);
281 /// isAlias - Return true if there is any possibility that the two addresses
283 bool isAlias(SDValue Ptr1, int64_t Size1,
284 const Value *SrcValue1, int SrcValueOffset1,
285 unsigned SrcValueAlign1,
286 const MDNode *TBAAInfo1,
287 SDValue Ptr2, int64_t Size2,
288 const Value *SrcValue2, int SrcValueOffset2,
289 unsigned SrcValueAlign2,
290 const MDNode *TBAAInfo2) const;
292 /// FindAliasInfo - Extracts the relevant alias information from the memory
293 /// node. Returns true if the operand was a load.
294 bool FindAliasInfo(SDNode *N,
295 SDValue &Ptr, int64_t &Size,
296 const Value *&SrcValue, int &SrcValueOffset,
297 unsigned &SrcValueAlignment,
298 const MDNode *&TBAAInfo) const;
300 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
301 /// looking for a better chain (aliasing node.)
302 SDValue FindBetterChain(SDNode *N, SDValue Chain);
304 /// Merge consecutive store operations into a wide store.
305 /// This optimization uses wide integers or vectors when possible.
306 /// \return True if some memory operations were changed.
307 bool MergeConsecutiveStores(StoreSDNode *N);
310 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
311 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
312 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
314 /// Run - runs the dag combiner on all nodes in the work list
315 void Run(CombineLevel AtLevel);
317 SelectionDAG &getDAG() const { return DAG; }
319 /// getShiftAmountTy - Returns a type large enough to hold any valid
320 /// shift amount - before type legalization these can be huge.
321 EVT getShiftAmountTy(EVT LHSTy) {
322 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy();
325 /// isTypeLegal - This method returns true if we are running before type
326 /// legalization or if the specified VT is legal.
327 bool isTypeLegal(const EVT &VT) {
328 if (!LegalTypes) return true;
329 return TLI.isTypeLegal(VT);
336 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
337 /// nodes from the worklist.
338 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
341 explicit WorkListRemover(DAGCombiner &dc)
342 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
344 virtual void NodeDeleted(SDNode *N, SDNode *E) {
345 DC.removeFromWorkList(N);
350 //===----------------------------------------------------------------------===//
351 // TargetLowering::DAGCombinerInfo implementation
352 //===----------------------------------------------------------------------===//
354 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
355 ((DAGCombiner*)DC)->AddToWorkList(N);
358 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
359 ((DAGCombiner*)DC)->removeFromWorkList(N);
362 SDValue TargetLowering::DAGCombinerInfo::
363 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
364 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
367 SDValue TargetLowering::DAGCombinerInfo::
368 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
369 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
373 SDValue TargetLowering::DAGCombinerInfo::
374 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
375 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
378 void TargetLowering::DAGCombinerInfo::
379 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
380 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
383 //===----------------------------------------------------------------------===//
385 //===----------------------------------------------------------------------===//
387 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
388 /// specified expression for the same cost as the expression itself, or 2 if we
389 /// can compute the negated form more cheaply than the expression itself.
390 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
391 const TargetLowering &TLI,
392 const TargetOptions *Options,
393 unsigned Depth = 0) {
394 // No compile time optimizations on this type.
395 if (Op.getValueType() == MVT::ppcf128)
398 // fneg is removable even if it has multiple uses.
399 if (Op.getOpcode() == ISD::FNEG) return 2;
401 // Don't allow anything with multiple uses.
402 if (!Op.hasOneUse()) return 0;
404 // Don't recurse exponentially.
405 if (Depth > 6) return 0;
407 switch (Op.getOpcode()) {
408 default: return false;
409 case ISD::ConstantFP:
410 // Don't invert constant FP values after legalize. The negated constant
411 // isn't necessarily legal.
412 return LegalOperations ? 0 : 1;
414 // FIXME: determine better conditions for this xform.
415 if (!Options->UnsafeFPMath) return 0;
417 // After operation legalization, it might not be legal to create new FSUBs.
418 if (LegalOperations &&
419 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
422 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
423 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
426 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
427 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
430 // We can't turn -(A-B) into B-A when we honor signed zeros.
431 if (!Options->UnsafeFPMath) return 0;
433 // fold (fneg (fsub A, B)) -> (fsub B, A)
438 if (Options->HonorSignDependentRoundingFPMath()) return 0;
440 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
441 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
445 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
451 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
456 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
457 /// returns the newly negated expression.
458 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
459 bool LegalOperations, unsigned Depth = 0) {
460 // fneg is removable even if it has multiple uses.
461 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
463 // Don't allow anything with multiple uses.
464 assert(Op.hasOneUse() && "Unknown reuse!");
466 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
467 switch (Op.getOpcode()) {
468 default: llvm_unreachable("Unknown code");
469 case ISD::ConstantFP: {
470 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
472 return DAG.getConstantFP(V, Op.getValueType());
475 // FIXME: determine better conditions for this xform.
476 assert(DAG.getTarget().Options.UnsafeFPMath);
478 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
479 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
480 DAG.getTargetLoweringInfo(),
481 &DAG.getTarget().Options, Depth+1))
482 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
483 GetNegatedExpression(Op.getOperand(0), DAG,
484 LegalOperations, Depth+1),
486 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
487 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
488 GetNegatedExpression(Op.getOperand(1), DAG,
489 LegalOperations, Depth+1),
492 // We can't turn -(A-B) into B-A when we honor signed zeros.
493 assert(DAG.getTarget().Options.UnsafeFPMath);
495 // fold (fneg (fsub 0, B)) -> B
496 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
497 if (N0CFP->getValueAPF().isZero())
498 return Op.getOperand(1);
500 // fold (fneg (fsub A, B)) -> (fsub B, A)
501 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
502 Op.getOperand(1), Op.getOperand(0));
506 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath());
508 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
509 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
510 DAG.getTargetLoweringInfo(),
511 &DAG.getTarget().Options, Depth+1))
512 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
513 GetNegatedExpression(Op.getOperand(0), DAG,
514 LegalOperations, Depth+1),
517 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
518 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
520 GetNegatedExpression(Op.getOperand(1), DAG,
521 LegalOperations, Depth+1));
525 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
526 GetNegatedExpression(Op.getOperand(0), DAG,
527 LegalOperations, Depth+1));
529 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
530 GetNegatedExpression(Op.getOperand(0), DAG,
531 LegalOperations, Depth+1),
537 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
538 // that selects between the values 1 and 0, making it equivalent to a setcc.
539 // Also, set the incoming LHS, RHS, and CC references to the appropriate
540 // nodes based on the type of node we are checking. This simplifies life a
541 // bit for the callers.
542 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
544 if (N.getOpcode() == ISD::SETCC) {
545 LHS = N.getOperand(0);
546 RHS = N.getOperand(1);
547 CC = N.getOperand(2);
550 if (N.getOpcode() == ISD::SELECT_CC &&
551 N.getOperand(2).getOpcode() == ISD::Constant &&
552 N.getOperand(3).getOpcode() == ISD::Constant &&
553 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
554 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
555 LHS = N.getOperand(0);
556 RHS = N.getOperand(1);
557 CC = N.getOperand(4);
563 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
564 // one use. If this is true, it allows the users to invert the operation for
565 // free when it is profitable to do so.
566 static bool isOneUseSetCC(SDValue N) {
568 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
573 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
574 SDValue N0, SDValue N1) {
575 EVT VT = N0.getValueType();
576 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
577 if (isa<ConstantSDNode>(N1)) {
578 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
580 DAG.FoldConstantArithmetic(Opc, VT,
581 cast<ConstantSDNode>(N0.getOperand(1)),
582 cast<ConstantSDNode>(N1));
583 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
585 if (N0.hasOneUse()) {
586 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
587 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
588 N0.getOperand(0), N1);
589 AddToWorkList(OpNode.getNode());
590 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
594 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
595 if (isa<ConstantSDNode>(N0)) {
596 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
598 DAG.FoldConstantArithmetic(Opc, VT,
599 cast<ConstantSDNode>(N1.getOperand(1)),
600 cast<ConstantSDNode>(N0));
601 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
603 if (N1.hasOneUse()) {
604 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
605 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
606 N1.getOperand(0), N0);
607 AddToWorkList(OpNode.getNode());
608 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
615 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
617 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
619 DEBUG(dbgs() << "\nReplacing.1 ";
621 dbgs() << "\nWith: ";
622 To[0].getNode()->dump(&DAG);
623 dbgs() << " and " << NumTo-1 << " other values\n";
624 for (unsigned i = 0, e = NumTo; i != e; ++i)
625 assert((!To[i].getNode() ||
626 N->getValueType(i) == To[i].getValueType()) &&
627 "Cannot combine value to value of different type!"));
628 WorkListRemover DeadNodes(*this);
629 DAG.ReplaceAllUsesWith(N, To);
631 // Push the new nodes and any users onto the worklist
632 for (unsigned i = 0, e = NumTo; i != e; ++i) {
633 if (To[i].getNode()) {
634 AddToWorkList(To[i].getNode());
635 AddUsersToWorkList(To[i].getNode());
640 // Finally, if the node is now dead, remove it from the graph. The node
641 // may not be dead if the replacement process recursively simplified to
642 // something else needing this node.
643 if (N->use_empty()) {
644 // Nodes can be reintroduced into the worklist. Make sure we do not
645 // process a node that has been replaced.
646 removeFromWorkList(N);
648 // Finally, since the node is now dead, remove it from the graph.
651 return SDValue(N, 0);
655 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
656 // Replace all uses. If any nodes become isomorphic to other nodes and
657 // are deleted, make sure to remove them from our worklist.
658 WorkListRemover DeadNodes(*this);
659 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
661 // Push the new node and any (possibly new) users onto the worklist.
662 AddToWorkList(TLO.New.getNode());
663 AddUsersToWorkList(TLO.New.getNode());
665 // Finally, if the node is now dead, remove it from the graph. The node
666 // may not be dead if the replacement process recursively simplified to
667 // something else needing this node.
668 if (TLO.Old.getNode()->use_empty()) {
669 removeFromWorkList(TLO.Old.getNode());
671 // If the operands of this node are only used by the node, they will now
672 // be dead. Make sure to visit them first to delete dead nodes early.
673 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
674 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
675 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
677 DAG.DeleteNode(TLO.Old.getNode());
681 /// SimplifyDemandedBits - Check the specified integer node value to see if
682 /// it can be simplified or if things it uses can be simplified by bit
683 /// propagation. If so, return true.
684 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
685 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
686 APInt KnownZero, KnownOne;
687 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
691 AddToWorkList(Op.getNode());
693 // Replace the old value with the new one.
695 DEBUG(dbgs() << "\nReplacing.2 ";
696 TLO.Old.getNode()->dump(&DAG);
697 dbgs() << "\nWith: ";
698 TLO.New.getNode()->dump(&DAG);
701 CommitTargetLoweringOpt(TLO);
705 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
706 DebugLoc dl = Load->getDebugLoc();
707 EVT VT = Load->getValueType(0);
708 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
710 DEBUG(dbgs() << "\nReplacing.9 ";
712 dbgs() << "\nWith: ";
713 Trunc.getNode()->dump(&DAG);
715 WorkListRemover DeadNodes(*this);
716 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
717 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
718 removeFromWorkList(Load);
719 DAG.DeleteNode(Load);
720 AddToWorkList(Trunc.getNode());
723 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
725 DebugLoc dl = Op.getDebugLoc();
726 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
727 EVT MemVT = LD->getMemoryVT();
728 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
729 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
731 : LD->getExtensionType();
733 return DAG.getExtLoad(ExtType, dl, PVT,
734 LD->getChain(), LD->getBasePtr(),
735 LD->getPointerInfo(),
736 MemVT, LD->isVolatile(),
737 LD->isNonTemporal(), LD->getAlignment());
740 unsigned Opc = Op.getOpcode();
743 case ISD::AssertSext:
744 return DAG.getNode(ISD::AssertSext, dl, PVT,
745 SExtPromoteOperand(Op.getOperand(0), PVT),
747 case ISD::AssertZext:
748 return DAG.getNode(ISD::AssertZext, dl, PVT,
749 ZExtPromoteOperand(Op.getOperand(0), PVT),
751 case ISD::Constant: {
753 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
754 return DAG.getNode(ExtOpc, dl, PVT, Op);
758 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
760 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
763 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
764 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
766 EVT OldVT = Op.getValueType();
767 DebugLoc dl = Op.getDebugLoc();
768 bool Replace = false;
769 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
770 if (NewOp.getNode() == 0)
772 AddToWorkList(NewOp.getNode());
775 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
776 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
777 DAG.getValueType(OldVT));
780 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
781 EVT OldVT = Op.getValueType();
782 DebugLoc dl = Op.getDebugLoc();
783 bool Replace = false;
784 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
785 if (NewOp.getNode() == 0)
787 AddToWorkList(NewOp.getNode());
790 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
791 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
794 /// PromoteIntBinOp - Promote the specified integer binary operation if the
795 /// target indicates it is beneficial. e.g. On x86, it's usually better to
796 /// promote i16 operations to i32 since i16 instructions are longer.
797 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
798 if (!LegalOperations)
801 EVT VT = Op.getValueType();
802 if (VT.isVector() || !VT.isInteger())
805 // If operation type is 'undesirable', e.g. i16 on x86, consider
807 unsigned Opc = Op.getOpcode();
808 if (TLI.isTypeDesirableForOp(Opc, VT))
812 // Consult target whether it is a good idea to promote this operation and
813 // what's the right type to promote it to.
814 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
815 assert(PVT != VT && "Don't know what type to promote to!");
817 bool Replace0 = false;
818 SDValue N0 = Op.getOperand(0);
819 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
820 if (NN0.getNode() == 0)
823 bool Replace1 = false;
824 SDValue N1 = Op.getOperand(1);
829 NN1 = PromoteOperand(N1, PVT, Replace1);
830 if (NN1.getNode() == 0)
834 AddToWorkList(NN0.getNode());
836 AddToWorkList(NN1.getNode());
839 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
841 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
843 DEBUG(dbgs() << "\nPromoting ";
844 Op.getNode()->dump(&DAG));
845 DebugLoc dl = Op.getDebugLoc();
846 return DAG.getNode(ISD::TRUNCATE, dl, VT,
847 DAG.getNode(Opc, dl, PVT, NN0, NN1));
852 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
853 /// target indicates it is beneficial. e.g. On x86, it's usually better to
854 /// promote i16 operations to i32 since i16 instructions are longer.
855 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
856 if (!LegalOperations)
859 EVT VT = Op.getValueType();
860 if (VT.isVector() || !VT.isInteger())
863 // If operation type is 'undesirable', e.g. i16 on x86, consider
865 unsigned Opc = Op.getOpcode();
866 if (TLI.isTypeDesirableForOp(Opc, VT))
870 // Consult target whether it is a good idea to promote this operation and
871 // what's the right type to promote it to.
872 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
873 assert(PVT != VT && "Don't know what type to promote to!");
875 bool Replace = false;
876 SDValue N0 = Op.getOperand(0);
878 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
879 else if (Opc == ISD::SRL)
880 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
882 N0 = PromoteOperand(N0, PVT, Replace);
883 if (N0.getNode() == 0)
886 AddToWorkList(N0.getNode());
888 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
890 DEBUG(dbgs() << "\nPromoting ";
891 Op.getNode()->dump(&DAG));
892 DebugLoc dl = Op.getDebugLoc();
893 return DAG.getNode(ISD::TRUNCATE, dl, VT,
894 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
899 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
900 if (!LegalOperations)
903 EVT VT = Op.getValueType();
904 if (VT.isVector() || !VT.isInteger())
907 // If operation type is 'undesirable', e.g. i16 on x86, consider
909 unsigned Opc = Op.getOpcode();
910 if (TLI.isTypeDesirableForOp(Opc, VT))
914 // Consult target whether it is a good idea to promote this operation and
915 // what's the right type to promote it to.
916 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
917 assert(PVT != VT && "Don't know what type to promote to!");
918 // fold (aext (aext x)) -> (aext x)
919 // fold (aext (zext x)) -> (zext x)
920 // fold (aext (sext x)) -> (sext x)
921 DEBUG(dbgs() << "\nPromoting ";
922 Op.getNode()->dump(&DAG));
923 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
928 bool DAGCombiner::PromoteLoad(SDValue Op) {
929 if (!LegalOperations)
932 EVT VT = Op.getValueType();
933 if (VT.isVector() || !VT.isInteger())
936 // If operation type is 'undesirable', e.g. i16 on x86, consider
938 unsigned Opc = Op.getOpcode();
939 if (TLI.isTypeDesirableForOp(Opc, VT))
943 // Consult target whether it is a good idea to promote this operation and
944 // what's the right type to promote it to.
945 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
946 assert(PVT != VT && "Don't know what type to promote to!");
948 DebugLoc dl = Op.getDebugLoc();
949 SDNode *N = Op.getNode();
950 LoadSDNode *LD = cast<LoadSDNode>(N);
951 EVT MemVT = LD->getMemoryVT();
952 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
953 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
955 : LD->getExtensionType();
956 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
957 LD->getChain(), LD->getBasePtr(),
958 LD->getPointerInfo(),
959 MemVT, LD->isVolatile(),
960 LD->isNonTemporal(), LD->getAlignment());
961 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
963 DEBUG(dbgs() << "\nPromoting ";
966 Result.getNode()->dump(&DAG);
968 WorkListRemover DeadNodes(*this);
969 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
970 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
971 removeFromWorkList(N);
973 AddToWorkList(Result.getNode());
980 //===----------------------------------------------------------------------===//
981 // Main DAG Combiner implementation
982 //===----------------------------------------------------------------------===//
984 void DAGCombiner::Run(CombineLevel AtLevel) {
985 // set the instance variables, so that the various visit routines may use it.
987 LegalOperations = Level >= AfterLegalizeVectorOps;
988 LegalTypes = Level >= AfterLegalizeTypes;
990 // Add all the dag nodes to the worklist.
991 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
992 E = DAG.allnodes_end(); I != E; ++I)
995 // Create a dummy node (which is not added to allnodes), that adds a reference
996 // to the root node, preventing it from being deleted, and tracking any
997 // changes of the root.
998 HandleSDNode Dummy(DAG.getRoot());
1000 // The root of the dag may dangle to deleted nodes until the dag combiner is
1001 // done. Set it to null to avoid confusion.
1002 DAG.setRoot(SDValue());
1004 // while the worklist isn't empty, find a node and
1005 // try and combine it.
1006 while (!WorkListContents.empty()) {
1008 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates.
1009 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the
1010 // worklist *should* contain, and check the node we want to visit is should
1011 // actually be visited.
1013 N = WorkListOrder.pop_back_val();
1014 } while (!WorkListContents.erase(N));
1016 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1017 // N is deleted from the DAG, since they too may now be dead or may have a
1018 // reduced number of uses, allowing other xforms.
1019 if (N->use_empty() && N != &Dummy) {
1020 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1021 AddToWorkList(N->getOperand(i).getNode());
1027 SDValue RV = combine(N);
1029 if (RV.getNode() == 0)
1034 // If we get back the same node we passed in, rather than a new node or
1035 // zero, we know that the node must have defined multiple values and
1036 // CombineTo was used. Since CombineTo takes care of the worklist
1037 // mechanics for us, we have no work to do in this case.
1038 if (RV.getNode() == N)
1041 assert(N->getOpcode() != ISD::DELETED_NODE &&
1042 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1043 "Node was deleted but visit returned new node!");
1045 DEBUG(dbgs() << "\nReplacing.3 ";
1047 dbgs() << "\nWith: ";
1048 RV.getNode()->dump(&DAG);
1051 // Transfer debug value.
1052 DAG.TransferDbgValues(SDValue(N, 0), RV);
1053 WorkListRemover DeadNodes(*this);
1054 if (N->getNumValues() == RV.getNode()->getNumValues())
1055 DAG.ReplaceAllUsesWith(N, RV.getNode());
1057 assert(N->getValueType(0) == RV.getValueType() &&
1058 N->getNumValues() == 1 && "Type mismatch");
1060 DAG.ReplaceAllUsesWith(N, &OpV);
1063 // Push the new node and any users onto the worklist
1064 AddToWorkList(RV.getNode());
1065 AddUsersToWorkList(RV.getNode());
1067 // Add any uses of the old node to the worklist in case this node is the
1068 // last one that uses them. They may become dead after this node is
1070 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1071 AddToWorkList(N->getOperand(i).getNode());
1073 // Finally, if the node is now dead, remove it from the graph. The node
1074 // may not be dead if the replacement process recursively simplified to
1075 // something else needing this node.
1076 if (N->use_empty()) {
1077 // Nodes can be reintroduced into the worklist. Make sure we do not
1078 // process a node that has been replaced.
1079 removeFromWorkList(N);
1081 // Finally, since the node is now dead, remove it from the graph.
1086 // If the root changed (e.g. it was a dead load, update the root).
1087 DAG.setRoot(Dummy.getValue());
1088 DAG.RemoveDeadNodes();
1091 SDValue DAGCombiner::visit(SDNode *N) {
1092 switch (N->getOpcode()) {
1094 case ISD::TokenFactor: return visitTokenFactor(N);
1095 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1096 case ISD::ADD: return visitADD(N);
1097 case ISD::SUB: return visitSUB(N);
1098 case ISD::ADDC: return visitADDC(N);
1099 case ISD::SUBC: return visitSUBC(N);
1100 case ISD::ADDE: return visitADDE(N);
1101 case ISD::SUBE: return visitSUBE(N);
1102 case ISD::MUL: return visitMUL(N);
1103 case ISD::SDIV: return visitSDIV(N);
1104 case ISD::UDIV: return visitUDIV(N);
1105 case ISD::SREM: return visitSREM(N);
1106 case ISD::UREM: return visitUREM(N);
1107 case ISD::MULHU: return visitMULHU(N);
1108 case ISD::MULHS: return visitMULHS(N);
1109 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1110 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1111 case ISD::SMULO: return visitSMULO(N);
1112 case ISD::UMULO: return visitUMULO(N);
1113 case ISD::SDIVREM: return visitSDIVREM(N);
1114 case ISD::UDIVREM: return visitUDIVREM(N);
1115 case ISD::AND: return visitAND(N);
1116 case ISD::OR: return visitOR(N);
1117 case ISD::XOR: return visitXOR(N);
1118 case ISD::SHL: return visitSHL(N);
1119 case ISD::SRA: return visitSRA(N);
1120 case ISD::SRL: return visitSRL(N);
1121 case ISD::CTLZ: return visitCTLZ(N);
1122 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1123 case ISD::CTTZ: return visitCTTZ(N);
1124 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1125 case ISD::CTPOP: return visitCTPOP(N);
1126 case ISD::SELECT: return visitSELECT(N);
1127 case ISD::SELECT_CC: return visitSELECT_CC(N);
1128 case ISD::SETCC: return visitSETCC(N);
1129 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1130 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1131 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1132 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1133 case ISD::TRUNCATE: return visitTRUNCATE(N);
1134 case ISD::BITCAST: return visitBITCAST(N);
1135 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1136 case ISD::FADD: return visitFADD(N);
1137 case ISD::FSUB: return visitFSUB(N);
1138 case ISD::FMUL: return visitFMUL(N);
1139 case ISD::FMA: return visitFMA(N);
1140 case ISD::FDIV: return visitFDIV(N);
1141 case ISD::FREM: return visitFREM(N);
1142 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1143 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1144 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1145 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1146 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1147 case ISD::FP_ROUND: return visitFP_ROUND(N);
1148 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1149 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1150 case ISD::FNEG: return visitFNEG(N);
1151 case ISD::FABS: return visitFABS(N);
1152 case ISD::FFLOOR: return visitFFLOOR(N);
1153 case ISD::FCEIL: return visitFCEIL(N);
1154 case ISD::FTRUNC: return visitFTRUNC(N);
1155 case ISD::BRCOND: return visitBRCOND(N);
1156 case ISD::BR_CC: return visitBR_CC(N);
1157 case ISD::LOAD: return visitLOAD(N);
1158 case ISD::STORE: return visitSTORE(N);
1159 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1160 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1161 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1162 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1163 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1164 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1165 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1170 SDValue DAGCombiner::combine(SDNode *N) {
1171 SDValue RV = visit(N);
1173 // If nothing happened, try a target-specific DAG combine.
1174 if (RV.getNode() == 0) {
1175 assert(N->getOpcode() != ISD::DELETED_NODE &&
1176 "Node was deleted but visit returned NULL!");
1178 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1179 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1181 // Expose the DAG combiner to the target combiner impls.
1182 TargetLowering::DAGCombinerInfo
1183 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1185 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1189 // If nothing happened still, try promoting the operation.
1190 if (RV.getNode() == 0) {
1191 switch (N->getOpcode()) {
1199 RV = PromoteIntBinOp(SDValue(N, 0));
1204 RV = PromoteIntShiftOp(SDValue(N, 0));
1206 case ISD::SIGN_EXTEND:
1207 case ISD::ZERO_EXTEND:
1208 case ISD::ANY_EXTEND:
1209 RV = PromoteExtend(SDValue(N, 0));
1212 if (PromoteLoad(SDValue(N, 0)))
1218 // If N is a commutative binary node, try commuting it to enable more
1220 if (RV.getNode() == 0 &&
1221 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1222 N->getNumValues() == 1) {
1223 SDValue N0 = N->getOperand(0);
1224 SDValue N1 = N->getOperand(1);
1226 // Constant operands are canonicalized to RHS.
1227 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1228 SDValue Ops[] = { N1, N0 };
1229 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1232 return SDValue(CSENode, 0);
1239 /// getInputChainForNode - Given a node, return its input chain if it has one,
1240 /// otherwise return a null sd operand.
1241 static SDValue getInputChainForNode(SDNode *N) {
1242 if (unsigned NumOps = N->getNumOperands()) {
1243 if (N->getOperand(0).getValueType() == MVT::Other)
1244 return N->getOperand(0);
1245 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1246 return N->getOperand(NumOps-1);
1247 for (unsigned i = 1; i < NumOps-1; ++i)
1248 if (N->getOperand(i).getValueType() == MVT::Other)
1249 return N->getOperand(i);
1254 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1255 // If N has two operands, where one has an input chain equal to the other,
1256 // the 'other' chain is redundant.
1257 if (N->getNumOperands() == 2) {
1258 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1259 return N->getOperand(0);
1260 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1261 return N->getOperand(1);
1264 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1265 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1266 SmallPtrSet<SDNode*, 16> SeenOps;
1267 bool Changed = false; // If we should replace this token factor.
1269 // Start out with this token factor.
1272 // Iterate through token factors. The TFs grows when new token factors are
1274 for (unsigned i = 0; i < TFs.size(); ++i) {
1275 SDNode *TF = TFs[i];
1277 // Check each of the operands.
1278 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1279 SDValue Op = TF->getOperand(i);
1281 switch (Op.getOpcode()) {
1282 case ISD::EntryToken:
1283 // Entry tokens don't need to be added to the list. They are
1288 case ISD::TokenFactor:
1289 if (Op.hasOneUse() &&
1290 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1291 // Queue up for processing.
1292 TFs.push_back(Op.getNode());
1293 // Clean up in case the token factor is removed.
1294 AddToWorkList(Op.getNode());
1301 // Only add if it isn't already in the list.
1302 if (SeenOps.insert(Op.getNode()))
1313 // If we've change things around then replace token factor.
1316 // The entry token is the only possible outcome.
1317 Result = DAG.getEntryNode();
1319 // New and improved token factor.
1320 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1321 MVT::Other, &Ops[0], Ops.size());
1324 // Don't add users to work list.
1325 return CombineTo(N, Result, false);
1331 /// MERGE_VALUES can always be eliminated.
1332 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1333 WorkListRemover DeadNodes(*this);
1334 // Replacing results may cause a different MERGE_VALUES to suddenly
1335 // be CSE'd with N, and carry its uses with it. Iterate until no
1336 // uses remain, to ensure that the node can be safely deleted.
1337 // First add the users of this node to the work list so that they
1338 // can be tried again once they have new operands.
1339 AddUsersToWorkList(N);
1341 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1342 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1343 } while (!N->use_empty());
1344 removeFromWorkList(N);
1346 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1350 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1351 SelectionDAG &DAG) {
1352 EVT VT = N0.getValueType();
1353 SDValue N00 = N0.getOperand(0);
1354 SDValue N01 = N0.getOperand(1);
1355 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1357 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1358 isa<ConstantSDNode>(N00.getOperand(1))) {
1359 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1360 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1361 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1362 N00.getOperand(0), N01),
1363 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1364 N00.getOperand(1), N01));
1365 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1371 SDValue DAGCombiner::visitADD(SDNode *N) {
1372 SDValue N0 = N->getOperand(0);
1373 SDValue N1 = N->getOperand(1);
1374 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1375 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1376 EVT VT = N0.getValueType();
1379 if (VT.isVector()) {
1380 SDValue FoldedVOp = SimplifyVBinOp(N);
1381 if (FoldedVOp.getNode()) return FoldedVOp;
1384 // fold (add x, undef) -> undef
1385 if (N0.getOpcode() == ISD::UNDEF)
1387 if (N1.getOpcode() == ISD::UNDEF)
1389 // fold (add c1, c2) -> c1+c2
1391 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1392 // canonicalize constant to RHS
1394 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1395 // fold (add x, 0) -> x
1396 if (N1C && N1C->isNullValue())
1398 // fold (add Sym, c) -> Sym+c
1399 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1400 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1401 GA->getOpcode() == ISD::GlobalAddress)
1402 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1404 (uint64_t)N1C->getSExtValue());
1405 // fold ((c1-A)+c2) -> (c1+c2)-A
1406 if (N1C && N0.getOpcode() == ISD::SUB)
1407 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1408 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1409 DAG.getConstant(N1C->getAPIntValue()+
1410 N0C->getAPIntValue(), VT),
1413 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1414 if (RADD.getNode() != 0)
1416 // fold ((0-A) + B) -> B-A
1417 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1418 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1419 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1420 // fold (A + (0-B)) -> A-B
1421 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1422 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1423 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1424 // fold (A+(B-A)) -> B
1425 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1426 return N1.getOperand(0);
1427 // fold ((B-A)+A) -> B
1428 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1429 return N0.getOperand(0);
1430 // fold (A+(B-(A+C))) to (B-C)
1431 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1432 N0 == N1.getOperand(1).getOperand(0))
1433 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1434 N1.getOperand(1).getOperand(1));
1435 // fold (A+(B-(C+A))) to (B-C)
1436 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1437 N0 == N1.getOperand(1).getOperand(1))
1438 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1439 N1.getOperand(1).getOperand(0));
1440 // fold (A+((B-A)+or-C)) to (B+or-C)
1441 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1442 N1.getOperand(0).getOpcode() == ISD::SUB &&
1443 N0 == N1.getOperand(0).getOperand(1))
1444 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1445 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1447 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1448 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1449 SDValue N00 = N0.getOperand(0);
1450 SDValue N01 = N0.getOperand(1);
1451 SDValue N10 = N1.getOperand(0);
1452 SDValue N11 = N1.getOperand(1);
1454 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1455 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1456 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1457 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1460 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1461 return SDValue(N, 0);
1463 // fold (a+b) -> (a|b) iff a and b share no bits.
1464 if (VT.isInteger() && !VT.isVector()) {
1465 APInt LHSZero, LHSOne;
1466 APInt RHSZero, RHSOne;
1467 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1469 if (LHSZero.getBoolValue()) {
1470 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1472 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1473 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1474 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1475 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1479 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1480 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1481 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1482 if (Result.getNode()) return Result;
1484 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1485 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1486 if (Result.getNode()) return Result;
1489 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1490 if (N1.getOpcode() == ISD::SHL &&
1491 N1.getOperand(0).getOpcode() == ISD::SUB)
1492 if (ConstantSDNode *C =
1493 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1494 if (C->getAPIntValue() == 0)
1495 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1496 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1497 N1.getOperand(0).getOperand(1),
1499 if (N0.getOpcode() == ISD::SHL &&
1500 N0.getOperand(0).getOpcode() == ISD::SUB)
1501 if (ConstantSDNode *C =
1502 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1503 if (C->getAPIntValue() == 0)
1504 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1505 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1506 N0.getOperand(0).getOperand(1),
1509 if (N1.getOpcode() == ISD::AND) {
1510 SDValue AndOp0 = N1.getOperand(0);
1511 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1512 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1513 unsigned DestBits = VT.getScalarType().getSizeInBits();
1515 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1516 // and similar xforms where the inner op is either ~0 or 0.
1517 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1518 DebugLoc DL = N->getDebugLoc();
1519 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1523 // add (sext i1), X -> sub X, (zext i1)
1524 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1525 N0.getOperand(0).getValueType() == MVT::i1 &&
1526 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1527 DebugLoc DL = N->getDebugLoc();
1528 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1529 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1535 SDValue DAGCombiner::visitADDC(SDNode *N) {
1536 SDValue N0 = N->getOperand(0);
1537 SDValue N1 = N->getOperand(1);
1538 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1539 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1540 EVT VT = N0.getValueType();
1542 // If the flag result is dead, turn this into an ADD.
1543 if (!N->hasAnyUseOfValue(1))
1544 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1),
1545 DAG.getNode(ISD::CARRY_FALSE,
1546 N->getDebugLoc(), MVT::Glue));
1548 // canonicalize constant to RHS.
1550 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1552 // fold (addc x, 0) -> x + no carry out
1553 if (N1C && N1C->isNullValue())
1554 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1555 N->getDebugLoc(), MVT::Glue));
1557 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1558 APInt LHSZero, LHSOne;
1559 APInt RHSZero, RHSOne;
1560 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne);
1562 if (LHSZero.getBoolValue()) {
1563 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne);
1565 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1566 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1567 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1568 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1569 DAG.getNode(ISD::CARRY_FALSE,
1570 N->getDebugLoc(), MVT::Glue));
1576 SDValue DAGCombiner::visitADDE(SDNode *N) {
1577 SDValue N0 = N->getOperand(0);
1578 SDValue N1 = N->getOperand(1);
1579 SDValue CarryIn = N->getOperand(2);
1580 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1581 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1583 // canonicalize constant to RHS
1585 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1588 // fold (adde x, y, false) -> (addc x, y)
1589 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1590 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1);
1595 // Since it may not be valid to emit a fold to zero for vector initializers
1596 // check if we can before folding.
1597 static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT,
1598 SelectionDAG &DAG, bool LegalOperations) {
1599 if (!VT.isVector()) {
1600 return DAG.getConstant(0, VT);
1602 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1603 // Produce a vector of zeros.
1604 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
1605 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
1606 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
1607 &Ops[0], Ops.size());
1612 SDValue DAGCombiner::visitSUB(SDNode *N) {
1613 SDValue N0 = N->getOperand(0);
1614 SDValue N1 = N->getOperand(1);
1615 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1616 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1617 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 :
1618 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1619 EVT VT = N0.getValueType();
1622 if (VT.isVector()) {
1623 SDValue FoldedVOp = SimplifyVBinOp(N);
1624 if (FoldedVOp.getNode()) return FoldedVOp;
1627 // fold (sub x, x) -> 0
1628 // FIXME: Refactor this and xor and other similar operations together.
1630 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
1631 // fold (sub c1, c2) -> c1-c2
1633 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1634 // fold (sub x, c) -> (add x, -c)
1636 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1637 DAG.getConstant(-N1C->getAPIntValue(), VT));
1638 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1639 if (N0C && N0C->isAllOnesValue())
1640 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1641 // fold A-(A-B) -> B
1642 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1643 return N1.getOperand(1);
1644 // fold (A+B)-A -> B
1645 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1646 return N0.getOperand(1);
1647 // fold (A+B)-B -> A
1648 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1649 return N0.getOperand(0);
1650 // fold C2-(A+C1) -> (C2-C1)-A
1651 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1652 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(),
1654 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC,
1657 // fold ((A+(B+or-C))-B) -> A+or-C
1658 if (N0.getOpcode() == ISD::ADD &&
1659 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1660 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1661 N0.getOperand(1).getOperand(0) == N1)
1662 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1663 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1664 // fold ((A+(C+B))-B) -> A+C
1665 if (N0.getOpcode() == ISD::ADD &&
1666 N0.getOperand(1).getOpcode() == ISD::ADD &&
1667 N0.getOperand(1).getOperand(1) == N1)
1668 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1669 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1670 // fold ((A-(B-C))-C) -> A-B
1671 if (N0.getOpcode() == ISD::SUB &&
1672 N0.getOperand(1).getOpcode() == ISD::SUB &&
1673 N0.getOperand(1).getOperand(1) == N1)
1674 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1675 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1677 // If either operand of a sub is undef, the result is undef
1678 if (N0.getOpcode() == ISD::UNDEF)
1680 if (N1.getOpcode() == ISD::UNDEF)
1683 // If the relocation model supports it, consider symbol offsets.
1684 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1685 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1686 // fold (sub Sym, c) -> Sym-c
1687 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1688 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1690 (uint64_t)N1C->getSExtValue());
1691 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1692 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1693 if (GA->getGlobal() == GB->getGlobal())
1694 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1701 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1702 SDValue N0 = N->getOperand(0);
1703 SDValue N1 = N->getOperand(1);
1704 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1705 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1706 EVT VT = N0.getValueType();
1708 // If the flag result is dead, turn this into an SUB.
1709 if (!N->hasAnyUseOfValue(1))
1710 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1),
1711 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1714 // fold (subc x, x) -> 0 + no borrow
1716 return CombineTo(N, DAG.getConstant(0, VT),
1717 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1720 // fold (subc x, 0) -> x + no borrow
1721 if (N1C && N1C->isNullValue())
1722 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1725 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1726 if (N0C && N0C->isAllOnesValue())
1727 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0),
1728 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1734 SDValue DAGCombiner::visitSUBE(SDNode *N) {
1735 SDValue N0 = N->getOperand(0);
1736 SDValue N1 = N->getOperand(1);
1737 SDValue CarryIn = N->getOperand(2);
1739 // fold (sube x, y, false) -> (subc x, y)
1740 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1741 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1);
1746 SDValue DAGCombiner::visitMUL(SDNode *N) {
1747 SDValue N0 = N->getOperand(0);
1748 SDValue N1 = N->getOperand(1);
1749 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1750 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1751 EVT VT = N0.getValueType();
1754 if (VT.isVector()) {
1755 SDValue FoldedVOp = SimplifyVBinOp(N);
1756 if (FoldedVOp.getNode()) return FoldedVOp;
1759 // fold (mul x, undef) -> 0
1760 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1761 return DAG.getConstant(0, VT);
1762 // fold (mul c1, c2) -> c1*c2
1764 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1765 // canonicalize constant to RHS
1767 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1768 // fold (mul x, 0) -> 0
1769 if (N1C && N1C->isNullValue())
1771 // fold (mul x, -1) -> 0-x
1772 if (N1C && N1C->isAllOnesValue())
1773 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1774 DAG.getConstant(0, VT), N0);
1775 // fold (mul x, (1 << c)) -> x << c
1776 if (N1C && N1C->getAPIntValue().isPowerOf2())
1777 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1778 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1779 getShiftAmountTy(N0.getValueType())));
1780 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1781 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1782 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1783 // FIXME: If the input is something that is easily negated (e.g. a
1784 // single-use add), we should put the negate there.
1785 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1786 DAG.getConstant(0, VT),
1787 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1788 DAG.getConstant(Log2Val,
1789 getShiftAmountTy(N0.getValueType()))));
1791 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1792 if (N1C && N0.getOpcode() == ISD::SHL &&
1793 isa<ConstantSDNode>(N0.getOperand(1))) {
1794 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1795 N1, N0.getOperand(1));
1796 AddToWorkList(C3.getNode());
1797 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1798 N0.getOperand(0), C3);
1801 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1804 SDValue Sh(0,0), Y(0,0);
1805 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1806 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1807 N0.getNode()->hasOneUse()) {
1809 } else if (N1.getOpcode() == ISD::SHL &&
1810 isa<ConstantSDNode>(N1.getOperand(1)) &&
1811 N1.getNode()->hasOneUse()) {
1816 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1817 Sh.getOperand(0), Y);
1818 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1819 Mul, Sh.getOperand(1));
1823 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1824 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1825 isa<ConstantSDNode>(N0.getOperand(1)))
1826 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1827 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1828 N0.getOperand(0), N1),
1829 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1830 N0.getOperand(1), N1));
1833 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1834 if (RMUL.getNode() != 0)
1840 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1841 SDValue N0 = N->getOperand(0);
1842 SDValue N1 = N->getOperand(1);
1843 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1844 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1845 EVT VT = N->getValueType(0);
1848 if (VT.isVector()) {
1849 SDValue FoldedVOp = SimplifyVBinOp(N);
1850 if (FoldedVOp.getNode()) return FoldedVOp;
1853 // fold (sdiv c1, c2) -> c1/c2
1854 if (N0C && N1C && !N1C->isNullValue())
1855 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1856 // fold (sdiv X, 1) -> X
1857 if (N1C && N1C->getAPIntValue() == 1LL)
1859 // fold (sdiv X, -1) -> 0-X
1860 if (N1C && N1C->isAllOnesValue())
1861 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1862 DAG.getConstant(0, VT), N0);
1863 // If we know the sign bits of both operands are zero, strength reduce to a
1864 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1865 if (!VT.isVector()) {
1866 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1867 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1870 // fold (sdiv X, pow2) -> simple ops after legalize
1871 if (N1C && !N1C->isNullValue() &&
1872 (N1C->getAPIntValue().isPowerOf2() ||
1873 (-N1C->getAPIntValue()).isPowerOf2())) {
1874 // If dividing by powers of two is cheap, then don't perform the following
1876 if (TLI.isPow2DivCheap())
1879 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
1881 // Splat the sign bit into the register
1882 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1883 DAG.getConstant(VT.getSizeInBits()-1,
1884 getShiftAmountTy(N0.getValueType())));
1885 AddToWorkList(SGN.getNode());
1887 // Add (N0 < 0) ? abs2 - 1 : 0;
1888 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1889 DAG.getConstant(VT.getSizeInBits() - lg2,
1890 getShiftAmountTy(SGN.getValueType())));
1891 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1892 AddToWorkList(SRL.getNode());
1893 AddToWorkList(ADD.getNode()); // Divide by pow2
1894 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1895 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1897 // If we're dividing by a positive value, we're done. Otherwise, we must
1898 // negate the result.
1899 if (N1C->getAPIntValue().isNonNegative())
1902 AddToWorkList(SRA.getNode());
1903 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1904 DAG.getConstant(0, VT), SRA);
1907 // if integer divide is expensive and we satisfy the requirements, emit an
1908 // alternate sequence.
1909 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1910 SDValue Op = BuildSDIV(N);
1911 if (Op.getNode()) return Op;
1915 if (N0.getOpcode() == ISD::UNDEF)
1916 return DAG.getConstant(0, VT);
1917 // X / undef -> undef
1918 if (N1.getOpcode() == ISD::UNDEF)
1924 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1925 SDValue N0 = N->getOperand(0);
1926 SDValue N1 = N->getOperand(1);
1927 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1928 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1929 EVT VT = N->getValueType(0);
1932 if (VT.isVector()) {
1933 SDValue FoldedVOp = SimplifyVBinOp(N);
1934 if (FoldedVOp.getNode()) return FoldedVOp;
1937 // fold (udiv c1, c2) -> c1/c2
1938 if (N0C && N1C && !N1C->isNullValue())
1939 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1940 // fold (udiv x, (1 << c)) -> x >>u c
1941 if (N1C && N1C->getAPIntValue().isPowerOf2())
1942 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1943 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1944 getShiftAmountTy(N0.getValueType())));
1945 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1946 if (N1.getOpcode() == ISD::SHL) {
1947 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1948 if (SHC->getAPIntValue().isPowerOf2()) {
1949 EVT ADDVT = N1.getOperand(1).getValueType();
1950 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1952 DAG.getConstant(SHC->getAPIntValue()
1955 AddToWorkList(Add.getNode());
1956 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1960 // fold (udiv x, c) -> alternate
1961 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1962 SDValue Op = BuildUDIV(N);
1963 if (Op.getNode()) return Op;
1967 if (N0.getOpcode() == ISD::UNDEF)
1968 return DAG.getConstant(0, VT);
1969 // X / undef -> undef
1970 if (N1.getOpcode() == ISD::UNDEF)
1976 SDValue DAGCombiner::visitSREM(SDNode *N) {
1977 SDValue N0 = N->getOperand(0);
1978 SDValue N1 = N->getOperand(1);
1979 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1980 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1981 EVT VT = N->getValueType(0);
1983 // fold (srem c1, c2) -> c1%c2
1984 if (N0C && N1C && !N1C->isNullValue())
1985 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1986 // If we know the sign bits of both operands are zero, strength reduce to a
1987 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1988 if (!VT.isVector()) {
1989 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1990 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1993 // If X/C can be simplified by the division-by-constant logic, lower
1994 // X%C to the equivalent of X-X/C*C.
1995 if (N1C && !N1C->isNullValue()) {
1996 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1997 AddToWorkList(Div.getNode());
1998 SDValue OptimizedDiv = combine(Div.getNode());
1999 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2000 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
2002 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
2003 AddToWorkList(Mul.getNode());
2009 if (N0.getOpcode() == ISD::UNDEF)
2010 return DAG.getConstant(0, VT);
2011 // X % undef -> undef
2012 if (N1.getOpcode() == ISD::UNDEF)
2018 SDValue DAGCombiner::visitUREM(SDNode *N) {
2019 SDValue N0 = N->getOperand(0);
2020 SDValue N1 = N->getOperand(1);
2021 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2022 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2023 EVT VT = N->getValueType(0);
2025 // fold (urem c1, c2) -> c1%c2
2026 if (N0C && N1C && !N1C->isNullValue())
2027 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2028 // fold (urem x, pow2) -> (and x, pow2-1)
2029 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
2030 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
2031 DAG.getConstant(N1C->getAPIntValue()-1,VT));
2032 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2033 if (N1.getOpcode() == ISD::SHL) {
2034 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2035 if (SHC->getAPIntValue().isPowerOf2()) {
2037 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
2038 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
2040 AddToWorkList(Add.getNode());
2041 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
2046 // If X/C can be simplified by the division-by-constant logic, lower
2047 // X%C to the equivalent of X-X/C*C.
2048 if (N1C && !N1C->isNullValue()) {
2049 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
2050 AddToWorkList(Div.getNode());
2051 SDValue OptimizedDiv = combine(Div.getNode());
2052 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2053 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
2055 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
2056 AddToWorkList(Mul.getNode());
2062 if (N0.getOpcode() == ISD::UNDEF)
2063 return DAG.getConstant(0, VT);
2064 // X % undef -> undef
2065 if (N1.getOpcode() == ISD::UNDEF)
2071 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2072 SDValue N0 = N->getOperand(0);
2073 SDValue N1 = N->getOperand(1);
2074 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2075 EVT VT = N->getValueType(0);
2076 DebugLoc DL = N->getDebugLoc();
2078 // fold (mulhs x, 0) -> 0
2079 if (N1C && N1C->isNullValue())
2081 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2082 if (N1C && N1C->getAPIntValue() == 1)
2083 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
2084 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2085 getShiftAmountTy(N0.getValueType())));
2086 // fold (mulhs x, undef) -> 0
2087 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2088 return DAG.getConstant(0, VT);
2090 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2092 if (VT.isSimple() && !VT.isVector()) {
2093 MVT Simple = VT.getSimpleVT();
2094 unsigned SimpleSize = Simple.getSizeInBits();
2095 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2096 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2097 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2098 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2099 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2100 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2101 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2102 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2109 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2110 SDValue N0 = N->getOperand(0);
2111 SDValue N1 = N->getOperand(1);
2112 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2113 EVT VT = N->getValueType(0);
2114 DebugLoc DL = N->getDebugLoc();
2116 // fold (mulhu x, 0) -> 0
2117 if (N1C && N1C->isNullValue())
2119 // fold (mulhu x, 1) -> 0
2120 if (N1C && N1C->getAPIntValue() == 1)
2121 return DAG.getConstant(0, N0.getValueType());
2122 // fold (mulhu x, undef) -> 0
2123 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2124 return DAG.getConstant(0, VT);
2126 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2128 if (VT.isSimple() && !VT.isVector()) {
2129 MVT Simple = VT.getSimpleVT();
2130 unsigned SimpleSize = Simple.getSizeInBits();
2131 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2132 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2133 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2134 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2135 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2136 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2137 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2138 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2145 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2146 /// compute two values. LoOp and HiOp give the opcodes for the two computations
2147 /// that are being performed. Return true if a simplification was made.
2149 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2151 // If the high half is not needed, just compute the low half.
2152 bool HiExists = N->hasAnyUseOfValue(1);
2154 (!LegalOperations ||
2155 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2156 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2157 N->op_begin(), N->getNumOperands());
2158 return CombineTo(N, Res, Res);
2161 // If the low half is not needed, just compute the high half.
2162 bool LoExists = N->hasAnyUseOfValue(0);
2164 (!LegalOperations ||
2165 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2166 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2167 N->op_begin(), N->getNumOperands());
2168 return CombineTo(N, Res, Res);
2171 // If both halves are used, return as it is.
2172 if (LoExists && HiExists)
2175 // If the two computed results can be simplified separately, separate them.
2177 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2178 N->op_begin(), N->getNumOperands());
2179 AddToWorkList(Lo.getNode());
2180 SDValue LoOpt = combine(Lo.getNode());
2181 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2182 (!LegalOperations ||
2183 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2184 return CombineTo(N, LoOpt, LoOpt);
2188 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2189 N->op_begin(), N->getNumOperands());
2190 AddToWorkList(Hi.getNode());
2191 SDValue HiOpt = combine(Hi.getNode());
2192 if (HiOpt.getNode() && HiOpt != Hi &&
2193 (!LegalOperations ||
2194 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2195 return CombineTo(N, HiOpt, HiOpt);
2201 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2202 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2203 if (Res.getNode()) return Res;
2205 EVT VT = N->getValueType(0);
2206 DebugLoc DL = N->getDebugLoc();
2208 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2210 if (VT.isSimple() && !VT.isVector()) {
2211 MVT Simple = VT.getSimpleVT();
2212 unsigned SimpleSize = Simple.getSizeInBits();
2213 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2214 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2215 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2216 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2217 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2218 // Compute the high part as N1.
2219 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2220 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2221 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2222 // Compute the low part as N0.
2223 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2224 return CombineTo(N, Lo, Hi);
2231 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2232 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2233 if (Res.getNode()) return Res;
2235 EVT VT = N->getValueType(0);
2236 DebugLoc DL = N->getDebugLoc();
2238 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2240 if (VT.isSimple() && !VT.isVector()) {
2241 MVT Simple = VT.getSimpleVT();
2242 unsigned SimpleSize = Simple.getSizeInBits();
2243 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2244 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2245 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2246 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2247 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2248 // Compute the high part as N1.
2249 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2250 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2251 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2252 // Compute the low part as N0.
2253 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2254 return CombineTo(N, Lo, Hi);
2261 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2262 // (smulo x, 2) -> (saddo x, x)
2263 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2264 if (C2->getAPIntValue() == 2)
2265 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(),
2266 N->getOperand(0), N->getOperand(0));
2271 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2272 // (umulo x, 2) -> (uaddo x, x)
2273 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2274 if (C2->getAPIntValue() == 2)
2275 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(),
2276 N->getOperand(0), N->getOperand(0));
2281 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2282 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2283 if (Res.getNode()) return Res;
2288 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2289 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2290 if (Res.getNode()) return Res;
2295 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2296 /// two operands of the same opcode, try to simplify it.
2297 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2298 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2299 EVT VT = N0.getValueType();
2300 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2302 // Bail early if none of these transforms apply.
2303 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2305 // For each of OP in AND/OR/XOR:
2306 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2307 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2308 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2309 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2311 // do not sink logical op inside of a vector extend, since it may combine
2313 EVT Op0VT = N0.getOperand(0).getValueType();
2314 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2315 N0.getOpcode() == ISD::SIGN_EXTEND ||
2316 // Avoid infinite looping with PromoteIntBinOp.
2317 (N0.getOpcode() == ISD::ANY_EXTEND &&
2318 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2319 (N0.getOpcode() == ISD::TRUNCATE &&
2320 (!TLI.isZExtFree(VT, Op0VT) ||
2321 !TLI.isTruncateFree(Op0VT, VT)) &&
2322 TLI.isTypeLegal(Op0VT))) &&
2324 Op0VT == N1.getOperand(0).getValueType() &&
2325 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2326 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2327 N0.getOperand(0).getValueType(),
2328 N0.getOperand(0), N1.getOperand(0));
2329 AddToWorkList(ORNode.getNode());
2330 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2333 // For each of OP in SHL/SRL/SRA/AND...
2334 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2335 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2336 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2337 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2338 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2339 N0.getOperand(1) == N1.getOperand(1)) {
2340 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2341 N0.getOperand(0).getValueType(),
2342 N0.getOperand(0), N1.getOperand(0));
2343 AddToWorkList(ORNode.getNode());
2344 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2345 ORNode, N0.getOperand(1));
2348 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
2349 // Only perform this optimization after type legalization and before
2350 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
2351 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
2352 // we don't want to undo this promotion.
2353 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
2355 if ((N0.getOpcode() == ISD::BITCAST ||
2356 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2357 Level == AfterLegalizeTypes) {
2358 SDValue In0 = N0.getOperand(0);
2359 SDValue In1 = N1.getOperand(0);
2360 EVT In0Ty = In0.getValueType();
2361 EVT In1Ty = In1.getValueType();
2362 DebugLoc DL = N->getDebugLoc();
2363 // If both incoming values are integers, and the original types are the
2365 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
2366 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1);
2367 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
2368 AddToWorkList(Op.getNode());
2373 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
2374 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
2375 // If both shuffles use the same mask, and both shuffle within a single
2376 // vector, then it is worthwhile to move the swizzle after the operation.
2377 // The type-legalizer generates this pattern when loading illegal
2378 // vector types from memory. In many cases this allows additional shuffle
2380 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
2381 N0.getOperand(1).getOpcode() == ISD::UNDEF &&
2382 N1.getOperand(1).getOpcode() == ISD::UNDEF) {
2383 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2384 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
2386 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() &&
2387 "Inputs to shuffles are not the same type");
2389 unsigned NumElts = VT.getVectorNumElements();
2391 // Check that both shuffles use the same mask. The masks are known to be of
2392 // the same length because the result vector type is the same.
2393 bool SameMask = true;
2394 for (unsigned i = 0; i != NumElts; ++i) {
2395 int Idx0 = SVN0->getMaskElt(i);
2396 int Idx1 = SVN1->getMaskElt(i);
2404 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT,
2405 N0.getOperand(0), N1.getOperand(0));
2406 AddToWorkList(Op.getNode());
2407 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op,
2408 DAG.getUNDEF(VT), &SVN0->getMask()[0]);
2415 SDValue DAGCombiner::visitAND(SDNode *N) {
2416 SDValue N0 = N->getOperand(0);
2417 SDValue N1 = N->getOperand(1);
2418 SDValue LL, LR, RL, RR, CC0, CC1;
2419 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2420 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2421 EVT VT = N1.getValueType();
2422 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2425 if (VT.isVector()) {
2426 SDValue FoldedVOp = SimplifyVBinOp(N);
2427 if (FoldedVOp.getNode()) return FoldedVOp;
2430 // fold (and x, undef) -> 0
2431 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2432 return DAG.getConstant(0, VT);
2433 // fold (and c1, c2) -> c1&c2
2435 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2436 // canonicalize constant to RHS
2438 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2439 // fold (and x, -1) -> x
2440 if (N1C && N1C->isAllOnesValue())
2442 // if (and x, c) is known to be zero, return 0
2443 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2444 APInt::getAllOnesValue(BitWidth)))
2445 return DAG.getConstant(0, VT);
2447 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2448 if (RAND.getNode() != 0)
2450 // fold (and (or x, C), D) -> D if (C & D) == D
2451 if (N1C && N0.getOpcode() == ISD::OR)
2452 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2453 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2455 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2456 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2457 SDValue N0Op0 = N0.getOperand(0);
2458 APInt Mask = ~N1C->getAPIntValue();
2459 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2460 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2461 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2462 N0.getValueType(), N0Op0);
2464 // Replace uses of the AND with uses of the Zero extend node.
2467 // We actually want to replace all uses of the any_extend with the
2468 // zero_extend, to avoid duplicating things. This will later cause this
2469 // AND to be folded.
2470 CombineTo(N0.getNode(), Zext);
2471 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2474 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2475 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2476 // already be zero by virtue of the width of the base type of the load.
2478 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2480 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2481 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2482 N0.getOpcode() == ISD::LOAD) {
2483 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2484 N0 : N0.getOperand(0) );
2486 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2487 // This can be a pure constant or a vector splat, in which case we treat the
2488 // vector as a scalar and use the splat value.
2489 APInt Constant = APInt::getNullValue(1);
2490 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2491 Constant = C->getAPIntValue();
2492 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2493 APInt SplatValue, SplatUndef;
2494 unsigned SplatBitSize;
2496 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2497 SplatBitSize, HasAnyUndefs);
2499 // Undef bits can contribute to a possible optimisation if set, so
2501 SplatValue |= SplatUndef;
2503 // The splat value may be something like "0x00FFFFFF", which means 0 for
2504 // the first vector value and FF for the rest, repeating. We need a mask
2505 // that will apply equally to all members of the vector, so AND all the
2506 // lanes of the constant together.
2507 EVT VT = Vector->getValueType(0);
2508 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2510 // If the splat value has been compressed to a bitlength lower
2511 // than the size of the vector lane, we need to re-expand it to
2513 if (BitWidth > SplatBitSize)
2514 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
2515 SplatBitSize < BitWidth;
2516 SplatBitSize = SplatBitSize * 2)
2517 SplatValue |= SplatValue.shl(SplatBitSize);
2519 Constant = APInt::getAllOnesValue(BitWidth);
2520 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
2521 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
2525 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
2526 // actually legal and isn't going to get expanded, else this is a false
2528 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2529 Load->getMemoryVT());
2531 // Resize the constant to the same size as the original memory access before
2532 // extension. If it is still the AllOnesValue then this AND is completely
2535 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
2538 switch (Load->getExtensionType()) {
2539 default: B = false; break;
2540 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2542 case ISD::NON_EXTLOAD: B = true; break;
2545 if (B && Constant.isAllOnesValue()) {
2546 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
2547 // preserve semantics once we get rid of the AND.
2548 SDValue NewLoad(Load, 0);
2549 if (Load->getExtensionType() == ISD::EXTLOAD) {
2550 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2551 Load->getValueType(0), Load->getDebugLoc(),
2552 Load->getChain(), Load->getBasePtr(),
2553 Load->getOffset(), Load->getMemoryVT(),
2554 Load->getMemOperand());
2555 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
2556 if (Load->getNumValues() == 3) {
2557 // PRE/POST_INC loads have 3 values.
2558 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
2559 NewLoad.getValue(2) };
2560 CombineTo(Load, To, 3, true);
2562 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
2566 // Fold the AND away, taking care not to fold to the old load node if we
2568 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
2570 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2573 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2574 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2575 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2576 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2578 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2579 LL.getValueType().isInteger()) {
2580 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2581 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2582 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2583 LR.getValueType(), LL, RL);
2584 AddToWorkList(ORNode.getNode());
2585 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2587 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2588 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2589 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2590 LR.getValueType(), LL, RL);
2591 AddToWorkList(ANDNode.getNode());
2592 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2594 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2595 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2596 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2597 LR.getValueType(), LL, RL);
2598 AddToWorkList(ORNode.getNode());
2599 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2602 // canonicalize equivalent to ll == rl
2603 if (LL == RR && LR == RL) {
2604 Op1 = ISD::getSetCCSwappedOperands(Op1);
2607 if (LL == RL && LR == RR) {
2608 bool isInteger = LL.getValueType().isInteger();
2609 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2610 if (Result != ISD::SETCC_INVALID &&
2611 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2612 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2617 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2618 if (N0.getOpcode() == N1.getOpcode()) {
2619 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2620 if (Tmp.getNode()) return Tmp;
2623 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2624 // fold (and (sra)) -> (and (srl)) when possible.
2625 if (!VT.isVector() &&
2626 SimplifyDemandedBits(SDValue(N, 0)))
2627 return SDValue(N, 0);
2629 // fold (zext_inreg (extload x)) -> (zextload x)
2630 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2631 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2632 EVT MemVT = LN0->getMemoryVT();
2633 // If we zero all the possible extended bits, then we can turn this into
2634 // a zextload if we are running before legalize or the operation is legal.
2635 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2636 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2637 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2638 ((!LegalOperations && !LN0->isVolatile()) ||
2639 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2640 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2641 LN0->getChain(), LN0->getBasePtr(),
2642 LN0->getPointerInfo(), MemVT,
2643 LN0->isVolatile(), LN0->isNonTemporal(),
2644 LN0->getAlignment());
2646 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2647 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2650 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2651 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2653 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2654 EVT MemVT = LN0->getMemoryVT();
2655 // If we zero all the possible extended bits, then we can turn this into
2656 // a zextload if we are running before legalize or the operation is legal.
2657 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2658 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2659 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2660 ((!LegalOperations && !LN0->isVolatile()) ||
2661 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2662 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2664 LN0->getBasePtr(), LN0->getPointerInfo(),
2666 LN0->isVolatile(), LN0->isNonTemporal(),
2667 LN0->getAlignment());
2669 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2670 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2674 // fold (and (load x), 255) -> (zextload x, i8)
2675 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2676 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2677 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2678 (N0.getOpcode() == ISD::ANY_EXTEND &&
2679 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2680 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2681 LoadSDNode *LN0 = HasAnyExt
2682 ? cast<LoadSDNode>(N0.getOperand(0))
2683 : cast<LoadSDNode>(N0);
2684 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2685 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2686 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2687 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2688 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2689 EVT LoadedVT = LN0->getMemoryVT();
2691 if (ExtVT == LoadedVT &&
2692 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2693 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2696 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2697 LN0->getChain(), LN0->getBasePtr(),
2698 LN0->getPointerInfo(),
2699 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2700 LN0->getAlignment());
2702 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2703 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2706 // Do not change the width of a volatile load.
2707 // Do not generate loads of non-round integer types since these can
2708 // be expensive (and would be wrong if the type is not byte sized).
2709 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2710 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2711 EVT PtrType = LN0->getOperand(1).getValueType();
2713 unsigned Alignment = LN0->getAlignment();
2714 SDValue NewPtr = LN0->getBasePtr();
2716 // For big endian targets, we need to add an offset to the pointer
2717 // to load the correct bytes. For little endian systems, we merely
2718 // need to read fewer bytes from the same pointer.
2719 if (TLI.isBigEndian()) {
2720 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2721 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2722 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2723 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2724 NewPtr, DAG.getConstant(PtrOff, PtrType));
2725 Alignment = MinAlign(Alignment, PtrOff);
2728 AddToWorkList(NewPtr.getNode());
2730 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2732 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2733 LN0->getChain(), NewPtr,
2734 LN0->getPointerInfo(),
2735 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2738 CombineTo(LN0, Load, Load.getValue(1));
2739 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2745 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
2746 VT.getSizeInBits() <= 64) {
2747 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2748 APInt ADDC = ADDI->getAPIntValue();
2749 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2750 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
2751 // immediate for an add, but it is legal if its top c2 bits are set,
2752 // transform the ADD so the immediate doesn't need to be materialized
2754 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
2755 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
2756 SRLI->getZExtValue());
2757 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
2759 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2761 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
2762 N0.getOperand(0), DAG.getConstant(ADDC, VT));
2763 CombineTo(N0.getNode(), NewAdd);
2764 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2776 /// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
2778 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2779 bool DemandHighBits) {
2780 if (!LegalOperations)
2783 EVT VT = N->getValueType(0);
2784 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
2786 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2789 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2790 bool LookPassAnd0 = false;
2791 bool LookPassAnd1 = false;
2792 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2794 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2796 if (N0.getOpcode() == ISD::AND) {
2797 if (!N0.getNode()->hasOneUse())
2799 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2800 if (!N01C || N01C->getZExtValue() != 0xFF00)
2802 N0 = N0.getOperand(0);
2803 LookPassAnd0 = true;
2806 if (N1.getOpcode() == ISD::AND) {
2807 if (!N1.getNode()->hasOneUse())
2809 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2810 if (!N11C || N11C->getZExtValue() != 0xFF)
2812 N1 = N1.getOperand(0);
2813 LookPassAnd1 = true;
2816 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2818 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2820 if (!N0.getNode()->hasOneUse() ||
2821 !N1.getNode()->hasOneUse())
2824 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2825 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2828 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
2831 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2832 SDValue N00 = N0->getOperand(0);
2833 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
2834 if (!N00.getNode()->hasOneUse())
2836 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
2837 if (!N001C || N001C->getZExtValue() != 0xFF)
2839 N00 = N00.getOperand(0);
2840 LookPassAnd0 = true;
2843 SDValue N10 = N1->getOperand(0);
2844 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
2845 if (!N10.getNode()->hasOneUse())
2847 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
2848 if (!N101C || N101C->getZExtValue() != 0xFF00)
2850 N10 = N10.getOperand(0);
2851 LookPassAnd1 = true;
2857 // Make sure everything beyond the low halfword is zero since the SRL 16
2858 // will clear the top bits.
2859 unsigned OpSizeInBits = VT.getSizeInBits();
2860 if (DemandHighBits && OpSizeInBits > 16 &&
2861 (!LookPassAnd0 || !LookPassAnd1) &&
2862 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16)))
2865 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00);
2866 if (OpSizeInBits > 16)
2867 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2868 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
2872 /// isBSwapHWordElement - Return true if the specified node is an element
2873 /// that makes up a 32-bit packed halfword byteswap. i.e.
2874 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2875 static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) {
2876 if (!N.getNode()->hasOneUse())
2879 unsigned Opc = N.getOpcode();
2880 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2883 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2888 switch (N1C->getZExtValue()) {
2891 case 0xFF: Num = 0; break;
2892 case 0xFF00: Num = 1; break;
2893 case 0xFF0000: Num = 2; break;
2894 case 0xFF000000: Num = 3; break;
2897 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
2898 SDValue N0 = N.getOperand(0);
2899 if (Opc == ISD::AND) {
2900 if (Num == 0 || Num == 2) {
2902 // (x >> 8) & 0xff0000
2903 if (N0.getOpcode() != ISD::SRL)
2905 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2906 if (!C || C->getZExtValue() != 8)
2909 // (x << 8) & 0xff00
2910 // (x << 8) & 0xff000000
2911 if (N0.getOpcode() != ISD::SHL)
2913 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2914 if (!C || C->getZExtValue() != 8)
2917 } else if (Opc == ISD::SHL) {
2919 // (x & 0xff0000) << 8
2920 if (Num != 0 && Num != 2)
2922 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2923 if (!C || C->getZExtValue() != 8)
2925 } else { // Opc == ISD::SRL
2926 // (x & 0xff00) >> 8
2927 // (x & 0xff000000) >> 8
2928 if (Num != 1 && Num != 3)
2930 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2931 if (!C || C->getZExtValue() != 8)
2938 Parts[Num] = N0.getOperand(0).getNode();
2942 /// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
2943 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2944 /// => (rotl (bswap x), 16)
2945 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
2946 if (!LegalOperations)
2949 EVT VT = N->getValueType(0);
2952 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2955 SmallVector<SDNode*,4> Parts(4, (SDNode*)0);
2957 // (or (or (and), (and)), (or (and), (and)))
2958 // (or (or (or (and), (and)), (and)), (and))
2959 if (N0.getOpcode() != ISD::OR)
2961 SDValue N00 = N0.getOperand(0);
2962 SDValue N01 = N0.getOperand(1);
2964 if (N1.getOpcode() == ISD::OR) {
2965 // (or (or (and), (and)), (or (and), (and)))
2966 SDValue N000 = N00.getOperand(0);
2967 if (!isBSwapHWordElement(N000, Parts))
2970 SDValue N001 = N00.getOperand(1);
2971 if (!isBSwapHWordElement(N001, Parts))
2973 SDValue N010 = N01.getOperand(0);
2974 if (!isBSwapHWordElement(N010, Parts))
2976 SDValue N011 = N01.getOperand(1);
2977 if (!isBSwapHWordElement(N011, Parts))
2980 // (or (or (or (and), (and)), (and)), (and))
2981 if (!isBSwapHWordElement(N1, Parts))
2983 if (!isBSwapHWordElement(N01, Parts))
2985 if (N00.getOpcode() != ISD::OR)
2987 SDValue N000 = N00.getOperand(0);
2988 if (!isBSwapHWordElement(N000, Parts))
2990 SDValue N001 = N00.getOperand(1);
2991 if (!isBSwapHWordElement(N001, Parts))
2995 // Make sure the parts are all coming from the same node.
2996 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
2999 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT,
3000 SDValue(Parts[0],0));
3002 // Result of the bswap should be rotated by 16. If it's not legal, than
3003 // do (x << 16) | (x >> 16).
3004 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
3005 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
3006 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt);
3007 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
3008 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt);
3009 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT,
3010 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt),
3011 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
3014 SDValue DAGCombiner::visitOR(SDNode *N) {
3015 SDValue N0 = N->getOperand(0);
3016 SDValue N1 = N->getOperand(1);
3017 SDValue LL, LR, RL, RR, CC0, CC1;
3018 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3019 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3020 EVT VT = N1.getValueType();
3023 if (VT.isVector()) {
3024 SDValue FoldedVOp = SimplifyVBinOp(N);
3025 if (FoldedVOp.getNode()) return FoldedVOp;
3028 // fold (or x, undef) -> -1
3029 if (!LegalOperations &&
3030 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3031 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
3032 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
3034 // fold (or c1, c2) -> c1|c2
3036 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
3037 // canonicalize constant to RHS
3039 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
3040 // fold (or x, 0) -> x
3041 if (N1C && N1C->isNullValue())
3043 // fold (or x, -1) -> -1
3044 if (N1C && N1C->isAllOnesValue())
3046 // fold (or x, c) -> c iff (x & ~c) == 0
3047 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3050 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
3051 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
3052 if (BSwap.getNode() != 0)
3054 BSwap = MatchBSwapHWordLow(N, N0, N1);
3055 if (BSwap.getNode() != 0)
3059 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
3060 if (ROR.getNode() != 0)
3062 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
3063 // iff (c1 & c2) == 0.
3064 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3065 isa<ConstantSDNode>(N0.getOperand(1))) {
3066 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3067 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
3068 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3069 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3070 N0.getOperand(0), N1),
3071 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
3073 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3074 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3075 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3076 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3078 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
3079 LL.getValueType().isInteger()) {
3080 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
3081 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
3082 if (cast<ConstantSDNode>(LR)->isNullValue() &&
3083 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3084 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
3085 LR.getValueType(), LL, RL);
3086 AddToWorkList(ORNode.getNode());
3087 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
3089 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
3090 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
3091 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
3092 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3093 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
3094 LR.getValueType(), LL, RL);
3095 AddToWorkList(ANDNode.getNode());
3096 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
3099 // canonicalize equivalent to ll == rl
3100 if (LL == RR && LR == RL) {
3101 Op1 = ISD::getSetCCSwappedOperands(Op1);
3104 if (LL == RL && LR == RR) {
3105 bool isInteger = LL.getValueType().isInteger();
3106 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3107 if (Result != ISD::SETCC_INVALID &&
3108 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
3109 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
3114 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
3115 if (N0.getOpcode() == N1.getOpcode()) {
3116 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3117 if (Tmp.getNode()) return Tmp;
3120 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3121 if (N0.getOpcode() == ISD::AND &&
3122 N1.getOpcode() == ISD::AND &&
3123 N0.getOperand(1).getOpcode() == ISD::Constant &&
3124 N1.getOperand(1).getOpcode() == ISD::Constant &&
3125 // Don't increase # computations.
3126 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3127 // We can only do this xform if we know that bits from X that are set in C2
3128 // but not in C1 are already zero. Likewise for Y.
3129 const APInt &LHSMask =
3130 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3131 const APInt &RHSMask =
3132 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
3134 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3135 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3136 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3137 N0.getOperand(0), N1.getOperand(0));
3138 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
3139 DAG.getConstant(LHSMask | RHSMask, VT));
3143 // See if this is some rotate idiom.
3144 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
3145 return SDValue(Rot, 0);
3147 // Simplify the operands using demanded-bits information.
3148 if (!VT.isVector() &&
3149 SimplifyDemandedBits(SDValue(N, 0)))
3150 return SDValue(N, 0);
3155 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
3156 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3157 if (Op.getOpcode() == ISD::AND) {
3158 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3159 Mask = Op.getOperand(1);
3160 Op = Op.getOperand(0);
3166 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3174 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3175 // idioms for rotate, and if the target supports rotation instructions, generate
3177 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
3178 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3179 EVT VT = LHS.getValueType();
3180 if (!TLI.isTypeLegal(VT)) return 0;
3182 // The target must have at least one rotate flavor.
3183 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3184 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3185 if (!HasROTL && !HasROTR) return 0;
3187 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3188 SDValue LHSShift; // The shift.
3189 SDValue LHSMask; // AND value if any.
3190 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3191 return 0; // Not part of a rotate.
3193 SDValue RHSShift; // The shift.
3194 SDValue RHSMask; // AND value if any.
3195 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3196 return 0; // Not part of a rotate.
3198 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3199 return 0; // Not shifting the same value.
3201 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3202 return 0; // Shifts must disagree.
3204 // Canonicalize shl to left side in a shl/srl pair.
3205 if (RHSShift.getOpcode() == ISD::SHL) {
3206 std::swap(LHS, RHS);
3207 std::swap(LHSShift, RHSShift);
3208 std::swap(LHSMask , RHSMask );
3211 unsigned OpSizeInBits = VT.getSizeInBits();
3212 SDValue LHSShiftArg = LHSShift.getOperand(0);
3213 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3214 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3216 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3217 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3218 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3219 RHSShiftAmt.getOpcode() == ISD::Constant) {
3220 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3221 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3222 if ((LShVal + RShVal) != OpSizeInBits)
3225 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3226 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt);
3228 // If there is an AND of either shifted operand, apply it to the result.
3229 if (LHSMask.getNode() || RHSMask.getNode()) {
3230 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3232 if (LHSMask.getNode()) {
3233 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3234 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3236 if (RHSMask.getNode()) {
3237 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3238 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3241 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3244 return Rot.getNode();
3247 // If there is a mask here, and we have a variable shift, we can't be sure
3248 // that we're masking out the right stuff.
3249 if (LHSMask.getNode() || RHSMask.getNode())
3252 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
3253 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
3254 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
3255 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
3256 if (ConstantSDNode *SUBC =
3257 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
3258 if (SUBC->getAPIntValue() == OpSizeInBits) {
3259 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg,
3260 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3265 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
3266 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
3267 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
3268 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
3269 if (ConstantSDNode *SUBC =
3270 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
3271 if (SUBC->getAPIntValue() == OpSizeInBits) {
3272 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg,
3273 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3278 // Look for sign/zext/any-extended or truncate cases:
3279 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3280 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3281 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3282 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3283 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3284 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3285 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3286 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3287 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
3288 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
3289 if (RExtOp0.getOpcode() == ISD::SUB &&
3290 RExtOp0.getOperand(1) == LExtOp0) {
3291 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3293 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3294 // (rotr x, (sub 32, y))
3295 if (ConstantSDNode *SUBC =
3296 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
3297 if (SUBC->getAPIntValue() == OpSizeInBits) {
3298 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3300 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3303 } else if (LExtOp0.getOpcode() == ISD::SUB &&
3304 RExtOp0 == LExtOp0.getOperand(1)) {
3305 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3307 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3308 // (rotl x, (sub 32, y))
3309 if (ConstantSDNode *SUBC =
3310 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
3311 if (SUBC->getAPIntValue() == OpSizeInBits) {
3312 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
3314 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3323 SDValue DAGCombiner::visitXOR(SDNode *N) {
3324 SDValue N0 = N->getOperand(0);
3325 SDValue N1 = N->getOperand(1);
3326 SDValue LHS, RHS, CC;
3327 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3328 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3329 EVT VT = N0.getValueType();
3332 if (VT.isVector()) {
3333 SDValue FoldedVOp = SimplifyVBinOp(N);
3334 if (FoldedVOp.getNode()) return FoldedVOp;
3337 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3338 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3339 return DAG.getConstant(0, VT);
3340 // fold (xor x, undef) -> undef
3341 if (N0.getOpcode() == ISD::UNDEF)
3343 if (N1.getOpcode() == ISD::UNDEF)
3345 // fold (xor c1, c2) -> c1^c2
3347 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3348 // canonicalize constant to RHS
3350 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
3351 // fold (xor x, 0) -> x
3352 if (N1C && N1C->isNullValue())
3355 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
3356 if (RXOR.getNode() != 0)
3359 // fold !(x cc y) -> (x !cc y)
3360 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3361 bool isInt = LHS.getValueType().isInteger();
3362 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3365 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
3366 switch (N0.getOpcode()) {
3368 llvm_unreachable("Unhandled SetCC Equivalent!");
3370 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
3371 case ISD::SELECT_CC:
3372 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
3373 N0.getOperand(3), NotCC);
3378 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3379 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3380 N0.getNode()->hasOneUse() &&
3381 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3382 SDValue V = N0.getOperand(0);
3383 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
3384 DAG.getConstant(1, V.getValueType()));
3385 AddToWorkList(V.getNode());
3386 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
3389 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3390 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3391 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3392 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3393 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3394 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3395 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3396 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3397 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3398 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3401 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3402 if (N1C && N1C->isAllOnesValue() &&
3403 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3404 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3405 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3406 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3407 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3408 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3409 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3410 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3413 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3414 if (N1C && N0.getOpcode() == ISD::XOR) {
3415 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3416 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3418 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
3419 DAG.getConstant(N1C->getAPIntValue() ^
3420 N00C->getAPIntValue(), VT));
3422 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
3423 DAG.getConstant(N1C->getAPIntValue() ^
3424 N01C->getAPIntValue(), VT));
3426 // fold (xor x, x) -> 0
3428 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
3430 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3431 if (N0.getOpcode() == N1.getOpcode()) {
3432 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3433 if (Tmp.getNode()) return Tmp;
3436 // Simplify the expression using non-local knowledge.
3437 if (!VT.isVector() &&
3438 SimplifyDemandedBits(SDValue(N, 0)))
3439 return SDValue(N, 0);
3444 /// visitShiftByConstant - Handle transforms common to the three shifts, when
3445 /// the shift amount is a constant.
3446 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
3447 SDNode *LHS = N->getOperand(0).getNode();
3448 if (!LHS->hasOneUse()) return SDValue();
3450 // We want to pull some binops through shifts, so that we have (and (shift))
3451 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3452 // thing happens with address calculations, so it's important to canonicalize
3454 bool HighBitSet = false; // Can we transform this if the high bit is set?
3456 switch (LHS->getOpcode()) {
3457 default: return SDValue();
3460 HighBitSet = false; // We can only transform sra if the high bit is clear.
3463 HighBitSet = true; // We can only transform sra if the high bit is set.
3466 if (N->getOpcode() != ISD::SHL)
3467 return SDValue(); // only shl(add) not sr[al](add).
3468 HighBitSet = false; // We can only transform sra if the high bit is clear.
3472 // We require the RHS of the binop to be a constant as well.
3473 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3474 if (!BinOpCst) return SDValue();
3476 // FIXME: disable this unless the input to the binop is a shift by a constant.
3477 // If it is not a shift, it pessimizes some common cases like:
3479 // void foo(int *X, int i) { X[i & 1235] = 1; }
3480 // int bar(int *X, int i) { return X[i & 255]; }
3481 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3482 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3483 BinOpLHSVal->getOpcode() != ISD::SRA &&
3484 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3485 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3488 EVT VT = N->getValueType(0);
3490 // If this is a signed shift right, and the high bit is modified by the
3491 // logical operation, do not perform the transformation. The highBitSet
3492 // boolean indicates the value of the high bit of the constant which would
3493 // cause it to be modified for this operation.
3494 if (N->getOpcode() == ISD::SRA) {
3495 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3496 if (BinOpRHSSignSet != HighBitSet)
3500 // Fold the constants, shifting the binop RHS by the shift amount.
3501 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
3503 LHS->getOperand(1), N->getOperand(1));
3505 // Create the new shift.
3506 SDValue NewShift = DAG.getNode(N->getOpcode(),
3507 LHS->getOperand(0).getDebugLoc(),
3508 VT, LHS->getOperand(0), N->getOperand(1));
3510 // Create the new binop.
3511 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
3514 SDValue DAGCombiner::visitSHL(SDNode *N) {
3515 SDValue N0 = N->getOperand(0);
3516 SDValue N1 = N->getOperand(1);
3517 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3518 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3519 EVT VT = N0.getValueType();
3520 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3522 // fold (shl c1, c2) -> c1<<c2
3524 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3525 // fold (shl 0, x) -> 0
3526 if (N0C && N0C->isNullValue())
3528 // fold (shl x, c >= size(x)) -> undef
3529 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3530 return DAG.getUNDEF(VT);
3531 // fold (shl x, 0) -> x
3532 if (N1C && N1C->isNullValue())
3534 // fold (shl undef, x) -> 0
3535 if (N0.getOpcode() == ISD::UNDEF)
3536 return DAG.getConstant(0, VT);
3537 // if (shl x, c) is known to be zero, return 0
3538 if (DAG.MaskedValueIsZero(SDValue(N, 0),
3539 APInt::getAllOnesValue(OpSizeInBits)))
3540 return DAG.getConstant(0, VT);
3541 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
3542 if (N1.getOpcode() == ISD::TRUNCATE &&
3543 N1.getOperand(0).getOpcode() == ISD::AND &&
3544 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3545 SDValue N101 = N1.getOperand(0).getOperand(1);
3546 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3547 EVT TruncVT = N1.getValueType();
3548 SDValue N100 = N1.getOperand(0).getOperand(0);
3549 APInt TruncC = N101C->getAPIntValue();
3550 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3551 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
3552 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
3553 DAG.getNode(ISD::TRUNCATE,
3556 DAG.getConstant(TruncC, TruncVT)));
3560 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3561 return SDValue(N, 0);
3563 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
3564 if (N1C && N0.getOpcode() == ISD::SHL &&
3565 N0.getOperand(1).getOpcode() == ISD::Constant) {
3566 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3567 uint64_t c2 = N1C->getZExtValue();
3568 if (c1 + c2 >= OpSizeInBits)
3569 return DAG.getConstant(0, VT);
3570 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3571 DAG.getConstant(c1 + c2, N1.getValueType()));
3574 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
3575 // For this to be valid, the second form must not preserve any of the bits
3576 // that are shifted out by the inner shift in the first form. This means
3577 // the outer shift size must be >= the number of bits added by the ext.
3578 // As a corollary, we don't care what kind of ext it is.
3579 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3580 N0.getOpcode() == ISD::ANY_EXTEND ||
3581 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3582 N0.getOperand(0).getOpcode() == ISD::SHL &&
3583 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3585 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3586 uint64_t c2 = N1C->getZExtValue();
3587 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3588 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3589 if (c2 >= OpSizeInBits - InnerShiftSize) {
3590 if (c1 + c2 >= OpSizeInBits)
3591 return DAG.getConstant(0, VT);
3592 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
3593 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT,
3594 N0.getOperand(0)->getOperand(0)),
3595 DAG.getConstant(c1 + c2, N1.getValueType()));
3599 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3600 // (and (srl x, (sub c1, c2), MASK)
3601 // Only fold this if the inner shift has no other uses -- if it does, folding
3602 // this will increase the total number of instructions.
3603 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
3604 N0.getOperand(1).getOpcode() == ISD::Constant) {
3605 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3606 if (c1 < VT.getSizeInBits()) {
3607 uint64_t c2 = N1C->getZExtValue();
3608 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3609 VT.getSizeInBits() - c1);
3612 Mask = Mask.shl(c2-c1);
3613 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3614 DAG.getConstant(c2-c1, N1.getValueType()));
3616 Mask = Mask.lshr(c1-c2);
3617 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3618 DAG.getConstant(c1-c2, N1.getValueType()));
3620 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift,
3621 DAG.getConstant(Mask, VT));
3624 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
3625 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3626 SDValue HiBitsMask =
3627 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3628 VT.getSizeInBits() -
3629 N1C->getZExtValue()),
3631 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3636 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3637 if (NewSHL.getNode())
3644 SDValue DAGCombiner::visitSRA(SDNode *N) {
3645 SDValue N0 = N->getOperand(0);
3646 SDValue N1 = N->getOperand(1);
3647 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3648 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3649 EVT VT = N0.getValueType();
3650 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3652 // fold (sra c1, c2) -> (sra c1, c2)
3654 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3655 // fold (sra 0, x) -> 0
3656 if (N0C && N0C->isNullValue())
3658 // fold (sra -1, x) -> -1
3659 if (N0C && N0C->isAllOnesValue())
3661 // fold (sra x, (setge c, size(x))) -> undef
3662 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3663 return DAG.getUNDEF(VT);
3664 // fold (sra x, 0) -> x
3665 if (N1C && N1C->isNullValue())
3667 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3669 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3670 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3671 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3673 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3674 ExtVT, VT.getVectorNumElements());
3675 if ((!LegalOperations ||
3676 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3677 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3678 N0.getOperand(0), DAG.getValueType(ExtVT));
3681 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3682 if (N1C && N0.getOpcode() == ISD::SRA) {
3683 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3684 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3685 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3686 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3687 DAG.getConstant(Sum, N1C->getValueType(0)));
3691 // fold (sra (shl X, m), (sub result_size, n))
3692 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3693 // result_size - n != m.
3694 // If truncate is free for the target sext(shl) is likely to result in better
3696 if (N0.getOpcode() == ISD::SHL) {
3697 // Get the two constanst of the shifts, CN0 = m, CN = n.
3698 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3700 // Determine what the truncate's result bitsize and type would be.
3702 EVT::getIntegerVT(*DAG.getContext(),
3703 OpSizeInBits - N1C->getZExtValue());
3704 // Determine the residual right-shift amount.
3705 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3707 // If the shift is not a no-op (in which case this should be just a sign
3708 // extend already), the truncated to type is legal, sign_extend is legal
3709 // on that type, and the truncate to that type is both legal and free,
3710 // perform the transform.
3711 if ((ShiftAmt > 0) &&
3712 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3713 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3714 TLI.isTruncateFree(VT, TruncVT)) {
3716 SDValue Amt = DAG.getConstant(ShiftAmt,
3717 getShiftAmountTy(N0.getOperand(0).getValueType()));
3718 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3719 N0.getOperand(0), Amt);
3720 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3722 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3723 N->getValueType(0), Trunc);
3728 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3729 if (N1.getOpcode() == ISD::TRUNCATE &&
3730 N1.getOperand(0).getOpcode() == ISD::AND &&
3731 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3732 SDValue N101 = N1.getOperand(0).getOperand(1);
3733 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3734 EVT TruncVT = N1.getValueType();
3735 SDValue N100 = N1.getOperand(0).getOperand(0);
3736 APInt TruncC = N101C->getAPIntValue();
3737 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3738 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3739 DAG.getNode(ISD::AND, N->getDebugLoc(),
3741 DAG.getNode(ISD::TRUNCATE,
3744 DAG.getConstant(TruncC, TruncVT)));
3748 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2))
3749 // if c1 is equal to the number of bits the trunc removes
3750 if (N0.getOpcode() == ISD::TRUNCATE &&
3751 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3752 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3753 N0.getOperand(0).hasOneUse() &&
3754 N0.getOperand(0).getOperand(1).hasOneUse() &&
3755 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3756 EVT LargeVT = N0.getOperand(0).getValueType();
3757 ConstantSDNode *LargeShiftAmt =
3758 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3760 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits ==
3761 LargeShiftAmt->getZExtValue()) {
3763 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(),
3764 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3765 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT,
3766 N0.getOperand(0).getOperand(0), Amt);
3767 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA);
3771 // Simplify, based on bits shifted out of the LHS.
3772 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3773 return SDValue(N, 0);
3776 // If the sign bit is known to be zero, switch this to a SRL.
3777 if (DAG.SignBitIsZero(N0))
3778 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3781 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3782 if (NewSRA.getNode())
3789 SDValue DAGCombiner::visitSRL(SDNode *N) {
3790 SDValue N0 = N->getOperand(0);
3791 SDValue N1 = N->getOperand(1);
3792 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3793 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3794 EVT VT = N0.getValueType();
3795 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3797 // fold (srl c1, c2) -> c1 >>u c2
3799 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3800 // fold (srl 0, x) -> 0
3801 if (N0C && N0C->isNullValue())
3803 // fold (srl x, c >= size(x)) -> undef
3804 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3805 return DAG.getUNDEF(VT);
3806 // fold (srl x, 0) -> x
3807 if (N1C && N1C->isNullValue())
3809 // if (srl x, c) is known to be zero, return 0
3810 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3811 APInt::getAllOnesValue(OpSizeInBits)))
3812 return DAG.getConstant(0, VT);
3814 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3815 if (N1C && N0.getOpcode() == ISD::SRL &&
3816 N0.getOperand(1).getOpcode() == ISD::Constant) {
3817 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3818 uint64_t c2 = N1C->getZExtValue();
3819 if (c1 + c2 >= OpSizeInBits)
3820 return DAG.getConstant(0, VT);
3821 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3822 DAG.getConstant(c1 + c2, N1.getValueType()));
3825 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3826 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3827 N0.getOperand(0).getOpcode() == ISD::SRL &&
3828 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3830 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3831 uint64_t c2 = N1C->getZExtValue();
3832 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3833 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3834 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3835 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
3836 if (c1 + OpSizeInBits == InnerShiftSize) {
3837 if (c1 + c2 >= InnerShiftSize)
3838 return DAG.getConstant(0, VT);
3839 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
3840 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3841 N0.getOperand(0)->getOperand(0),
3842 DAG.getConstant(c1 + c2, ShiftCountVT)));
3846 // fold (srl (shl x, c), c) -> (and x, cst2)
3847 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3848 N0.getValueSizeInBits() <= 64) {
3849 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3850 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3851 DAG.getConstant(~0ULL >> ShAmt, VT));
3855 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3856 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3857 // Shifting in all undef bits?
3858 EVT SmallVT = N0.getOperand(0).getValueType();
3859 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3860 return DAG.getUNDEF(VT);
3862 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3863 uint64_t ShiftAmt = N1C->getZExtValue();
3864 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3866 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
3867 AddToWorkList(SmallShift.getNode());
3868 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3872 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3873 // bit, which is unmodified by sra.
3874 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3875 if (N0.getOpcode() == ISD::SRA)
3876 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3879 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3880 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3881 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3882 APInt KnownZero, KnownOne;
3883 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne);
3885 // If any of the input bits are KnownOne, then the input couldn't be all
3886 // zeros, thus the result of the srl will always be zero.
3887 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3889 // If all of the bits input the to ctlz node are known to be zero, then
3890 // the result of the ctlz is "32" and the result of the shift is one.
3891 APInt UnknownBits = ~KnownZero;
3892 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3894 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3895 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3896 // Okay, we know that only that the single bit specified by UnknownBits
3897 // could be set on input to the CTLZ node. If this bit is set, the SRL
3898 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3899 // to an SRL/XOR pair, which is likely to simplify more.
3900 unsigned ShAmt = UnknownBits.countTrailingZeros();
3901 SDValue Op = N0.getOperand(0);
3904 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3905 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
3906 AddToWorkList(Op.getNode());
3909 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3910 Op, DAG.getConstant(1, VT));
3914 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3915 if (N1.getOpcode() == ISD::TRUNCATE &&
3916 N1.getOperand(0).getOpcode() == ISD::AND &&
3917 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3918 SDValue N101 = N1.getOperand(0).getOperand(1);
3919 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3920 EVT TruncVT = N1.getValueType();
3921 SDValue N100 = N1.getOperand(0).getOperand(0);
3922 APInt TruncC = N101C->getAPIntValue();
3923 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3924 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3925 DAG.getNode(ISD::AND, N->getDebugLoc(),
3927 DAG.getNode(ISD::TRUNCATE,
3930 DAG.getConstant(TruncC, TruncVT)));
3934 // fold operands of srl based on knowledge that the low bits are not
3936 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3937 return SDValue(N, 0);
3940 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3941 if (NewSRL.getNode())
3945 // Attempt to convert a srl of a load into a narrower zero-extending load.
3946 SDValue NarrowLoad = ReduceLoadWidth(N);
3947 if (NarrowLoad.getNode())
3950 // Here is a common situation. We want to optimize:
3953 // %b = and i32 %a, 2
3954 // %c = srl i32 %b, 1
3955 // brcond i32 %c ...
3961 // %c = setcc eq %b, 0
3964 // However when after the source operand of SRL is optimized into AND, the SRL
3965 // itself may not be optimized further. Look for it and add the BRCOND into
3967 if (N->hasOneUse()) {
3968 SDNode *Use = *N->use_begin();
3969 if (Use->getOpcode() == ISD::BRCOND)
3971 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3972 // Also look pass the truncate.
3973 Use = *Use->use_begin();
3974 if (Use->getOpcode() == ISD::BRCOND)
3982 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
3983 SDValue N0 = N->getOperand(0);
3984 EVT VT = N->getValueType(0);
3986 // fold (ctlz c1) -> c2
3987 if (isa<ConstantSDNode>(N0))
3988 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3992 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
3993 SDValue N0 = N->getOperand(0);
3994 EVT VT = N->getValueType(0);
3996 // fold (ctlz_zero_undef c1) -> c2
3997 if (isa<ConstantSDNode>(N0))
3998 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
4002 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
4003 SDValue N0 = N->getOperand(0);
4004 EVT VT = N->getValueType(0);
4006 // fold (cttz c1) -> c2
4007 if (isa<ConstantSDNode>(N0))
4008 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
4012 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
4013 SDValue N0 = N->getOperand(0);
4014 EVT VT = N->getValueType(0);
4016 // fold (cttz_zero_undef c1) -> c2
4017 if (isa<ConstantSDNode>(N0))
4018 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
4022 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
4023 SDValue N0 = N->getOperand(0);
4024 EVT VT = N->getValueType(0);
4026 // fold (ctpop c1) -> c2
4027 if (isa<ConstantSDNode>(N0))
4028 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
4032 SDValue DAGCombiner::visitSELECT(SDNode *N) {
4033 SDValue N0 = N->getOperand(0);
4034 SDValue N1 = N->getOperand(1);
4035 SDValue N2 = N->getOperand(2);
4036 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4037 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4038 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
4039 EVT VT = N->getValueType(0);
4040 EVT VT0 = N0.getValueType();
4042 // fold (select C, X, X) -> X
4045 // fold (select true, X, Y) -> X
4046 if (N0C && !N0C->isNullValue())
4048 // fold (select false, X, Y) -> Y
4049 if (N0C && N0C->isNullValue())
4051 // fold (select C, 1, X) -> (or C, X)
4052 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
4053 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
4054 // fold (select C, 0, 1) -> (xor C, 1)
4055 if (VT.isInteger() &&
4058 TLI.getBooleanContents(false) ==
4059 TargetLowering::ZeroOrOneBooleanContent)) &&
4060 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
4063 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
4064 N0, DAG.getConstant(1, VT0));
4065 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
4066 N0, DAG.getConstant(1, VT0));
4067 AddToWorkList(XORNode.getNode());
4069 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
4070 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
4072 // fold (select C, 0, X) -> (and (not C), X)
4073 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
4074 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
4075 AddToWorkList(NOTNode.getNode());
4076 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
4078 // fold (select C, X, 1) -> (or (not C), X)
4079 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
4080 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
4081 AddToWorkList(NOTNode.getNode());
4082 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
4084 // fold (select C, X, 0) -> (and C, X)
4085 if (VT == MVT::i1 && N2C && N2C->isNullValue())
4086 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
4087 // fold (select X, X, Y) -> (or X, Y)
4088 // fold (select X, 1, Y) -> (or X, Y)
4089 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
4090 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
4091 // fold (select X, Y, X) -> (and X, Y)
4092 // fold (select X, Y, 0) -> (and X, Y)
4093 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
4094 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
4096 // If we can fold this based on the true/false value, do so.
4097 if (SimplifySelectOps(N, N1, N2))
4098 return SDValue(N, 0); // Don't revisit N.
4100 // fold selects based on a setcc into other things, such as min/max/abs
4101 if (N0.getOpcode() == ISD::SETCC) {
4103 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
4104 // having to say they don't support SELECT_CC on every type the DAG knows
4105 // about, since there is no way to mark an opcode illegal at all value types
4106 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
4107 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
4108 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
4109 N0.getOperand(0), N0.getOperand(1),
4110 N1, N2, N0.getOperand(2));
4111 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
4117 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
4118 SDValue N0 = N->getOperand(0);
4119 SDValue N1 = N->getOperand(1);
4120 SDValue N2 = N->getOperand(2);
4121 SDValue N3 = N->getOperand(3);
4122 SDValue N4 = N->getOperand(4);
4123 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
4125 // fold select_cc lhs, rhs, x, x, cc -> x
4129 // Determine if the condition we're dealing with is constant
4130 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
4131 N0, N1, CC, N->getDebugLoc(), false);
4132 if (SCC.getNode()) AddToWorkList(SCC.getNode());
4134 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
4135 if (!SCCC->isNullValue())
4136 return N2; // cond always true -> true val
4138 return N3; // cond always false -> false val
4141 // Fold to a simpler select_cc
4142 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
4143 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
4144 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
4147 // If we can fold this based on the true/false value, do so.
4148 if (SimplifySelectOps(N, N2, N3))
4149 return SDValue(N, 0); // Don't revisit N.
4151 // fold select_cc into other things, such as min/max/abs
4152 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
4155 SDValue DAGCombiner::visitSETCC(SDNode *N) {
4156 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
4157 cast<CondCodeSDNode>(N->getOperand(2))->get(),
4161 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
4162 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
4163 // transformation. Returns true if extension are possible and the above
4164 // mentioned transformation is profitable.
4165 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
4167 SmallVector<SDNode*, 4> &ExtendNodes,
4168 const TargetLowering &TLI) {
4169 bool HasCopyToRegUses = false;
4170 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
4171 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
4172 UE = N0.getNode()->use_end();
4177 if (UI.getUse().getResNo() != N0.getResNo())
4179 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
4180 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
4181 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
4182 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
4183 // Sign bits will be lost after a zext.
4186 for (unsigned i = 0; i != 2; ++i) {
4187 SDValue UseOp = User->getOperand(i);
4190 if (!isa<ConstantSDNode>(UseOp))
4195 ExtendNodes.push_back(User);
4198 // If truncates aren't free and there are users we can't
4199 // extend, it isn't worthwhile.
4202 // Remember if this value is live-out.
4203 if (User->getOpcode() == ISD::CopyToReg)
4204 HasCopyToRegUses = true;
4207 if (HasCopyToRegUses) {
4208 bool BothLiveOut = false;
4209 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4211 SDUse &Use = UI.getUse();
4212 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
4218 // Both unextended and extended values are live out. There had better be
4219 // a good reason for the transformation.
4220 return ExtendNodes.size();
4225 void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
4226 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
4227 ISD::NodeType ExtType) {
4228 // Extend SetCC uses if necessary.
4229 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
4230 SDNode *SetCC = SetCCs[i];
4231 SmallVector<SDValue, 4> Ops;
4233 for (unsigned j = 0; j != 2; ++j) {
4234 SDValue SOp = SetCC->getOperand(j);
4236 Ops.push_back(ExtLoad);
4238 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
4241 Ops.push_back(SetCC->getOperand(2));
4242 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
4243 &Ops[0], Ops.size()));
4247 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
4248 SDValue N0 = N->getOperand(0);
4249 EVT VT = N->getValueType(0);
4251 // fold (sext c1) -> c1
4252 if (isa<ConstantSDNode>(N0))
4253 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
4255 // fold (sext (sext x)) -> (sext x)
4256 // fold (sext (aext x)) -> (sext x)
4257 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4258 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
4261 if (N0.getOpcode() == ISD::TRUNCATE) {
4262 // fold (sext (truncate (load x))) -> (sext (smaller load x))
4263 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
4264 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4265 if (NarrowLoad.getNode()) {
4266 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4267 if (NarrowLoad.getNode() != N0.getNode()) {
4268 CombineTo(N0.getNode(), NarrowLoad);
4269 // CombineTo deleted the truncate, if needed, but not what's under it.
4272 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4275 // See if the value being truncated is already sign extended. If so, just
4276 // eliminate the trunc/sext pair.
4277 SDValue Op = N0.getOperand(0);
4278 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
4279 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
4280 unsigned DestBits = VT.getScalarType().getSizeInBits();
4281 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
4283 if (OpBits == DestBits) {
4284 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
4285 // bits, it is already ready.
4286 if (NumSignBits > DestBits-MidBits)
4288 } else if (OpBits < DestBits) {
4289 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
4290 // bits, just sext from i32.
4291 if (NumSignBits > OpBits-MidBits)
4292 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
4294 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
4295 // bits, just truncate to i32.
4296 if (NumSignBits > OpBits-MidBits)
4297 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4300 // fold (sext (truncate x)) -> (sextinreg x).
4301 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
4302 N0.getValueType())) {
4303 if (OpBits < DestBits)
4304 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
4305 else if (OpBits > DestBits)
4306 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
4307 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
4308 DAG.getValueType(N0.getValueType()));
4312 // fold (sext (load x)) -> (sext (truncate (sextload x)))
4313 // None of the supported targets knows how to perform load and sign extend
4314 // on vectors in one instruction. We only perform this transformation on
4316 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4317 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4318 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4319 bool DoXform = true;
4320 SmallVector<SDNode*, 4> SetCCs;
4321 if (!N0.hasOneUse())
4322 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4324 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4325 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4327 LN0->getBasePtr(), LN0->getPointerInfo(),
4329 LN0->isVolatile(), LN0->isNonTemporal(),
4330 LN0->getAlignment());
4331 CombineTo(N, ExtLoad);
4332 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4333 N0.getValueType(), ExtLoad);
4334 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4335 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4337 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4341 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
4342 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
4343 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4344 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4345 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4346 EVT MemVT = LN0->getMemoryVT();
4347 if ((!LegalOperations && !LN0->isVolatile()) ||
4348 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
4349 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4351 LN0->getBasePtr(), LN0->getPointerInfo(),
4353 LN0->isVolatile(), LN0->isNonTemporal(),
4354 LN0->getAlignment());
4355 CombineTo(N, ExtLoad);
4356 CombineTo(N0.getNode(),
4357 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4358 N0.getValueType(), ExtLoad),
4359 ExtLoad.getValue(1));
4360 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4364 // fold (sext (and/or/xor (load x), cst)) ->
4365 // (and/or/xor (sextload x), (sext cst))
4366 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4367 N0.getOpcode() == ISD::XOR) &&
4368 isa<LoadSDNode>(N0.getOperand(0)) &&
4369 N0.getOperand(1).getOpcode() == ISD::Constant &&
4370 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4371 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4372 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4373 if (LN0->getExtensionType() != ISD::ZEXTLOAD) {
4374 bool DoXform = true;
4375 SmallVector<SDNode*, 4> SetCCs;
4376 if (!N0.hasOneUse())
4377 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4380 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT,
4381 LN0->getChain(), LN0->getBasePtr(),
4382 LN0->getPointerInfo(),
4385 LN0->isNonTemporal(),
4386 LN0->getAlignment());
4387 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4388 Mask = Mask.sext(VT.getSizeInBits());
4389 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4390 ExtLoad, DAG.getConstant(Mask, VT));
4391 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4392 N0.getOperand(0).getDebugLoc(),
4393 N0.getOperand(0).getValueType(), ExtLoad);
4395 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4396 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4398 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4403 if (N0.getOpcode() == ISD::SETCC) {
4404 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
4405 // Only do this before legalize for now.
4406 if (VT.isVector() && !LegalOperations) {
4407 EVT N0VT = N0.getOperand(0).getValueType();
4408 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
4409 // of the same size as the compared operands. Only optimize sext(setcc())
4410 // if this is the case.
4411 EVT SVT = TLI.getSetCCResultType(N0VT);
4413 // We know that the # elements of the results is the same as the
4414 // # elements of the compare (and the # elements of the compare result
4415 // for that matter). Check to see that they are the same size. If so,
4416 // we know that the element size of the sext'd result matches the
4417 // element size of the compare operands.
4418 if (VT.getSizeInBits() == SVT.getSizeInBits())
4419 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4421 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4422 // If the desired elements are smaller or larger than the source
4423 // elements we can use a matching integer vector type and then
4424 // truncate/sign extend
4425 EVT MatchingElementType =
4426 EVT::getIntegerVT(*DAG.getContext(),
4427 N0VT.getScalarType().getSizeInBits());
4428 EVT MatchingVectorType =
4429 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4430 N0VT.getVectorNumElements());
4432 if (SVT == MatchingVectorType) {
4433 SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType,
4434 N0.getOperand(0), N0.getOperand(1),
4435 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4436 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4440 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
4441 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
4443 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
4445 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4446 NegOne, DAG.getConstant(0, VT),
4447 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4448 if (SCC.getNode()) return SCC;
4449 if (!LegalOperations ||
4450 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
4451 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4452 DAG.getSetCC(N->getDebugLoc(),
4453 TLI.getSetCCResultType(VT),
4454 N0.getOperand(0), N0.getOperand(1),
4455 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4456 NegOne, DAG.getConstant(0, VT));
4459 // fold (sext x) -> (zext x) if the sign bit is known zero.
4460 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
4461 DAG.SignBitIsZero(N0))
4462 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4467 // isTruncateOf - If N is a truncate of some other value, return true, record
4468 // the value being truncated in Op and which of Op's bits are zero in KnownZero.
4469 // This function computes KnownZero to avoid a duplicated call to
4470 // ComputeMaskedBits in the caller.
4471 static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
4474 if (N->getOpcode() == ISD::TRUNCATE) {
4475 Op = N->getOperand(0);
4476 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4480 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
4481 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
4484 SDValue Op0 = N->getOperand(0);
4485 SDValue Op1 = N->getOperand(1);
4486 assert(Op0.getValueType() == Op1.getValueType());
4488 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0);
4489 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1);
4490 if (COp0 && COp0->isNullValue())
4492 else if (COp1 && COp1->isNullValue())
4497 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
4499 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
4505 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
4506 SDValue N0 = N->getOperand(0);
4507 EVT VT = N->getValueType(0);
4509 // fold (zext c1) -> c1
4510 if (isa<ConstantSDNode>(N0))
4511 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4512 // fold (zext (zext x)) -> (zext x)
4513 // fold (zext (aext x)) -> (zext x)
4514 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4515 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
4518 // fold (zext (truncate x)) -> (zext x) or
4519 // (zext (truncate x)) -> (truncate x)
4520 // This is valid when the truncated bits of x are already zero.
4521 // FIXME: We should extend this to work for vectors too.
4524 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
4525 APInt TruncatedBits =
4526 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
4527 APInt(Op.getValueSizeInBits(), 0) :
4528 APInt::getBitsSet(Op.getValueSizeInBits(),
4529 N0.getValueSizeInBits(),
4530 std::min(Op.getValueSizeInBits(),
4531 VT.getSizeInBits()));
4532 if (TruncatedBits == (KnownZero & TruncatedBits)) {
4533 if (VT.bitsGT(Op.getValueType()))
4534 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op);
4535 if (VT.bitsLT(Op.getValueType()))
4536 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4542 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4543 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
4544 if (N0.getOpcode() == ISD::TRUNCATE) {
4545 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4546 if (NarrowLoad.getNode()) {
4547 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4548 if (NarrowLoad.getNode() != N0.getNode()) {
4549 CombineTo(N0.getNode(), NarrowLoad);
4550 // CombineTo deleted the truncate, if needed, but not what's under it.
4553 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4557 // fold (zext (truncate x)) -> (and x, mask)
4558 if (N0.getOpcode() == ISD::TRUNCATE &&
4559 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
4561 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4562 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
4563 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4564 if (NarrowLoad.getNode()) {
4565 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4566 if (NarrowLoad.getNode() != N0.getNode()) {
4567 CombineTo(N0.getNode(), NarrowLoad);
4568 // CombineTo deleted the truncate, if needed, but not what's under it.
4571 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4574 SDValue Op = N0.getOperand(0);
4575 if (Op.getValueType().bitsLT(VT)) {
4576 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
4577 AddToWorkList(Op.getNode());
4578 } else if (Op.getValueType().bitsGT(VT)) {
4579 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4580 AddToWorkList(Op.getNode());
4582 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
4583 N0.getValueType().getScalarType());
4586 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
4587 // if either of the casts is not free.
4588 if (N0.getOpcode() == ISD::AND &&
4589 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4590 N0.getOperand(1).getOpcode() == ISD::Constant &&
4591 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4592 N0.getValueType()) ||
4593 !TLI.isZExtFree(N0.getValueType(), VT))) {
4594 SDValue X = N0.getOperand(0).getOperand(0);
4595 if (X.getValueType().bitsLT(VT)) {
4596 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
4597 } else if (X.getValueType().bitsGT(VT)) {
4598 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4600 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4601 Mask = Mask.zext(VT.getSizeInBits());
4602 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4603 X, DAG.getConstant(Mask, VT));
4606 // fold (zext (load x)) -> (zext (truncate (zextload x)))
4607 // None of the supported targets knows how to perform load and vector_zext
4608 // on vectors in one instruction. We only perform this transformation on
4610 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4611 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4612 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4613 bool DoXform = true;
4614 SmallVector<SDNode*, 4> SetCCs;
4615 if (!N0.hasOneUse())
4616 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4618 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4619 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4621 LN0->getBasePtr(), LN0->getPointerInfo(),
4623 LN0->isVolatile(), LN0->isNonTemporal(),
4624 LN0->getAlignment());
4625 CombineTo(N, ExtLoad);
4626 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4627 N0.getValueType(), ExtLoad);
4628 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4630 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4632 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4636 // fold (zext (and/or/xor (load x), cst)) ->
4637 // (and/or/xor (zextload x), (zext cst))
4638 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4639 N0.getOpcode() == ISD::XOR) &&
4640 isa<LoadSDNode>(N0.getOperand(0)) &&
4641 N0.getOperand(1).getOpcode() == ISD::Constant &&
4642 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4643 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4644 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4645 if (LN0->getExtensionType() != ISD::SEXTLOAD) {
4646 bool DoXform = true;
4647 SmallVector<SDNode*, 4> SetCCs;
4648 if (!N0.hasOneUse())
4649 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4652 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT,
4653 LN0->getChain(), LN0->getBasePtr(),
4654 LN0->getPointerInfo(),
4657 LN0->isNonTemporal(),
4658 LN0->getAlignment());
4659 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4660 Mask = Mask.zext(VT.getSizeInBits());
4661 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4662 ExtLoad, DAG.getConstant(Mask, VT));
4663 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4664 N0.getOperand(0).getDebugLoc(),
4665 N0.getOperand(0).getValueType(), ExtLoad);
4667 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4668 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4670 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4675 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
4676 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
4677 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4678 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4679 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4680 EVT MemVT = LN0->getMemoryVT();
4681 if ((!LegalOperations && !LN0->isVolatile()) ||
4682 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
4683 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4685 LN0->getBasePtr(), LN0->getPointerInfo(),
4687 LN0->isVolatile(), LN0->isNonTemporal(),
4688 LN0->getAlignment());
4689 CombineTo(N, ExtLoad);
4690 CombineTo(N0.getNode(),
4691 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
4693 ExtLoad.getValue(1));
4694 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4698 if (N0.getOpcode() == ISD::SETCC) {
4699 if (!LegalOperations && VT.isVector()) {
4700 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4701 // Only do this before legalize for now.
4702 EVT N0VT = N0.getOperand(0).getValueType();
4703 EVT EltVT = VT.getVectorElementType();
4704 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
4705 DAG.getConstant(1, EltVT));
4706 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4707 // We know that the # elements of the results is the same as the
4708 // # elements of the compare (and the # elements of the compare result
4709 // for that matter). Check to see that they are the same size. If so,
4710 // we know that the element size of the sext'd result matches the
4711 // element size of the compare operands.
4712 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4713 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4715 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4716 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4717 &OneOps[0], OneOps.size()));
4719 // If the desired elements are smaller or larger than the source
4720 // elements we can use a matching integer vector type and then
4721 // truncate/sign extend
4722 EVT MatchingElementType =
4723 EVT::getIntegerVT(*DAG.getContext(),
4724 N0VT.getScalarType().getSizeInBits());
4725 EVT MatchingVectorType =
4726 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4727 N0VT.getVectorNumElements());
4729 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4731 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4732 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4733 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
4734 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4735 &OneOps[0], OneOps.size()));
4738 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4740 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4741 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4742 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4743 if (SCC.getNode()) return SCC;
4746 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
4747 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4748 isa<ConstantSDNode>(N0.getOperand(1)) &&
4749 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4751 SDValue ShAmt = N0.getOperand(1);
4752 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4753 if (N0.getOpcode() == ISD::SHL) {
4754 SDValue InnerZExt = N0.getOperand(0);
4755 // If the original shl may be shifting out bits, do not perform this
4757 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
4758 InnerZExt.getOperand(0).getValueType().getSizeInBits();
4759 if (ShAmtVal > KnownZeroBits)
4763 DebugLoc DL = N->getDebugLoc();
4765 // Ensure that the shift amount is wide enough for the shifted value.
4766 if (VT.getSizeInBits() >= 256)
4767 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
4769 return DAG.getNode(N0.getOpcode(), DL, VT,
4770 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4777 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
4778 SDValue N0 = N->getOperand(0);
4779 EVT VT = N->getValueType(0);
4781 // fold (aext c1) -> c1
4782 if (isa<ConstantSDNode>(N0))
4783 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
4784 // fold (aext (aext x)) -> (aext x)
4785 // fold (aext (zext x)) -> (zext x)
4786 // fold (aext (sext x)) -> (sext x)
4787 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4788 N0.getOpcode() == ISD::ZERO_EXTEND ||
4789 N0.getOpcode() == ISD::SIGN_EXTEND)
4790 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
4792 // fold (aext (truncate (load x))) -> (aext (smaller load x))
4793 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4794 if (N0.getOpcode() == ISD::TRUNCATE) {
4795 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4796 if (NarrowLoad.getNode()) {
4797 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4798 if (NarrowLoad.getNode() != N0.getNode()) {
4799 CombineTo(N0.getNode(), NarrowLoad);
4800 // CombineTo deleted the truncate, if needed, but not what's under it.
4803 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4807 // fold (aext (truncate x))
4808 if (N0.getOpcode() == ISD::TRUNCATE) {
4809 SDValue TruncOp = N0.getOperand(0);
4810 if (TruncOp.getValueType() == VT)
4811 return TruncOp; // x iff x size == zext size.
4812 if (TruncOp.getValueType().bitsGT(VT))
4813 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
4814 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
4817 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
4818 // if the trunc is not free.
4819 if (N0.getOpcode() == ISD::AND &&
4820 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4821 N0.getOperand(1).getOpcode() == ISD::Constant &&
4822 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4823 N0.getValueType())) {
4824 SDValue X = N0.getOperand(0).getOperand(0);
4825 if (X.getValueType().bitsLT(VT)) {
4826 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
4827 } else if (X.getValueType().bitsGT(VT)) {
4828 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
4830 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4831 Mask = Mask.zext(VT.getSizeInBits());
4832 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4833 X, DAG.getConstant(Mask, VT));
4836 // fold (aext (load x)) -> (aext (truncate (extload x)))
4837 // None of the supported targets knows how to perform load and any_ext
4838 // on vectors in one instruction. We only perform this transformation on
4840 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4841 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4842 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4843 bool DoXform = true;
4844 SmallVector<SDNode*, 4> SetCCs;
4845 if (!N0.hasOneUse())
4846 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4848 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4849 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4851 LN0->getBasePtr(), LN0->getPointerInfo(),
4853 LN0->isVolatile(), LN0->isNonTemporal(),
4854 LN0->getAlignment());
4855 CombineTo(N, ExtLoad);
4856 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4857 N0.getValueType(), ExtLoad);
4858 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4859 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4861 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4865 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
4866 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4867 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
4868 if (N0.getOpcode() == ISD::LOAD &&
4869 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4871 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4872 EVT MemVT = LN0->getMemoryVT();
4873 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
4874 VT, LN0->getChain(), LN0->getBasePtr(),
4875 LN0->getPointerInfo(), MemVT,
4876 LN0->isVolatile(), LN0->isNonTemporal(),
4877 LN0->getAlignment());
4878 CombineTo(N, ExtLoad);
4879 CombineTo(N0.getNode(),
4880 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4881 N0.getValueType(), ExtLoad),
4882 ExtLoad.getValue(1));
4883 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4886 if (N0.getOpcode() == ISD::SETCC) {
4887 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
4888 // Only do this before legalize for now.
4889 if (VT.isVector() && !LegalOperations) {
4890 EVT N0VT = N0.getOperand(0).getValueType();
4891 // We know that the # elements of the results is the same as the
4892 // # elements of the compare (and the # elements of the compare result
4893 // for that matter). Check to see that they are the same size. If so,
4894 // we know that the element size of the sext'd result matches the
4895 // element size of the compare operands.
4896 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4897 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4899 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4900 // If the desired elements are smaller or larger than the source
4901 // elements we can use a matching integer vector type and then
4902 // truncate/sign extend
4904 EVT MatchingElementType =
4905 EVT::getIntegerVT(*DAG.getContext(),
4906 N0VT.getScalarType().getSizeInBits());
4907 EVT MatchingVectorType =
4908 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4909 N0VT.getVectorNumElements());
4911 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4913 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4914 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4918 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4920 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4921 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4922 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4930 /// GetDemandedBits - See if the specified operand can be simplified with the
4931 /// knowledge that only the bits specified by Mask are used. If so, return the
4932 /// simpler operand, otherwise return a null SDValue.
4933 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4934 switch (V.getOpcode()) {
4936 case ISD::Constant: {
4937 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
4938 assert(CV != 0 && "Const value should be ConstSDNode.");
4939 const APInt &CVal = CV->getAPIntValue();
4940 APInt NewVal = CVal & Mask;
4941 if (NewVal != CVal) {
4942 return DAG.getConstant(NewVal, V.getValueType());
4948 // If the LHS or RHS don't contribute bits to the or, drop them.
4949 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4950 return V.getOperand(1);
4951 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4952 return V.getOperand(0);
4955 // Only look at single-use SRLs.
4956 if (!V.getNode()->hasOneUse())
4958 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4959 // See if we can recursively simplify the LHS.
4960 unsigned Amt = RHSC->getZExtValue();
4962 // Watch out for shift count overflow though.
4963 if (Amt >= Mask.getBitWidth()) break;
4964 APInt NewMask = Mask << Amt;
4965 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4966 if (SimplifyLHS.getNode())
4967 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4968 SimplifyLHS, V.getOperand(1));
4974 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
4975 /// bits and then truncated to a narrower type and where N is a multiple
4976 /// of number of bits of the narrower type, transform it to a narrower load
4977 /// from address + N / num of bits of new type. If the result is to be
4978 /// extended, also fold the extension to form a extending load.
4979 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
4980 unsigned Opc = N->getOpcode();
4982 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4983 SDValue N0 = N->getOperand(0);
4984 EVT VT = N->getValueType(0);
4987 // This transformation isn't valid for vector loads.
4991 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4993 if (Opc == ISD::SIGN_EXTEND_INREG) {
4994 ExtType = ISD::SEXTLOAD;
4995 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4996 } else if (Opc == ISD::SRL) {
4997 // Another special-case: SRL is basically zero-extending a narrower value.
4998 ExtType = ISD::ZEXTLOAD;
5000 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5001 if (!N01) return SDValue();
5002 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
5003 VT.getSizeInBits() - N01->getZExtValue());
5005 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
5008 unsigned EVTBits = ExtVT.getSizeInBits();
5010 // Do not generate loads of non-round integer types since these can
5011 // be expensive (and would be wrong if the type is not byte sized).
5012 if (!ExtVT.isRound())
5016 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5017 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5018 ShAmt = N01->getZExtValue();
5019 // Is the shift amount a multiple of size of VT?
5020 if ((ShAmt & (EVTBits-1)) == 0) {
5021 N0 = N0.getOperand(0);
5022 // Is the load width a multiple of size of VT?
5023 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
5027 // At this point, we must have a load or else we can't do the transform.
5028 if (!isa<LoadSDNode>(N0)) return SDValue();
5030 // If the shift amount is larger than the input type then we're not
5031 // accessing any of the loaded bytes. If the load was a zextload/extload
5032 // then the result of the shift+trunc is zero/undef (handled elsewhere).
5033 // If the load was a sextload then the result is a splat of the sign bit
5034 // of the extended byte. This is not worth optimizing for.
5035 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
5040 // If the load is shifted left (and the result isn't shifted back right),
5041 // we can fold the truncate through the shift.
5042 unsigned ShLeftAmt = 0;
5043 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
5044 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
5045 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5046 ShLeftAmt = N01->getZExtValue();
5047 N0 = N0.getOperand(0);
5051 // If we haven't found a load, we can't narrow it. Don't transform one with
5052 // multiple uses, this would require adding a new load.
5053 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() ||
5054 // Don't change the width of a volatile load.
5055 cast<LoadSDNode>(N0)->isVolatile())
5058 // Verify that we are actually reducing a load width here.
5059 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits)
5062 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5063 EVT PtrType = N0.getOperand(1).getValueType();
5065 if (PtrType == MVT::Untyped || PtrType.isExtended())
5066 // It's not possible to generate a constant of extended or untyped type.
5069 // For big endian targets, we need to adjust the offset to the pointer to
5070 // load the correct bytes.
5071 if (TLI.isBigEndian()) {
5072 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
5073 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
5074 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
5077 uint64_t PtrOff = ShAmt / 8;
5078 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
5079 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
5080 PtrType, LN0->getBasePtr(),
5081 DAG.getConstant(PtrOff, PtrType));
5082 AddToWorkList(NewPtr.getNode());
5085 if (ExtType == ISD::NON_EXTLOAD)
5086 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
5087 LN0->getPointerInfo().getWithOffset(PtrOff),
5088 LN0->isVolatile(), LN0->isNonTemporal(),
5089 LN0->isInvariant(), NewAlign);
5091 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr,
5092 LN0->getPointerInfo().getWithOffset(PtrOff),
5093 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
5096 // Replace the old load's chain with the new load's chain.
5097 WorkListRemover DeadNodes(*this);
5098 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
5100 // Shift the result left, if we've swallowed a left shift.
5101 SDValue Result = Load;
5102 if (ShLeftAmt != 0) {
5103 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
5104 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
5106 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
5107 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
5110 // Return the new loaded value.
5114 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
5115 SDValue N0 = N->getOperand(0);
5116 SDValue N1 = N->getOperand(1);
5117 EVT VT = N->getValueType(0);
5118 EVT EVT = cast<VTSDNode>(N1)->getVT();
5119 unsigned VTBits = VT.getScalarType().getSizeInBits();
5120 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
5122 // fold (sext_in_reg c1) -> c1
5123 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
5124 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
5126 // If the input is already sign extended, just drop the extension.
5127 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
5130 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
5131 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
5132 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
5133 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5134 N0.getOperand(0), N1);
5137 // fold (sext_in_reg (sext x)) -> (sext x)
5138 // fold (sext_in_reg (aext x)) -> (sext x)
5139 // if x is small enough.
5140 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
5141 SDValue N00 = N0.getOperand(0);
5142 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
5143 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
5144 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
5147 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
5148 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
5149 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
5151 // fold operands of sext_in_reg based on knowledge that the top bits are not
5153 if (SimplifyDemandedBits(SDValue(N, 0)))
5154 return SDValue(N, 0);
5156 // fold (sext_in_reg (load x)) -> (smaller sextload x)
5157 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
5158 SDValue NarrowLoad = ReduceLoadWidth(N);
5159 if (NarrowLoad.getNode())
5162 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
5163 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
5164 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
5165 if (N0.getOpcode() == ISD::SRL) {
5166 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
5167 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
5168 // We can turn this into an SRA iff the input to the SRL is already sign
5170 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
5171 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
5172 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
5173 N0.getOperand(0), N0.getOperand(1));
5177 // fold (sext_inreg (extload x)) -> (sextload x)
5178 if (ISD::isEXTLoad(N0.getNode()) &&
5179 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5180 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5181 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5182 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5183 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5184 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5186 LN0->getBasePtr(), LN0->getPointerInfo(),
5188 LN0->isVolatile(), LN0->isNonTemporal(),
5189 LN0->getAlignment());
5190 CombineTo(N, ExtLoad);
5191 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5192 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5194 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
5195 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5197 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5198 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5199 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5200 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5201 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5203 LN0->getBasePtr(), LN0->getPointerInfo(),
5205 LN0->isVolatile(), LN0->isNonTemporal(),
5206 LN0->getAlignment());
5207 CombineTo(N, ExtLoad);
5208 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5209 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5212 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
5213 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
5214 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5215 N0.getOperand(1), false);
5216 if (BSwap.getNode() != 0)
5217 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5224 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
5225 SDValue N0 = N->getOperand(0);
5226 EVT VT = N->getValueType(0);
5227 bool isLE = TLI.isLittleEndian();
5230 if (N0.getValueType() == N->getValueType(0))
5232 // fold (truncate c1) -> c1
5233 if (isa<ConstantSDNode>(N0))
5234 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
5235 // fold (truncate (truncate x)) -> (truncate x)
5236 if (N0.getOpcode() == ISD::TRUNCATE)
5237 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5238 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
5239 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
5240 N0.getOpcode() == ISD::SIGN_EXTEND ||
5241 N0.getOpcode() == ISD::ANY_EXTEND) {
5242 if (N0.getOperand(0).getValueType().bitsLT(VT))
5243 // if the source is smaller than the dest, we still need an extend
5244 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
5246 if (N0.getOperand(0).getValueType().bitsGT(VT))
5247 // if the source is larger than the dest, than we just need the truncate
5248 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5249 // if the source and dest are the same type, we can drop both the extend
5250 // and the truncate.
5251 return N0.getOperand(0);
5254 // Fold extract-and-trunc into a narrow extract. For example:
5255 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
5256 // i32 y = TRUNCATE(i64 x)
5258 // v16i8 b = BITCAST (v2i64 val)
5259 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
5261 // Note: We only run this optimization after type legalization (which often
5262 // creates this pattern) and before operation legalization after which
5263 // we need to be more careful about the vector instructions that we generate.
5264 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5265 LegalTypes && !LegalOperations && N0->hasOneUse()) {
5267 EVT VecTy = N0.getOperand(0).getValueType();
5268 EVT ExTy = N0.getValueType();
5269 EVT TrTy = N->getValueType(0);
5271 unsigned NumElem = VecTy.getVectorNumElements();
5272 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
5274 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
5275 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
5277 SDValue EltNo = N0->getOperand(1);
5278 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
5279 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5280 EVT IndexTy = N0->getOperand(1).getValueType();
5281 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
5283 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5284 NVT, N0.getOperand(0));
5286 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
5287 N->getDebugLoc(), TrTy, V,
5288 DAG.getConstant(Index, IndexTy));
5292 // See if we can simplify the input to this truncate through knowledge that
5293 // only the low bits are being used.
5294 // For example "trunc (or (shl x, 8), y)" // -> trunc y
5295 // Currently we only perform this optimization on scalars because vectors
5296 // may have different active low bits.
5297 if (!VT.isVector()) {
5299 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
5300 VT.getSizeInBits()));
5301 if (Shorter.getNode())
5302 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
5304 // fold (truncate (load x)) -> (smaller load x)
5305 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
5306 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
5307 SDValue Reduced = ReduceLoadWidth(N);
5308 if (Reduced.getNode())
5312 // Simplify the operands using demanded-bits information.
5313 if (!VT.isVector() &&
5314 SimplifyDemandedBits(SDValue(N, 0)))
5315 return SDValue(N, 0);
5320 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
5321 SDValue Elt = N->getOperand(i);
5322 if (Elt.getOpcode() != ISD::MERGE_VALUES)
5323 return Elt.getNode();
5324 return Elt.getOperand(Elt.getResNo()).getNode();
5327 /// CombineConsecutiveLoads - build_pair (load, load) -> load
5328 /// if load locations are consecutive.
5329 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
5330 assert(N->getOpcode() == ISD::BUILD_PAIR);
5332 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
5333 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
5334 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
5335 LD1->getPointerInfo().getAddrSpace() !=
5336 LD2->getPointerInfo().getAddrSpace())
5338 EVT LD1VT = LD1->getValueType(0);
5340 if (ISD::isNON_EXTLoad(LD2) &&
5342 // If both are volatile this would reduce the number of volatile loads.
5343 // If one is volatile it might be ok, but play conservative and bail out.
5344 !LD1->isVolatile() &&
5345 !LD2->isVolatile() &&
5346 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
5347 unsigned Align = LD1->getAlignment();
5348 unsigned NewAlign = TLI.getDataLayout()->
5349 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5351 if (NewAlign <= Align &&
5352 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
5353 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
5354 LD1->getBasePtr(), LD1->getPointerInfo(),
5355 false, false, false, Align);
5361 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
5362 SDValue N0 = N->getOperand(0);
5363 EVT VT = N->getValueType(0);
5365 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
5366 // Only do this before legalize, since afterward the target may be depending
5367 // on the bitconvert.
5368 // First check to see if this is all constant.
5370 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
5372 bool isSimple = true;
5373 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
5374 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
5375 N0.getOperand(i).getOpcode() != ISD::Constant &&
5376 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
5381 EVT DestEltVT = N->getValueType(0).getVectorElementType();
5382 assert(!DestEltVT.isVector() &&
5383 "Element type of vector ValueType must not be vector!");
5385 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
5388 // If the input is a constant, let getNode fold it.
5389 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
5390 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
5391 if (Res.getNode() != N) {
5392 if (!LegalOperations ||
5393 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
5396 // Folding it resulted in an illegal node, and it's too late to
5397 // do that. Clean up the old node and forego the transformation.
5398 // Ideally this won't happen very often, because instcombine
5399 // and the earlier dagcombine runs (where illegal nodes are
5400 // permitted) should have folded most of them already.
5401 DAG.DeleteNode(Res.getNode());
5405 // (conv (conv x, t1), t2) -> (conv x, t2)
5406 if (N0.getOpcode() == ISD::BITCAST)
5407 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
5410 // fold (conv (load x)) -> (load (conv*)x)
5411 // If the resultant load doesn't need a higher alignment than the original!
5412 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
5413 // Do not change the width of a volatile load.
5414 !cast<LoadSDNode>(N0)->isVolatile() &&
5415 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
5416 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5417 unsigned Align = TLI.getDataLayout()->
5418 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5419 unsigned OrigAlign = LN0->getAlignment();
5421 if (Align <= OrigAlign) {
5422 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
5423 LN0->getBasePtr(), LN0->getPointerInfo(),
5424 LN0->isVolatile(), LN0->isNonTemporal(),
5425 LN0->isInvariant(), OrigAlign);
5427 CombineTo(N0.getNode(),
5428 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5429 N0.getValueType(), Load),
5435 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5436 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
5437 // This often reduces constant pool loads.
5438 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) ||
5439 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) &&
5440 N0.getNode()->hasOneUse() && VT.isInteger() &&
5441 !VT.isVector() && !N0.getValueType().isVector()) {
5442 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
5444 AddToWorkList(NewConv.getNode());
5446 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5447 if (N0.getOpcode() == ISD::FNEG)
5448 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
5449 NewConv, DAG.getConstant(SignBit, VT));
5450 assert(N0.getOpcode() == ISD::FABS);
5451 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
5452 NewConv, DAG.getConstant(~SignBit, VT));
5455 // fold (bitconvert (fcopysign cst, x)) ->
5456 // (or (and (bitconvert x), sign), (and cst, (not sign)))
5457 // Note that we don't handle (copysign x, cst) because this can always be
5458 // folded to an fneg or fabs.
5459 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5460 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
5461 VT.isInteger() && !VT.isVector()) {
5462 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
5463 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
5464 if (isTypeLegal(IntXVT)) {
5465 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5466 IntXVT, N0.getOperand(1));
5467 AddToWorkList(X.getNode());
5469 // If X has a different width than the result/lhs, sext it or truncate it.
5470 unsigned VTWidth = VT.getSizeInBits();
5471 if (OrigXWidth < VTWidth) {
5472 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
5473 AddToWorkList(X.getNode());
5474 } else if (OrigXWidth > VTWidth) {
5475 // To get the sign bit in the right place, we have to shift it right
5476 // before truncating.
5477 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
5478 X.getValueType(), X,
5479 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
5480 AddToWorkList(X.getNode());
5481 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
5482 AddToWorkList(X.getNode());
5485 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5486 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
5487 X, DAG.getConstant(SignBit, VT));
5488 AddToWorkList(X.getNode());
5490 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5491 VT, N0.getOperand(0));
5492 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
5493 Cst, DAG.getConstant(~SignBit, VT));
5494 AddToWorkList(Cst.getNode());
5496 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
5500 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
5501 if (N0.getOpcode() == ISD::BUILD_PAIR) {
5502 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
5503 if (CombineLD.getNode())
5510 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
5511 EVT VT = N->getValueType(0);
5512 return CombineConsecutiveLoads(N, VT);
5515 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
5516 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
5517 /// destination element value type.
5518 SDValue DAGCombiner::
5519 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
5520 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
5522 // If this is already the right type, we're done.
5523 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
5525 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
5526 unsigned DstBitSize = DstEltVT.getSizeInBits();
5528 // If this is a conversion of N elements of one type to N elements of another
5529 // type, convert each element. This handles FP<->INT cases.
5530 if (SrcBitSize == DstBitSize) {
5531 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5532 BV->getValueType(0).getVectorNumElements());
5534 // Due to the FP element handling below calling this routine recursively,
5535 // we can end up with a scalar-to-vector node here.
5536 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
5537 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5538 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5539 DstEltVT, BV->getOperand(0)));
5541 SmallVector<SDValue, 8> Ops;
5542 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5543 SDValue Op = BV->getOperand(i);
5544 // If the vector element type is not legal, the BUILD_VECTOR operands
5545 // are promoted and implicitly truncated. Make that explicit here.
5546 if (Op.getValueType() != SrcEltVT)
5547 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
5548 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5550 AddToWorkList(Ops.back().getNode());
5552 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5553 &Ops[0], Ops.size());
5556 // Otherwise, we're growing or shrinking the elements. To avoid having to
5557 // handle annoying details of growing/shrinking FP values, we convert them to
5559 if (SrcEltVT.isFloatingPoint()) {
5560 // Convert the input float vector to a int vector where the elements are the
5562 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
5563 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
5564 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
5568 // Now we know the input is an integer vector. If the output is a FP type,
5569 // convert to integer first, then to FP of the right size.
5570 if (DstEltVT.isFloatingPoint()) {
5571 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
5572 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
5573 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
5575 // Next, convert to FP elements of the same size.
5576 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
5579 // Okay, we know the src/dst types are both integers of differing types.
5580 // Handling growing first.
5581 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
5582 if (SrcBitSize < DstBitSize) {
5583 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
5585 SmallVector<SDValue, 8> Ops;
5586 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
5587 i += NumInputsPerOutput) {
5588 bool isLE = TLI.isLittleEndian();
5589 APInt NewBits = APInt(DstBitSize, 0);
5590 bool EltIsUndef = true;
5591 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
5592 // Shift the previously computed bits over.
5593 NewBits <<= SrcBitSize;
5594 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
5595 if (Op.getOpcode() == ISD::UNDEF) continue;
5598 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
5599 zextOrTrunc(SrcBitSize).zext(DstBitSize);
5603 Ops.push_back(DAG.getUNDEF(DstEltVT));
5605 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
5608 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
5609 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5610 &Ops[0], Ops.size());
5613 // Finally, this must be the case where we are shrinking elements: each input
5614 // turns into multiple outputs.
5615 bool isS2V = ISD::isScalarToVector(BV);
5616 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
5617 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5618 NumOutputsPerInput*BV->getNumOperands());
5619 SmallVector<SDValue, 8> Ops;
5621 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5622 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
5623 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
5624 Ops.push_back(DAG.getUNDEF(DstEltVT));
5628 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
5629 getAPIntValue().zextOrTrunc(SrcBitSize);
5631 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
5632 APInt ThisVal = OpVal.trunc(DstBitSize);
5633 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
5634 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
5635 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
5636 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5638 OpVal = OpVal.lshr(DstBitSize);
5641 // For big endian targets, swap the order of the pieces of each element.
5642 if (TLI.isBigEndian())
5643 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
5646 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5647 &Ops[0], Ops.size());
5650 SDValue DAGCombiner::visitFADD(SDNode *N) {
5651 SDValue N0 = N->getOperand(0);
5652 SDValue N1 = N->getOperand(1);
5653 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5654 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5655 EVT VT = N->getValueType(0);
5658 if (VT.isVector()) {
5659 SDValue FoldedVOp = SimplifyVBinOp(N);
5660 if (FoldedVOp.getNode()) return FoldedVOp;
5663 // fold (fadd c1, c2) -> c1 + c2
5664 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5665 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
5666 // canonicalize constant to RHS
5667 if (N0CFP && !N1CFP)
5668 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
5669 // fold (fadd A, 0) -> A
5670 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5671 N1CFP->getValueAPF().isZero())
5673 // fold (fadd A, (fneg B)) -> (fsub A, B)
5674 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5675 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5676 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5677 GetNegatedExpression(N1, DAG, LegalOperations));
5678 // fold (fadd (fneg A), B) -> (fsub B, A)
5679 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5680 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
5681 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
5682 GetNegatedExpression(N0, DAG, LegalOperations));
5684 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
5685 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5686 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
5687 isa<ConstantFPSDNode>(N0.getOperand(1)))
5688 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
5689 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5690 N0.getOperand(1), N1));
5692 // In unsafe math mode, we can fold chains of FADD's of the same value
5693 // into multiplications. This transform is not safe in general because
5694 // we are reducing the number of rounding steps.
5695 if (DAG.getTarget().Options.UnsafeFPMath &&
5696 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) &&
5698 if (N0.getOpcode() == ISD::FMUL) {
5699 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
5700 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
5702 // (fadd (fmul c, x), x) -> (fmul c+1, x)
5703 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) {
5704 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5706 DAG.getConstantFP(1.0, VT));
5707 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5711 // (fadd (fmul x, c), x) -> (fmul c+1, x)
5712 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
5713 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5715 DAG.getConstantFP(1.0, VT));
5716 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5720 // (fadd (fadd x, x), x) -> (fmul 3.0, x)
5721 if (!CFP00 && !CFP01 && N0.getOperand(0) == N0.getOperand(1) &&
5722 N0.getOperand(0) == N1) {
5723 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5724 N1, DAG.getConstantFP(3.0, VT));
5727 // (fadd (fmul c, x), (fadd x, x)) -> (fmul c+2, x)
5728 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD &&
5729 N1.getOperand(0) == N1.getOperand(1) &&
5730 N0.getOperand(1) == N1.getOperand(0)) {
5731 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5733 DAG.getConstantFP(2.0, VT));
5734 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5735 N0.getOperand(1), NewCFP);
5738 // (fadd (fmul x, c), (fadd x, x)) -> (fmul c+2, x)
5739 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
5740 N1.getOperand(0) == N1.getOperand(1) &&
5741 N0.getOperand(0) == N1.getOperand(0)) {
5742 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5744 DAG.getConstantFP(2.0, VT));
5745 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5746 N0.getOperand(0), NewCFP);
5750 if (N1.getOpcode() == ISD::FMUL) {
5751 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
5752 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1));
5754 // (fadd x, (fmul c, x)) -> (fmul c+1, x)
5755 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) {
5756 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5758 DAG.getConstantFP(1.0, VT));
5759 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5763 // (fadd x, (fmul x, c)) -> (fmul c+1, x)
5764 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
5765 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5767 DAG.getConstantFP(1.0, VT));
5768 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5772 // (fadd x, (fadd x, x)) -> (fmul 3.0, x)
5773 if (!CFP10 && !CFP11 && N1.getOperand(0) == N1.getOperand(1) &&
5774 N1.getOperand(0) == N0) {
5775 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5776 N0, DAG.getConstantFP(3.0, VT));
5779 // (fadd (fadd x, x), (fmul c, x)) -> (fmul c+2, x)
5780 if (CFP10 && !CFP11 && N1.getOpcode() == ISD::FADD &&
5781 N1.getOperand(0) == N1.getOperand(1) &&
5782 N0.getOperand(1) == N1.getOperand(0)) {
5783 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5785 DAG.getConstantFP(2.0, VT));
5786 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5787 N0.getOperand(1), NewCFP);
5790 // (fadd (fadd x, x), (fmul x, c)) -> (fmul c+2, x)
5791 if (CFP11 && !CFP10 && N1.getOpcode() == ISD::FADD &&
5792 N1.getOperand(0) == N1.getOperand(1) &&
5793 N0.getOperand(0) == N1.getOperand(0)) {
5794 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5796 DAG.getConstantFP(2.0, VT));
5797 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5798 N0.getOperand(0), NewCFP);
5802 // (fadd (fadd x, x), (fadd x, x)) -> (fmul 4.0, x)
5803 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
5804 N0.getOperand(0) == N0.getOperand(1) &&
5805 N1.getOperand(0) == N1.getOperand(1) &&
5806 N0.getOperand(0) == N1.getOperand(0)) {
5807 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5809 DAG.getConstantFP(4.0, VT));
5813 // FADD -> FMA combines:
5814 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
5815 DAG.getTarget().Options.UnsafeFPMath) &&
5816 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) &&
5817 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) {
5819 // fold (fadd (fmul x, y), z) -> (fma x, y, z)
5820 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) {
5821 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT,
5822 N0.getOperand(0), N0.getOperand(1), N1);
5825 // fold (fadd x, (fmul y, z)) -> (fma y, z, x)
5826 // Note: Commutes FADD operands.
5827 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) {
5828 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT,
5829 N1.getOperand(0), N1.getOperand(1), N0);
5836 SDValue DAGCombiner::visitFSUB(SDNode *N) {
5837 SDValue N0 = N->getOperand(0);
5838 SDValue N1 = N->getOperand(1);
5839 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5840 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5841 EVT VT = N->getValueType(0);
5842 DebugLoc dl = N->getDebugLoc();
5845 if (VT.isVector()) {
5846 SDValue FoldedVOp = SimplifyVBinOp(N);
5847 if (FoldedVOp.getNode()) return FoldedVOp;
5850 // fold (fsub c1, c2) -> c1-c2
5851 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5852 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
5853 // fold (fsub A, 0) -> A
5854 if (DAG.getTarget().Options.UnsafeFPMath &&
5855 N1CFP && N1CFP->getValueAPF().isZero())
5857 // fold (fsub 0, B) -> -B
5858 if (DAG.getTarget().Options.UnsafeFPMath &&
5859 N0CFP && N0CFP->getValueAPF().isZero()) {
5860 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
5861 return GetNegatedExpression(N1, DAG, LegalOperations);
5862 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5863 return DAG.getNode(ISD::FNEG, dl, VT, N1);
5865 // fold (fsub A, (fneg B)) -> (fadd A, B)
5866 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options))
5867 return DAG.getNode(ISD::FADD, dl, VT, N0,
5868 GetNegatedExpression(N1, DAG, LegalOperations));
5870 // If 'unsafe math' is enabled, fold
5871 // (fsub x, x) -> 0.0 &
5872 // (fsub x, (fadd x, y)) -> (fneg y) &
5873 // (fsub x, (fadd y, x)) -> (fneg y)
5874 if (DAG.getTarget().Options.UnsafeFPMath) {
5876 return DAG.getConstantFP(0.0f, VT);
5878 if (N1.getOpcode() == ISD::FADD) {
5879 SDValue N10 = N1->getOperand(0);
5880 SDValue N11 = N1->getOperand(1);
5882 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI,
5883 &DAG.getTarget().Options))
5884 return GetNegatedExpression(N11, DAG, LegalOperations);
5885 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI,
5886 &DAG.getTarget().Options))
5887 return GetNegatedExpression(N10, DAG, LegalOperations);
5891 // FSUB -> FMA combines:
5892 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
5893 DAG.getTarget().Options.UnsafeFPMath) &&
5894 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) &&
5895 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) {
5897 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
5898 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) {
5899 return DAG.getNode(ISD::FMA, dl, VT,
5900 N0.getOperand(0), N0.getOperand(1),
5901 DAG.getNode(ISD::FNEG, dl, VT, N1));
5904 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
5905 // Note: Commutes FSUB operands.
5906 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) {
5907 return DAG.getNode(ISD::FMA, dl, VT,
5908 DAG.getNode(ISD::FNEG, dl, VT,
5910 N1.getOperand(1), N0);
5913 // fold (fsub (-(fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
5914 if (N0.getOpcode() == ISD::FNEG &&
5915 N0.getOperand(0).getOpcode() == ISD::FMUL &&
5916 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) {
5917 SDValue N00 = N0.getOperand(0).getOperand(0);
5918 SDValue N01 = N0.getOperand(0).getOperand(1);
5919 return DAG.getNode(ISD::FMA, dl, VT,
5920 DAG.getNode(ISD::FNEG, dl, VT, N00), N01,
5921 DAG.getNode(ISD::FNEG, dl, VT, N1));
5928 SDValue DAGCombiner::visitFMUL(SDNode *N) {
5929 SDValue N0 = N->getOperand(0);
5930 SDValue N1 = N->getOperand(1);
5931 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5932 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5933 EVT VT = N->getValueType(0);
5934 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5937 if (VT.isVector()) {
5938 SDValue FoldedVOp = SimplifyVBinOp(N);
5939 if (FoldedVOp.getNode()) return FoldedVOp;
5942 // fold (fmul c1, c2) -> c1*c2
5943 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5944 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
5945 // canonicalize constant to RHS
5946 if (N0CFP && !N1CFP)
5947 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
5948 // fold (fmul A, 0) -> 0
5949 if (DAG.getTarget().Options.UnsafeFPMath &&
5950 N1CFP && N1CFP->getValueAPF().isZero())
5952 // fold (fmul A, 0) -> 0, vector edition.
5953 if (DAG.getTarget().Options.UnsafeFPMath &&
5954 ISD::isBuildVectorAllZeros(N1.getNode()))
5956 // fold (fmul A, 1.0) -> A
5957 if (N1CFP && N1CFP->isExactlyValue(1.0))
5959 // fold (fmul X, 2.0) -> (fadd X, X)
5960 if (N1CFP && N1CFP->isExactlyValue(+2.0))
5961 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
5962 // fold (fmul X, -1.0) -> (fneg X)
5963 if (N1CFP && N1CFP->isExactlyValue(-1.0))
5964 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5965 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
5967 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
5968 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
5969 &DAG.getTarget().Options)) {
5970 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
5971 &DAG.getTarget().Options)) {
5972 // Both can be negated for free, check to see if at least one is cheaper
5974 if (LHSNeg == 2 || RHSNeg == 2)
5975 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5976 GetNegatedExpression(N0, DAG, LegalOperations),
5977 GetNegatedExpression(N1, DAG, LegalOperations));
5981 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
5982 if (DAG.getTarget().Options.UnsafeFPMath &&
5983 N1CFP && N0.getOpcode() == ISD::FMUL &&
5984 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
5985 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
5986 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5987 N0.getOperand(1), N1));
5992 SDValue DAGCombiner::visitFMA(SDNode *N) {
5993 SDValue N0 = N->getOperand(0);
5994 SDValue N1 = N->getOperand(1);
5995 SDValue N2 = N->getOperand(2);
5996 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5997 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5998 EVT VT = N->getValueType(0);
5999 DebugLoc dl = N->getDebugLoc();
6001 if (N0CFP && N0CFP->isExactlyValue(1.0))
6002 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2);
6003 if (N1CFP && N1CFP->isExactlyValue(1.0))
6004 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2);
6006 // Canonicalize (fma c, x, y) -> (fma x, c, y)
6007 if (N0CFP && !N1CFP)
6008 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, N1, N0, N2);
6010 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)
6011 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6012 N2.getOpcode() == ISD::FMUL &&
6013 N0 == N2.getOperand(0) &&
6014 N2.getOperand(1).getOpcode() == ISD::ConstantFP) {
6015 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6016 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1)));
6020 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y)
6021 if (DAG.getTarget().Options.UnsafeFPMath &&
6022 N0.getOpcode() == ISD::FMUL && N1CFP &&
6023 N0.getOperand(1).getOpcode() == ISD::ConstantFP) {
6024 return DAG.getNode(ISD::FMA, dl, VT,
6026 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)),
6030 // (fma x, 1, y) -> (fadd x, y)
6031 // (fma x, -1, y) -> (fadd (fneg x), y)
6033 if (N1CFP->isExactlyValue(1.0))
6034 return DAG.getNode(ISD::FADD, dl, VT, N0, N2);
6036 if (N1CFP->isExactlyValue(-1.0) &&
6037 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {
6038 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0);
6039 AddToWorkList(RHSNeg.getNode());
6040 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg);
6044 // (fma x, c, x) -> (fmul x, (c+1))
6045 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2) {
6046 return DAG.getNode(ISD::FMUL, dl, VT,
6048 DAG.getNode(ISD::FADD, dl, VT,
6049 N1, DAG.getConstantFP(1.0, VT)));
6052 // (fma x, c, (fneg x)) -> (fmul x, (c-1))
6053 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6054 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) {
6055 return DAG.getNode(ISD::FMUL, dl, VT,
6057 DAG.getNode(ISD::FADD, dl, VT,
6058 N1, DAG.getConstantFP(-1.0, VT)));
6065 SDValue DAGCombiner::visitFDIV(SDNode *N) {
6066 SDValue N0 = N->getOperand(0);
6067 SDValue N1 = N->getOperand(1);
6068 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6069 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6070 EVT VT = N->getValueType(0);
6071 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6074 if (VT.isVector()) {
6075 SDValue FoldedVOp = SimplifyVBinOp(N);
6076 if (FoldedVOp.getNode()) return FoldedVOp;
6079 // fold (fdiv c1, c2) -> c1/c2
6080 if (N0CFP && N1CFP && VT != MVT::ppcf128)
6081 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
6083 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
6084 if (N1CFP && VT != MVT::ppcf128 && DAG.getTarget().Options.UnsafeFPMath) {
6085 // Compute the reciprocal 1.0 / c2.
6086 APFloat N1APF = N1CFP->getValueAPF();
6087 APFloat Recip(N1APF.getSemantics(), 1); // 1.0
6088 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven);
6089 // Only do the transform if the reciprocal is a legal fp immediate that
6090 // isn't too nasty (eg NaN, denormal, ...).
6091 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty
6092 (!LegalOperations ||
6093 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
6094 // backend)... we should handle this gracefully after Legalize.
6095 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
6096 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
6097 TLI.isFPImmLegal(Recip, VT)))
6098 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0,
6099 DAG.getConstantFP(Recip, VT));
6102 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
6103 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
6104 &DAG.getTarget().Options)) {
6105 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
6106 &DAG.getTarget().Options)) {
6107 // Both can be negated for free, check to see if at least one is cheaper
6109 if (LHSNeg == 2 || RHSNeg == 2)
6110 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
6111 GetNegatedExpression(N0, DAG, LegalOperations),
6112 GetNegatedExpression(N1, DAG, LegalOperations));
6119 SDValue DAGCombiner::visitFREM(SDNode *N) {
6120 SDValue N0 = N->getOperand(0);
6121 SDValue N1 = N->getOperand(1);
6122 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6123 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6124 EVT VT = N->getValueType(0);
6126 // fold (frem c1, c2) -> fmod(c1,c2)
6127 if (N0CFP && N1CFP && VT != MVT::ppcf128)
6128 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
6133 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
6134 SDValue N0 = N->getOperand(0);
6135 SDValue N1 = N->getOperand(1);
6136 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6137 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6138 EVT VT = N->getValueType(0);
6140 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
6141 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
6144 const APFloat& V = N1CFP->getValueAPF();
6145 // copysign(x, c1) -> fabs(x) iff ispos(c1)
6146 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
6147 if (!V.isNegative()) {
6148 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
6149 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6151 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6152 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
6153 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
6157 // copysign(fabs(x), y) -> copysign(x, y)
6158 // copysign(fneg(x), y) -> copysign(x, y)
6159 // copysign(copysign(x,z), y) -> copysign(x, y)
6160 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
6161 N0.getOpcode() == ISD::FCOPYSIGN)
6162 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6163 N0.getOperand(0), N1);
6165 // copysign(x, abs(y)) -> abs(x)
6166 if (N1.getOpcode() == ISD::FABS)
6167 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6169 // copysign(x, copysign(y,z)) -> copysign(x, z)
6170 if (N1.getOpcode() == ISD::FCOPYSIGN)
6171 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6172 N0, N1.getOperand(1));
6174 // copysign(x, fp_extend(y)) -> copysign(x, y)
6175 // copysign(x, fp_round(y)) -> copysign(x, y)
6176 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
6177 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6178 N0, N1.getOperand(0));
6183 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
6184 SDValue N0 = N->getOperand(0);
6185 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
6186 EVT VT = N->getValueType(0);
6187 EVT OpVT = N0.getValueType();
6189 // fold (sint_to_fp c1) -> c1fp
6190 if (N0C && OpVT != MVT::ppcf128 &&
6191 // ...but only if the target supports immediate floating-point values
6192 (!LegalOperations ||
6193 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
6194 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
6196 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
6197 // but UINT_TO_FP is legal on this target, try to convert.
6198 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
6199 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
6200 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
6201 if (DAG.SignBitIsZero(N0))
6202 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
6205 // The next optimizations are desireable only if SELECT_CC can be lowered.
6206 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
6207 // having to say they don't support SELECT_CC on every type the DAG knows
6208 // about, since there is no way to mark an opcode illegal at all value types
6209 // (See also visitSELECT)
6210 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) {
6211 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6212 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
6214 (!LegalOperations ||
6215 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6217 { N0.getOperand(0), N0.getOperand(1),
6218 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT),
6220 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6223 // fold (sint_to_fp (zext (setcc x, y, cc))) ->
6224 // (select_cc x, y, 1.0, 0.0,, cc)
6225 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
6226 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
6227 (!LegalOperations ||
6228 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6230 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
6231 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT),
6232 N0.getOperand(0).getOperand(2) };
6233 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6240 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
6241 SDValue N0 = N->getOperand(0);
6242 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
6243 EVT VT = N->getValueType(0);
6244 EVT OpVT = N0.getValueType();
6246 // fold (uint_to_fp c1) -> c1fp
6247 if (N0C && OpVT != MVT::ppcf128 &&
6248 // ...but only if the target supports immediate floating-point values
6249 (!LegalOperations ||
6250 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
6251 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
6253 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
6254 // but SINT_TO_FP is legal on this target, try to convert.
6255 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
6256 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
6257 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
6258 if (DAG.SignBitIsZero(N0))
6259 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
6262 // The next optimizations are desireable only if SELECT_CC can be lowered.
6263 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
6264 // having to say they don't support SELECT_CC on every type the DAG knows
6265 // about, since there is no way to mark an opcode illegal at all value types
6266 // (See also visitSELECT)
6267 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) {
6268 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
6270 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
6271 (!LegalOperations ||
6272 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
6274 { N0.getOperand(0), N0.getOperand(1),
6275 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT),
6277 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5);
6284 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
6285 SDValue N0 = N->getOperand(0);
6286 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6287 EVT VT = N->getValueType(0);
6289 // fold (fp_to_sint c1fp) -> c1
6291 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
6296 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
6297 SDValue N0 = N->getOperand(0);
6298 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6299 EVT VT = N->getValueType(0);
6301 // fold (fp_to_uint c1fp) -> c1
6302 if (N0CFP && VT != MVT::ppcf128)
6303 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
6308 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
6309 SDValue N0 = N->getOperand(0);
6310 SDValue N1 = N->getOperand(1);
6311 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6312 EVT VT = N->getValueType(0);
6314 // fold (fp_round c1fp) -> c1fp
6315 if (N0CFP && N0.getValueType() != MVT::ppcf128)
6316 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
6318 // fold (fp_round (fp_extend x)) -> x
6319 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
6320 return N0.getOperand(0);
6322 // fold (fp_round (fp_round x)) -> (fp_round x)
6323 if (N0.getOpcode() == ISD::FP_ROUND) {
6324 // This is a value preserving truncation if both round's are.
6325 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
6326 N0.getNode()->getConstantOperandVal(1) == 1;
6327 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
6328 DAG.getIntPtrConstant(IsTrunc));
6331 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
6332 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
6333 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
6334 N0.getOperand(0), N1);
6335 AddToWorkList(Tmp.getNode());
6336 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
6337 Tmp, N0.getOperand(1));
6343 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
6344 SDValue N0 = N->getOperand(0);
6345 EVT VT = N->getValueType(0);
6346 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
6347 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6349 // fold (fp_round_inreg c1fp) -> c1fp
6350 if (N0CFP && isTypeLegal(EVT)) {
6351 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
6352 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
6358 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
6359 SDValue N0 = N->getOperand(0);
6360 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6361 EVT VT = N->getValueType(0);
6363 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
6364 if (N->hasOneUse() &&
6365 N->use_begin()->getOpcode() == ISD::FP_ROUND)
6368 // fold (fp_extend c1fp) -> c1fp
6369 if (N0CFP && VT != MVT::ppcf128)
6370 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
6372 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
6374 if (N0.getOpcode() == ISD::FP_ROUND
6375 && N0.getNode()->getConstantOperandVal(1) == 1) {
6376 SDValue In = N0.getOperand(0);
6377 if (In.getValueType() == VT) return In;
6378 if (VT.bitsLT(In.getValueType()))
6379 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
6380 In, N0.getOperand(1));
6381 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
6384 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
6385 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
6386 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6387 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
6388 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6389 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
6391 LN0->getBasePtr(), LN0->getPointerInfo(),
6393 LN0->isVolatile(), LN0->isNonTemporal(),
6394 LN0->getAlignment());
6395 CombineTo(N, ExtLoad);
6396 CombineTo(N0.getNode(),
6397 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
6398 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
6399 ExtLoad.getValue(1));
6400 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6406 SDValue DAGCombiner::visitFNEG(SDNode *N) {
6407 SDValue N0 = N->getOperand(0);
6408 EVT VT = N->getValueType(0);
6410 if (VT.isVector()) {
6411 SDValue FoldedVOp = SimplifyVUnaryOp(N);
6412 if (FoldedVOp.getNode()) return FoldedVOp;
6415 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
6416 &DAG.getTarget().Options))
6417 return GetNegatedExpression(N0, DAG, LegalOperations);
6419 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
6420 // constant pool values.
6421 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST &&
6423 N0.getNode()->hasOneUse() &&
6424 N0.getOperand(0).getValueType().isInteger()) {
6425 SDValue Int = N0.getOperand(0);
6426 EVT IntVT = Int.getValueType();
6427 if (IntVT.isInteger() && !IntVT.isVector()) {
6428 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
6429 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6430 AddToWorkList(Int.getNode());
6431 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6436 // (fneg (fmul c, x)) -> (fmul -c, x)
6437 if (N0.getOpcode() == ISD::FMUL) {
6438 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
6440 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
6442 DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
6450 SDValue DAGCombiner::visitFCEIL(SDNode *N) {
6451 SDValue N0 = N->getOperand(0);
6452 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6453 EVT VT = N->getValueType(0);
6455 // fold (fceil c1) -> fceil(c1)
6456 if (N0CFP && VT != MVT::ppcf128)
6457 return DAG.getNode(ISD::FCEIL, N->getDebugLoc(), VT, N0);
6462 SDValue DAGCombiner::visitFTRUNC(SDNode *N) {
6463 SDValue N0 = N->getOperand(0);
6464 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6465 EVT VT = N->getValueType(0);
6467 // fold (ftrunc c1) -> ftrunc(c1)
6468 if (N0CFP && VT != MVT::ppcf128)
6469 return DAG.getNode(ISD::FTRUNC, N->getDebugLoc(), VT, N0);
6474 SDValue DAGCombiner::visitFFLOOR(SDNode *N) {
6475 SDValue N0 = N->getOperand(0);
6476 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6477 EVT VT = N->getValueType(0);
6479 // fold (ffloor c1) -> ffloor(c1)
6480 if (N0CFP && VT != MVT::ppcf128)
6481 return DAG.getNode(ISD::FFLOOR, N->getDebugLoc(), VT, N0);
6486 SDValue DAGCombiner::visitFABS(SDNode *N) {
6487 SDValue N0 = N->getOperand(0);
6488 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6489 EVT VT = N->getValueType(0);
6491 if (VT.isVector()) {
6492 SDValue FoldedVOp = SimplifyVUnaryOp(N);
6493 if (FoldedVOp.getNode()) return FoldedVOp;
6496 // fold (fabs c1) -> fabs(c1)
6497 if (N0CFP && VT != MVT::ppcf128)
6498 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
6499 // fold (fabs (fabs x)) -> (fabs x)
6500 if (N0.getOpcode() == ISD::FABS)
6501 return N->getOperand(0);
6502 // fold (fabs (fneg x)) -> (fabs x)
6503 // fold (fabs (fcopysign x, y)) -> (fabs x)
6504 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
6505 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
6507 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
6508 // constant pool values.
6509 if (!TLI.isFAbsFree(VT) &&
6510 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
6511 N0.getOperand(0).getValueType().isInteger() &&
6512 !N0.getOperand(0).getValueType().isVector()) {
6513 SDValue Int = N0.getOperand(0);
6514 EVT IntVT = Int.getValueType();
6515 if (IntVT.isInteger() && !IntVT.isVector()) {
6516 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
6517 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
6518 AddToWorkList(Int.getNode());
6519 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6520 N->getValueType(0), Int);
6527 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
6528 SDValue Chain = N->getOperand(0);
6529 SDValue N1 = N->getOperand(1);
6530 SDValue N2 = N->getOperand(2);
6532 // If N is a constant we could fold this into a fallthrough or unconditional
6533 // branch. However that doesn't happen very often in normal code, because
6534 // Instcombine/SimplifyCFG should have handled the available opportunities.
6535 // If we did this folding here, it would be necessary to update the
6536 // MachineBasicBlock CFG, which is awkward.
6538 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
6540 if (N1.getOpcode() == ISD::SETCC &&
6541 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
6542 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6543 Chain, N1.getOperand(2),
6544 N1.getOperand(0), N1.getOperand(1), N2);
6547 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
6548 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
6549 (N1.getOperand(0).hasOneUse() &&
6550 N1.getOperand(0).getOpcode() == ISD::SRL))) {
6552 if (N1.getOpcode() == ISD::TRUNCATE) {
6553 // Look pass the truncate.
6554 Trunc = N1.getNode();
6555 N1 = N1.getOperand(0);
6558 // Match this pattern so that we can generate simpler code:
6561 // %b = and i32 %a, 2
6562 // %c = srl i32 %b, 1
6563 // brcond i32 %c ...
6568 // %b = and i32 %a, 2
6569 // %c = setcc eq %b, 0
6572 // This applies only when the AND constant value has one bit set and the
6573 // SRL constant is equal to the log2 of the AND constant. The back-end is
6574 // smart enough to convert the result into a TEST/JMP sequence.
6575 SDValue Op0 = N1.getOperand(0);
6576 SDValue Op1 = N1.getOperand(1);
6578 if (Op0.getOpcode() == ISD::AND &&
6579 Op1.getOpcode() == ISD::Constant) {
6580 SDValue AndOp1 = Op0.getOperand(1);
6582 if (AndOp1.getOpcode() == ISD::Constant) {
6583 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
6585 if (AndConst.isPowerOf2() &&
6586 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
6588 DAG.getSetCC(N->getDebugLoc(),
6589 TLI.getSetCCResultType(Op0.getValueType()),
6590 Op0, DAG.getConstant(0, Op0.getValueType()),
6593 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6594 MVT::Other, Chain, SetCC, N2);
6595 // Don't add the new BRCond into the worklist or else SimplifySelectCC
6596 // will convert it back to (X & C1) >> C2.
6597 CombineTo(N, NewBRCond, false);
6598 // Truncate is dead.
6600 removeFromWorkList(Trunc);
6601 DAG.DeleteNode(Trunc);
6603 // Replace the uses of SRL with SETCC
6604 WorkListRemover DeadNodes(*this);
6605 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6606 removeFromWorkList(N1.getNode());
6607 DAG.DeleteNode(N1.getNode());
6608 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6614 // Restore N1 if the above transformation doesn't match.
6615 N1 = N->getOperand(1);
6618 // Transform br(xor(x, y)) -> br(x != y)
6619 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
6620 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
6621 SDNode *TheXor = N1.getNode();
6622 SDValue Op0 = TheXor->getOperand(0);
6623 SDValue Op1 = TheXor->getOperand(1);
6624 if (Op0.getOpcode() == Op1.getOpcode()) {
6625 // Avoid missing important xor optimizations.
6626 SDValue Tmp = visitXOR(TheXor);
6627 if (Tmp.getNode() && Tmp.getNode() != TheXor) {
6628 DEBUG(dbgs() << "\nReplacing.8 ";
6630 dbgs() << "\nWith: ";
6631 Tmp.getNode()->dump(&DAG);
6633 WorkListRemover DeadNodes(*this);
6634 DAG.ReplaceAllUsesOfValueWith(N1, Tmp);
6635 removeFromWorkList(TheXor);
6636 DAG.DeleteNode(TheXor);
6637 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6638 MVT::Other, Chain, Tmp, N2);
6642 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
6644 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
6645 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
6646 Op0.getOpcode() == ISD::XOR) {
6647 TheXor = Op0.getNode();
6651 EVT SetCCVT = N1.getValueType();
6653 SetCCVT = TLI.getSetCCResultType(SetCCVT);
6654 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
6657 Equal ? ISD::SETEQ : ISD::SETNE);
6658 // Replace the uses of XOR with SETCC
6659 WorkListRemover DeadNodes(*this);
6660 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
6661 removeFromWorkList(N1.getNode());
6662 DAG.DeleteNode(N1.getNode());
6663 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6664 MVT::Other, Chain, SetCC, N2);
6671 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
6673 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
6674 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
6675 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
6677 // If N is a constant we could fold this into a fallthrough or unconditional
6678 // branch. However that doesn't happen very often in normal code, because
6679 // Instcombine/SimplifyCFG should have handled the available opportunities.
6680 // If we did this folding here, it would be necessary to update the
6681 // MachineBasicBlock CFG, which is awkward.
6683 // Use SimplifySetCC to simplify SETCC's.
6684 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
6685 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
6687 if (Simp.getNode()) AddToWorkList(Simp.getNode());
6689 // fold to a simpler setcc
6690 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
6691 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6692 N->getOperand(0), Simp.getOperand(2),
6693 Simp.getOperand(0), Simp.getOperand(1),
6699 /// canFoldInAddressingMode - Return true if 'Use' is a load or a store that
6700 /// uses N as its base pointer and that N may be folded in the load / store
6701 /// addressing mode.
6702 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
6704 const TargetLowering &TLI) {
6706 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
6707 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
6709 VT = Use->getValueType(0);
6710 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
6711 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
6713 VT = ST->getValue().getValueType();
6718 if (N->getOpcode() == ISD::ADD) {
6719 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6722 AM.BaseOffs = Offset->getSExtValue();
6726 } else if (N->getOpcode() == ISD::SUB) {
6727 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6730 AM.BaseOffs = -Offset->getSExtValue();
6737 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
6740 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
6741 /// pre-indexed load / store when the base pointer is an add or subtract
6742 /// and it has other uses besides the load / store. After the
6743 /// transformation, the new indexed load / store has effectively folded
6744 /// the add / subtract in and all of its other uses are redirected to the
6745 /// new load / store.
6746 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
6747 if (Level < AfterLegalizeDAG)
6753 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6754 if (LD->isIndexed())
6756 VT = LD->getMemoryVT();
6757 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
6758 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
6760 Ptr = LD->getBasePtr();
6761 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6762 if (ST->isIndexed())
6764 VT = ST->getMemoryVT();
6765 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
6766 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
6768 Ptr = ST->getBasePtr();
6774 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
6775 // out. There is no reason to make this a preinc/predec.
6776 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
6777 Ptr.getNode()->hasOneUse())
6780 // Ask the target to do addressing mode selection.
6783 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6784 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
6786 // Don't create a indexed load / store with zero offset.
6787 if (isa<ConstantSDNode>(Offset) &&
6788 cast<ConstantSDNode>(Offset)->isNullValue())
6791 // Try turning it into a pre-indexed load / store except when:
6792 // 1) The new base ptr is a frame index.
6793 // 2) If N is a store and the new base ptr is either the same as or is a
6794 // predecessor of the value being stored.
6795 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
6796 // that would create a cycle.
6797 // 4) All uses are load / store ops that use it as old base ptr.
6799 // Check #1. Preinc'ing a frame index would require copying the stack pointer
6800 // (plus the implicit offset) to a register to preinc anyway.
6801 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6806 SDValue Val = cast<StoreSDNode>(N)->getValue();
6807 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
6811 // Now check for #3 and #4.
6812 bool RealUse = false;
6814 // Caches for hasPredecessorHelper
6815 SmallPtrSet<const SDNode *, 32> Visited;
6816 SmallVector<const SDNode *, 16> Worklist;
6818 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6819 E = Ptr.getNode()->use_end(); I != E; ++I) {
6823 if (N->hasPredecessorHelper(Use, Visited, Worklist))
6826 // If Ptr may be folded in addressing mode of other use, then it's
6827 // not profitable to do this transformation.
6828 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
6837 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6838 BasePtr, Offset, AM);
6840 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6841 BasePtr, Offset, AM);
6844 DEBUG(dbgs() << "\nReplacing.4 ";
6846 dbgs() << "\nWith: ";
6847 Result.getNode()->dump(&DAG);
6849 WorkListRemover DeadNodes(*this);
6851 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
6852 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
6854 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
6857 // Finally, since the node is now dead, remove it from the graph.
6860 // Replace the uses of Ptr with uses of the updated base value.
6861 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0));
6862 removeFromWorkList(Ptr.getNode());
6863 DAG.DeleteNode(Ptr.getNode());
6868 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
6869 /// add / sub of the base pointer node into a post-indexed load / store.
6870 /// The transformation folded the add / subtract into the new indexed
6871 /// load / store effectively and all of its uses are redirected to the
6872 /// new load / store.
6873 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
6874 if (Level < AfterLegalizeDAG)
6880 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6881 if (LD->isIndexed())
6883 VT = LD->getMemoryVT();
6884 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
6885 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
6887 Ptr = LD->getBasePtr();
6888 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6889 if (ST->isIndexed())
6891 VT = ST->getMemoryVT();
6892 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
6893 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
6895 Ptr = ST->getBasePtr();
6901 if (Ptr.getNode()->hasOneUse())
6904 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6905 E = Ptr.getNode()->use_end(); I != E; ++I) {
6908 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
6913 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6914 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
6915 // Don't create a indexed load / store with zero offset.
6916 if (isa<ConstantSDNode>(Offset) &&
6917 cast<ConstantSDNode>(Offset)->isNullValue())
6920 // Try turning it into a post-indexed load / store except when
6921 // 1) All uses are load / store ops that use it as base ptr (and
6922 // it may be folded as addressing mmode).
6923 // 2) Op must be independent of N, i.e. Op is neither a predecessor
6924 // nor a successor of N. Otherwise, if Op is folded that would
6927 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6931 bool TryNext = false;
6932 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
6933 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
6935 if (Use == Ptr.getNode())
6938 // If all the uses are load / store addresses, then don't do the
6940 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
6941 bool RealUse = false;
6942 for (SDNode::use_iterator III = Use->use_begin(),
6943 EEE = Use->use_end(); III != EEE; ++III) {
6944 SDNode *UseUse = *III;
6945 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
6960 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
6961 SDValue Result = isLoad
6962 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6963 BasePtr, Offset, AM)
6964 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6965 BasePtr, Offset, AM);
6968 DEBUG(dbgs() << "\nReplacing.5 ";
6970 dbgs() << "\nWith: ";
6971 Result.getNode()->dump(&DAG);
6973 WorkListRemover DeadNodes(*this);
6975 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
6976 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
6978 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
6981 // Finally, since the node is now dead, remove it from the graph.
6984 // Replace the uses of Use with uses of the updated base value.
6985 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
6986 Result.getValue(isLoad ? 1 : 0));
6987 removeFromWorkList(Op);
6997 SDValue DAGCombiner::visitLOAD(SDNode *N) {
6998 LoadSDNode *LD = cast<LoadSDNode>(N);
6999 SDValue Chain = LD->getChain();
7000 SDValue Ptr = LD->getBasePtr();
7002 // If load is not volatile and there are no uses of the loaded value (and
7003 // the updated indexed value in case of indexed loads), change uses of the
7004 // chain value into uses of the chain input (i.e. delete the dead load).
7005 if (!LD->isVolatile()) {
7006 if (N->getValueType(1) == MVT::Other) {
7008 if (!N->hasAnyUseOfValue(0)) {
7009 // It's not safe to use the two value CombineTo variant here. e.g.
7010 // v1, chain2 = load chain1, loc
7011 // v2, chain3 = load chain2, loc
7013 // Now we replace use of chain2 with chain1. This makes the second load
7014 // isomorphic to the one we are deleting, and thus makes this load live.
7015 DEBUG(dbgs() << "\nReplacing.6 ";
7017 dbgs() << "\nWith chain: ";
7018 Chain.getNode()->dump(&DAG);
7020 WorkListRemover DeadNodes(*this);
7021 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
7023 if (N->use_empty()) {
7024 removeFromWorkList(N);
7028 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7032 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
7033 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) {
7034 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
7035 DEBUG(dbgs() << "\nReplacing.7 ";
7037 dbgs() << "\nWith: ";
7038 Undef.getNode()->dump(&DAG);
7039 dbgs() << " and 2 other values\n");
7040 WorkListRemover DeadNodes(*this);
7041 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef);
7042 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
7043 DAG.getUNDEF(N->getValueType(1)));
7044 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain);
7045 removeFromWorkList(N);
7047 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7052 // If this load is directly stored, replace the load value with the stored
7054 // TODO: Handle store large -> read small portion.
7055 // TODO: Handle TRUNCSTORE/LOADEXT
7056 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
7057 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
7058 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
7059 if (PrevST->getBasePtr() == Ptr &&
7060 PrevST->getValue().getValueType() == N->getValueType(0))
7061 return CombineTo(N, Chain.getOperand(1), Chain);
7065 // Try to infer better alignment information than the load already has.
7066 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
7067 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
7068 if (Align > LD->getAlignment())
7069 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
7070 LD->getValueType(0),
7071 Chain, Ptr, LD->getPointerInfo(),
7073 LD->isVolatile(), LD->isNonTemporal(), Align);
7078 // Walk up chain skipping non-aliasing memory nodes.
7079 SDValue BetterChain = FindBetterChain(N, Chain);
7081 // If there is a better chain.
7082 if (Chain != BetterChain) {
7085 // Replace the chain to void dependency.
7086 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
7087 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
7088 BetterChain, Ptr, LD->getPointerInfo(),
7089 LD->isVolatile(), LD->isNonTemporal(),
7090 LD->isInvariant(), LD->getAlignment());
7092 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
7093 LD->getValueType(0),
7094 BetterChain, Ptr, LD->getPointerInfo(),
7097 LD->isNonTemporal(),
7098 LD->getAlignment());
7101 // Create token factor to keep old chain connected.
7102 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
7103 MVT::Other, Chain, ReplLoad.getValue(1));
7105 // Make sure the new and old chains are cleaned up.
7106 AddToWorkList(Token.getNode());
7108 // Replace uses with load result and token factor. Don't add users
7110 return CombineTo(N, ReplLoad.getValue(0), Token, false);
7114 // Try transforming N to an indexed load.
7115 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
7116 return SDValue(N, 0);
7121 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
7122 /// load is having specific bytes cleared out. If so, return the byte size
7123 /// being masked out and the shift amount.
7124 static std::pair<unsigned, unsigned>
7125 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
7126 std::pair<unsigned, unsigned> Result(0, 0);
7128 // Check for the structure we're looking for.
7129 if (V->getOpcode() != ISD::AND ||
7130 !isa<ConstantSDNode>(V->getOperand(1)) ||
7131 !ISD::isNormalLoad(V->getOperand(0).getNode()))
7134 // Check the chain and pointer.
7135 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
7136 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
7138 // The store should be chained directly to the load or be an operand of a
7140 if (LD == Chain.getNode())
7142 else if (Chain->getOpcode() != ISD::TokenFactor)
7143 return Result; // Fail.
7146 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
7147 if (Chain->getOperand(i).getNode() == LD) {
7151 if (!isOk) return Result;
7154 // This only handles simple types.
7155 if (V.getValueType() != MVT::i16 &&
7156 V.getValueType() != MVT::i32 &&
7157 V.getValueType() != MVT::i64)
7160 // Check the constant mask. Invert it so that the bits being masked out are
7161 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
7162 // follow the sign bit for uniformity.
7163 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
7164 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
7165 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
7166 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
7167 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
7168 if (NotMaskLZ == 64) return Result; // All zero mask.
7170 // See if we have a continuous run of bits. If so, we have 0*1+0*
7171 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
7174 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
7175 if (V.getValueType() != MVT::i64 && NotMaskLZ)
7176 NotMaskLZ -= 64-V.getValueSizeInBits();
7178 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
7179 switch (MaskedBytes) {
7183 default: return Result; // All one mask, or 5-byte mask.
7186 // Verify that the first bit starts at a multiple of mask so that the access
7187 // is aligned the same as the access width.
7188 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
7190 Result.first = MaskedBytes;
7191 Result.second = NotMaskTZ/8;
7196 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
7197 /// provides a value as specified by MaskInfo. If so, replace the specified
7198 /// store with a narrower store of truncated IVal.
7200 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
7201 SDValue IVal, StoreSDNode *St,
7203 unsigned NumBytes = MaskInfo.first;
7204 unsigned ByteShift = MaskInfo.second;
7205 SelectionDAG &DAG = DC->getDAG();
7207 // Check to see if IVal is all zeros in the part being masked in by the 'or'
7208 // that uses this. If not, this is not a replacement.
7209 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
7210 ByteShift*8, (ByteShift+NumBytes)*8);
7211 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
7213 // Check that it is legal on the target to do this. It is legal if the new
7214 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
7216 MVT VT = MVT::getIntegerVT(NumBytes*8);
7217 if (!DC->isTypeLegal(VT))
7220 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
7221 // shifted by ByteShift and truncated down to NumBytes.
7223 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
7224 DAG.getConstant(ByteShift*8,
7225 DC->getShiftAmountTy(IVal.getValueType())));
7227 // Figure out the offset for the store and the alignment of the access.
7229 unsigned NewAlign = St->getAlignment();
7231 if (DAG.getTargetLoweringInfo().isLittleEndian())
7232 StOffset = ByteShift;
7234 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
7236 SDValue Ptr = St->getBasePtr();
7238 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
7239 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
7240 NewAlign = MinAlign(NewAlign, StOffset);
7243 // Truncate down to the new size.
7244 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
7247 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
7248 St->getPointerInfo().getWithOffset(StOffset),
7249 false, false, NewAlign).getNode();
7253 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
7254 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
7255 /// of the loaded bits, try narrowing the load and store if it would end up
7256 /// being a win for performance or code size.
7257 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
7258 StoreSDNode *ST = cast<StoreSDNode>(N);
7259 if (ST->isVolatile())
7262 SDValue Chain = ST->getChain();
7263 SDValue Value = ST->getValue();
7264 SDValue Ptr = ST->getBasePtr();
7265 EVT VT = Value.getValueType();
7267 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
7270 unsigned Opc = Value.getOpcode();
7272 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
7273 // is a byte mask indicating a consecutive number of bytes, check to see if
7274 // Y is known to provide just those bytes. If so, we try to replace the
7275 // load + replace + store sequence with a single (narrower) store, which makes
7277 if (Opc == ISD::OR) {
7278 std::pair<unsigned, unsigned> MaskedLoad;
7279 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
7280 if (MaskedLoad.first)
7281 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
7282 Value.getOperand(1), ST,this))
7283 return SDValue(NewST, 0);
7285 // Or is commutative, so try swapping X and Y.
7286 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
7287 if (MaskedLoad.first)
7288 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
7289 Value.getOperand(0), ST,this))
7290 return SDValue(NewST, 0);
7293 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
7294 Value.getOperand(1).getOpcode() != ISD::Constant)
7297 SDValue N0 = Value.getOperand(0);
7298 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7299 Chain == SDValue(N0.getNode(), 1)) {
7300 LoadSDNode *LD = cast<LoadSDNode>(N0);
7301 if (LD->getBasePtr() != Ptr ||
7302 LD->getPointerInfo().getAddrSpace() !=
7303 ST->getPointerInfo().getAddrSpace())
7306 // Find the type to narrow it the load / op / store to.
7307 SDValue N1 = Value.getOperand(1);
7308 unsigned BitWidth = N1.getValueSizeInBits();
7309 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
7310 if (Opc == ISD::AND)
7311 Imm ^= APInt::getAllOnesValue(BitWidth);
7312 if (Imm == 0 || Imm.isAllOnesValue())
7314 unsigned ShAmt = Imm.countTrailingZeros();
7315 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
7316 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
7317 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
7318 while (NewBW < BitWidth &&
7319 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
7320 TLI.isNarrowingProfitable(VT, NewVT))) {
7321 NewBW = NextPowerOf2(NewBW);
7322 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
7324 if (NewBW >= BitWidth)
7327 // If the lsb changed does not start at the type bitwidth boundary,
7328 // start at the previous one.
7330 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
7331 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
7332 if ((Imm & Mask) == Imm) {
7333 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
7334 if (Opc == ISD::AND)
7335 NewImm ^= APInt::getAllOnesValue(NewBW);
7336 uint64_t PtrOff = ShAmt / 8;
7337 // For big endian targets, we need to adjust the offset to the pointer to
7338 // load the correct bytes.
7339 if (TLI.isBigEndian())
7340 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
7342 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
7343 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
7344 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy))
7347 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
7348 Ptr.getValueType(), Ptr,
7349 DAG.getConstant(PtrOff, Ptr.getValueType()));
7350 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
7351 LD->getChain(), NewPtr,
7352 LD->getPointerInfo().getWithOffset(PtrOff),
7353 LD->isVolatile(), LD->isNonTemporal(),
7354 LD->isInvariant(), NewAlign);
7355 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
7356 DAG.getConstant(NewImm, NewVT));
7357 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
7359 ST->getPointerInfo().getWithOffset(PtrOff),
7360 false, false, NewAlign);
7362 AddToWorkList(NewPtr.getNode());
7363 AddToWorkList(NewLD.getNode());
7364 AddToWorkList(NewVal.getNode());
7365 WorkListRemover DeadNodes(*this);
7366 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
7375 /// TransformFPLoadStorePair - For a given floating point load / store pair,
7376 /// if the load value isn't used by any other operations, then consider
7377 /// transforming the pair to integer load / store operations if the target
7378 /// deems the transformation profitable.
7379 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
7380 StoreSDNode *ST = cast<StoreSDNode>(N);
7381 SDValue Chain = ST->getChain();
7382 SDValue Value = ST->getValue();
7383 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
7384 Value.hasOneUse() &&
7385 Chain == SDValue(Value.getNode(), 1)) {
7386 LoadSDNode *LD = cast<LoadSDNode>(Value);
7387 EVT VT = LD->getMemoryVT();
7388 if (!VT.isFloatingPoint() ||
7389 VT != ST->getMemoryVT() ||
7390 LD->isNonTemporal() ||
7391 ST->isNonTemporal() ||
7392 LD->getPointerInfo().getAddrSpace() != 0 ||
7393 ST->getPointerInfo().getAddrSpace() != 0)
7396 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
7397 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
7398 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
7399 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
7400 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
7403 unsigned LDAlign = LD->getAlignment();
7404 unsigned STAlign = ST->getAlignment();
7405 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
7406 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy);
7407 if (LDAlign < ABIAlign || STAlign < ABIAlign)
7410 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(),
7411 LD->getChain(), LD->getBasePtr(),
7412 LD->getPointerInfo(),
7413 false, false, false, LDAlign);
7415 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(),
7416 NewLD, ST->getBasePtr(),
7417 ST->getPointerInfo(),
7418 false, false, STAlign);
7420 AddToWorkList(NewLD.getNode());
7421 AddToWorkList(NewST.getNode());
7422 WorkListRemover DeadNodes(*this);
7423 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1));
7431 /// Returns the base pointer and an integer offset from that object.
7432 static std::pair<SDValue, int64_t> GetPointerBaseAndOffset(SDValue Ptr) {
7433 if (Ptr->getOpcode() == ISD::ADD && isa<ConstantSDNode>(Ptr->getOperand(1))) {
7434 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
7435 SDValue Base = Ptr->getOperand(0);
7436 return std::make_pair(Base, Offset);
7439 return std::make_pair(Ptr, 0);
7442 /// Holds a pointer to an LSBaseSDNode as well as information on where it
7443 /// is located in a sequence of memory operations connected by a chain.
7445 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq):
7446 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { }
7447 // Ptr to the mem node.
7448 LSBaseSDNode *MemNode;
7449 // Offset from the base ptr.
7450 int64_t OffsetFromBase;
7451 // What is the sequence number of this mem node.
7452 // Lowest mem operand in the DAG starts at zero.
7453 unsigned SequenceNum;
7456 /// Sorts store nodes in a link according to their offset from a shared
7458 struct ConsecutiveMemoryChainSorter {
7459 bool operator()(MemOpLink LHS, MemOpLink RHS) {
7460 return LHS.OffsetFromBase < RHS.OffsetFromBase;
7464 bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
7465 EVT MemVT = St->getMemoryVT();
7466 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8;
7468 // Don't merge vectors into wider inputs.
7469 if (MemVT.isVector() || !MemVT.isSimple())
7472 // Perform an early exit check. Do not bother looking at stored values that
7473 // are not constants or loads.
7474 SDValue StoredVal = St->getValue();
7475 bool IsLoadSrc = isa<LoadSDNode>(StoredVal);
7476 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) &&
7480 // Only look at ends of store sequences.
7481 SDValue Chain = SDValue(St, 1);
7482 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE)
7485 // This holds the base pointer and the offset in bytes from the base pointer.
7486 std::pair<SDValue, int64_t> BasePtr =
7487 GetPointerBaseAndOffset(St->getBasePtr());
7489 // We must have a base and an offset.
7490 if (!BasePtr.first.getNode())
7493 // Do not handle stores to undef base pointers.
7494 if (BasePtr.first.getOpcode() == ISD::UNDEF)
7497 SmallVector<MemOpLink, 8> StoreNodes;
7498 // Walk up the chain and look for nodes with offsets from the same
7499 // base pointer. Stop when reaching an instruction with a different kind
7500 // or instruction which has a different base pointer.
7502 StoreSDNode *Index = St;
7504 // If the chain has more than one use, then we can't reorder the mem ops.
7505 if (Index != St && !SDValue(Index, 1)->hasOneUse())
7508 // Find the base pointer and offset for this memory node.
7509 std::pair<SDValue, int64_t> Ptr =
7510 GetPointerBaseAndOffset(Index->getBasePtr());
7512 // Check that the base pointer is the same as the original one.
7513 if (Ptr.first.getNode() != BasePtr.first.getNode())
7516 // Check that the alignment is the same.
7517 if (Index->getAlignment() != St->getAlignment())
7520 // The memory operands must not be volatile.
7521 if (Index->isVolatile() || Index->isIndexed())
7525 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index))
7526 if (St->isTruncatingStore())
7529 // The stored memory type must be the same.
7530 if (Index->getMemoryVT() != MemVT)
7533 // We do not allow unaligned stores because we want to prevent overriding
7535 if (Index->getAlignment()*8 != MemVT.getSizeInBits())
7538 // We found a potential memory operand to merge.
7539 StoreNodes.push_back(MemOpLink(Index, Ptr.second, Seq++));
7541 // Move up the chain to the next memory operation.
7542 Index = dyn_cast<StoreSDNode>(Index->getChain().getNode());
7545 // Check if there is anything to merge.
7546 if (StoreNodes.size() < 2)
7549 // Sort the memory operands according to their distance from the base pointer.
7550 std::sort(StoreNodes.begin(), StoreNodes.end(),
7551 ConsecutiveMemoryChainSorter());
7553 // Scan the memory operations on the chain and find the first non-consecutive
7554 // store memory address.
7555 unsigned LastConsecutiveStore = 0;
7556 int64_t StartAddress = StoreNodes[0].OffsetFromBase;
7557 for (unsigned i=1; i<StoreNodes.size(); ++i) {
7558 int64_t CurrAddress = StoreNodes[i].OffsetFromBase;
7559 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
7562 // Mark this node as useful.
7563 LastConsecutiveStore = i;
7566 // The node with the lowest store address.
7567 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;
7569 // Store the constants into memory as one consecutive store.
7571 unsigned LastLegalType = 0;
7572 unsigned LastLegalVectorType = 0;
7573 bool NonZero = false;
7574 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
7575 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
7576 SDValue StoredVal = St->getValue();
7578 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) {
7579 NonZero |= !C->isNullValue();
7580 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) {
7581 NonZero |= !C->getConstantFPValue()->isNullValue();
7587 // Find a legal type for the constant store.
7588 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
7589 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
7590 if (TLI.isTypeLegal(StoreTy))
7591 LastLegalType = i+1;
7593 // Find a legal type for the vector store.
7594 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
7595 if (TLI.isTypeLegal(Ty))
7596 LastLegalVectorType = i + 1;
7599 // We only use vectors if the constant is known to be zero.
7601 LastLegalVectorType = 0;
7603 // Check if we found a legal integer type to store.
7604 if (LastLegalType == 0 && LastLegalVectorType == 0)
7607 bool UseVector = LastLegalVectorType > LastLegalType;
7608 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType;
7610 // Make sure we have something to merge.
7614 unsigned EarliestNodeUsed = 0;
7615 for (unsigned i=0; i < NumElem; ++i) {
7616 // Find a chain for the new wide-store operand. Notice that some
7617 // of the store nodes that we found may not be selected for inclusion
7618 // in the wide store. The chain we use needs to be the chain of the
7619 // earliest store node which is *used* and replaced by the wide store.
7620 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
7621 EarliestNodeUsed = i;
7624 // The earliest Node in the DAG.
7625 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
7626 DebugLoc DL = StoreNodes[0].MemNode->getDebugLoc();
7630 // Find a legal type for the vector store.
7631 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
7632 assert(TLI.isTypeLegal(Ty) && "Illegal vector store");
7633 StoredVal = DAG.getConstant(0, Ty);
7635 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
7636 APInt StoreInt(StoreBW, 0);
7638 // Construct a single integer constant which is made of the smaller
7640 bool IsLE = TLI.isLittleEndian();
7641 for (unsigned i = 0; i < NumElem ; ++i) {
7642 unsigned Idx = IsLE ?(NumElem - 1 - i) : i;
7643 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode);
7644 SDValue Val = St->getValue();
7645 StoreInt<<=ElementSizeBytes*8;
7646 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) {
7647 StoreInt|=C->getAPIntValue().zext(StoreBW);
7648 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) {
7649 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW);
7651 assert(false && "Invalid constant element type");
7655 // Create the new Load and Store operations.
7656 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
7657 StoredVal = DAG.getConstant(StoreInt, StoreTy);
7660 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal,
7661 FirstInChain->getBasePtr(),
7662 FirstInChain->getPointerInfo(),
7664 FirstInChain->getAlignment());
7666 // Replace the first store with the new store
7667 CombineTo(EarliestOp, NewStore);
7668 // Erase all other stores.
7669 for (unsigned i = 0; i < NumElem ; ++i) {
7670 if (StoreNodes[i].MemNode == EarliestOp)
7672 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
7673 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain());
7674 removeFromWorkList(St);
7681 // Below we handle the case of multiple consecutive stores that
7682 // come from multiple consecutive loads. We merge them into a single
7683 // wide load and a single wide store.
7685 // Look for load nodes which are used by the stored values.
7686 SmallVector<MemOpLink, 8> LoadNodes;
7688 // Find acceptable loads. Loads need to have the same chain (token factor),
7689 // must not be zext, volatile, indexed, and they must be consecutive.
7691 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
7692 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
7693 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue());
7696 // Loads must only have one use.
7697 if (!Ld->hasNUsesOfValue(1, 0))
7700 // Check that the alignment is the same as the stores.
7701 if (Ld->getAlignment() != St->getAlignment())
7704 // The memory operands must not be volatile.
7705 if (Ld->isVolatile() || Ld->isIndexed())
7708 // We do not accept ext loads.
7709 if (Ld->getExtensionType() != ISD::NON_EXTLOAD)
7712 // The stored memory type must be the same.
7713 if (Ld->getMemoryVT() != MemVT)
7716 std::pair<SDValue, int64_t> LdPtr =
7717 GetPointerBaseAndOffset(Ld->getBasePtr());
7719 // If this is not the first ptr that we check.
7720 if (LdBasePtr.getNode()) {
7721 // The base ptr must be the same.
7722 if (LdPtr.first != LdBasePtr)
7725 // Check that all other base pointers are the same as this one.
7726 LdBasePtr = LdPtr.first;
7729 // We found a potential memory operand to merge.
7730 LoadNodes.push_back(MemOpLink(Ld, LdPtr.second, 0));
7733 if (LoadNodes.size() < 2)
7736 // Scan the memory operations on the chain and find the first non-consecutive
7737 // load memory address. These variables hold the index in the store node
7739 unsigned LastConsecutiveLoad = 0;
7740 // This variable refers to the size and not index in the array.
7741 unsigned LastLegalVectorType = 0;
7742 unsigned LastLegalIntegerType = 0;
7743 StartAddress = LoadNodes[0].OffsetFromBase;
7744 SDValue FirstChain = LoadNodes[0].MemNode->getChain();
7745 for (unsigned i = 1; i < LoadNodes.size(); ++i) {
7746 // All loads much share the same chain.
7747 if (LoadNodes[i].MemNode->getChain() != FirstChain)
7750 int64_t CurrAddress = LoadNodes[i].OffsetFromBase;
7751 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
7753 LastConsecutiveLoad = i;
7755 // Find a legal type for the vector store.
7756 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
7757 if (TLI.isTypeLegal(StoreTy))
7758 LastLegalVectorType = i + 1;
7760 // Find a legal type for the integer store.
7761 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
7762 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
7763 if (TLI.isTypeLegal(StoreTy))
7764 LastLegalIntegerType = i + 1;
7767 // Only use vector types if the vector type is larger than the integer type.
7768 // If they are the same, use integers.
7769 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType;
7770 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType);
7772 // We add +1 here because the LastXXX variables refer to location while
7773 // the NumElem refers to array/index size.
7774 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1;
7775 NumElem = std::min(LastLegalType, NumElem);
7780 // The earliest Node in the DAG.
7781 unsigned EarliestNodeUsed = 0;
7782 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
7783 for (unsigned i=1; i<NumElem; ++i) {
7784 // Find a chain for the new wide-store operand. Notice that some
7785 // of the store nodes that we found may not be selected for inclusion
7786 // in the wide store. The chain we use needs to be the chain of the
7787 // earliest store node which is *used* and replaced by the wide store.
7788 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
7789 EarliestNodeUsed = i;
7792 // Find if it is better to use vectors or integers to load and store
7796 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
7798 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
7799 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
7802 DebugLoc LoadDL = LoadNodes[0].MemNode->getDebugLoc();
7803 DebugLoc StoreDL = StoreNodes[0].MemNode->getDebugLoc();
7805 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode);
7806 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL,
7807 FirstLoad->getChain(),
7808 FirstLoad->getBasePtr(),
7809 FirstLoad->getPointerInfo(),
7810 false, false, false,
7811 FirstLoad->getAlignment());
7813 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad,
7814 FirstInChain->getBasePtr(),
7815 FirstInChain->getPointerInfo(), false, false,
7816 FirstInChain->getAlignment());
7818 // Replace one of the loads with the new load.
7819 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode);
7820 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1),
7821 SDValue(NewLoad.getNode(), 1));
7823 // Remove the rest of the load chains.
7824 for (unsigned i = 1; i < NumElem ; ++i) {
7825 // Replace all chain users of the old load nodes with the chain of the new
7827 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode);
7828 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain());
7831 // Replace the first store with the new store.
7832 CombineTo(EarliestOp, NewStore);
7833 // Erase all other stores.
7834 for (unsigned i = 0; i < NumElem ; ++i) {
7835 // Remove all Store nodes.
7836 if (StoreNodes[i].MemNode == EarliestOp)
7838 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
7839 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain());
7840 removeFromWorkList(St);
7847 SDValue DAGCombiner::visitSTORE(SDNode *N) {
7848 StoreSDNode *ST = cast<StoreSDNode>(N);
7849 SDValue Chain = ST->getChain();
7850 SDValue Value = ST->getValue();
7851 SDValue Ptr = ST->getBasePtr();
7853 // If this is a store of a bit convert, store the input value if the
7854 // resultant store does not need a higher alignment than the original.
7855 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
7856 ST->isUnindexed()) {
7857 unsigned OrigAlign = ST->getAlignment();
7858 EVT SVT = Value.getOperand(0).getValueType();
7859 unsigned Align = TLI.getDataLayout()->
7860 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
7861 if (Align <= OrigAlign &&
7862 ((!LegalOperations && !ST->isVolatile()) ||
7863 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
7864 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
7865 Ptr, ST->getPointerInfo(), ST->isVolatile(),
7866 ST->isNonTemporal(), OrigAlign);
7869 // Turn 'store undef, Ptr' -> nothing.
7870 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
7873 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
7874 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
7875 // NOTE: If the original store is volatile, this transform must not increase
7876 // the number of stores. For example, on x86-32 an f64 can be stored in one
7877 // processor operation but an i64 (which is not legal) requires two. So the
7878 // transform should not be done in this case.
7879 if (Value.getOpcode() != ISD::TargetConstantFP) {
7881 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
7882 default: llvm_unreachable("Unknown FP type");
7883 case MVT::f16: // We don't do this for these yet.
7889 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
7890 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
7891 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
7892 bitcastToAPInt().getZExtValue(), MVT::i32);
7893 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
7894 Ptr, ST->getPointerInfo(), ST->isVolatile(),
7895 ST->isNonTemporal(), ST->getAlignment());
7899 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
7900 !ST->isVolatile()) ||
7901 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
7902 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
7903 getZExtValue(), MVT::i64);
7904 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
7905 Ptr, ST->getPointerInfo(), ST->isVolatile(),
7906 ST->isNonTemporal(), ST->getAlignment());
7909 if (!ST->isVolatile() &&
7910 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
7911 // Many FP stores are not made apparent until after legalize, e.g. for
7912 // argument passing. Since this is so common, custom legalize the
7913 // 64-bit integer store into two 32-bit stores.
7914 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
7915 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
7916 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
7917 if (TLI.isBigEndian()) std::swap(Lo, Hi);
7919 unsigned Alignment = ST->getAlignment();
7920 bool isVolatile = ST->isVolatile();
7921 bool isNonTemporal = ST->isNonTemporal();
7923 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
7924 Ptr, ST->getPointerInfo(),
7925 isVolatile, isNonTemporal,
7926 ST->getAlignment());
7927 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
7928 DAG.getConstant(4, Ptr.getValueType()));
7929 Alignment = MinAlign(Alignment, 4U);
7930 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
7931 Ptr, ST->getPointerInfo().getWithOffset(4),
7932 isVolatile, isNonTemporal,
7934 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
7943 // Try to infer better alignment information than the store already has.
7944 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
7945 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
7946 if (Align > ST->getAlignment())
7947 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
7948 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
7949 ST->isVolatile(), ST->isNonTemporal(), Align);
7953 // Try transforming a pair floating point load / store ops to integer
7954 // load / store ops.
7955 SDValue NewST = TransformFPLoadStorePair(N);
7956 if (NewST.getNode())
7960 // Walk up chain skipping non-aliasing memory nodes.
7961 SDValue BetterChain = FindBetterChain(N, Chain);
7963 // If there is a better chain.
7964 if (Chain != BetterChain) {
7967 // Replace the chain to avoid dependency.
7968 if (ST->isTruncatingStore()) {
7969 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
7970 ST->getPointerInfo(),
7971 ST->getMemoryVT(), ST->isVolatile(),
7972 ST->isNonTemporal(), ST->getAlignment());
7974 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
7975 ST->getPointerInfo(),
7976 ST->isVolatile(), ST->isNonTemporal(),
7977 ST->getAlignment());
7980 // Create token to keep both nodes around.
7981 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
7982 MVT::Other, Chain, ReplStore);
7984 // Make sure the new and old chains are cleaned up.
7985 AddToWorkList(Token.getNode());
7987 // Don't add users to work list.
7988 return CombineTo(N, Token, false);
7992 // Try transforming N to an indexed store.
7993 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
7994 return SDValue(N, 0);
7996 // FIXME: is there such a thing as a truncating indexed store?
7997 if (ST->isTruncatingStore() && ST->isUnindexed() &&
7998 Value.getValueType().isInteger()) {
7999 // See if we can simplify the input to this truncstore with knowledge that
8000 // only the low bits are being used. For example:
8001 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
8003 GetDemandedBits(Value,
8004 APInt::getLowBitsSet(
8005 Value.getValueType().getScalarType().getSizeInBits(),
8006 ST->getMemoryVT().getScalarType().getSizeInBits()));
8007 AddToWorkList(Value.getNode());
8008 if (Shorter.getNode())
8009 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
8010 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
8011 ST->isVolatile(), ST->isNonTemporal(),
8012 ST->getAlignment());
8014 // Otherwise, see if we can simplify the operation with
8015 // SimplifyDemandedBits, which only works if the value has a single use.
8016 if (SimplifyDemandedBits(Value,
8017 APInt::getLowBitsSet(
8018 Value.getValueType().getScalarType().getSizeInBits(),
8019 ST->getMemoryVT().getScalarType().getSizeInBits())))
8020 return SDValue(N, 0);
8023 // If this is a load followed by a store to the same location, then the store
8025 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
8026 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
8027 ST->isUnindexed() && !ST->isVolatile() &&
8028 // There can't be any side effects between the load and store, such as
8030 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
8031 // The store is dead, remove it.
8036 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
8037 // truncating store. We can do this even if this is already a truncstore.
8038 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
8039 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
8040 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
8041 ST->getMemoryVT())) {
8042 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
8043 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
8044 ST->isVolatile(), ST->isNonTemporal(),
8045 ST->getAlignment());
8048 // Only perform this optimization before the types are legal, because we
8049 // don't want to perform this optimization on every DAGCombine invocation.
8050 if (!LegalTypes && MergeConsecutiveStores(ST))
8051 return SDValue(N, 0);
8053 return ReduceLoadOpStoreWidth(N);
8056 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
8057 SDValue InVec = N->getOperand(0);
8058 SDValue InVal = N->getOperand(1);
8059 SDValue EltNo = N->getOperand(2);
8060 DebugLoc dl = N->getDebugLoc();
8062 // If the inserted element is an UNDEF, just use the input vector.
8063 if (InVal.getOpcode() == ISD::UNDEF)
8066 EVT VT = InVec.getValueType();
8068 // If we can't generate a legal BUILD_VECTOR, exit
8069 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
8072 // Check that we know which element is being inserted
8073 if (!isa<ConstantSDNode>(EltNo))
8075 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
8077 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
8078 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
8080 SmallVector<SDValue, 8> Ops;
8081 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
8082 Ops.append(InVec.getNode()->op_begin(),
8083 InVec.getNode()->op_end());
8084 } else if (InVec.getOpcode() == ISD::UNDEF) {
8085 unsigned NElts = VT.getVectorNumElements();
8086 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
8091 // Insert the element
8092 if (Elt < Ops.size()) {
8093 // All the operands of BUILD_VECTOR must have the same type;
8094 // we enforce that here.
8095 EVT OpVT = Ops[0].getValueType();
8096 if (InVal.getValueType() != OpVT)
8097 InVal = OpVT.bitsGT(InVal.getValueType()) ?
8098 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
8099 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
8103 // Return the new vector
8104 return DAG.getNode(ISD::BUILD_VECTOR, dl,
8105 VT, &Ops[0], Ops.size());
8108 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
8109 // (vextract (scalar_to_vector val, 0) -> val
8110 SDValue InVec = N->getOperand(0);
8111 EVT VT = InVec.getValueType();
8112 EVT NVT = N->getValueType(0);
8114 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
8115 // Check if the result type doesn't match the inserted element type. A
8116 // SCALAR_TO_VECTOR may truncate the inserted element and the
8117 // EXTRACT_VECTOR_ELT may widen the extracted vector.
8118 SDValue InOp = InVec.getOperand(0);
8119 if (InOp.getValueType() != NVT) {
8120 assert(InOp.getValueType().isInteger() && NVT.isInteger());
8121 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
8126 SDValue EltNo = N->getOperand(1);
8127 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
8129 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
8130 // We only perform this optimization before the op legalization phase because
8131 // we may introduce new vector instructions which are not backed by TD
8132 // patterns. For example on AVX, extracting elements from a wide vector
8133 // without using extract_subvector.
8134 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
8135 && ConstEltNo && !LegalOperations) {
8136 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
8137 int NumElem = VT.getVectorNumElements();
8138 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
8139 // Find the new index to extract from.
8140 int OrigElt = SVOp->getMaskElt(Elt);
8142 // Extracting an undef index is undef.
8144 return DAG.getUNDEF(NVT);
8146 // Select the right vector half to extract from.
8147 if (OrigElt < NumElem) {
8148 InVec = InVec->getOperand(0);
8150 InVec = InVec->getOperand(1);
8154 EVT IndexTy = N->getOperand(1).getValueType();
8155 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT,
8156 InVec, DAG.getConstant(OrigElt, IndexTy));
8159 // Perform only after legalization to ensure build_vector / vector_shuffle
8160 // optimizations have already been done.
8161 if (!LegalOperations) return SDValue();
8163 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
8164 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
8165 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
8168 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
8169 bool NewLoad = false;
8170 bool BCNumEltsChanged = false;
8171 EVT ExtVT = VT.getVectorElementType();
8174 // If the result of load has to be truncated, then it's not necessarily
8176 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT))
8179 if (InVec.getOpcode() == ISD::BITCAST) {
8180 // Don't duplicate a load with other uses.
8181 if (!InVec.hasOneUse())
8184 EVT BCVT = InVec.getOperand(0).getValueType();
8185 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
8187 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
8188 BCNumEltsChanged = true;
8189 InVec = InVec.getOperand(0);
8190 ExtVT = BCVT.getVectorElementType();
8194 LoadSDNode *LN0 = NULL;
8195 const ShuffleVectorSDNode *SVN = NULL;
8196 if (ISD::isNormalLoad(InVec.getNode())) {
8197 LN0 = cast<LoadSDNode>(InVec);
8198 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
8199 InVec.getOperand(0).getValueType() == ExtVT &&
8200 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
8201 // Don't duplicate a load with other uses.
8202 if (!InVec.hasOneUse())
8205 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
8206 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
8207 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
8209 // (load $addr+1*size)
8211 // Don't duplicate a load with other uses.
8212 if (!InVec.hasOneUse())
8215 // If the bit convert changed the number of elements, it is unsafe
8216 // to examine the mask.
8217 if (BCNumEltsChanged)
8220 // Select the input vector, guarding against out of range extract vector.
8221 unsigned NumElems = VT.getVectorNumElements();
8222 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
8223 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
8225 if (InVec.getOpcode() == ISD::BITCAST) {
8226 // Don't duplicate a load with other uses.
8227 if (!InVec.hasOneUse())
8230 InVec = InVec.getOperand(0);
8232 if (ISD::isNormalLoad(InVec.getNode())) {
8233 LN0 = cast<LoadSDNode>(InVec);
8234 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
8238 // Make sure we found a non-volatile load and the extractelement is
8240 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
8243 // If Idx was -1 above, Elt is going to be -1, so just return undef.
8245 return DAG.getUNDEF(LVT);
8247 unsigned Align = LN0->getAlignment();
8249 // Check the resultant load doesn't need a higher alignment than the
8253 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
8255 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
8261 SDValue NewPtr = LN0->getBasePtr();
8262 unsigned PtrOff = 0;
8265 PtrOff = LVT.getSizeInBits() * Elt / 8;
8266 EVT PtrType = NewPtr.getValueType();
8267 if (TLI.isBigEndian())
8268 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
8269 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
8270 DAG.getConstant(PtrOff, PtrType));
8273 // The replacement we need to do here is a little tricky: we need to
8274 // replace an extractelement of a load with a load.
8275 // Use ReplaceAllUsesOfValuesWith to do the replacement.
8276 // Note that this replacement assumes that the extractvalue is the only
8277 // use of the load; that's okay because we don't want to perform this
8278 // transformation in other cases anyway.
8281 if (NVT.bitsGT(LVT)) {
8282 // If the result type of vextract is wider than the load, then issue an
8283 // extending load instead.
8284 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT)
8285 ? ISD::ZEXTLOAD : ISD::EXTLOAD;
8286 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(),
8287 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff),
8288 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align);
8289 Chain = Load.getValue(1);
8291 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
8292 LN0->getPointerInfo().getWithOffset(PtrOff),
8293 LN0->isVolatile(), LN0->isNonTemporal(),
8294 LN0->isInvariant(), Align);
8295 Chain = Load.getValue(1);
8296 if (NVT.bitsLT(LVT))
8297 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load);
8299 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load);
8301 WorkListRemover DeadNodes(*this);
8302 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) };
8303 SDValue To[] = { Load, Chain };
8304 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
8305 // Since we're explcitly calling ReplaceAllUses, add the new node to the
8306 // worklist explicitly as well.
8307 AddToWorkList(Load.getNode());
8308 AddUsersToWorkList(Load.getNode()); // Add users too
8309 // Make sure to revisit this node to clean it up; it will usually be dead.
8311 return SDValue(N, 0);
8317 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
8318 unsigned NumInScalars = N->getNumOperands();
8319 DebugLoc dl = N->getDebugLoc();
8320 EVT VT = N->getValueType(0);
8322 // A vector built entirely of undefs is undef.
8323 if (ISD::allOperandsUndef(N))
8324 return DAG.getUNDEF(VT);
8326 // Check to see if this is a BUILD_VECTOR of a bunch of values
8327 // which come from any_extend or zero_extend nodes. If so, we can create
8328 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
8329 // optimizations. We do not handle sign-extend because we can't fill the sign
8331 EVT SourceType = MVT::Other;
8332 bool AllAnyExt = true;
8334 for (unsigned i = 0; i != NumInScalars; ++i) {
8335 SDValue In = N->getOperand(i);
8336 // Ignore undef inputs.
8337 if (In.getOpcode() == ISD::UNDEF) continue;
8339 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
8340 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
8342 // Abort if the element is not an extension.
8343 if (!ZeroExt && !AnyExt) {
8344 SourceType = MVT::Other;
8348 // The input is a ZeroExt or AnyExt. Check the original type.
8349 EVT InTy = In.getOperand(0).getValueType();
8351 // Check that all of the widened source types are the same.
8352 if (SourceType == MVT::Other)
8355 else if (InTy != SourceType) {
8356 // Multiple income types. Abort.
8357 SourceType = MVT::Other;
8361 // Check if all of the extends are ANY_EXTENDs.
8362 AllAnyExt &= AnyExt;
8365 // In order to have valid types, all of the inputs must be extended from the
8366 // same source type and all of the inputs must be any or zero extend.
8367 // Scalar sizes must be a power of two.
8368 EVT OutScalarTy = N->getValueType(0).getScalarType();
8369 bool ValidTypes = SourceType != MVT::Other &&
8370 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
8371 isPowerOf2_32(SourceType.getSizeInBits());
8373 // We perform this optimization post type-legalization because
8374 // the type-legalizer often scalarizes integer-promoted vectors.
8375 // Performing this optimization before may create bit-casts which
8376 // will be type-legalized to complex code sequences.
8377 // We perform this optimization only before the operation legalizer because we
8378 // may introduce illegal operations.
8379 // Create a new simpler BUILD_VECTOR sequence which other optimizations can
8380 // turn into a single shuffle instruction.
8381 if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) &&
8383 bool isLE = TLI.isLittleEndian();
8384 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
8385 assert(ElemRatio > 1 && "Invalid element size ratio");
8386 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
8387 DAG.getConstant(0, SourceType);
8389 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements();
8390 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
8392 // Populate the new build_vector
8393 for (unsigned i=0; i < N->getNumOperands(); ++i) {
8394 SDValue Cast = N->getOperand(i);
8395 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
8396 Cast.getOpcode() == ISD::ZERO_EXTEND ||
8397 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
8399 if (Cast.getOpcode() == ISD::UNDEF)
8400 In = DAG.getUNDEF(SourceType);
8402 In = Cast->getOperand(0);
8403 unsigned Index = isLE ? (i * ElemRatio) :
8404 (i * ElemRatio + (ElemRatio - 1));
8406 assert(Index < Ops.size() && "Invalid index");
8410 // The type of the new BUILD_VECTOR node.
8411 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
8412 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() &&
8413 "Invalid vector size");
8414 // Check if the new vector type is legal.
8415 if (!isTypeLegal(VecVT)) return SDValue();
8417 // Make the new BUILD_VECTOR.
8418 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
8419 VecVT, &Ops[0], Ops.size());
8421 // The new BUILD_VECTOR node has the potential to be further optimized.
8422 AddToWorkList(BV.getNode());
8423 // Bitcast to the desired type.
8424 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV);
8427 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
8428 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
8429 // at most two distinct vectors, turn this into a shuffle node.
8431 // May only combine to shuffle after legalize if shuffle is legal.
8432 if (LegalOperations &&
8433 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))
8436 SDValue VecIn1, VecIn2;
8437 for (unsigned i = 0; i != NumInScalars; ++i) {
8438 // Ignore undef inputs.
8439 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
8441 // If this input is something other than a EXTRACT_VECTOR_ELT with a
8442 // constant index, bail out.
8443 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
8444 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
8445 VecIn1 = VecIn2 = SDValue(0, 0);
8449 // We allow up to two distinct input vectors.
8450 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
8451 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
8454 if (VecIn1.getNode() == 0) {
8455 VecIn1 = ExtractedFromVec;
8456 } else if (VecIn2.getNode() == 0) {
8457 VecIn2 = ExtractedFromVec;
8460 VecIn1 = VecIn2 = SDValue(0, 0);
8465 // If everything is good, we can make a shuffle operation.
8466 if (VecIn1.getNode()) {
8467 SmallVector<int, 8> Mask;
8468 for (unsigned i = 0; i != NumInScalars; ++i) {
8469 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
8474 // If extracting from the first vector, just use the index directly.
8475 SDValue Extract = N->getOperand(i);
8476 SDValue ExtVal = Extract.getOperand(1);
8477 if (Extract.getOperand(0) == VecIn1) {
8478 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
8479 if (ExtIndex > VT.getVectorNumElements())
8482 Mask.push_back(ExtIndex);
8486 // Otherwise, use InIdx + VecSize
8487 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
8488 Mask.push_back(Idx+NumInScalars);
8491 // We can't generate a shuffle node with mismatched input and output types.
8492 // Attempt to transform a single input vector to the correct type.
8493 if ((VT != VecIn1.getValueType())) {
8494 // We don't support shuffeling between TWO values of different types.
8495 if (VecIn2.getNode() != 0)
8498 // We only support widening of vectors which are half the size of the
8499 // output registers. For example XMM->YMM widening on X86 with AVX.
8500 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits())
8503 // If the input vector type has a different base type to the output
8504 // vector type, bail out.
8505 if (VecIn1.getValueType().getVectorElementType() !=
8506 VT.getVectorElementType())
8509 // Widen the input vector by adding undef values.
8510 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
8511 VecIn1, DAG.getUNDEF(VecIn1.getValueType()));
8514 // If VecIn2 is unused then change it to undef.
8515 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
8517 // Check that we were able to transform all incoming values to the same
8519 if (VecIn2.getValueType() != VecIn1.getValueType() ||
8520 VecIn1.getValueType() != VT)
8523 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
8524 if (!isTypeLegal(VT))
8527 // Return the new VECTOR_SHUFFLE node.
8531 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
8537 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
8538 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
8539 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
8540 // inputs come from at most two distinct vectors, turn this into a shuffle
8543 // If we only have one input vector, we don't need to do any concatenation.
8544 if (N->getNumOperands() == 1)
8545 return N->getOperand(0);
8547 // Check if all of the operands are undefs.
8548 if (ISD::allOperandsUndef(N))
8549 return DAG.getUNDEF(N->getValueType(0));
8554 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
8555 EVT NVT = N->getValueType(0);
8556 SDValue V = N->getOperand(0);
8558 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
8559 // Handle only simple case where vector being inserted and vector
8560 // being extracted are of same type, and are half size of larger vectors.
8561 EVT BigVT = V->getOperand(0).getValueType();
8562 EVT SmallVT = V->getOperand(1).getValueType();
8563 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
8566 // Only handle cases where both indexes are constants with the same type.
8567 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
8568 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
8570 if (InsIdx && ExtIdx &&
8571 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
8572 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
8574 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
8576 // indices are equal => V1
8577 // otherwise => (extract_subvec V1, ExtIdx)
8578 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue())
8579 return V->getOperand(1);
8580 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT,
8581 V->getOperand(0), N->getOperand(1));
8585 if (V->getOpcode() == ISD::CONCAT_VECTORS) {
8587 // (extract_subvec (concat V1, V2, ...), i)
8590 for (unsigned i = 0, e = V->getNumOperands(); i != e; ++i)
8591 if (V->getOperand(i).getValueType() != NVT)
8593 unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8594 unsigned NumElems = NVT.getVectorNumElements();
8595 assert((Idx % NumElems) == 0 &&
8596 "IDX in concat is not a multiple of the result vector length.");
8597 return V->getOperand(Idx / NumElems);
8603 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
8604 EVT VT = N->getValueType(0);
8605 unsigned NumElts = VT.getVectorNumElements();
8607 SDValue N0 = N->getOperand(0);
8608 SDValue N1 = N->getOperand(1);
8610 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
8612 // Canonicalize shuffle undef, undef -> undef
8613 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
8614 return DAG.getUNDEF(VT);
8616 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8618 // Canonicalize shuffle v, v -> v, undef
8620 SmallVector<int, 8> NewMask;
8621 for (unsigned i = 0; i != NumElts; ++i) {
8622 int Idx = SVN->getMaskElt(i);
8623 if (Idx >= (int)NumElts) Idx -= NumElts;
8624 NewMask.push_back(Idx);
8626 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT),
8630 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
8631 if (N0.getOpcode() == ISD::UNDEF) {
8632 SmallVector<int, 8> NewMask;
8633 for (unsigned i = 0; i != NumElts; ++i) {
8634 int Idx = SVN->getMaskElt(i);
8636 if (Idx < (int)NumElts)
8641 NewMask.push_back(Idx);
8643 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT),
8647 // Remove references to rhs if it is undef
8648 if (N1.getOpcode() == ISD::UNDEF) {
8649 bool Changed = false;
8650 SmallVector<int, 8> NewMask;
8651 for (unsigned i = 0; i != NumElts; ++i) {
8652 int Idx = SVN->getMaskElt(i);
8653 if (Idx >= (int)NumElts) {
8657 NewMask.push_back(Idx);
8660 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]);
8663 // If it is a splat, check if the argument vector is another splat or a
8664 // build_vector with all scalar elements the same.
8665 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
8666 SDNode *V = N0.getNode();
8668 // If this is a bit convert that changes the element type of the vector but
8669 // not the number of vector elements, look through it. Be careful not to
8670 // look though conversions that change things like v4f32 to v2f64.
8671 if (V->getOpcode() == ISD::BITCAST) {
8672 SDValue ConvInput = V->getOperand(0);
8673 if (ConvInput.getValueType().isVector() &&
8674 ConvInput.getValueType().getVectorNumElements() == NumElts)
8675 V = ConvInput.getNode();
8678 if (V->getOpcode() == ISD::BUILD_VECTOR) {
8679 assert(V->getNumOperands() == NumElts &&
8680 "BUILD_VECTOR has wrong number of operands");
8682 bool AllSame = true;
8683 for (unsigned i = 0; i != NumElts; ++i) {
8684 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
8685 Base = V->getOperand(i);
8689 // Splat of <u, u, u, u>, return <u, u, u, u>
8690 if (!Base.getNode())
8692 for (unsigned i = 0; i != NumElts; ++i) {
8693 if (V->getOperand(i) != Base) {
8698 // Splat of <x, x, x, x>, return <x, x, x, x>
8704 // If this shuffle node is simply a swizzle of another shuffle node,
8705 // and it reverses the swizzle of the previous shuffle then we can
8706 // optimize shuffle(shuffle(x, undef), undef) -> x.
8707 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
8708 N1.getOpcode() == ISD::UNDEF) {
8710 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
8712 // Shuffle nodes can only reverse shuffles with a single non-undef value.
8713 if (N0.getOperand(1).getOpcode() != ISD::UNDEF)
8716 // The incoming shuffle must be of the same type as the result of the
8718 assert(OtherSV->getOperand(0).getValueType() == VT &&
8719 "Shuffle types don't match");
8721 for (unsigned i = 0; i != NumElts; ++i) {
8722 int Idx = SVN->getMaskElt(i);
8723 assert(Idx < (int)NumElts && "Index references undef operand");
8724 // Next, this index comes from the first value, which is the incoming
8725 // shuffle. Adopt the incoming index.
8727 Idx = OtherSV->getMaskElt(Idx);
8729 // The combined shuffle must map each index to itself.
8730 if (Idx >= 0 && (unsigned)Idx != i)
8734 return OtherSV->getOperand(0);
8740 SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
8741 if (!TLI.getShouldFoldAtomicFences())
8744 SDValue atomic = N->getOperand(0);
8745 switch (atomic.getOpcode()) {
8746 case ISD::ATOMIC_CMP_SWAP:
8747 case ISD::ATOMIC_SWAP:
8748 case ISD::ATOMIC_LOAD_ADD:
8749 case ISD::ATOMIC_LOAD_SUB:
8750 case ISD::ATOMIC_LOAD_AND:
8751 case ISD::ATOMIC_LOAD_OR:
8752 case ISD::ATOMIC_LOAD_XOR:
8753 case ISD::ATOMIC_LOAD_NAND:
8754 case ISD::ATOMIC_LOAD_MIN:
8755 case ISD::ATOMIC_LOAD_MAX:
8756 case ISD::ATOMIC_LOAD_UMIN:
8757 case ISD::ATOMIC_LOAD_UMAX:
8763 SDValue fence = atomic.getOperand(0);
8764 if (fence.getOpcode() != ISD::MEMBARRIER)
8767 switch (atomic.getOpcode()) {
8768 case ISD::ATOMIC_CMP_SWAP:
8769 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
8770 fence.getOperand(0),
8771 atomic.getOperand(1), atomic.getOperand(2),
8772 atomic.getOperand(3)), atomic.getResNo());
8773 case ISD::ATOMIC_SWAP:
8774 case ISD::ATOMIC_LOAD_ADD:
8775 case ISD::ATOMIC_LOAD_SUB:
8776 case ISD::ATOMIC_LOAD_AND:
8777 case ISD::ATOMIC_LOAD_OR:
8778 case ISD::ATOMIC_LOAD_XOR:
8779 case ISD::ATOMIC_LOAD_NAND:
8780 case ISD::ATOMIC_LOAD_MIN:
8781 case ISD::ATOMIC_LOAD_MAX:
8782 case ISD::ATOMIC_LOAD_UMIN:
8783 case ISD::ATOMIC_LOAD_UMAX:
8784 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
8785 fence.getOperand(0),
8786 atomic.getOperand(1), atomic.getOperand(2)),
8793 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
8794 /// an AND to a vector_shuffle with the destination vector and a zero vector.
8795 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
8796 /// vector_shuffle V, Zero, <0, 4, 2, 4>
8797 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
8798 EVT VT = N->getValueType(0);
8799 DebugLoc dl = N->getDebugLoc();
8800 SDValue LHS = N->getOperand(0);
8801 SDValue RHS = N->getOperand(1);
8802 if (N->getOpcode() == ISD::AND) {
8803 if (RHS.getOpcode() == ISD::BITCAST)
8804 RHS = RHS.getOperand(0);
8805 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
8806 SmallVector<int, 8> Indices;
8807 unsigned NumElts = RHS.getNumOperands();
8808 for (unsigned i = 0; i != NumElts; ++i) {
8809 SDValue Elt = RHS.getOperand(i);
8810 if (!isa<ConstantSDNode>(Elt))
8813 if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
8814 Indices.push_back(i);
8815 else if (cast<ConstantSDNode>(Elt)->isNullValue())
8816 Indices.push_back(NumElts);
8821 // Let's see if the target supports this vector_shuffle.
8822 EVT RVT = RHS.getValueType();
8823 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
8826 // Return the new VECTOR_SHUFFLE node.
8827 EVT EltVT = RVT.getVectorElementType();
8828 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
8829 DAG.getConstant(0, EltVT));
8830 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
8831 RVT, &ZeroOps[0], ZeroOps.size());
8832 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
8833 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
8834 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
8841 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
8842 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
8843 // After legalize, the target may be depending on adds and other
8844 // binary ops to provide legal ways to construct constants or other
8845 // things. Simplifying them may result in a loss of legality.
8846 if (LegalOperations) return SDValue();
8848 assert(N->getValueType(0).isVector() &&
8849 "SimplifyVBinOp only works on vectors!");
8851 SDValue LHS = N->getOperand(0);
8852 SDValue RHS = N->getOperand(1);
8853 SDValue Shuffle = XformToShuffleWithZero(N);
8854 if (Shuffle.getNode()) return Shuffle;
8856 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
8858 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
8859 RHS.getOpcode() == ISD::BUILD_VECTOR) {
8860 SmallVector<SDValue, 8> Ops;
8861 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
8862 SDValue LHSOp = LHS.getOperand(i);
8863 SDValue RHSOp = RHS.getOperand(i);
8864 // If these two elements can't be folded, bail out.
8865 if ((LHSOp.getOpcode() != ISD::UNDEF &&
8866 LHSOp.getOpcode() != ISD::Constant &&
8867 LHSOp.getOpcode() != ISD::ConstantFP) ||
8868 (RHSOp.getOpcode() != ISD::UNDEF &&
8869 RHSOp.getOpcode() != ISD::Constant &&
8870 RHSOp.getOpcode() != ISD::ConstantFP))
8873 // Can't fold divide by zero.
8874 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
8875 N->getOpcode() == ISD::FDIV) {
8876 if ((RHSOp.getOpcode() == ISD::Constant &&
8877 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
8878 (RHSOp.getOpcode() == ISD::ConstantFP &&
8879 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
8883 EVT VT = LHSOp.getValueType();
8884 EVT RVT = RHSOp.getValueType();
8886 // Integer BUILD_VECTOR operands may have types larger than the element
8887 // size (e.g., when the element type is not legal). Prior to type
8888 // legalization, the types may not match between the two BUILD_VECTORS.
8889 // Truncate one of the operands to make them match.
8890 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
8891 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp);
8893 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp);
8897 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT,
8899 if (FoldOp.getOpcode() != ISD::UNDEF &&
8900 FoldOp.getOpcode() != ISD::Constant &&
8901 FoldOp.getOpcode() != ISD::ConstantFP)
8903 Ops.push_back(FoldOp);
8904 AddToWorkList(FoldOp.getNode());
8907 if (Ops.size() == LHS.getNumOperands())
8908 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
8909 LHS.getValueType(), &Ops[0], Ops.size());
8915 /// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG.
8916 SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) {
8917 // After legalize, the target may be depending on adds and other
8918 // binary ops to provide legal ways to construct constants or other
8919 // things. Simplifying them may result in a loss of legality.
8920 if (LegalOperations) return SDValue();
8922 assert(N->getValueType(0).isVector() &&
8923 "SimplifyVUnaryOp only works on vectors!");
8925 SDValue N0 = N->getOperand(0);
8927 if (N0.getOpcode() != ISD::BUILD_VECTOR)
8930 // Operand is a BUILD_VECTOR node, see if we can constant fold it.
8931 SmallVector<SDValue, 8> Ops;
8932 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
8933 SDValue Op = N0.getOperand(i);
8934 if (Op.getOpcode() != ISD::UNDEF &&
8935 Op.getOpcode() != ISD::ConstantFP)
8937 EVT EltVT = Op.getValueType();
8938 SDValue FoldOp = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), EltVT, Op);
8939 if (FoldOp.getOpcode() != ISD::UNDEF &&
8940 FoldOp.getOpcode() != ISD::ConstantFP)
8942 Ops.push_back(FoldOp);
8943 AddToWorkList(FoldOp.getNode());
8946 if (Ops.size() != N0.getNumOperands())
8949 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
8950 N0.getValueType(), &Ops[0], Ops.size());
8953 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
8954 SDValue N1, SDValue N2){
8955 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
8957 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
8958 cast<CondCodeSDNode>(N0.getOperand(2))->get());
8960 // If we got a simplified select_cc node back from SimplifySelectCC, then
8961 // break it down into a new SETCC node, and a new SELECT node, and then return
8962 // the SELECT node, since we were called with a SELECT node.
8963 if (SCC.getNode()) {
8964 // Check to see if we got a select_cc back (to turn into setcc/select).
8965 // Otherwise, just return whatever node we got back, like fabs.
8966 if (SCC.getOpcode() == ISD::SELECT_CC) {
8967 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
8969 SCC.getOperand(0), SCC.getOperand(1),
8971 AddToWorkList(SETCC.getNode());
8972 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
8973 SCC.getOperand(2), SCC.getOperand(3), SETCC);
8981 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
8982 /// are the two values being selected between, see if we can simplify the
8983 /// select. Callers of this should assume that TheSelect is deleted if this
8984 /// returns true. As such, they should return the appropriate thing (e.g. the
8985 /// node) back to the top-level of the DAG combiner loop to avoid it being
8987 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
8990 // Cannot simplify select with vector condition
8991 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
8993 // If this is a select from two identical things, try to pull the operation
8994 // through the select.
8995 if (LHS.getOpcode() != RHS.getOpcode() ||
8996 !LHS.hasOneUse() || !RHS.hasOneUse())
8999 // If this is a load and the token chain is identical, replace the select
9000 // of two loads with a load through a select of the address to load from.
9001 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
9002 // constants have been dropped into the constant pool.
9003 if (LHS.getOpcode() == ISD::LOAD) {
9004 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
9005 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
9007 // Token chains must be identical.
9008 if (LHS.getOperand(0) != RHS.getOperand(0) ||
9009 // Do not let this transformation reduce the number of volatile loads.
9010 LLD->isVolatile() || RLD->isVolatile() ||
9011 // If this is an EXTLOAD, the VT's must match.
9012 LLD->getMemoryVT() != RLD->getMemoryVT() ||
9013 // If this is an EXTLOAD, the kind of extension must match.
9014 (LLD->getExtensionType() != RLD->getExtensionType() &&
9015 // The only exception is if one of the extensions is anyext.
9016 LLD->getExtensionType() != ISD::EXTLOAD &&
9017 RLD->getExtensionType() != ISD::EXTLOAD) ||
9018 // FIXME: this discards src value information. This is
9019 // over-conservative. It would be beneficial to be able to remember
9020 // both potential memory locations. Since we are discarding
9021 // src value info, don't do the transformation if the memory
9022 // locations are not in the default address space.
9023 LLD->getPointerInfo().getAddrSpace() != 0 ||
9024 RLD->getPointerInfo().getAddrSpace() != 0)
9027 // Check that the select condition doesn't reach either load. If so,
9028 // folding this will induce a cycle into the DAG. If not, this is safe to
9029 // xform, so create a select of the addresses.
9031 if (TheSelect->getOpcode() == ISD::SELECT) {
9032 SDNode *CondNode = TheSelect->getOperand(0).getNode();
9033 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
9034 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
9036 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
9037 LLD->getBasePtr().getValueType(),
9038 TheSelect->getOperand(0), LLD->getBasePtr(),
9040 } else { // Otherwise SELECT_CC
9041 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
9042 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
9044 if ((LLD->hasAnyUseOfValue(1) &&
9045 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
9046 (RLD->hasAnyUseOfValue(1) &&
9047 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS))))
9050 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
9051 LLD->getBasePtr().getValueType(),
9052 TheSelect->getOperand(0),
9053 TheSelect->getOperand(1),
9054 LLD->getBasePtr(), RLD->getBasePtr(),
9055 TheSelect->getOperand(4));
9059 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
9060 Load = DAG.getLoad(TheSelect->getValueType(0),
9061 TheSelect->getDebugLoc(),
9062 // FIXME: Discards pointer info.
9063 LLD->getChain(), Addr, MachinePointerInfo(),
9064 LLD->isVolatile(), LLD->isNonTemporal(),
9065 LLD->isInvariant(), LLD->getAlignment());
9067 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
9068 RLD->getExtensionType() : LLD->getExtensionType(),
9069 TheSelect->getDebugLoc(),
9070 TheSelect->getValueType(0),
9071 // FIXME: Discards pointer info.
9072 LLD->getChain(), Addr, MachinePointerInfo(),
9073 LLD->getMemoryVT(), LLD->isVolatile(),
9074 LLD->isNonTemporal(), LLD->getAlignment());
9077 // Users of the select now use the result of the load.
9078 CombineTo(TheSelect, Load);
9080 // Users of the old loads now use the new load's chain. We know the
9081 // old-load value is dead now.
9082 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
9083 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
9090 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
9091 /// where 'cond' is the comparison specified by CC.
9092 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
9093 SDValue N2, SDValue N3,
9094 ISD::CondCode CC, bool NotExtCompare) {
9095 // (x ? y : y) -> y.
9096 if (N2 == N3) return N2;
9098 EVT VT = N2.getValueType();
9099 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
9100 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
9101 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
9103 // Determine if the condition we're dealing with is constant
9104 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
9105 N0, N1, CC, DL, false);
9106 if (SCC.getNode()) AddToWorkList(SCC.getNode());
9107 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
9109 // fold select_cc true, x, y -> x
9110 if (SCCC && !SCCC->isNullValue())
9112 // fold select_cc false, x, y -> y
9113 if (SCCC && SCCC->isNullValue())
9116 // Check to see if we can simplify the select into an fabs node
9117 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
9118 // Allow either -0.0 or 0.0
9119 if (CFP->getValueAPF().isZero()) {
9120 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
9121 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
9122 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
9123 N2 == N3.getOperand(0))
9124 return DAG.getNode(ISD::FABS, DL, VT, N0);
9126 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
9127 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
9128 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
9129 N2.getOperand(0) == N3)
9130 return DAG.getNode(ISD::FABS, DL, VT, N3);
9134 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
9135 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
9136 // in it. This is a win when the constant is not otherwise available because
9137 // it replaces two constant pool loads with one. We only do this if the FP
9138 // type is known to be legal, because if it isn't, then we are before legalize
9139 // types an we want the other legalization to happen first (e.g. to avoid
9140 // messing with soft float) and if the ConstantFP is not legal, because if
9141 // it is legal, we may not need to store the FP constant in a constant pool.
9142 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
9143 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
9144 if (TLI.isTypeLegal(N2.getValueType()) &&
9145 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
9146 TargetLowering::Legal) &&
9147 // If both constants have multiple uses, then we won't need to do an
9148 // extra load, they are likely around in registers for other users.
9149 (TV->hasOneUse() || FV->hasOneUse())) {
9150 Constant *Elts[] = {
9151 const_cast<ConstantFP*>(FV->getConstantFPValue()),
9152 const_cast<ConstantFP*>(TV->getConstantFPValue())
9154 Type *FPTy = Elts[0]->getType();
9155 const DataLayout &TD = *TLI.getDataLayout();
9157 // Create a ConstantArray of the two constants.
9158 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
9159 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
9160 TD.getPrefTypeAlignment(FPTy));
9161 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9163 // Get the offsets to the 0 and 1 element of the array so that we can
9164 // select between them.
9165 SDValue Zero = DAG.getIntPtrConstant(0);
9166 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
9167 SDValue One = DAG.getIntPtrConstant(EltSize);
9169 SDValue Cond = DAG.getSetCC(DL,
9170 TLI.getSetCCResultType(N0.getValueType()),
9172 AddToWorkList(Cond.getNode());
9173 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
9175 AddToWorkList(CstOffset.getNode());
9176 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
9178 AddToWorkList(CPIdx.getNode());
9179 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
9180 MachinePointerInfo::getConstantPool(), false,
9181 false, false, Alignment);
9186 // Check to see if we can perform the "gzip trick", transforming
9187 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
9188 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
9189 (N1C->isNullValue() || // (a < 0) ? b : 0
9190 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
9191 EVT XType = N0.getValueType();
9192 EVT AType = N2.getValueType();
9193 if (XType.bitsGE(AType)) {
9194 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
9195 // single-bit constant.
9196 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
9197 unsigned ShCtV = N2C->getAPIntValue().logBase2();
9198 ShCtV = XType.getSizeInBits()-ShCtV-1;
9199 SDValue ShCt = DAG.getConstant(ShCtV,
9200 getShiftAmountTy(N0.getValueType()));
9201 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
9203 AddToWorkList(Shift.getNode());
9205 if (XType.bitsGT(AType)) {
9206 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
9207 AddToWorkList(Shift.getNode());
9210 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
9213 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
9215 DAG.getConstant(XType.getSizeInBits()-1,
9216 getShiftAmountTy(N0.getValueType())));
9217 AddToWorkList(Shift.getNode());
9219 if (XType.bitsGT(AType)) {
9220 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
9221 AddToWorkList(Shift.getNode());
9224 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
9228 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
9229 // where y is has a single bit set.
9230 // A plaintext description would be, we can turn the SELECT_CC into an AND
9231 // when the condition can be materialized as an all-ones register. Any
9232 // single bit-test can be materialized as an all-ones register with
9233 // shift-left and shift-right-arith.
9234 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
9235 N0->getValueType(0) == VT &&
9236 N1C && N1C->isNullValue() &&
9237 N2C && N2C->isNullValue()) {
9238 SDValue AndLHS = N0->getOperand(0);
9239 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
9240 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
9241 // Shift the tested bit over the sign bit.
9242 APInt AndMask = ConstAndRHS->getAPIntValue();
9244 DAG.getConstant(AndMask.countLeadingZeros(),
9245 getShiftAmountTy(AndLHS.getValueType()));
9246 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
9248 // Now arithmetic right shift it all the way over, so the result is either
9249 // all-ones, or zero.
9251 DAG.getConstant(AndMask.getBitWidth()-1,
9252 getShiftAmountTy(Shl.getValueType()));
9253 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
9255 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
9259 // fold select C, 16, 0 -> shl C, 4
9260 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
9261 TLI.getBooleanContents(N0.getValueType().isVector()) ==
9262 TargetLowering::ZeroOrOneBooleanContent) {
9264 // If the caller doesn't want us to simplify this into a zext of a compare,
9266 if (NotExtCompare && N2C->getAPIntValue() == 1)
9269 // Get a SetCC of the condition
9270 // FIXME: Should probably make sure that setcc is legal if we ever have a
9271 // target where it isn't.
9273 // cast from setcc result type to select result type
9275 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
9277 if (N2.getValueType().bitsLT(SCC.getValueType()))
9278 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
9280 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
9281 N2.getValueType(), SCC);
9283 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
9284 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
9285 N2.getValueType(), SCC);
9288 AddToWorkList(SCC.getNode());
9289 AddToWorkList(Temp.getNode());
9291 if (N2C->getAPIntValue() == 1)
9294 // shl setcc result by log2 n2c
9295 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
9296 DAG.getConstant(N2C->getAPIntValue().logBase2(),
9297 getShiftAmountTy(Temp.getValueType())));
9300 // Check to see if this is the equivalent of setcc
9301 // FIXME: Turn all of these into setcc if setcc if setcc is legal
9302 // otherwise, go ahead with the folds.
9303 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
9304 EVT XType = N0.getValueType();
9305 if (!LegalOperations ||
9306 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
9307 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
9308 if (Res.getValueType() != VT)
9309 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
9313 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
9314 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
9315 (!LegalOperations ||
9316 TLI.isOperationLegal(ISD::CTLZ, XType))) {
9317 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
9318 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
9319 DAG.getConstant(Log2_32(XType.getSizeInBits()),
9320 getShiftAmountTy(Ctlz.getValueType())));
9322 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
9323 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
9324 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
9325 XType, DAG.getConstant(0, XType), N0);
9326 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
9327 return DAG.getNode(ISD::SRL, DL, XType,
9328 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
9329 DAG.getConstant(XType.getSizeInBits()-1,
9330 getShiftAmountTy(XType)));
9332 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
9333 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
9334 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
9335 DAG.getConstant(XType.getSizeInBits()-1,
9336 getShiftAmountTy(N0.getValueType())));
9337 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
9341 // Check to see if this is an integer abs.
9342 // select_cc setg[te] X, 0, X, -X ->
9343 // select_cc setgt X, -1, X, -X ->
9344 // select_cc setl[te] X, 0, -X, X ->
9345 // select_cc setlt X, 1, -X, X ->
9346 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
9348 ConstantSDNode *SubC = NULL;
9349 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
9350 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
9351 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
9352 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
9353 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
9354 (N1C->isOne() && CC == ISD::SETLT)) &&
9355 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
9356 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
9358 EVT XType = N0.getValueType();
9359 if (SubC && SubC->isNullValue() && XType.isInteger()) {
9360 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
9362 DAG.getConstant(XType.getSizeInBits()-1,
9363 getShiftAmountTy(N0.getValueType())));
9364 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
9366 AddToWorkList(Shift.getNode());
9367 AddToWorkList(Add.getNode());
9368 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
9375 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
9376 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
9377 SDValue N1, ISD::CondCode Cond,
9378 DebugLoc DL, bool foldBooleans) {
9379 TargetLowering::DAGCombinerInfo
9380 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
9381 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
9384 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
9385 /// return a DAG expression to select that will generate the same value by
9386 /// multiplying by a magic number. See:
9387 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
9388 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
9389 std::vector<SDNode*> Built;
9390 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built);
9392 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
9398 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
9399 /// return a DAG expression to select that will generate the same value by
9400 /// multiplying by a magic number. See:
9401 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
9402 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
9403 std::vector<SDNode*> Built;
9404 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built);
9406 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
9412 /// FindBaseOffset - Return true if base is a frame index, which is known not
9413 // to alias with anything but itself. Provides base object and offset as
9415 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
9416 const GlobalValue *&GV, const void *&CV) {
9417 // Assume it is a primitive operation.
9418 Base = Ptr; Offset = 0; GV = 0; CV = 0;
9420 // If it's an adding a simple constant then integrate the offset.
9421 if (Base.getOpcode() == ISD::ADD) {
9422 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
9423 Base = Base.getOperand(0);
9424 Offset += C->getZExtValue();
9428 // Return the underlying GlobalValue, and update the Offset. Return false
9429 // for GlobalAddressSDNode since the same GlobalAddress may be represented
9430 // by multiple nodes with different offsets.
9431 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
9432 GV = G->getGlobal();
9433 Offset += G->getOffset();
9437 // Return the underlying Constant value, and update the Offset. Return false
9438 // for ConstantSDNodes since the same constant pool entry may be represented
9439 // by multiple nodes with different offsets.
9440 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
9441 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal()
9442 : (const void *)C->getConstVal();
9443 Offset += C->getOffset();
9446 // If it's any of the following then it can't alias with anything but itself.
9447 return isa<FrameIndexSDNode>(Base);
9450 /// isAlias - Return true if there is any possibility that the two addresses
9452 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
9453 const Value *SrcValue1, int SrcValueOffset1,
9454 unsigned SrcValueAlign1,
9455 const MDNode *TBAAInfo1,
9456 SDValue Ptr2, int64_t Size2,
9457 const Value *SrcValue2, int SrcValueOffset2,
9458 unsigned SrcValueAlign2,
9459 const MDNode *TBAAInfo2) const {
9460 // If they are the same then they must be aliases.
9461 if (Ptr1 == Ptr2) return true;
9463 // Gather base node and offset information.
9464 SDValue Base1, Base2;
9465 int64_t Offset1, Offset2;
9466 const GlobalValue *GV1, *GV2;
9467 const void *CV1, *CV2;
9468 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
9469 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
9471 // If they have a same base address then check to see if they overlap.
9472 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
9473 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
9475 // It is possible for different frame indices to alias each other, mostly
9476 // when tail call optimization reuses return address slots for arguments.
9477 // To catch this case, look up the actual index of frame indices to compute
9478 // the real alias relationship.
9479 if (isFrameIndex1 && isFrameIndex2) {
9480 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9481 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
9482 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
9483 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
9486 // Otherwise, if we know what the bases are, and they aren't identical, then
9487 // we know they cannot alias.
9488 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
9491 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
9492 // compared to the size and offset of the access, we may be able to prove they
9493 // do not alias. This check is conservative for now to catch cases created by
9494 // splitting vector types.
9495 if ((SrcValueAlign1 == SrcValueAlign2) &&
9496 (SrcValueOffset1 != SrcValueOffset2) &&
9497 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
9498 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
9499 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
9501 // There is no overlap between these relatively aligned accesses of similar
9502 // size, return no alias.
9503 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
9507 if (CombinerGlobalAA) {
9508 // Use alias analysis information.
9509 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
9510 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
9511 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
9512 AliasAnalysis::AliasResult AAResult =
9513 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
9514 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
9515 if (AAResult == AliasAnalysis::NoAlias)
9519 // Otherwise we have to assume they alias.
9523 /// FindAliasInfo - Extracts the relevant alias information from the memory
9524 /// node. Returns true if the operand was a load.
9525 bool DAGCombiner::FindAliasInfo(SDNode *N,
9526 SDValue &Ptr, int64_t &Size,
9527 const Value *&SrcValue,
9528 int &SrcValueOffset,
9529 unsigned &SrcValueAlign,
9530 const MDNode *&TBAAInfo) const {
9531 LSBaseSDNode *LS = cast<LSBaseSDNode>(N);
9533 Ptr = LS->getBasePtr();
9534 Size = LS->getMemoryVT().getSizeInBits() >> 3;
9535 SrcValue = LS->getSrcValue();
9536 SrcValueOffset = LS->getSrcValueOffset();
9537 SrcValueAlign = LS->getOriginalAlignment();
9538 TBAAInfo = LS->getTBAAInfo();
9539 return isa<LoadSDNode>(LS);
9542 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
9543 /// looking for aliasing nodes and adding them to the Aliases vector.
9544 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
9545 SmallVector<SDValue, 8> &Aliases) {
9546 SmallVector<SDValue, 8> Chains; // List of chains to visit.
9547 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
9549 // Get alias information for node.
9552 const Value *SrcValue;
9554 unsigned SrcValueAlign;
9555 const MDNode *SrcTBAAInfo;
9556 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
9557 SrcValueAlign, SrcTBAAInfo);
9560 Chains.push_back(OriginalChain);
9563 // Look at each chain and determine if it is an alias. If so, add it to the
9564 // aliases list. If not, then continue up the chain looking for the next
9566 while (!Chains.empty()) {
9567 SDValue Chain = Chains.back();
9570 // For TokenFactor nodes, look at each operand and only continue up the
9571 // chain until we find two aliases. If we've seen two aliases, assume we'll
9572 // find more and revert to original chain since the xform is unlikely to be
9575 // FIXME: The depth check could be made to return the last non-aliasing
9576 // chain we found before we hit a tokenfactor rather than the original
9578 if (Depth > 6 || Aliases.size() == 2) {
9580 Aliases.push_back(OriginalChain);
9584 // Don't bother if we've been before.
9585 if (!Visited.insert(Chain.getNode()))
9588 switch (Chain.getOpcode()) {
9589 case ISD::EntryToken:
9590 // Entry token is ideal chain operand, but handled in FindBetterChain.
9595 // Get alias information for Chain.
9598 const Value *OpSrcValue;
9599 int OpSrcValueOffset;
9600 unsigned OpSrcValueAlign;
9601 const MDNode *OpSrcTBAAInfo;
9602 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
9603 OpSrcValue, OpSrcValueOffset,
9607 // If chain is alias then stop here.
9608 if (!(IsLoad && IsOpLoad) &&
9609 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
9611 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
9612 OpSrcValueAlign, OpSrcTBAAInfo)) {
9613 Aliases.push_back(Chain);
9615 // Look further up the chain.
9616 Chains.push_back(Chain.getOperand(0));
9622 case ISD::TokenFactor:
9623 // We have to check each of the operands of the token factor for "small"
9624 // token factors, so we queue them up. Adding the operands to the queue
9625 // (stack) in reverse order maintains the original order and increases the
9626 // likelihood that getNode will find a matching token factor (CSE.)
9627 if (Chain.getNumOperands() > 16) {
9628 Aliases.push_back(Chain);
9631 for (unsigned n = Chain.getNumOperands(); n;)
9632 Chains.push_back(Chain.getOperand(--n));
9637 // For all other instructions we will just have to take what we can get.
9638 Aliases.push_back(Chain);
9644 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
9645 /// for a better chain (aliasing node.)
9646 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
9647 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
9649 // Accumulate all the aliases to this node.
9650 GatherAllAliases(N, OldChain, Aliases);
9652 // If no operands then chain to entry token.
9653 if (Aliases.size() == 0)
9654 return DAG.getEntryNode();
9656 // If a single operand then chain to it. We don't need to revisit it.
9657 if (Aliases.size() == 1)
9660 // Construct a custom tailored token factor.
9661 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
9662 &Aliases[0], Aliases.size());
9665 // SelectionDAG::Combine - This is the entry point for the file.
9667 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
9668 CodeGenOpt::Level OptLevel) {
9669 /// run - This is the main entry point to this class.
9671 DAGCombiner(*this, AA, OptLevel).Run(Level);