1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAGInstrs class, which implements re-scheduling
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "sched-instrs"
16 #include "ScheduleDAGInstrs.h"
17 #include "llvm/Operator.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Analysis/ValueTracking.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/MC/MCInstrItineraries.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetSubtargetInfo.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/ADT/SmallSet.h"
34 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
35 const MachineLoopInfo &mli,
36 const MachineDominatorTree &mdt,
38 : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
39 InstrItins(mf.getTarget().getInstrItineraryData()), IsPostRA(IsPostRAFlag),
40 UnitLatencies(false), Defs(TRI->getNumRegs()), Uses(TRI->getNumRegs()),
41 LoopRegs(MLI, MDT), FirstDbgValue(0) {
45 /// Run - perform scheduling.
47 void ScheduleDAGInstrs::Run(MachineBasicBlock *bb,
48 MachineBasicBlock::iterator begin,
49 MachineBasicBlock::iterator end,
53 InsertPosIndex = endcount;
55 // Check to see if the scheduler cares about latencies.
56 UnitLatencies = ForceUnitLatencies();
58 ScheduleDAG::Run(bb, end);
61 /// getUnderlyingObjectFromInt - This is the function that does the work of
62 /// looking through basic ptrtoint+arithmetic+inttoptr sequences.
63 static const Value *getUnderlyingObjectFromInt(const Value *V) {
65 if (const Operator *U = dyn_cast<Operator>(V)) {
66 // If we find a ptrtoint, we can transfer control back to the
67 // regular getUnderlyingObjectFromInt.
68 if (U->getOpcode() == Instruction::PtrToInt)
69 return U->getOperand(0);
70 // If we find an add of a constant or a multiplied value, it's
71 // likely that the other operand will lead us to the base
72 // object. We don't have to worry about the case where the
73 // object address is somehow being computed by the multiply,
74 // because our callers only care when the result is an
75 // identifibale object.
76 if (U->getOpcode() != Instruction::Add ||
77 (!isa<ConstantInt>(U->getOperand(1)) &&
78 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul))
84 assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
88 /// getUnderlyingObject - This is a wrapper around GetUnderlyingObject
89 /// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
90 static const Value *getUnderlyingObject(const Value *V) {
91 // First just call Value::getUnderlyingObject to let it do what it does.
93 V = GetUnderlyingObject(V);
94 // If it found an inttoptr, use special code to continue climing.
95 if (Operator::getOpcode(V) != Instruction::IntToPtr)
97 const Value *O = getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
98 // If that succeeded in finding a pointer, continue the search.
99 if (!O->getType()->isPointerTy())
106 /// getUnderlyingObjectForInstr - If this machine instr has memory reference
107 /// information and it can be tracked to a normal reference to a known
108 /// object, return the Value for that object. Otherwise return null.
109 static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI,
110 const MachineFrameInfo *MFI,
113 if (!MI->hasOneMemOperand() ||
114 !(*MI->memoperands_begin())->getValue() ||
115 (*MI->memoperands_begin())->isVolatile())
118 const Value *V = (*MI->memoperands_begin())->getValue();
122 V = getUnderlyingObject(V);
123 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
124 // For now, ignore PseudoSourceValues which may alias LLVM IR values
125 // because the code that uses this function has no way to cope with
127 if (PSV->isAliased(MFI))
130 MayAlias = PSV->mayAlias(MFI);
134 if (isIdentifiedObject(V))
140 void ScheduleDAGInstrs::StartBlock(MachineBasicBlock *BB) {
141 LoopRegs.Deps.clear();
142 if (MachineLoop *ML = MLI.getLoopFor(BB))
143 if (BB == ML->getLoopLatch())
144 LoopRegs.VisitLoop(ML);
147 /// AddSchedBarrierDeps - Add dependencies from instructions in the current
148 /// list of instructions being scheduled to scheduling barrier by adding
149 /// the exit SU to the register defs and use list. This is because we want to
150 /// make sure instructions which define registers that are either used by
151 /// the terminator or are live-out are properly scheduled. This is
152 /// especially important when the definition latency of the return value(s)
153 /// are too high to be hidden by the branch or when the liveout registers
154 /// used by instructions in the fallthrough block.
155 void ScheduleDAGInstrs::AddSchedBarrierDeps() {
156 MachineInstr *ExitMI = InsertPos != BB->end() ? &*InsertPos : 0;
157 ExitSU.setInstr(ExitMI);
158 bool AllDepKnown = ExitMI &&
159 (ExitMI->isCall() || ExitMI->isBarrier());
160 if (ExitMI && AllDepKnown) {
161 // If it's a call or a barrier, add dependencies on the defs and uses of
163 for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) {
164 const MachineOperand &MO = ExitMI->getOperand(i);
165 if (!MO.isReg() || MO.isDef()) continue;
166 unsigned Reg = MO.getReg();
167 if (Reg == 0) continue;
169 assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
170 Uses[Reg].push_back(&ExitSU);
173 // For others, e.g. fallthrough, conditional branch, assume the exit
174 // uses all the registers that are livein to the successor blocks.
175 SmallSet<unsigned, 8> Seen;
176 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
177 SE = BB->succ_end(); SI != SE; ++SI)
178 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
179 E = (*SI)->livein_end(); I != E; ++I) {
181 if (Seen.insert(Reg))
182 Uses[Reg].push_back(&ExitSU);
187 /// addPhysRegDeps - Add register dependencies (data, anti, and output) from
188 /// this SUnit to following instructions in the same scheduling region that
189 /// depend the physical register referenced at OperIdx.
190 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
191 const MachineInstr *MI = SU->getInstr();
192 const MachineOperand &MO = MI->getOperand(OperIdx);
193 unsigned Reg = MO.getReg();
195 // Ask the target if address-backscheduling is desirable, and if so how much.
196 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
197 unsigned SpecialAddressLatency = ST.getSpecialAddressLatency();
199 // Optionally add output and anti dependencies. For anti
200 // dependencies we use a latency of 0 because for a multi-issue
201 // target we want to allow the defining instruction to issue
202 // in the same cycle as the using instruction.
203 // TODO: Using a latency of 1 here for output dependencies assumes
204 // there's no cost for reusing registers.
205 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
206 for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias) {
207 std::vector<SUnit *> &DefList = Defs[*Alias];
208 for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
209 SUnit *DefSU = DefList[i];
210 if (DefSU == &ExitSU)
213 (Kind != SDep::Output || !MO.isDead() ||
214 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
215 if (Kind == SDep::Anti)
216 DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/*Alias));
218 unsigned AOLat = TII->getOutputLatency(InstrItins, MI, OperIdx,
220 DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/*Alias));
226 // Retrieve the UseList to add data dependencies and update uses.
227 std::vector<SUnit *> &UseList = Uses[Reg];
229 // Update DefList. Defs are pushed in the order they are visited and
231 std::vector<SUnit *> &DefList = Defs[Reg];
233 // Add any data dependencies.
234 unsigned DataLatency = SU->Latency;
235 for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
236 SUnit *UseSU = UseList[i];
239 unsigned LDataLatency = DataLatency;
240 // Optionally add in a special extra latency for nodes that
242 // TODO: Do this for register aliases too.
243 // TODO: Perhaps we should get rid of
244 // SpecialAddressLatency and just move this into
245 // adjustSchedDependency for the targets that care about it.
246 if (SpecialAddressLatency != 0 && !UnitLatencies &&
248 MachineInstr *UseMI = UseSU->getInstr();
249 const MCInstrDesc &UseMCID = UseMI->getDesc();
250 int RegUseIndex = UseMI->findRegisterUseOperandIdx(Reg);
251 assert(RegUseIndex >= 0 && "UseMI doesn's use register!");
252 if (RegUseIndex >= 0 &&
253 (UseMI->mayLoad() || UseMI->mayStore()) &&
254 (unsigned)RegUseIndex < UseMCID.getNumOperands() &&
255 UseMCID.OpInfo[RegUseIndex].isLookupPtrRegClass())
256 LDataLatency += SpecialAddressLatency;
258 // Adjust the dependence latency using operand def/use
259 // information (if any), and then allow the target to
260 // perform its own adjustments.
261 const SDep& dep = SDep(SU, SDep::Data, LDataLatency, Reg);
262 if (!UnitLatencies) {
263 ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
264 ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
268 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
269 std::vector<SUnit *> &UseList = Uses[*Alias];
270 for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
271 SUnit *UseSU = UseList[i];
274 const SDep& dep = SDep(SU, SDep::Data, DataLatency, *Alias);
275 if (!UnitLatencies) {
276 ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep));
277 ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep));
283 // If a def is going to wrap back around to the top of the loop,
285 if (!UnitLatencies && DefList.empty()) {
286 LoopDependencies::LoopDeps::iterator I = LoopRegs.Deps.find(Reg);
287 if (I != LoopRegs.Deps.end()) {
288 const MachineOperand *UseMO = I->second.first;
289 unsigned Count = I->second.second;
290 const MachineInstr *UseMI = UseMO->getParent();
291 unsigned UseMOIdx = UseMO - &UseMI->getOperand(0);
292 const MCInstrDesc &UseMCID = UseMI->getDesc();
293 // TODO: If we knew the total depth of the region here, we could
294 // handle the case where the whole loop is inside the region but
295 // is large enough that the isScheduleHigh trick isn't needed.
296 if (UseMOIdx < UseMCID.getNumOperands()) {
297 // Currently, we only support scheduling regions consisting of
298 // single basic blocks. Check to see if the instruction is in
299 // the same region by checking to see if it has the same parent.
300 if (UseMI->getParent() != MI->getParent()) {
301 unsigned Latency = SU->Latency;
302 if (UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass())
303 Latency += SpecialAddressLatency;
304 // This is a wild guess as to the portion of the latency which
305 // will be overlapped by work done outside the current
306 // scheduling region.
307 Latency -= std::min(Latency, Count);
308 // Add the artificial edge.
309 ExitSU.addPred(SDep(SU, SDep::Order, Latency,
310 /*Reg=*/0, /*isNormalMemory=*/false,
311 /*isMustAlias=*/false,
312 /*isArtificial=*/true));
313 } else if (SpecialAddressLatency > 0 &&
314 UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass()) {
315 // The entire loop body is within the current scheduling region
316 // and the latency of this operation is assumed to be greater
317 // than the latency of the loop.
318 // TODO: Recursively mark data-edge predecessors as
319 // isScheduleHigh too.
320 SU->isScheduleHigh = true;
323 LoopRegs.Deps.erase(I);
331 // Calls will not be reordered because of chain dependencies (see
332 // below). Since call operands are dead, calls may continue to be added
333 // to the DefList making dependence checking quadratic in the size of
334 // the block. Instead, we leave only one call at the back of the
337 while (!DefList.empty() && DefList.back()->isCall)
340 DefList.push_back(SU);
342 UseList.push_back(SU);
346 /// addVirtRegDeps - Add register dependencies (data, anti, and output) from
347 /// this SUnit to following instructions in the same scheduling region that
348 /// depend the virtual register referenced at OperIdx.
349 void ScheduleDAGInstrs::addVirtRegDeps(SUnit *SU, unsigned OperIdx) {
350 assert(false && "unimplemented");
353 void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
354 // We'll be allocating one SUnit for each instruction, plus one for
355 // the region exit node.
356 SUnits.reserve(BB->size());
358 // We build scheduling units by walking a block's instruction list from bottom
361 // Remember where a generic side-effecting instruction is as we procede.
362 SUnit *BarrierChain = 0, *AliasChain = 0;
364 // Memory references to specific known memory locations are tracked
365 // so that they can be given more precise dependencies. We track
366 // separately the known memory locations that may alias and those
367 // that are known not to alias
368 std::map<const Value *, SUnit *> AliasMemDefs, NonAliasMemDefs;
369 std::map<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
371 // Remove any stale debug info; sometimes BuildSchedGraph is called again
372 // without emitting the info from the previous call.
374 FirstDbgValue = NULL;
376 // Model data dependencies between instructions being scheduled and the
378 AddSchedBarrierDeps();
380 for (int i = 0, e = TRI->getNumRegs(); i != e; ++i) {
381 assert(Defs[i].empty() && "Only BuildGraph should push/pop Defs");
384 // Walk the list of instructions, from bottom moving up.
385 MachineInstr *PrevMI = NULL;
386 for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin;
388 MachineInstr *MI = prior(MII);
390 DbgValues.push_back(std::make_pair(PrevMI, MI));
394 if (MI->isDebugValue()) {
399 assert(!MI->isTerminator() && !MI->isLabel() &&
400 "Cannot schedule terminators or labels!");
401 // Create the SUnit for this MI.
402 SUnit *SU = NewSUnit(MI);
403 SU->isCall = MI->isCall();
404 SU->isCommutable = MI->isCommutable();
406 // Assign the Latency field of SU using target-provided information.
412 // Add register-based dependencies (data, anti, and output).
413 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
414 const MachineOperand &MO = MI->getOperand(j);
415 if (!MO.isReg()) continue;
416 unsigned Reg = MO.getReg();
417 if (Reg == 0) continue;
419 if (TRI->isPhysicalRegister(Reg))
420 addPhysRegDeps(SU, j);
422 assert(!IsPostRA && "Virtual register encountered!");
423 addVirtRegDeps(SU, j);
427 // Add chain dependencies.
428 // Chain dependencies used to enforce memory order should have
429 // latency of 0 (except for true dependency of Store followed by
430 // aliased Load... we estimate that with a single cycle of latency
431 // assuming the hardware will bypass)
432 // Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
433 // after stack slots are lowered to actual addresses.
434 // TODO: Use an AliasAnalysis and do real alias-analysis queries, and
435 // produce more precise dependence information.
436 #define STORE_LOAD_LATENCY 1
437 unsigned TrueMemOrderLatency = 0;
438 if (MI->isCall() || MI->hasUnmodeledSideEffects() ||
439 (MI->hasVolatileMemoryRef() &&
440 (!MI->mayLoad() || !MI->isInvariantLoad(AA)))) {
441 // Be conservative with these and add dependencies on all memory
442 // references, even those that are known to not alias.
443 for (std::map<const Value *, SUnit *>::iterator I =
444 NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
445 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
447 for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
448 NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) {
449 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
450 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
452 NonAliasMemDefs.clear();
453 NonAliasMemUses.clear();
454 // Add SU to the barrier chain.
456 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
461 // Chain all possibly aliasing memory references though SU.
463 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
465 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
466 PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
467 for (std::map<const Value *, SUnit *>::iterator I = AliasMemDefs.begin(),
468 E = AliasMemDefs.end(); I != E; ++I) {
469 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
471 for (std::map<const Value *, std::vector<SUnit *> >::iterator I =
472 AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
473 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
474 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
476 PendingLoads.clear();
477 AliasMemDefs.clear();
478 AliasMemUses.clear();
479 } else if (MI->mayStore()) {
480 bool MayAlias = true;
481 TrueMemOrderLatency = STORE_LOAD_LATENCY;
482 if (const Value *V = getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
483 // A store to a specific PseudoSourceValue. Add precise dependencies.
484 // Record the def in MemDefs, first adding a dep if there is
486 std::map<const Value *, SUnit *>::iterator I =
487 ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
488 std::map<const Value *, SUnit *>::iterator IE =
489 ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
491 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
492 /*isNormalMemory=*/true));
496 AliasMemDefs[V] = SU;
498 NonAliasMemDefs[V] = SU;
500 // Handle the uses in MemUses, if there are any.
501 std::map<const Value *, std::vector<SUnit *> >::iterator J =
502 ((MayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V));
503 std::map<const Value *, std::vector<SUnit *> >::iterator JE =
504 ((MayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
506 for (unsigned i = 0, e = J->second.size(); i != e; ++i)
507 J->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency,
508 /*Reg=*/0, /*isNormalMemory=*/true));
512 // Add dependencies from all the PendingLoads, i.e. loads
513 // with no underlying object.
514 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
515 PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
516 // Add dependence on alias chain, if needed.
518 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
520 // Add dependence on barrier chain, if needed.
522 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
524 // Treat all other stores conservatively.
525 goto new_alias_chain;
528 if (!ExitSU.isPred(SU))
529 // Push store's up a bit to avoid them getting in between cmp
531 ExitSU.addPred(SDep(SU, SDep::Order, 0,
532 /*Reg=*/0, /*isNormalMemory=*/false,
533 /*isMustAlias=*/false,
534 /*isArtificial=*/true));
535 } else if (MI->mayLoad()) {
536 bool MayAlias = true;
537 TrueMemOrderLatency = 0;
538 if (MI->isInvariantLoad(AA)) {
539 // Invariant load, no chain dependencies needed!
542 getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
543 // A load from a specific PseudoSourceValue. Add precise dependencies.
544 std::map<const Value *, SUnit *>::iterator I =
545 ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
546 std::map<const Value *, SUnit *>::iterator IE =
547 ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
549 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0, /*Reg=*/0,
550 /*isNormalMemory=*/true));
552 AliasMemUses[V].push_back(SU);
554 NonAliasMemUses[V].push_back(SU);
556 // A load with no underlying object. Depend on all
557 // potentially aliasing stores.
558 for (std::map<const Value *, SUnit *>::iterator I =
559 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
560 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
562 PendingLoads.push_back(SU);
566 // Add dependencies on alias and barrier chains, if needed.
567 if (MayAlias && AliasChain)
568 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
570 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
575 FirstDbgValue = PrevMI;
577 for (int i = 0, e = TRI->getNumRegs(); i != e; ++i) {
581 PendingLoads.clear();
584 void ScheduleDAGInstrs::FinishBlock() {
588 void ScheduleDAGInstrs::ComputeLatency(SUnit *SU) {
589 // Compute the latency for the node.
590 if (!InstrItins || InstrItins->isEmpty()) {
593 // Simplistic target-independent heuristic: assume that loads take
595 if (SU->getInstr()->mayLoad())
598 SU->Latency = TII->getInstrLatency(InstrItins, SU->getInstr());
602 void ScheduleDAGInstrs::ComputeOperandLatency(SUnit *Def, SUnit *Use,
604 if (!InstrItins || InstrItins->isEmpty())
607 // For a data dependency with a known register...
608 if ((dep.getKind() != SDep::Data) || (dep.getReg() == 0))
611 const unsigned Reg = dep.getReg();
613 // ... find the definition of the register in the defining
615 MachineInstr *DefMI = Def->getInstr();
616 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
618 const MachineOperand &MO = DefMI->getOperand(DefIdx);
619 if (MO.isReg() && MO.isImplicit() &&
620 DefIdx >= (int)DefMI->getDesc().getNumOperands()) {
621 // This is an implicit def, getOperandLatency() won't return the correct
623 // %D6<def>, %D7<def> = VLD1q16 %R2<kill>, 0, ..., %Q3<imp-def>
624 // %Q1<def> = VMULv8i16 %Q1<kill>, %Q3<kill>, ...
625 // What we want is to compute latency between def of %D6/%D7 and use of
627 DefIdx = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI);
629 MachineInstr *UseMI = Use->getInstr();
630 // For all uses of the register, calculate the maxmimum latency
633 for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
634 const MachineOperand &MO = UseMI->getOperand(i);
635 if (!MO.isReg() || !MO.isUse())
637 unsigned MOReg = MO.getReg();
641 int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx,
643 Latency = std::max(Latency, UseCycle);
646 // UseMI is null, then it must be a scheduling barrier.
647 if (!InstrItins || InstrItins->isEmpty())
649 unsigned DefClass = DefMI->getDesc().getSchedClass();
650 Latency = InstrItins->getOperandCycle(DefClass, DefIdx);
653 // If we found a latency, then replace the existing dependence latency.
655 dep.setLatency(Latency);
659 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
660 SU->getInstr()->dump();
663 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
665 raw_string_ostream oss(s);
668 else if (SU == &ExitSU)
671 SU->getInstr()->print(oss);
675 // EmitSchedule - Emit the machine code in scheduled order.
676 MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() {
679 // If first instruction was a DBG_VALUE then put it back.
681 BB->splice(InsertPos, BB, FirstDbgValue);
683 // Then re-insert them according to the given schedule.
684 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
685 if (SUnit *SU = Sequence[i])
686 BB->splice(InsertPos, BB, SU->getInstr());
688 // Null SUnit* is a noop.
691 // Update the Begin iterator, as the first instruction in the block
692 // may have been scheduled later.
694 Begin = prior(InsertPos);
697 // Reinsert any remaining debug_values.
698 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
699 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
700 std::pair<MachineInstr *, MachineInstr *> P = *prior(DI);
701 MachineInstr *DbgValue = P.first;
702 MachineBasicBlock::iterator OrigPrivMI = P.second;
703 BB->splice(++OrigPrivMI, BB, DbgValue);
706 FirstDbgValue = NULL;