1 //===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAGInstrs class, which implements re-scheduling
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "misched"
16 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
17 #include "llvm/ADT/MapVector.h"
18 #include "llvm/ADT/SmallPtrSet.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ValueTracking.h"
22 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineMemOperand.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/CodeGen/RegisterPressure.h"
29 #include "llvm/CodeGen/ScheduleDFS.h"
30 #include "llvm/IR/Operator.h"
31 #include "llvm/MC/MCInstrItineraries.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/Format.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
44 static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
45 cl::ZeroOrMore, cl::init(false),
46 cl::desc("Enable use of AA during MI GAD construction"));
48 // FIXME: Enable the use of TBAA. There are two known issues preventing this:
49 // 1. Stack coloring does not update TBAA when merging allocas
50 // 2. CGP inserts ptrtoint/inttoptr pairs when sinking address computations.
51 // Because BasicAA does not handle inttoptr, we'll often miss basic type
52 // punning idioms that we need to catch so we don't miscompile real-world
54 static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden,
55 cl::init(false), cl::desc("Enable use of TBAA during MI GAD construction"));
57 ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
58 const MachineLoopInfo &mli,
59 const MachineDominatorTree &mdt,
63 : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), LIS(lis),
64 IsPostRA(IsPostRAFlag), RemoveKillFlags(RemoveKillFlags),
65 CanHandleTerminators(false), FirstDbgValue(0) {
66 assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
68 assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
69 "Virtual registers must be removed prior to PostRA scheduling");
71 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
72 SchedModel.init(*ST.getSchedModel(), &ST, TII);
75 /// getUnderlyingObjectFromInt - This is the function that does the work of
76 /// looking through basic ptrtoint+arithmetic+inttoptr sequences.
77 static const Value *getUnderlyingObjectFromInt(const Value *V) {
79 if (const Operator *U = dyn_cast<Operator>(V)) {
80 // If we find a ptrtoint, we can transfer control back to the
81 // regular getUnderlyingObjectFromInt.
82 if (U->getOpcode() == Instruction::PtrToInt)
83 return U->getOperand(0);
84 // If we find an add of a constant, a multiplied value, or a phi, it's
85 // likely that the other operand will lead us to the base
86 // object. We don't have to worry about the case where the
87 // object address is somehow being computed by the multiply,
88 // because our callers only care when the result is an
89 // identifiable object.
90 if (U->getOpcode() != Instruction::Add ||
91 (!isa<ConstantInt>(U->getOperand(1)) &&
92 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul &&
93 !isa<PHINode>(U->getOperand(1))))
99 assert(V->getType()->isIntegerTy() && "Unexpected operand type!");
103 /// getUnderlyingObjects - This is a wrapper around GetUnderlyingObjects
104 /// and adds support for basic ptrtoint+arithmetic+inttoptr sequences.
105 static void getUnderlyingObjects(const Value *V,
106 SmallVectorImpl<Value *> &Objects) {
107 SmallPtrSet<const Value*, 16> Visited;
108 SmallVector<const Value *, 4> Working(1, V);
110 V = Working.pop_back_val();
112 SmallVector<Value *, 4> Objs;
113 GetUnderlyingObjects(const_cast<Value *>(V), Objs);
115 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), IE = Objs.end();
118 if (!Visited.insert(V))
120 if (Operator::getOpcode(V) == Instruction::IntToPtr) {
122 getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0));
123 if (O->getType()->isPointerTy()) {
124 Working.push_back(O);
128 Objects.push_back(const_cast<Value *>(V));
130 } while (!Working.empty());
133 typedef SmallVector<PointerIntPair<const Value *, 1, bool>, 4>
134 UnderlyingObjectsVector;
136 /// getUnderlyingObjectsForInstr - If this machine instr has memory reference
137 /// information and it can be tracked to a normal reference to a known
138 /// object, return the Value for that object.
139 static void getUnderlyingObjectsForInstr(const MachineInstr *MI,
140 const MachineFrameInfo *MFI,
141 UnderlyingObjectsVector &Objects) {
142 if (!MI->hasOneMemOperand() ||
143 !(*MI->memoperands_begin())->getValue() ||
144 (*MI->memoperands_begin())->isVolatile())
147 const Value *V = (*MI->memoperands_begin())->getValue();
151 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
152 // For now, ignore PseudoSourceValues which may alias LLVM IR values
153 // because the code that uses this function has no way to cope with
155 if (!PSV->isAliased(MFI))
156 Objects.push_back(UnderlyingObjectsVector::value_type(V, false));
160 SmallVector<Value *, 4> Objs;
161 getUnderlyingObjects(V, Objs);
163 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), IE = Objs.end();
167 assert(!isa<PseudoSourceValue>(V) && "Underlying value is a stack slot!");
169 if (!isIdentifiedObject(V)) {
174 Objects.push_back(UnderlyingObjectsVector::value_type(V, true));
178 void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) {
182 void ScheduleDAGInstrs::finishBlock() {
183 // Subclasses should no longer refer to the old block.
187 /// Initialize the DAG and common scheduler state for the current scheduling
188 /// region. This does not actually create the DAG, only clears it. The
189 /// scheduling driver may call BuildSchedGraph multiple times per scheduling
191 void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
192 MachineBasicBlock::iterator begin,
193 MachineBasicBlock::iterator end,
194 unsigned regioninstrs) {
195 assert(bb == BB && "startBlock should set BB");
198 NumRegionInstrs = regioninstrs;
201 /// Close the current scheduling region. Don't clear any state in case the
202 /// driver wants to refer to the previous scheduling region.
203 void ScheduleDAGInstrs::exitRegion() {
207 /// addSchedBarrierDeps - Add dependencies from instructions in the current
208 /// list of instructions being scheduled to scheduling barrier by adding
209 /// the exit SU to the register defs and use list. This is because we want to
210 /// make sure instructions which define registers that are either used by
211 /// the terminator or are live-out are properly scheduled. This is
212 /// especially important when the definition latency of the return value(s)
213 /// are too high to be hidden by the branch or when the liveout registers
214 /// used by instructions in the fallthrough block.
215 void ScheduleDAGInstrs::addSchedBarrierDeps() {
216 MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : 0;
217 ExitSU.setInstr(ExitMI);
218 bool AllDepKnown = ExitMI &&
219 (ExitMI->isCall() || ExitMI->isBarrier());
220 if (ExitMI && AllDepKnown) {
221 // If it's a call or a barrier, add dependencies on the defs and uses of
223 for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) {
224 const MachineOperand &MO = ExitMI->getOperand(i);
225 if (!MO.isReg() || MO.isDef()) continue;
226 unsigned Reg = MO.getReg();
227 if (Reg == 0) continue;
229 if (TRI->isPhysicalRegister(Reg))
230 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
232 assert(!IsPostRA && "Virtual register encountered after regalloc.");
233 if (MO.readsReg()) // ignore undef operands
234 addVRegUseDeps(&ExitSU, i);
238 // For others, e.g. fallthrough, conditional branch, assume the exit
239 // uses all the registers that are livein to the successor blocks.
240 assert(Uses.empty() && "Uses in set before adding deps?");
241 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
242 SE = BB->succ_end(); SI != SE; ++SI)
243 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
244 E = (*SI)->livein_end(); I != E; ++I) {
246 if (!Uses.contains(Reg))
247 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
252 /// MO is an operand of SU's instruction that defines a physical register. Add
253 /// data dependencies from SU to any uses of the physical register.
254 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
255 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
256 assert(MO.isDef() && "expect physreg def");
258 // Ask the target if address-backscheduling is desirable, and if so how much.
259 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
261 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
262 Alias.isValid(); ++Alias) {
263 if (!Uses.contains(*Alias))
265 for (Reg2SUnitsMap::iterator I = Uses.find(*Alias); I != Uses.end(); ++I) {
266 SUnit *UseSU = I->SU;
270 // Adjust the dependence latency using operand def/use information,
271 // then allow the target to perform its own adjustments.
272 int UseOp = I->OpIdx;
273 MachineInstr *RegUse = 0;
276 Dep = SDep(SU, SDep::Artificial);
278 // Set the hasPhysRegDefs only for physreg defs that have a use within
279 // the scheduling region.
280 SU->hasPhysRegDefs = true;
281 Dep = SDep(SU, SDep::Data, *Alias);
282 RegUse = UseSU->getInstr();
285 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse,
288 ST.adjustSchedDependency(SU, UseSU, Dep);
294 /// addPhysRegDeps - Add register dependencies (data, anti, and output) from
295 /// this SUnit to following instructions in the same scheduling region that
296 /// depend the physical register referenced at OperIdx.
297 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
298 MachineInstr *MI = SU->getInstr();
299 MachineOperand &MO = MI->getOperand(OperIdx);
301 // Optionally add output and anti dependencies. For anti
302 // dependencies we use a latency of 0 because for a multi-issue
303 // target we want to allow the defining instruction to issue
304 // in the same cycle as the using instruction.
305 // TODO: Using a latency of 1 here for output dependencies assumes
306 // there's no cost for reusing registers.
307 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
308 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
309 Alias.isValid(); ++Alias) {
310 if (!Defs.contains(*Alias))
312 for (Reg2SUnitsMap::iterator I = Defs.find(*Alias); I != Defs.end(); ++I) {
313 SUnit *DefSU = I->SU;
314 if (DefSU == &ExitSU)
317 (Kind != SDep::Output || !MO.isDead() ||
318 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
319 if (Kind == SDep::Anti)
320 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias));
322 SDep Dep(SU, Kind, /*Reg=*/*Alias);
324 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
332 SU->hasPhysRegUses = true;
333 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
334 // retrieve the existing SUnits list for this register's uses.
335 // Push this SUnit on the use list.
336 Uses.insert(PhysRegSUOper(SU, OperIdx, MO.getReg()));
341 addPhysRegDataDeps(SU, OperIdx);
342 unsigned Reg = MO.getReg();
344 // clear this register's use list
345 if (Uses.contains(Reg))
350 } else if (SU->isCall) {
351 // Calls will not be reordered because of chain dependencies (see
352 // below). Since call operands are dead, calls may continue to be added
353 // to the DefList making dependence checking quadratic in the size of
354 // the block. Instead, we leave only one call at the back of the
356 Reg2SUnitsMap::RangePair P = Defs.equal_range(Reg);
357 Reg2SUnitsMap::iterator B = P.first;
358 Reg2SUnitsMap::iterator I = P.second;
359 for (bool isBegin = I == B; !isBegin; /* empty */) {
360 isBegin = (--I) == B;
367 // Defs are pushed in the order they are visited and never reordered.
368 Defs.insert(PhysRegSUOper(SU, OperIdx, Reg));
372 /// addVRegDefDeps - Add register output and data dependencies from this SUnit
373 /// to instructions that occur later in the same scheduling region if they read
374 /// from or write to the virtual register defined at OperIdx.
376 /// TODO: Hoist loop induction variable increments. This has to be
377 /// reevaluated. Generally, IV scheduling should be done before coalescing.
378 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
379 const MachineInstr *MI = SU->getInstr();
380 unsigned Reg = MI->getOperand(OperIdx).getReg();
382 // Singly defined vregs do not have output/anti dependencies.
383 // The current operand is a def, so we have at least one.
384 // Check here if there are any others...
385 if (MRI.hasOneDef(Reg))
388 // Add output dependence to the next nearest def of this vreg.
390 // Unless this definition is dead, the output dependence should be
391 // transitively redundant with antidependencies from this definition's
392 // uses. We're conservative for now until we have a way to guarantee the uses
393 // are not eliminated sometime during scheduling. The output dependence edge
394 // is also useful if output latency exceeds def-use latency.
395 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
396 if (DefI == VRegDefs.end())
397 VRegDefs.insert(VReg2SUnit(Reg, SU));
399 SUnit *DefSU = DefI->SU;
400 if (DefSU != SU && DefSU != &ExitSU) {
401 SDep Dep(SU, SDep::Output, Reg);
403 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
410 /// addVRegUseDeps - Add a register data dependency if the instruction that
411 /// defines the virtual register used at OperIdx is mapped to an SUnit. Add a
412 /// register antidependency from this SUnit to instructions that occur later in
413 /// the same scheduling region if they write the virtual register.
415 /// TODO: Handle ExitSU "uses" properly.
416 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
417 MachineInstr *MI = SU->getInstr();
418 unsigned Reg = MI->getOperand(OperIdx).getReg();
420 // Record this local VReg use.
421 VReg2UseMap::iterator UI = VRegUses.find(Reg);
422 for (; UI != VRegUses.end(); ++UI) {
426 if (UI == VRegUses.end())
427 VRegUses.insert(VReg2SUnit(Reg, SU));
429 // Lookup this operand's reaching definition.
430 assert(LIS && "vreg dependencies requires LiveIntervals");
432 = LIS->getInterval(Reg).Query(LIS->getInstructionIndex(MI));
433 VNInfo *VNI = LRQ.valueIn();
435 // VNI will be valid because MachineOperand::readsReg() is checked by caller.
436 assert(VNI && "No value to read by operand");
437 MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
438 // Phis and other noninstructions (after coalescing) have a NULL Def.
440 SUnit *DefSU = getSUnit(Def);
442 // The reaching Def lives within this scheduling region.
443 // Create a data dependence.
444 SDep dep(DefSU, SDep::Data, Reg);
445 // Adjust the dependence latency using operand def/use information, then
446 // allow the target to perform its own adjustments.
447 int DefOp = Def->findRegisterDefOperandIdx(Reg);
448 dep.setLatency(SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx));
450 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
451 ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep));
456 // Add antidependence to the following def of the vreg it uses.
457 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
458 if (DefI != VRegDefs.end() && DefI->SU != SU)
459 DefI->SU->addPred(SDep(SU, SDep::Anti, Reg));
462 /// Return true if MI is an instruction we are unable to reason about
463 /// (like a call or something with unmodeled side effects).
464 static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) {
465 if (MI->isCall() || MI->hasUnmodeledSideEffects() ||
466 (MI->hasOrderedMemoryRef() &&
467 (!MI->mayLoad() || !MI->isInvariantLoad(AA))))
472 // This MI might have either incomplete info, or known to be unsafe
473 // to deal with (i.e. volatile object).
474 static inline bool isUnsafeMemoryObject(MachineInstr *MI,
475 const MachineFrameInfo *MFI) {
476 if (!MI || MI->memoperands_empty())
478 // We purposefully do no check for hasOneMemOperand() here
479 // in hope to trigger an assert downstream in order to
480 // finish implementation.
481 if ((*MI->memoperands_begin())->isVolatile() ||
482 MI->hasUnmodeledSideEffects())
484 const Value *V = (*MI->memoperands_begin())->getValue();
488 SmallVector<Value *, 4> Objs;
489 getUnderlyingObjects(V, Objs);
490 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(),
491 IE = Objs.end(); I != IE; ++I) {
494 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
495 // Similarly to getUnderlyingObjectForInstr:
496 // For now, ignore PseudoSourceValues which may alias LLVM IR values
497 // because the code that uses this function has no way to cope with
499 if (PSV->isAliased(MFI))
503 // Does this pointer refer to a distinct and identifiable object?
504 if (!isIdentifiedObject(V))
511 /// This returns true if the two MIs need a chain edge betwee them.
512 /// If these are not even memory operations, we still may need
513 /// chain deps between them. The question really is - could
514 /// these two MIs be reordered during scheduling from memory dependency
516 static bool MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI,
519 // Cover a trivial case - no edge is need to itself.
523 // FIXME: Need to handle multiple memory operands to support all targets.
524 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand())
527 if (isUnsafeMemoryObject(MIa, MFI) || isUnsafeMemoryObject(MIb, MFI))
530 // If we are dealing with two "normal" loads, we do not need an edge
531 // between them - they could be reordered.
532 if (!MIa->mayStore() && !MIb->mayStore())
535 // To this point analysis is generic. From here on we do need AA.
539 MachineMemOperand *MMOa = *MIa->memoperands_begin();
540 MachineMemOperand *MMOb = *MIb->memoperands_begin();
542 // The following interface to AA is fashioned after DAGCombiner::isAlias
543 // and operates with MachineMemOperand offset with some important
545 // - LLVM fundamentally assumes flat address spaces.
546 // - MachineOperand offset can *only* result from legalization and
547 // cannot affect queries other than the trivial case of overlap
549 // - These offsets never wrap and never step outside
550 // of allocated objects.
551 // - There should never be any negative offsets here.
553 // FIXME: Modify API to hide this math from "user"
554 // FIXME: Even before we go to AA we can reason locally about some
555 // memory objects. It can save compile time, and possibly catch some
556 // corner cases not currently covered.
558 assert ((MMOa->getOffset() >= 0) && "Negative MachineMemOperand offset");
559 assert ((MMOb->getOffset() >= 0) && "Negative MachineMemOperand offset");
561 int64_t MinOffset = std::min(MMOa->getOffset(), MMOb->getOffset());
562 int64_t Overlapa = MMOa->getSize() + MMOa->getOffset() - MinOffset;
563 int64_t Overlapb = MMOb->getSize() + MMOb->getOffset() - MinOffset;
565 AliasAnalysis::AliasResult AAResult = AA->alias(
566 AliasAnalysis::Location(MMOa->getValue(), Overlapa,
567 UseTBAA ? MMOa->getTBAAInfo() : 0),
568 AliasAnalysis::Location(MMOb->getValue(), Overlapb,
569 UseTBAA ? MMOb->getTBAAInfo() : 0));
571 return (AAResult != AliasAnalysis::NoAlias);
574 /// This recursive function iterates over chain deps of SUb looking for
575 /// "latest" node that needs a chain edge to SUa.
577 iterateChainSucc(AliasAnalysis *AA, const MachineFrameInfo *MFI,
578 SUnit *SUa, SUnit *SUb, SUnit *ExitSU, unsigned *Depth,
579 SmallPtrSet<const SUnit*, 16> &Visited) {
580 if (!SUa || !SUb || SUb == ExitSU)
583 // Remember visited nodes.
584 if (!Visited.insert(SUb))
586 // If there is _some_ dependency already in place, do not
587 // descend any further.
588 // TODO: Need to make sure that if that dependency got eliminated or ignored
589 // for any reason in the future, we would not violate DAG topology.
590 // Currently it does not happen, but makes an implicit assumption about
591 // future implementation.
593 // Independently, if we encounter node that is some sort of global
594 // object (like a call) we already have full set of dependencies to it
595 // and we can stop descending.
596 if (SUa->isSucc(SUb) ||
597 isGlobalMemoryObject(AA, SUb->getInstr()))
600 // If we do need an edge, or we have exceeded depth budget,
601 // add that edge to the predecessors chain of SUb,
602 // and stop descending.
604 MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) {
605 SUb->addPred(SDep(SUa, SDep::MayAliasMem));
608 // Track current depth.
610 // Iterate over chain dependencies only.
611 for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E = SUb->Succs.end();
614 iterateChainSucc (AA, MFI, SUa, I->getSUnit(), ExitSU, Depth, Visited);
618 /// This function assumes that "downward" from SU there exist
619 /// tail/leaf of already constructed DAG. It iterates downward and
620 /// checks whether SU can be aliasing any node dominated
622 static void adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI,
623 SUnit *SU, SUnit *ExitSU, std::set<SUnit *> &CheckList,
624 unsigned LatencyToLoad) {
628 SmallPtrSet<const SUnit*, 16> Visited;
631 for (std::set<SUnit *>::iterator I = CheckList.begin(), IE = CheckList.end();
635 if (MIsNeedChainEdge(AA, MFI, SU->getInstr(), (*I)->getInstr())) {
636 SDep Dep(SU, SDep::MayAliasMem);
637 Dep.setLatency(((*I)->getInstr()->mayLoad()) ? LatencyToLoad : 0);
640 // Now go through all the chain successors and iterate from them.
641 // Keep track of visited nodes.
642 for (SUnit::const_succ_iterator J = (*I)->Succs.begin(),
643 JE = (*I)->Succs.end(); J != JE; ++J)
645 iterateChainSucc (AA, MFI, SU, J->getSUnit(),
646 ExitSU, &Depth, Visited);
650 /// Check whether two objects need a chain edge, if so, add it
651 /// otherwise remember the rejected SU.
653 void addChainDependency (AliasAnalysis *AA, const MachineFrameInfo *MFI,
654 SUnit *SUa, SUnit *SUb,
655 std::set<SUnit *> &RejectList,
656 unsigned TrueMemOrderLatency = 0,
657 bool isNormalMemory = false) {
658 // If this is a false dependency,
659 // do not add the edge, but rememeber the rejected node.
660 if (!AA || MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) {
661 SDep Dep(SUa, isNormalMemory ? SDep::MayAliasMem : SDep::Barrier);
662 Dep.setLatency(TrueMemOrderLatency);
666 // Duplicate entries should be ignored.
667 RejectList.insert(SUb);
668 DEBUG(dbgs() << "\tReject chain dep between SU("
669 << SUa->NodeNum << ") and SU("
670 << SUb->NodeNum << ")\n");
674 /// Create an SUnit for each real instruction, numbered in top-down toplological
675 /// order. The instruction order A < B, implies that no edge exists from B to A.
677 /// Map each real instruction to its SUnit.
679 /// After initSUnits, the SUnits vector cannot be resized and the scheduler may
680 /// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs
681 /// instead of pointers.
683 /// MachineScheduler relies on initSUnits numbering the nodes by their order in
684 /// the original instruction list.
685 void ScheduleDAGInstrs::initSUnits() {
686 // We'll be allocating one SUnit for each real instruction in the region,
687 // which is contained within a basic block.
688 SUnits.reserve(NumRegionInstrs);
690 for (MachineBasicBlock::iterator I = RegionBegin; I != RegionEnd; ++I) {
691 MachineInstr *MI = I;
692 if (MI->isDebugValue())
695 SUnit *SU = newSUnit(MI);
698 SU->isCall = MI->isCall();
699 SU->isCommutable = MI->isCommutable();
701 // Assign the Latency field of SU using target-provided information.
702 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
704 // If this SUnit uses an unbuffered resource, mark it as such.
705 // These resources are used for in-order execution pipelines within an
706 // out-of-order core and are identified by BufferSize=1. BufferSize=0 is
707 // used for dispatch/issue groups and is not considered here.
708 if (SchedModel.hasInstrSchedModel()) {
709 const MCSchedClassDesc *SC = getSchedClass(SU);
710 for (TargetSchedModel::ProcResIter
711 PI = SchedModel.getWriteProcResBegin(SC),
712 PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
713 switch (SchedModel.getProcResource(PI->ProcResourceIdx)->BufferSize) {
715 SU->hasReservedResource = true;
718 SU->isUnbuffered = true;
728 /// If RegPressure is non-null, compute register pressure as a side effect. The
729 /// DAG builder is an efficient place to do it because it already visits
731 void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
732 RegPressureTracker *RPTracker,
733 PressureDiffs *PDiffs) {
734 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
735 bool UseAA = EnableAASchedMI.getNumOccurrences() > 0 ? EnableAASchedMI
737 AliasAnalysis *AAForDep = UseAA ? AA : 0;
740 ScheduleDAG::clearDAG();
742 // Create an SUnit for each real instruction.
746 PDiffs->init(SUnits.size());
748 // We build scheduling units by walking a block's instruction list from bottom
751 // Remember where a generic side-effecting instruction is as we procede.
752 SUnit *BarrierChain = 0, *AliasChain = 0;
754 // Memory references to specific known memory locations are tracked
755 // so that they can be given more precise dependencies. We track
756 // separately the known memory locations that may alias and those
757 // that are known not to alias
758 MapVector<const Value *, std::vector<SUnit *> > AliasMemDefs, NonAliasMemDefs;
759 MapVector<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
760 std::set<SUnit*> RejectMemNodes;
762 // Remove any stale debug info; sometimes BuildSchedGraph is called again
763 // without emitting the info from the previous call.
765 FirstDbgValue = NULL;
767 assert(Defs.empty() && Uses.empty() &&
768 "Only BuildGraph should update Defs/Uses");
769 Defs.setUniverse(TRI->getNumRegs());
770 Uses.setUniverse(TRI->getNumRegs());
772 assert(VRegDefs.empty() && "Only BuildSchedGraph may access VRegDefs");
774 VRegDefs.setUniverse(MRI.getNumVirtRegs());
775 VRegUses.setUniverse(MRI.getNumVirtRegs());
777 // Model data dependencies between instructions being scheduled and the
779 addSchedBarrierDeps();
781 // Walk the list of instructions, from bottom moving up.
782 MachineInstr *DbgMI = NULL;
783 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
785 MachineInstr *MI = prior(MII);
787 DbgValues.push_back(std::make_pair(DbgMI, MI));
791 if (MI->isDebugValue()) {
795 SUnit *SU = MISUnitMap[MI];
796 assert(SU && "No SUnit mapped to this MI");
799 PressureDiff *PDiff = PDiffs ? &(*PDiffs)[SU->NodeNum] : 0;
800 RPTracker->recede(/*LiveUses=*/0, PDiff);
801 assert(RPTracker->getPos() == prior(MII) && "RPTracker can't find MI");
804 assert((CanHandleTerminators || (!MI->isTerminator() && !MI->isLabel())) &&
805 "Cannot schedule terminators or labels!");
807 // Add register-based dependencies (data, anti, and output).
808 bool HasVRegDef = false;
809 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) {
810 const MachineOperand &MO = MI->getOperand(j);
811 if (!MO.isReg()) continue;
812 unsigned Reg = MO.getReg();
813 if (Reg == 0) continue;
815 if (TRI->isPhysicalRegister(Reg))
816 addPhysRegDeps(SU, j);
818 assert(!IsPostRA && "Virtual register encountered!");
821 addVRegDefDeps(SU, j);
823 else if (MO.readsReg()) // ignore undef operands
824 addVRegUseDeps(SU, j);
827 // If we haven't seen any uses in this scheduling region, create a
828 // dependence edge to ExitSU to model the live-out latency. This is required
829 // for vreg defs with no in-region use, and prefetches with no vreg def.
831 // FIXME: NumDataSuccs would be more precise than NumSuccs here. This
832 // check currently relies on being called before adding chain deps.
833 if (SU->NumSuccs == 0 && SU->Latency > 1
834 && (HasVRegDef || MI->mayLoad())) {
835 SDep Dep(SU, SDep::Artificial);
836 Dep.setLatency(SU->Latency - 1);
840 // Add chain dependencies.
841 // Chain dependencies used to enforce memory order should have
842 // latency of 0 (except for true dependency of Store followed by
843 // aliased Load... we estimate that with a single cycle of latency
844 // assuming the hardware will bypass)
845 // Note that isStoreToStackSlot and isLoadFromStackSLot are not usable
846 // after stack slots are lowered to actual addresses.
847 // TODO: Use an AliasAnalysis and do real alias-analysis queries, and
848 // produce more precise dependence information.
849 unsigned TrueMemOrderLatency = MI->mayStore() ? 1 : 0;
850 if (isGlobalMemoryObject(AA, MI)) {
851 // Be conservative with these and add dependencies on all memory
852 // references, even those that are known to not alias.
853 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I =
854 NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) {
855 for (unsigned i = 0, e = I->second.size(); i != e; ++i) {
856 I->second[i]->addPred(SDep(SU, SDep::Barrier));
859 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I =
860 NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) {
861 for (unsigned i = 0, e = I->second.size(); i != e; ++i) {
862 SDep Dep(SU, SDep::Barrier);
863 Dep.setLatency(TrueMemOrderLatency);
864 I->second[i]->addPred(Dep);
867 // Add SU to the barrier chain.
869 BarrierChain->addPred(SDep(SU, SDep::Barrier));
871 // This is a barrier event that acts as a pivotal node in the DAG,
872 // so it is safe to clear list of exposed nodes.
873 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
874 TrueMemOrderLatency);
875 RejectMemNodes.clear();
876 NonAliasMemDefs.clear();
877 NonAliasMemUses.clear();
881 // Chain all possibly aliasing memory references though SU.
883 unsigned ChainLatency = 0;
884 if (AliasChain->getInstr()->mayLoad())
885 ChainLatency = TrueMemOrderLatency;
886 addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes,
890 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
891 addChainDependency(AAForDep, MFI, SU, PendingLoads[k], RejectMemNodes,
892 TrueMemOrderLatency);
893 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I =
894 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I) {
895 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
896 addChainDependency(AAForDep, MFI, SU, I->second[i], RejectMemNodes);
898 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I =
899 AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
900 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
901 addChainDependency(AAForDep, MFI, SU, I->second[i], RejectMemNodes,
902 TrueMemOrderLatency);
904 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
905 TrueMemOrderLatency);
906 PendingLoads.clear();
907 AliasMemDefs.clear();
908 AliasMemUses.clear();
909 } else if (MI->mayStore()) {
910 UnderlyingObjectsVector Objs;
911 getUnderlyingObjectsForInstr(MI, MFI, Objs);
914 // Treat all other stores conservatively.
915 goto new_alias_chain;
918 bool MayAlias = false;
919 for (UnderlyingObjectsVector::iterator K = Objs.begin(), KE = Objs.end();
921 const Value *V = K->getPointer();
922 bool ThisMayAlias = K->getInt();
926 // A store to a specific PseudoSourceValue. Add precise dependencies.
927 // Record the def in MemDefs, first adding a dep if there is
929 MapVector<const Value *, std::vector<SUnit *> >::iterator I =
930 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
931 MapVector<const Value *, std::vector<SUnit *> >::iterator IE =
932 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
934 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
935 addChainDependency(AAForDep, MFI, SU, I->second[i], RejectMemNodes,
938 // If we're not using AA, then we only need one store per object.
941 I->second.push_back(SU);
945 AliasMemDefs[V].clear();
946 AliasMemDefs[V].push_back(SU);
949 NonAliasMemDefs[V].clear();
950 NonAliasMemDefs[V].push_back(SU);
953 // Handle the uses in MemUses, if there are any.
954 MapVector<const Value *, std::vector<SUnit *> >::iterator J =
955 ((ThisMayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V));
956 MapVector<const Value *, std::vector<SUnit *> >::iterator JE =
957 ((ThisMayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
959 for (unsigned i = 0, e = J->second.size(); i != e; ++i)
960 addChainDependency(AAForDep, MFI, SU, J->second[i], RejectMemNodes,
961 TrueMemOrderLatency, true);
966 // Add dependencies from all the PendingLoads, i.e. loads
967 // with no underlying object.
968 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
969 addChainDependency(AAForDep, MFI, SU, PendingLoads[k], RejectMemNodes,
970 TrueMemOrderLatency);
971 // Add dependence on alias chain, if needed.
973 addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes);
974 // But we also should check dependent instructions for the
976 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
977 TrueMemOrderLatency);
979 // Add dependence on barrier chain, if needed.
980 // There is no point to check aliasing on barrier event. Even if
981 // SU and barrier _could_ be reordered, they should not. In addition,
982 // we have lost all RejectMemNodes below barrier.
984 BarrierChain->addPred(SDep(SU, SDep::Barrier));
986 if (!ExitSU.isPred(SU))
987 // Push store's up a bit to avoid them getting in between cmp
989 ExitSU.addPred(SDep(SU, SDep::Artificial));
990 } else if (MI->mayLoad()) {
991 bool MayAlias = true;
992 if (MI->isInvariantLoad(AA)) {
993 // Invariant load, no chain dependencies needed!
995 UnderlyingObjectsVector Objs;
996 getUnderlyingObjectsForInstr(MI, MFI, Objs);
999 // A load with no underlying object. Depend on all
1000 // potentially aliasing stores.
1001 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I =
1002 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
1003 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
1004 addChainDependency(AAForDep, MFI, SU, I->second[i],
1007 PendingLoads.push_back(SU);
1013 for (UnderlyingObjectsVector::iterator
1014 J = Objs.begin(), JE = Objs.end(); J != JE; ++J) {
1015 const Value *V = J->getPointer();
1016 bool ThisMayAlias = J->getInt();
1021 // A load from a specific PseudoSourceValue. Add precise dependencies.
1022 MapVector<const Value *, std::vector<SUnit *> >::iterator I =
1023 ((ThisMayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V));
1024 MapVector<const Value *, std::vector<SUnit *> >::iterator IE =
1025 ((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
1027 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
1028 addChainDependency(AAForDep, MFI, SU, I->second[i],
1029 RejectMemNodes, 0, true);
1031 AliasMemUses[V].push_back(SU);
1033 NonAliasMemUses[V].push_back(SU);
1036 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, /*Latency=*/0);
1037 // Add dependencies on alias and barrier chains, if needed.
1038 if (MayAlias && AliasChain)
1039 addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes);
1041 BarrierChain->addPred(SDep(SU, SDep::Barrier));
1046 FirstDbgValue = DbgMI;
1051 PendingLoads.clear();
1054 /// \brief Initialize register live-range state for updating kills.
1055 void ScheduleDAGInstrs::startBlockForKills(MachineBasicBlock *BB) {
1056 // Start with no live registers.
1059 // Examine the live-in regs of all successors.
1060 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
1061 SE = BB->succ_end(); SI != SE; ++SI) {
1062 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
1063 E = (*SI)->livein_end(); I != E; ++I) {
1065 // Repeat, for reg and all subregs.
1066 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1067 SubRegs.isValid(); ++SubRegs)
1068 LiveRegs.set(*SubRegs);
1073 bool ScheduleDAGInstrs::toggleKillFlag(MachineInstr *MI, MachineOperand &MO) {
1074 // Setting kill flag...
1080 // If MO itself is live, clear the kill flag...
1081 if (LiveRegs.test(MO.getReg())) {
1082 MO.setIsKill(false);
1086 // If any subreg of MO is live, then create an imp-def for that
1087 // subreg and keep MO marked as killed.
1088 MO.setIsKill(false);
1089 bool AllDead = true;
1090 const unsigned SuperReg = MO.getReg();
1091 MachineInstrBuilder MIB(MF, MI);
1092 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) {
1093 if (LiveRegs.test(*SubRegs)) {
1094 MIB.addReg(*SubRegs, RegState::ImplicitDefine);
1104 // FIXME: Reuse the LivePhysRegs utility for this.
1105 void ScheduleDAGInstrs::fixupKills(MachineBasicBlock *MBB) {
1106 DEBUG(dbgs() << "Fixup kills for BB#" << MBB->getNumber() << '\n');
1108 LiveRegs.resize(TRI->getNumRegs());
1109 BitVector killedRegs(TRI->getNumRegs());
1111 startBlockForKills(MBB);
1113 // Examine block from end to start...
1114 unsigned Count = MBB->size();
1115 for (MachineBasicBlock::iterator I = MBB->end(), E = MBB->begin();
1117 MachineInstr *MI = --I;
1118 if (MI->isDebugValue())
1121 // Update liveness. Registers that are defed but not used in this
1122 // instruction are now dead. Mark register and all subregs as they
1123 // are completely defined.
1124 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1125 MachineOperand &MO = MI->getOperand(i);
1127 LiveRegs.clearBitsNotInMask(MO.getRegMask());
1128 if (!MO.isReg()) continue;
1129 unsigned Reg = MO.getReg();
1130 if (Reg == 0) continue;
1131 if (!MO.isDef()) continue;
1132 // Ignore two-addr defs.
1133 if (MI->isRegTiedToUseOperand(i)) continue;
1135 // Repeat for reg and all subregs.
1136 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1137 SubRegs.isValid(); ++SubRegs)
1138 LiveRegs.reset(*SubRegs);
1141 // Examine all used registers and set/clear kill flag. When a
1142 // register is used multiple times we only set the kill flag on
1143 // the first use. Don't set kill flags on undef operands.
1145 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1146 MachineOperand &MO = MI->getOperand(i);
1147 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
1148 unsigned Reg = MO.getReg();
1149 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
1152 if (!killedRegs.test(Reg)) {
1154 // A register is not killed if any subregs are live...
1155 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
1156 if (LiveRegs.test(*SubRegs)) {
1162 // If subreg is not live, then register is killed if it became
1163 // live in this instruction
1165 kill = !LiveRegs.test(Reg);
1168 if (MO.isKill() != kill) {
1169 DEBUG(dbgs() << "Fixing " << MO << " in ");
1170 // Warning: toggleKillFlag may invalidate MO.
1171 toggleKillFlag(MI, MO);
1175 killedRegs.set(Reg);
1178 // Mark any used register (that is not using undef) and subregs as
1180 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1181 MachineOperand &MO = MI->getOperand(i);
1182 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
1183 unsigned Reg = MO.getReg();
1184 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
1186 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1187 SubRegs.isValid(); ++SubRegs)
1188 LiveRegs.set(*SubRegs);
1193 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
1194 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1195 SU->getInstr()->dump();
1199 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
1201 raw_string_ostream oss(s);
1204 else if (SU == &ExitSU)
1207 SU->getInstr()->print(oss, &TM, /*SkipOpers=*/true);
1211 /// Return the basic block label. It is not necessarilly unique because a block
1212 /// contains multiple scheduling regions. But it is fine for visualization.
1213 std::string ScheduleDAGInstrs::getDAGName() const {
1214 return "dag." + BB->getFullName();
1217 //===----------------------------------------------------------------------===//
1218 // SchedDFSResult Implementation
1219 //===----------------------------------------------------------------------===//
1222 /// \brief Internal state used to compute SchedDFSResult.
1223 class SchedDFSImpl {
1226 /// Join DAG nodes into equivalence classes by their subtree.
1227 IntEqClasses SubtreeClasses;
1228 /// List PredSU, SuccSU pairs that represent data edges between subtrees.
1229 std::vector<std::pair<const SUnit*, const SUnit*> > ConnectionPairs;
1233 unsigned ParentNodeID; // Parent node (member of the parent subtree).
1234 unsigned SubInstrCount; // Instr count in this tree only, not children.
1236 RootData(unsigned id): NodeID(id),
1237 ParentNodeID(SchedDFSResult::InvalidSubtreeID),
1240 unsigned getSparseSetIndex() const { return NodeID; }
1243 SparseSet<RootData> RootSet;
1246 SchedDFSImpl(SchedDFSResult &r): R(r), SubtreeClasses(R.DFSNodeData.size()) {
1247 RootSet.setUniverse(R.DFSNodeData.size());
1250 /// Return true if this node been visited by the DFS traversal.
1252 /// During visitPostorderNode the Node's SubtreeID is assigned to the Node
1253 /// ID. Later, SubtreeID is updated but remains valid.
1254 bool isVisited(const SUnit *SU) const {
1255 return R.DFSNodeData[SU->NodeNum].SubtreeID
1256 != SchedDFSResult::InvalidSubtreeID;
1259 /// Initialize this node's instruction count. We don't need to flag the node
1260 /// visited until visitPostorder because the DAG cannot have cycles.
1261 void visitPreorder(const SUnit *SU) {
1262 R.DFSNodeData[SU->NodeNum].InstrCount =
1263 SU->getInstr()->isTransient() ? 0 : 1;
1266 /// Called once for each node after all predecessors are visited. Revisit this
1267 /// node's predecessors and potentially join them now that we know the ILP of
1268 /// the other predecessors.
1269 void visitPostorderNode(const SUnit *SU) {
1270 // Mark this node as the root of a subtree. It may be joined with its
1271 // successors later.
1272 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum;
1273 RootData RData(SU->NodeNum);
1274 RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1;
1276 // If any predecessors are still in their own subtree, they either cannot be
1277 // joined or are large enough to remain separate. If this parent node's
1278 // total instruction count is not greater than a child subtree by at least
1279 // the subtree limit, then try to join it now since splitting subtrees is
1280 // only useful if multiple high-pressure paths are possible.
1281 unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount;
1282 for (SUnit::const_pred_iterator
1283 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
1284 if (PI->getKind() != SDep::Data)
1286 unsigned PredNum = PI->getSUnit()->NodeNum;
1287 if ((InstrCount - R.DFSNodeData[PredNum].InstrCount) < R.SubtreeLimit)
1288 joinPredSubtree(*PI, SU, /*CheckLimit=*/false);
1290 // Either link or merge the TreeData entry from the child to the parent.
1291 if (R.DFSNodeData[PredNum].SubtreeID == PredNum) {
1292 // If the predecessor's parent is invalid, this is a tree edge and the
1293 // current node is the parent.
1294 if (RootSet[PredNum].ParentNodeID == SchedDFSResult::InvalidSubtreeID)
1295 RootSet[PredNum].ParentNodeID = SU->NodeNum;
1297 else if (RootSet.count(PredNum)) {
1298 // The predecessor is not a root, but is still in the root set. This
1299 // must be the new parent that it was just joined to. Note that
1300 // RootSet[PredNum].ParentNodeID may either be invalid or may still be
1301 // set to the original parent.
1302 RData.SubInstrCount += RootSet[PredNum].SubInstrCount;
1303 RootSet.erase(PredNum);
1306 RootSet[SU->NodeNum] = RData;
1309 /// Called once for each tree edge after calling visitPostOrderNode on the
1310 /// predecessor. Increment the parent node's instruction count and
1311 /// preemptively join this subtree to its parent's if it is small enough.
1312 void visitPostorderEdge(const SDep &PredDep, const SUnit *Succ) {
1313 R.DFSNodeData[Succ->NodeNum].InstrCount
1314 += R.DFSNodeData[PredDep.getSUnit()->NodeNum].InstrCount;
1315 joinPredSubtree(PredDep, Succ);
1318 /// Add a connection for cross edges.
1319 void visitCrossEdge(const SDep &PredDep, const SUnit *Succ) {
1320 ConnectionPairs.push_back(std::make_pair(PredDep.getSUnit(), Succ));
1323 /// Set each node's subtree ID to the representative ID and record connections
1326 SubtreeClasses.compress();
1327 R.DFSTreeData.resize(SubtreeClasses.getNumClasses());
1328 assert(SubtreeClasses.getNumClasses() == RootSet.size()
1329 && "number of roots should match trees");
1330 for (SparseSet<RootData>::const_iterator
1331 RI = RootSet.begin(), RE = RootSet.end(); RI != RE; ++RI) {
1332 unsigned TreeID = SubtreeClasses[RI->NodeID];
1333 if (RI->ParentNodeID != SchedDFSResult::InvalidSubtreeID)
1334 R.DFSTreeData[TreeID].ParentTreeID = SubtreeClasses[RI->ParentNodeID];
1335 R.DFSTreeData[TreeID].SubInstrCount = RI->SubInstrCount;
1336 // Note that SubInstrCount may be greater than InstrCount if we joined
1337 // subtrees across a cross edge. InstrCount will be attributed to the
1338 // original parent, while SubInstrCount will be attributed to the joined
1341 R.SubtreeConnections.resize(SubtreeClasses.getNumClasses());
1342 R.SubtreeConnectLevels.resize(SubtreeClasses.getNumClasses());
1343 DEBUG(dbgs() << R.getNumSubtrees() << " subtrees:\n");
1344 for (unsigned Idx = 0, End = R.DFSNodeData.size(); Idx != End; ++Idx) {
1345 R.DFSNodeData[Idx].SubtreeID = SubtreeClasses[Idx];
1346 DEBUG(dbgs() << " SU(" << Idx << ") in tree "
1347 << R.DFSNodeData[Idx].SubtreeID << '\n');
1349 for (std::vector<std::pair<const SUnit*, const SUnit*> >::const_iterator
1350 I = ConnectionPairs.begin(), E = ConnectionPairs.end();
1352 unsigned PredTree = SubtreeClasses[I->first->NodeNum];
1353 unsigned SuccTree = SubtreeClasses[I->second->NodeNum];
1354 if (PredTree == SuccTree)
1356 unsigned Depth = I->first->getDepth();
1357 addConnection(PredTree, SuccTree, Depth);
1358 addConnection(SuccTree, PredTree, Depth);
1363 /// Join the predecessor subtree with the successor that is its DFS
1364 /// parent. Apply some heuristics before joining.
1365 bool joinPredSubtree(const SDep &PredDep, const SUnit *Succ,
1366 bool CheckLimit = true) {
1367 assert(PredDep.getKind() == SDep::Data && "Subtrees are for data edges");
1369 // Check if the predecessor is already joined.
1370 const SUnit *PredSU = PredDep.getSUnit();
1371 unsigned PredNum = PredSU->NodeNum;
1372 if (R.DFSNodeData[PredNum].SubtreeID != PredNum)
1375 // Four is the magic number of successors before a node is considered a
1377 unsigned NumDataSucs = 0;
1378 for (SUnit::const_succ_iterator SI = PredSU->Succs.begin(),
1379 SE = PredSU->Succs.end(); SI != SE; ++SI) {
1380 if (SI->getKind() == SDep::Data) {
1381 if (++NumDataSucs >= 4)
1385 if (CheckLimit && R.DFSNodeData[PredNum].InstrCount > R.SubtreeLimit)
1387 R.DFSNodeData[PredNum].SubtreeID = Succ->NodeNum;
1388 SubtreeClasses.join(Succ->NodeNum, PredNum);
1392 /// Called by finalize() to record a connection between trees.
1393 void addConnection(unsigned FromTree, unsigned ToTree, unsigned Depth) {
1398 SmallVectorImpl<SchedDFSResult::Connection> &Connections =
1399 R.SubtreeConnections[FromTree];
1400 for (SmallVectorImpl<SchedDFSResult::Connection>::iterator
1401 I = Connections.begin(), E = Connections.end(); I != E; ++I) {
1402 if (I->TreeID == ToTree) {
1403 I->Level = std::max(I->Level, Depth);
1407 Connections.push_back(SchedDFSResult::Connection(ToTree, Depth));
1408 FromTree = R.DFSTreeData[FromTree].ParentTreeID;
1409 } while (FromTree != SchedDFSResult::InvalidSubtreeID);
1415 /// \brief Manage the stack used by a reverse depth-first search over the DAG.
1416 class SchedDAGReverseDFS {
1417 std::vector<std::pair<const SUnit*, SUnit::const_pred_iterator> > DFSStack;
1419 bool isComplete() const { return DFSStack.empty(); }
1421 void follow(const SUnit *SU) {
1422 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin()));
1424 void advance() { ++DFSStack.back().second; }
1426 const SDep *backtrack() {
1427 DFSStack.pop_back();
1428 return DFSStack.empty() ? 0 : llvm::prior(DFSStack.back().second);
1431 const SUnit *getCurr() const { return DFSStack.back().first; }
1433 SUnit::const_pred_iterator getPred() const { return DFSStack.back().second; }
1435 SUnit::const_pred_iterator getPredEnd() const {
1436 return getCurr()->Preds.end();
1441 static bool hasDataSucc(const SUnit *SU) {
1442 for (SUnit::const_succ_iterator
1443 SI = SU->Succs.begin(), SE = SU->Succs.end(); SI != SE; ++SI) {
1444 if (SI->getKind() == SDep::Data && !SI->getSUnit()->isBoundaryNode())
1450 /// Compute an ILP metric for all nodes in the subDAG reachable via depth-first
1451 /// search from this root.
1452 void SchedDFSResult::compute(ArrayRef<SUnit> SUnits) {
1454 llvm_unreachable("Top-down ILP metric is unimplemnted");
1456 SchedDFSImpl Impl(*this);
1457 for (ArrayRef<SUnit>::const_iterator
1458 SI = SUnits.begin(), SE = SUnits.end(); SI != SE; ++SI) {
1459 const SUnit *SU = &*SI;
1460 if (Impl.isVisited(SU) || hasDataSucc(SU))
1463 SchedDAGReverseDFS DFS;
1464 Impl.visitPreorder(SU);
1467 // Traverse the leftmost path as far as possible.
1468 while (DFS.getPred() != DFS.getPredEnd()) {
1469 const SDep &PredDep = *DFS.getPred();
1471 // Ignore non-data edges.
1472 if (PredDep.getKind() != SDep::Data
1473 || PredDep.getSUnit()->isBoundaryNode()) {
1476 // An already visited edge is a cross edge, assuming an acyclic DAG.
1477 if (Impl.isVisited(PredDep.getSUnit())) {
1478 Impl.visitCrossEdge(PredDep, DFS.getCurr());
1481 Impl.visitPreorder(PredDep.getSUnit());
1482 DFS.follow(PredDep.getSUnit());
1484 // Visit the top of the stack in postorder and backtrack.
1485 const SUnit *Child = DFS.getCurr();
1486 const SDep *PredDep = DFS.backtrack();
1487 Impl.visitPostorderNode(Child);
1489 Impl.visitPostorderEdge(*PredDep, DFS.getCurr());
1490 if (DFS.isComplete())
1497 /// The root of the given SubtreeID was just scheduled. For all subtrees
1498 /// connected to this tree, record the depth of the connection so that the
1499 /// nearest connected subtrees can be prioritized.
1500 void SchedDFSResult::scheduleTree(unsigned SubtreeID) {
1501 for (SmallVectorImpl<Connection>::const_iterator
1502 I = SubtreeConnections[SubtreeID].begin(),
1503 E = SubtreeConnections[SubtreeID].end(); I != E; ++I) {
1504 SubtreeConnectLevels[I->TreeID] =
1505 std::max(SubtreeConnectLevels[I->TreeID], I->Level);
1506 DEBUG(dbgs() << " Tree: " << I->TreeID
1507 << " @" << SubtreeConnectLevels[I->TreeID] << '\n');
1511 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1512 void ILPValue::print(raw_ostream &OS) const {
1513 OS << InstrCount << " / " << Length << " = ";
1517 OS << format("%g", ((double)InstrCount / Length));
1520 void ILPValue::dump() const {
1521 dbgs() << *this << '\n';
1526 raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val) {
1532 #endif // !NDEBUG || LLVM_ENABLE_DUMP