1 //===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
11 // register allocator for LLVM. This allocator works by constructing a PBQP
12 // problem representing the register allocation problem under consideration,
13 // solving this using a PBQP solver, and mapping the solution back to a
14 // register assignment. If any variables are selected for spilling then spill
15 // code is inserted and the process repeated.
17 // The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
18 // for register allocation. For more information on PBQP for register
19 // allocation, see the following papers:
21 // (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
22 // PBQP. In Proceedings of the 7th Joint Modular Languages Conference
23 // (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
25 // (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
26 // architectures. In Proceedings of the Joint Conference on Languages,
27 // Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
30 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "regalloc"
34 #include "llvm/CodeGen/RegAllocPBQP.h"
35 #include "RegisterCoalescer.h"
37 #include "llvm/ADT/OwningPtr.h"
38 #include "llvm/Analysis/AliasAnalysis.h"
39 #include "llvm/CodeGen/CalcSpillWeights.h"
40 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
41 #include "llvm/CodeGen/LiveRangeEdit.h"
42 #include "llvm/CodeGen/LiveStackAnalysis.h"
43 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
44 #include "llvm/CodeGen/MachineDominators.h"
45 #include "llvm/CodeGen/MachineFunctionPass.h"
46 #include "llvm/CodeGen/MachineLoopInfo.h"
47 #include "llvm/CodeGen/MachineRegisterInfo.h"
48 #include "llvm/CodeGen/RegAllocRegistry.h"
49 #include "llvm/CodeGen/VirtRegMap.h"
50 #include "llvm/IR/Module.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetMachine.h"
63 static RegisterRegAlloc
64 registerPBQPRepAlloc("pbqp", "PBQP register allocator",
65 createDefaultPBQPRegisterAllocator);
68 pbqpCoalescing("pbqp-coalescing",
69 cl::desc("Attempt coalescing during PBQP register allocation."),
70 cl::init(false), cl::Hidden);
74 pbqpDumpGraphs("pbqp-dump-graphs",
75 cl::desc("Dump graphs for each function/round in the compilation unit."),
76 cl::init(false), cl::Hidden);
82 /// PBQP based allocators solve the register allocation problem by mapping
83 /// register allocation problems to Partitioned Boolean Quadratic
84 /// Programming problems.
85 class RegAllocPBQP : public MachineFunctionPass {
90 /// Construct a PBQP register allocator.
91 RegAllocPBQP(OwningPtr<PBQPBuilder> &b, char *cPassID=0)
92 : MachineFunctionPass(ID), builder(b.take()), customPassID(cPassID) {
93 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
94 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
95 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
96 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
99 /// Return the pass name.
100 virtual const char* getPassName() const {
101 return "PBQP Register Allocator";
104 /// PBQP analysis usage.
105 virtual void getAnalysisUsage(AnalysisUsage &au) const;
107 /// Perform register allocation
108 virtual bool runOnMachineFunction(MachineFunction &MF);
112 typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
113 typedef std::vector<const LiveInterval*> Node2LIMap;
114 typedef std::vector<unsigned> AllowedSet;
115 typedef std::vector<AllowedSet> AllowedSetMap;
116 typedef std::pair<unsigned, unsigned> RegPair;
117 typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
118 typedef std::set<unsigned> RegSet;
121 OwningPtr<PBQPBuilder> builder;
126 const TargetMachine *tm;
127 const TargetRegisterInfo *tri;
128 const TargetInstrInfo *tii;
129 MachineRegisterInfo *mri;
130 const MachineBlockFrequencyInfo *mbfi;
132 OwningPtr<Spiller> spiller;
137 RegSet vregsToAlloc, emptyIntervalVRegs;
139 /// \brief Finds the initial set of vreg intervals to allocate.
140 void findVRegIntervalsToAlloc();
142 /// \brief Given a solved PBQP problem maps this solution back to a register
144 bool mapPBQPToRegAlloc(const PBQPRAProblem &problem,
145 const PBQP::Solution &solution);
147 /// \brief Postprocessing before final spilling. Sets basic block "live in"
149 void finalizeAlloc() const;
153 char RegAllocPBQP::ID = 0;
155 } // End anonymous namespace.
157 unsigned PBQPRAProblem::getVRegForNode(PBQPRAGraph::NodeId node) const {
158 Node2VReg::const_iterator vregItr = node2VReg.find(node);
159 assert(vregItr != node2VReg.end() && "No vreg for node.");
160 return vregItr->second;
163 PBQPRAGraph::NodeId PBQPRAProblem::getNodeForVReg(unsigned vreg) const {
164 VReg2Node::const_iterator nodeItr = vreg2Node.find(vreg);
165 assert(nodeItr != vreg2Node.end() && "No node for vreg.");
166 return nodeItr->second;
170 const PBQPRAProblem::AllowedSet&
171 PBQPRAProblem::getAllowedSet(unsigned vreg) const {
172 AllowedSetMap::const_iterator allowedSetItr = allowedSets.find(vreg);
173 assert(allowedSetItr != allowedSets.end() && "No pregs for vreg.");
174 const AllowedSet &allowedSet = allowedSetItr->second;
178 unsigned PBQPRAProblem::getPRegForOption(unsigned vreg, unsigned option) const {
179 assert(isPRegOption(vreg, option) && "Not a preg option.");
181 const AllowedSet& allowedSet = getAllowedSet(vreg);
182 assert(option <= allowedSet.size() && "Option outside allowed set.");
183 return allowedSet[option - 1];
186 PBQPRAProblem *PBQPBuilder::build(MachineFunction *mf, const LiveIntervals *lis,
187 const MachineBlockFrequencyInfo *mbfi,
188 const RegSet &vregs) {
190 LiveIntervals *LIS = const_cast<LiveIntervals*>(lis);
191 MachineRegisterInfo *mri = &mf->getRegInfo();
192 const TargetRegisterInfo *tri = mf->getTarget().getRegisterInfo();
194 OwningPtr<PBQPRAProblem> p(new PBQPRAProblem());
195 PBQPRAGraph &g = p->getGraph();
198 // Collect the set of preg intervals, record that they're used in the MF.
199 for (unsigned Reg = 1, e = tri->getNumRegs(); Reg != e; ++Reg) {
200 if (mri->def_empty(Reg))
203 mri->setPhysRegUsed(Reg);
206 // Iterate over vregs.
207 for (RegSet::const_iterator vregItr = vregs.begin(), vregEnd = vregs.end();
208 vregItr != vregEnd; ++vregItr) {
209 unsigned vreg = *vregItr;
210 const TargetRegisterClass *trc = mri->getRegClass(vreg);
211 LiveInterval *vregLI = &LIS->getInterval(vreg);
213 // Record any overlaps with regmask operands.
214 BitVector regMaskOverlaps;
215 LIS->checkRegMaskInterference(*vregLI, regMaskOverlaps);
217 // Compute an initial allowed set for the current vreg.
218 typedef std::vector<unsigned> VRAllowed;
220 ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(*mf);
221 for (unsigned i = 0; i != rawOrder.size(); ++i) {
222 unsigned preg = rawOrder[i];
223 if (mri->isReserved(preg))
226 // vregLI crosses a regmask operand that clobbers preg.
227 if (!regMaskOverlaps.empty() && !regMaskOverlaps.test(preg))
230 // vregLI overlaps fixed regunit interference.
231 bool Interference = false;
232 for (MCRegUnitIterator Units(preg, tri); Units.isValid(); ++Units) {
233 if (vregLI->overlaps(LIS->getRegUnit(*Units))) {
241 // preg is usable for this virtual register.
242 vrAllowed.push_back(preg);
245 PBQP::Vector nodeCosts(vrAllowed.size() + 1, 0);
247 PBQP::PBQPNum spillCost = (vregLI->weight != 0.0) ?
248 vregLI->weight : std::numeric_limits<PBQP::PBQPNum>::min();
250 addSpillCosts(nodeCosts, spillCost);
252 // Construct the node.
253 PBQPRAGraph::NodeId nId = g.addNode(std::move(nodeCosts));
255 // Record the mapping and allowed set in the problem.
256 p->recordVReg(vreg, nId, vrAllowed.begin(), vrAllowed.end());
260 for (RegSet::const_iterator vr1Itr = vregs.begin(), vrEnd = vregs.end();
261 vr1Itr != vrEnd; ++vr1Itr) {
262 unsigned vr1 = *vr1Itr;
263 const LiveInterval &l1 = lis->getInterval(vr1);
264 const PBQPRAProblem::AllowedSet &vr1Allowed = p->getAllowedSet(vr1);
266 for (RegSet::const_iterator vr2Itr = std::next(vr1Itr); vr2Itr != vrEnd;
268 unsigned vr2 = *vr2Itr;
269 const LiveInterval &l2 = lis->getInterval(vr2);
270 const PBQPRAProblem::AllowedSet &vr2Allowed = p->getAllowedSet(vr2);
272 assert(!l2.empty() && "Empty interval in vreg set?");
273 if (l1.overlaps(l2)) {
274 PBQP::Matrix edgeCosts(vr1Allowed.size()+1, vr2Allowed.size()+1, 0);
275 addInterferenceCosts(edgeCosts, vr1Allowed, vr2Allowed, tri);
277 g.addEdge(p->getNodeForVReg(vr1), p->getNodeForVReg(vr2),
278 std::move(edgeCosts));
286 void PBQPBuilder::addSpillCosts(PBQP::Vector &costVec,
287 PBQP::PBQPNum spillCost) {
288 costVec[0] = spillCost;
291 void PBQPBuilder::addInterferenceCosts(
292 PBQP::Matrix &costMat,
293 const PBQPRAProblem::AllowedSet &vr1Allowed,
294 const PBQPRAProblem::AllowedSet &vr2Allowed,
295 const TargetRegisterInfo *tri) {
296 assert(costMat.getRows() == vr1Allowed.size() + 1 && "Matrix height mismatch.");
297 assert(costMat.getCols() == vr2Allowed.size() + 1 && "Matrix width mismatch.");
299 for (unsigned i = 0; i != vr1Allowed.size(); ++i) {
300 unsigned preg1 = vr1Allowed[i];
302 for (unsigned j = 0; j != vr2Allowed.size(); ++j) {
303 unsigned preg2 = vr2Allowed[j];
305 if (tri->regsOverlap(preg1, preg2)) {
306 costMat[i + 1][j + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
312 PBQPRAProblem *PBQPBuilderWithCoalescing::build(MachineFunction *mf,
313 const LiveIntervals *lis,
314 const MachineBlockFrequencyInfo *mbfi,
315 const RegSet &vregs) {
317 OwningPtr<PBQPRAProblem> p(PBQPBuilder::build(mf, lis, mbfi, vregs));
318 PBQPRAGraph &g = p->getGraph();
320 const TargetMachine &tm = mf->getTarget();
321 CoalescerPair cp(*tm.getRegisterInfo());
323 // Scan the machine function and add a coalescing cost whenever CoalescerPair
325 for (MachineFunction::const_iterator mbbItr = mf->begin(),
327 mbbItr != mbbEnd; ++mbbItr) {
328 const MachineBasicBlock *mbb = &*mbbItr;
330 for (MachineBasicBlock::const_iterator miItr = mbb->begin(),
332 miItr != miEnd; ++miItr) {
333 const MachineInstr *mi = &*miItr;
335 if (!cp.setRegisters(mi)) {
336 continue; // Not coalescable.
339 if (cp.getSrcReg() == cp.getDstReg()) {
340 continue; // Already coalesced.
343 unsigned dst = cp.getDstReg(),
344 src = cp.getSrcReg();
346 const float copyFactor = 0.5; // Cost of copy relative to load. Current
347 // value plucked randomly out of the air.
349 PBQP::PBQPNum cBenefit =
350 copyFactor * LiveIntervals::getSpillWeight(false, true, mbfi, mi);
353 if (!mf->getRegInfo().isAllocatable(dst)) {
357 const PBQPRAProblem::AllowedSet &allowed = p->getAllowedSet(src);
358 unsigned pregOpt = 0;
359 while (pregOpt < allowed.size() && allowed[pregOpt] != dst) {
362 if (pregOpt < allowed.size()) {
363 ++pregOpt; // +1 to account for spill option.
364 PBQPRAGraph::NodeId node = p->getNodeForVReg(src);
365 llvm::dbgs() << "Reading node costs for node " << node << "\n";
366 llvm::dbgs() << "Source node: " << &g.getNodeCosts(node) << "\n";
367 PBQP::Vector newCosts(g.getNodeCosts(node));
368 addPhysRegCoalesce(newCosts, pregOpt, cBenefit);
369 g.setNodeCosts(node, newCosts);
372 const PBQPRAProblem::AllowedSet *allowed1 = &p->getAllowedSet(dst);
373 const PBQPRAProblem::AllowedSet *allowed2 = &p->getAllowedSet(src);
374 PBQPRAGraph::NodeId node1 = p->getNodeForVReg(dst);
375 PBQPRAGraph::NodeId node2 = p->getNodeForVReg(src);
376 PBQPRAGraph::EdgeId edge = g.findEdge(node1, node2);
377 if (edge == g.invalidEdgeId()) {
378 PBQP::Matrix costs(allowed1->size() + 1, allowed2->size() + 1, 0);
379 addVirtRegCoalesce(costs, *allowed1, *allowed2, cBenefit);
380 g.addEdge(node1, node2, costs);
382 if (g.getEdgeNode1Id(edge) == node2) {
383 std::swap(node1, node2);
384 std::swap(allowed1, allowed2);
386 PBQP::Matrix costs(g.getEdgeCosts(edge));
387 addVirtRegCoalesce(costs, *allowed1, *allowed2, cBenefit);
388 g.setEdgeCosts(edge, costs);
397 void PBQPBuilderWithCoalescing::addPhysRegCoalesce(PBQP::Vector &costVec,
399 PBQP::PBQPNum benefit) {
400 costVec[pregOption] += -benefit;
403 void PBQPBuilderWithCoalescing::addVirtRegCoalesce(
404 PBQP::Matrix &costMat,
405 const PBQPRAProblem::AllowedSet &vr1Allowed,
406 const PBQPRAProblem::AllowedSet &vr2Allowed,
407 PBQP::PBQPNum benefit) {
409 assert(costMat.getRows() == vr1Allowed.size() + 1 && "Size mismatch.");
410 assert(costMat.getCols() == vr2Allowed.size() + 1 && "Size mismatch.");
412 for (unsigned i = 0; i != vr1Allowed.size(); ++i) {
413 unsigned preg1 = vr1Allowed[i];
414 for (unsigned j = 0; j != vr2Allowed.size(); ++j) {
415 unsigned preg2 = vr2Allowed[j];
417 if (preg1 == preg2) {
418 costMat[i + 1][j + 1] += -benefit;
425 void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
426 au.setPreservesCFG();
427 au.addRequired<AliasAnalysis>();
428 au.addPreserved<AliasAnalysis>();
429 au.addRequired<SlotIndexes>();
430 au.addPreserved<SlotIndexes>();
431 au.addRequired<LiveIntervals>();
432 au.addPreserved<LiveIntervals>();
433 //au.addRequiredID(SplitCriticalEdgesID);
435 au.addRequiredID(*customPassID);
436 au.addRequired<LiveStacks>();
437 au.addPreserved<LiveStacks>();
438 au.addRequired<MachineBlockFrequencyInfo>();
439 au.addPreserved<MachineBlockFrequencyInfo>();
440 au.addRequired<MachineLoopInfo>();
441 au.addPreserved<MachineLoopInfo>();
442 au.addRequired<MachineDominatorTree>();
443 au.addPreserved<MachineDominatorTree>();
444 au.addRequired<VirtRegMap>();
445 au.addPreserved<VirtRegMap>();
446 MachineFunctionPass::getAnalysisUsage(au);
449 void RegAllocPBQP::findVRegIntervalsToAlloc() {
451 // Iterate over all live ranges.
452 for (unsigned i = 0, e = mri->getNumVirtRegs(); i != e; ++i) {
453 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
454 if (mri->reg_nodbg_empty(Reg))
456 LiveInterval *li = &lis->getInterval(Reg);
458 // If this live interval is non-empty we will use pbqp to allocate it.
459 // Empty intervals we allocate in a simple post-processing stage in
462 vregsToAlloc.insert(li->reg);
464 emptyIntervalVRegs.insert(li->reg);
469 bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAProblem &problem,
470 const PBQP::Solution &solution) {
471 // Set to true if we have any spills
472 bool anotherRoundNeeded = false;
474 // Clear the existing allocation.
477 const PBQPRAGraph &g = problem.getGraph();
478 // Iterate over the nodes mapping the PBQP solution to a register
480 for (auto NId : g.nodeIds()) {
481 unsigned vreg = problem.getVRegForNode(NId);
482 unsigned alloc = solution.getSelection(NId);
484 if (problem.isPRegOption(vreg, alloc)) {
485 unsigned preg = problem.getPRegForOption(vreg, alloc);
486 DEBUG(dbgs() << "VREG " << PrintReg(vreg, tri) << " -> "
487 << tri->getName(preg) << "\n");
488 assert(preg != 0 && "Invalid preg selected.");
489 vrm->assignVirt2Phys(vreg, preg);
490 } else if (problem.isSpillOption(vreg, alloc)) {
491 vregsToAlloc.erase(vreg);
492 SmallVector<unsigned, 8> newSpills;
493 LiveRangeEdit LRE(&lis->getInterval(vreg), newSpills, *mf, *lis, vrm);
496 DEBUG(dbgs() << "VREG " << PrintReg(vreg, tri) << " -> SPILLED (Cost: "
497 << LRE.getParent().weight << ", New vregs: ");
499 // Copy any newly inserted live intervals into the list of regs to
501 for (LiveRangeEdit::iterator itr = LRE.begin(), end = LRE.end();
503 LiveInterval &li = lis->getInterval(*itr);
504 assert(!li.empty() && "Empty spill range.");
505 DEBUG(dbgs() << PrintReg(li.reg, tri) << " ");
506 vregsToAlloc.insert(li.reg);
509 DEBUG(dbgs() << ")\n");
511 // We need another round if spill intervals were added.
512 anotherRoundNeeded |= !LRE.empty();
514 llvm_unreachable("Unknown allocation option.");
518 return !anotherRoundNeeded;
522 void RegAllocPBQP::finalizeAlloc() const {
523 // First allocate registers for the empty intervals.
524 for (RegSet::const_iterator
525 itr = emptyIntervalVRegs.begin(), end = emptyIntervalVRegs.end();
527 LiveInterval *li = &lis->getInterval(*itr);
529 unsigned physReg = mri->getSimpleHint(li->reg);
532 const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
533 physReg = liRC->getRawAllocationOrder(*mf).front();
536 vrm->assignVirt2Phys(li->reg, physReg);
540 bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
543 tm = &mf->getTarget();
544 tri = tm->getRegisterInfo();
545 tii = tm->getInstrInfo();
546 mri = &mf->getRegInfo();
548 lis = &getAnalysis<LiveIntervals>();
549 lss = &getAnalysis<LiveStacks>();
550 mbfi = &getAnalysis<MachineBlockFrequencyInfo>();
552 calculateSpillWeightsAndHints(*lis, MF, getAnalysis<MachineLoopInfo>(),
555 vrm = &getAnalysis<VirtRegMap>();
556 spiller.reset(createInlineSpiller(*this, MF, *vrm));
558 mri->freezeReservedRegs(MF);
560 DEBUG(dbgs() << "PBQP Register Allocating for " << mf->getName() << "\n");
562 // Allocator main loop:
564 // * Map current regalloc problem to a PBQP problem
565 // * Solve the PBQP problem
566 // * Map the solution back to a register allocation
567 // * Spill if necessary
569 // This process is continued till no more spills are generated.
571 // Find the vreg intervals in need of allocation.
572 findVRegIntervalsToAlloc();
575 const Function* func = mf->getFunction();
577 func->getParent()->getModuleIdentifier() + "." +
578 func->getName().str();
581 // If there are non-empty intervals allocate them using pbqp.
582 if (!vregsToAlloc.empty()) {
584 bool pbqpAllocComplete = false;
587 while (!pbqpAllocComplete) {
588 DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n");
590 OwningPtr<PBQPRAProblem> problem(
591 builder->build(mf, lis, mbfi, vregsToAlloc));
594 if (pbqpDumpGraphs) {
595 std::ostringstream rs;
597 std::string graphFileName(fqn + "." + rs.str() + ".pbqpgraph");
599 raw_fd_ostream os(graphFileName.c_str(), tmp, sys::fs::F_Text);
600 DEBUG(dbgs() << "Dumping graph for round " << round << " to \""
601 << graphFileName << "\"\n");
602 problem->getGraph().dump(os);
606 PBQP::Solution solution =
607 PBQP::RegAlloc::solve(problem->getGraph());
609 pbqpAllocComplete = mapPBQPToRegAlloc(*problem, solution);
615 // Finalise allocation, allocate empty ranges.
617 vregsToAlloc.clear();
618 emptyIntervalVRegs.clear();
620 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm << "\n");
625 FunctionPass* llvm::createPBQPRegisterAllocator(
626 OwningPtr<PBQPBuilder> &builder,
627 char *customPassID) {
628 return new RegAllocPBQP(builder, customPassID);
631 FunctionPass* llvm::createDefaultPBQPRegisterAllocator() {
632 OwningPtr<PBQPBuilder> Builder;
634 Builder.reset(new PBQPBuilderWithCoalescing());
636 Builder.reset(new PBQPBuilder());
637 return createPBQPRegisterAllocator(Builder);