1 //===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
11 // register allocator for LLVM. This allocator works by constructing a PBQP
12 // problem representing the register allocation problem under consideration,
13 // solving this using a PBQP solver, and mapping the solution back to a
14 // register assignment. If any variables are selected for spilling then spill
15 // code is inserted and the process repeated.
17 // The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
18 // for register allocation. For more information on PBQP for register
19 // allocation, see the following papers:
21 // (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
22 // PBQP. In Proceedings of the 7th Joint Modular Languages Conference
23 // (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
25 // (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
26 // architectures. In Proceedings of the Joint Conference on Languages,
27 // Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
30 //===----------------------------------------------------------------------===//
32 #include "llvm/CodeGen/RegAllocPBQP.h"
33 #include "RegisterCoalescer.h"
35 #include "llvm/Analysis/AliasAnalysis.h"
36 #include "llvm/CodeGen/CalcSpillWeights.h"
37 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
38 #include "llvm/CodeGen/LiveRangeEdit.h"
39 #include "llvm/CodeGen/LiveStackAnalysis.h"
40 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
41 #include "llvm/CodeGen/MachineDominators.h"
42 #include "llvm/CodeGen/MachineFunctionPass.h"
43 #include "llvm/CodeGen/MachineLoopInfo.h"
44 #include "llvm/CodeGen/MachineRegisterInfo.h"
45 #include "llvm/CodeGen/RegAllocRegistry.h"
46 #include "llvm/CodeGen/VirtRegMap.h"
47 #include "llvm/IR/Module.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/FileSystem.h"
50 #include "llvm/Support/raw_ostream.h"
51 #include "llvm/Target/TargetInstrInfo.h"
52 #include "llvm/Target/TargetSubtargetInfo.h"
62 #define DEBUG_TYPE "regalloc"
64 static RegisterRegAlloc
65 RegisterPBQPRepAlloc("pbqp", "PBQP register allocator",
66 createDefaultPBQPRegisterAllocator);
69 PBQPCoalescing("pbqp-coalescing",
70 cl::desc("Attempt coalescing during PBQP register allocation."),
71 cl::init(false), cl::Hidden);
75 PBQPDumpGraphs("pbqp-dump-graphs",
76 cl::desc("Dump graphs for each function/round in the compilation unit."),
77 cl::init(false), cl::Hidden);
83 /// PBQP based allocators solve the register allocation problem by mapping
84 /// register allocation problems to Partitioned Boolean Quadratic
85 /// Programming problems.
86 class RegAllocPBQP : public MachineFunctionPass {
91 /// Construct a PBQP register allocator.
92 RegAllocPBQP(char *cPassID = nullptr)
93 : MachineFunctionPass(ID), customPassID(cPassID) {
94 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
95 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
96 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
97 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
100 /// Return the pass name.
101 const char* getPassName() const override {
102 return "PBQP Register Allocator";
105 /// PBQP analysis usage.
106 void getAnalysisUsage(AnalysisUsage &au) const override;
108 /// Perform register allocation
109 bool runOnMachineFunction(MachineFunction &MF) override;
113 typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
114 typedef std::vector<const LiveInterval*> Node2LIMap;
115 typedef std::vector<unsigned> AllowedSet;
116 typedef std::vector<AllowedSet> AllowedSetMap;
117 typedef std::pair<unsigned, unsigned> RegPair;
118 typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
119 typedef std::set<unsigned> RegSet;
123 RegSet VRegsToAlloc, EmptyIntervalVRegs;
125 /// \brief Finds the initial set of vreg intervals to allocate.
126 void findVRegIntervalsToAlloc(const MachineFunction &MF, LiveIntervals &LIS);
128 /// \brief Constructs an initial graph.
129 void initializeGraph(PBQPRAGraph &G);
131 /// \brief Given a solved PBQP problem maps this solution back to a register
133 bool mapPBQPToRegAlloc(const PBQPRAGraph &G,
134 const PBQP::Solution &Solution,
136 Spiller &VRegSpiller);
138 /// \brief Postprocessing before final spilling. Sets basic block "live in"
140 void finalizeAlloc(MachineFunction &MF, LiveIntervals &LIS,
141 VirtRegMap &VRM) const;
145 char RegAllocPBQP::ID = 0;
147 /// @brief Set spill costs for each node in the PBQP reg-alloc graph.
148 class SpillCosts : public PBQPRAConstraint {
150 void apply(PBQPRAGraph &G) override {
151 LiveIntervals &LIS = G.getMetadata().LIS;
153 for (auto NId : G.nodeIds()) {
154 PBQP::PBQPNum SpillCost =
155 LIS.getInterval(G.getNodeMetadata(NId).getVReg()).weight;
156 if (SpillCost == 0.0)
157 SpillCost = std::numeric_limits<PBQP::PBQPNum>::min();
158 PBQPRAGraph::RawVector NodeCosts(G.getNodeCosts(NId));
159 NodeCosts[PBQP::RegAlloc::getSpillOptionIdx()] = SpillCost;
160 G.setNodeCosts(NId, std::move(NodeCosts));
165 /// @brief Add interference edges between overlapping vregs.
166 class Interference : public PBQPRAConstraint {
169 // Holds (Interval, CurrentSegmentID, and NodeId). The first two are required
170 // for the fast interference graph construction algorithm. The last is there
171 // to save us from looking up node ids via the VRegToNode map in the graph
173 typedef std::tuple<LiveInterval*, size_t, PBQP::GraphBase::NodeId>
176 static SlotIndex getStartPoint(const IntervalInfo &I) {
177 return std::get<0>(I)->segments[std::get<1>(I)].start;
180 static SlotIndex getEndPoint(const IntervalInfo &I) {
181 return std::get<0>(I)->segments[std::get<1>(I)].end;
184 static PBQP::GraphBase::NodeId getNodeId(const IntervalInfo &I) {
185 return std::get<2>(I);
188 static bool lowestStartPoint(const IntervalInfo &I1,
189 const IntervalInfo &I2) {
190 // Condition reversed because priority queue has the *highest* element at
191 // the front, rather than the lowest.
192 return getStartPoint(I1) > getStartPoint(I2);
195 static bool lowestEndPoint(const IntervalInfo &I1,
196 const IntervalInfo &I2) {
197 SlotIndex E1 = getEndPoint(I1);
198 SlotIndex E2 = getEndPoint(I2);
206 // If two intervals end at the same point, we need a way to break the tie or
207 // the set will assume they're actually equal and refuse to insert a
208 // "duplicate". Just compare the vregs - fast and guaranteed unique.
209 return std::get<0>(I1)->reg < std::get<0>(I2)->reg;
212 static bool isAtLastSegment(const IntervalInfo &I) {
213 return std::get<1>(I) == std::get<0>(I)->size() - 1;
216 static IntervalInfo nextSegment(const IntervalInfo &I) {
217 return std::make_tuple(std::get<0>(I), std::get<1>(I) + 1, std::get<2>(I));
222 void apply(PBQPRAGraph &G) override {
223 // The following is loosely based on the linear scan algorithm introduced in
224 // "Linear Scan Register Allocation" by Poletto and Sarkar. This version
225 // isn't linear, because the size of the active set isn't bound by the
226 // number of registers, but rather the size of the largest clique in the
227 // graph. Still, we expect this to be better than N^2.
228 LiveIntervals &LIS = G.getMetadata().LIS;
229 const TargetRegisterInfo &TRI =
230 *G.getMetadata().MF.getTarget().getSubtargetImpl()->getRegisterInfo();
232 typedef std::set<IntervalInfo, decltype(&lowestEndPoint)> IntervalSet;
233 typedef std::priority_queue<IntervalInfo, std::vector<IntervalInfo>,
234 decltype(&lowestStartPoint)> IntervalQueue;
235 IntervalSet Active(lowestEndPoint);
236 IntervalQueue Inactive(lowestStartPoint);
238 // Start by building the inactive set.
239 for (auto NId : G.nodeIds()) {
240 unsigned VReg = G.getNodeMetadata(NId).getVReg();
241 LiveInterval &LI = LIS.getInterval(VReg);
242 assert(!LI.empty() && "PBQP graph contains node for empty interval");
243 Inactive.push(std::make_tuple(&LI, 0, NId));
246 while (!Inactive.empty()) {
247 // Tentatively grab the "next" interval - this choice may be overriden
249 IntervalInfo Cur = Inactive.top();
251 // Retire any active intervals that end before Cur starts.
252 IntervalSet::iterator RetireItr = Active.begin();
253 while (RetireItr != Active.end() &&
254 (getEndPoint(*RetireItr) <= getStartPoint(Cur))) {
255 // If this interval has subsequent segments, add the next one to the
257 if (!isAtLastSegment(*RetireItr))
258 Inactive.push(nextSegment(*RetireItr));
262 Active.erase(Active.begin(), RetireItr);
264 // One of the newly retired segments may actually start before the
265 // Cur segment, so re-grab the front of the inactive list.
266 Cur = Inactive.top();
269 // At this point we know that Cur overlaps all active intervals. Add the
270 // interference edges.
271 PBQP::GraphBase::NodeId NId = getNodeId(Cur);
272 for (const auto &A : Active) {
273 PBQP::GraphBase::NodeId MId = getNodeId(A);
275 // Check that we haven't already added this edge
276 // FIXME: findEdge is expensive in the worst case (O(max_clique(G))).
277 // It might be better to replace this with a local bit-matrix.
278 if (G.findEdge(NId, MId) != PBQP::GraphBase::invalidEdgeId())
281 // This is a new edge - add it to the graph.
282 const auto &NOpts = G.getNodeMetadata(NId).getOptionRegs();
283 const auto &MOpts = G.getNodeMetadata(MId).getOptionRegs();
284 G.addEdge(NId, MId, createInterferenceMatrix(TRI, NOpts, MOpts));
287 // Finally, add Cur to the Active set.
294 PBQPRAGraph::RawMatrix createInterferenceMatrix(
295 const TargetRegisterInfo &TRI,
296 const PBQPRAGraph::NodeMetadata::OptionToRegMap &NOpts,
297 const PBQPRAGraph::NodeMetadata::OptionToRegMap &MOpts) {
298 PBQPRAGraph::RawMatrix M(NOpts.size() + 1, MOpts.size() + 1, 0);
299 for (unsigned I = 0; I != NOpts.size(); ++I) {
300 unsigned PRegN = NOpts[I];
301 for (unsigned J = 0; J != MOpts.size(); ++J) {
302 unsigned PRegM = MOpts[J];
303 if (TRI.regsOverlap(PRegN, PRegM))
304 M[I + 1][J + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
313 class Coalescing : public PBQPRAConstraint {
315 void apply(PBQPRAGraph &G) override {
316 MachineFunction &MF = G.getMetadata().MF;
317 MachineBlockFrequencyInfo &MBFI = G.getMetadata().MBFI;
318 CoalescerPair CP(*MF.getTarget().getSubtargetImpl()->getRegisterInfo());
320 // Scan the machine function and add a coalescing cost whenever CoalescerPair
322 for (const auto &MBB : MF) {
323 for (const auto &MI : MBB) {
325 // Skip not-coalescable or already coalesced copies.
326 if (!CP.setRegisters(&MI) || CP.getSrcReg() == CP.getDstReg())
329 unsigned DstReg = CP.getDstReg();
330 unsigned SrcReg = CP.getSrcReg();
332 const float CopyFactor = 0.5; // Cost of copy relative to load. Current
333 // value plucked randomly out of the air.
335 PBQP::PBQPNum CBenefit =
336 CopyFactor * LiveIntervals::getSpillWeight(false, true, &MBFI, &MI);
339 if (!MF.getRegInfo().isAllocatable(DstReg))
342 PBQPRAGraph::NodeId NId = G.getMetadata().getNodeIdForVReg(SrcReg);
344 const PBQPRAGraph::NodeMetadata::OptionToRegMap &Allowed =
345 G.getNodeMetadata(NId).getOptionRegs();
347 unsigned PRegOpt = 0;
348 while (PRegOpt < Allowed.size() && Allowed[PRegOpt] != DstReg)
351 if (PRegOpt < Allowed.size()) {
352 PBQPRAGraph::RawVector NewCosts(G.getNodeCosts(NId));
353 NewCosts[PRegOpt + 1] += CBenefit;
354 G.setNodeCosts(NId, std::move(NewCosts));
357 PBQPRAGraph::NodeId N1Id = G.getMetadata().getNodeIdForVReg(DstReg);
358 PBQPRAGraph::NodeId N2Id = G.getMetadata().getNodeIdForVReg(SrcReg);
359 const PBQPRAGraph::NodeMetadata::OptionToRegMap *Allowed1 =
360 &G.getNodeMetadata(N1Id).getOptionRegs();
361 const PBQPRAGraph::NodeMetadata::OptionToRegMap *Allowed2 =
362 &G.getNodeMetadata(N2Id).getOptionRegs();
364 PBQPRAGraph::EdgeId EId = G.findEdge(N1Id, N2Id);
365 if (EId == G.invalidEdgeId()) {
366 PBQPRAGraph::RawMatrix Costs(Allowed1->size() + 1,
367 Allowed2->size() + 1, 0);
368 addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
369 G.addEdge(N1Id, N2Id, std::move(Costs));
371 if (G.getEdgeNode1Id(EId) == N2Id) {
372 std::swap(N1Id, N2Id);
373 std::swap(Allowed1, Allowed2);
375 PBQPRAGraph::RawMatrix Costs(G.getEdgeCosts(EId));
376 addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
377 G.setEdgeCosts(EId, std::move(Costs));
386 void addVirtRegCoalesce(
387 PBQPRAGraph::RawMatrix &CostMat,
388 const PBQPRAGraph::NodeMetadata::OptionToRegMap &Allowed1,
389 const PBQPRAGraph::NodeMetadata::OptionToRegMap &Allowed2,
390 PBQP::PBQPNum Benefit) {
391 assert(CostMat.getRows() == Allowed1.size() + 1 && "Size mismatch.");
392 assert(CostMat.getCols() == Allowed2.size() + 1 && "Size mismatch.");
393 for (unsigned I = 0; I != Allowed1.size(); ++I) {
394 unsigned PReg1 = Allowed1[I];
395 for (unsigned J = 0; J != Allowed2.size(); ++J) {
396 unsigned PReg2 = Allowed2[J];
398 CostMat[I + 1][J + 1] += -Benefit;
405 } // End anonymous namespace.
407 // Out-of-line destructor/anchor for PBQPRAConstraint.
408 PBQPRAConstraint::~PBQPRAConstraint() {}
409 void PBQPRAConstraint::anchor() {}
410 void PBQPRAConstraintList::anchor() {}
412 void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
413 au.setPreservesCFG();
414 au.addRequired<AliasAnalysis>();
415 au.addPreserved<AliasAnalysis>();
416 au.addRequired<SlotIndexes>();
417 au.addPreserved<SlotIndexes>();
418 au.addRequired<LiveIntervals>();
419 au.addPreserved<LiveIntervals>();
420 //au.addRequiredID(SplitCriticalEdgesID);
422 au.addRequiredID(*customPassID);
423 au.addRequired<LiveStacks>();
424 au.addPreserved<LiveStacks>();
425 au.addRequired<MachineBlockFrequencyInfo>();
426 au.addPreserved<MachineBlockFrequencyInfo>();
427 au.addRequired<MachineLoopInfo>();
428 au.addPreserved<MachineLoopInfo>();
429 au.addRequired<MachineDominatorTree>();
430 au.addPreserved<MachineDominatorTree>();
431 au.addRequired<VirtRegMap>();
432 au.addPreserved<VirtRegMap>();
433 MachineFunctionPass::getAnalysisUsage(au);
436 void RegAllocPBQP::findVRegIntervalsToAlloc(const MachineFunction &MF,
437 LiveIntervals &LIS) {
438 const MachineRegisterInfo &MRI = MF.getRegInfo();
440 // Iterate over all live ranges.
441 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
442 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
443 if (MRI.reg_nodbg_empty(Reg))
445 LiveInterval &LI = LIS.getInterval(Reg);
447 // If this live interval is non-empty we will use pbqp to allocate it.
448 // Empty intervals we allocate in a simple post-processing stage in
451 VRegsToAlloc.insert(LI.reg);
453 EmptyIntervalVRegs.insert(LI.reg);
458 void RegAllocPBQP::initializeGraph(PBQPRAGraph &G) {
459 MachineFunction &MF = G.getMetadata().MF;
461 LiveIntervals &LIS = G.getMetadata().LIS;
462 const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
463 const TargetRegisterInfo &TRI =
464 *G.getMetadata().MF.getTarget().getSubtargetImpl()->getRegisterInfo();
466 for (auto VReg : VRegsToAlloc) {
467 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
468 LiveInterval &VRegLI = LIS.getInterval(VReg);
470 // Record any overlaps with regmask operands.
471 BitVector RegMaskOverlaps;
472 LIS.checkRegMaskInterference(VRegLI, RegMaskOverlaps);
474 // Compute an initial allowed set for the current vreg.
475 std::vector<unsigned> VRegAllowed;
476 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF);
477 for (unsigned I = 0; I != RawPRegOrder.size(); ++I) {
478 unsigned PReg = RawPRegOrder[I];
479 if (MRI.isReserved(PReg))
482 // vregLI crosses a regmask operand that clobbers preg.
483 if (!RegMaskOverlaps.empty() && !RegMaskOverlaps.test(PReg))
486 // vregLI overlaps fixed regunit interference.
487 bool Interference = false;
488 for (MCRegUnitIterator Units(PReg, &TRI); Units.isValid(); ++Units) {
489 if (VRegLI.overlaps(LIS.getRegUnit(*Units))) {
497 // preg is usable for this virtual register.
498 VRegAllowed.push_back(PReg);
501 PBQPRAGraph::RawVector NodeCosts(VRegAllowed.size() + 1, 0);
502 PBQPRAGraph::NodeId NId = G.addNode(std::move(NodeCosts));
503 G.getNodeMetadata(NId).setVReg(VReg);
504 G.getNodeMetadata(NId).setOptionRegs(std::move(VRegAllowed));
505 G.getMetadata().setNodeIdForVReg(VReg, NId);
509 bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAGraph &G,
510 const PBQP::Solution &Solution,
512 Spiller &VRegSpiller) {
513 MachineFunction &MF = G.getMetadata().MF;
514 LiveIntervals &LIS = G.getMetadata().LIS;
515 const TargetRegisterInfo &TRI =
516 *MF.getTarget().getSubtargetImpl()->getRegisterInfo();
519 // Set to true if we have any spills
520 bool AnotherRoundNeeded = false;
522 // Clear the existing allocation.
525 // Iterate over the nodes mapping the PBQP solution to a register
527 for (auto NId : G.nodeIds()) {
528 unsigned VReg = G.getNodeMetadata(NId).getVReg();
529 unsigned AllocOption = Solution.getSelection(NId);
531 if (AllocOption != PBQP::RegAlloc::getSpillOptionIdx()) {
532 unsigned PReg = G.getNodeMetadata(NId).getOptionRegs()[AllocOption - 1];
533 DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> "
534 << TRI.getName(PReg) << "\n");
535 assert(PReg != 0 && "Invalid preg selected.");
536 VRM.assignVirt2Phys(VReg, PReg);
538 VRegsToAlloc.erase(VReg);
539 SmallVector<unsigned, 8> NewSpills;
540 LiveRangeEdit LRE(&LIS.getInterval(VReg), NewSpills, MF, LIS, &VRM);
541 VRegSpiller.spill(LRE);
543 DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> SPILLED (Cost: "
544 << LRE.getParent().weight << ", New vregs: ");
546 // Copy any newly inserted live intervals into the list of regs to
548 for (LiveRangeEdit::iterator I = LRE.begin(), E = LRE.end();
550 LiveInterval &LI = LIS.getInterval(*I);
551 assert(!LI.empty() && "Empty spill range.");
552 DEBUG(dbgs() << PrintReg(LI.reg, &TRI) << " ");
553 VRegsToAlloc.insert(LI.reg);
556 DEBUG(dbgs() << ")\n");
558 // We need another round if spill intervals were added.
559 AnotherRoundNeeded |= !LRE.empty();
563 return !AnotherRoundNeeded;
567 void RegAllocPBQP::finalizeAlloc(MachineFunction &MF,
569 VirtRegMap &VRM) const {
570 MachineRegisterInfo &MRI = MF.getRegInfo();
572 // First allocate registers for the empty intervals.
573 for (RegSet::const_iterator
574 I = EmptyIntervalVRegs.begin(), E = EmptyIntervalVRegs.end();
576 LiveInterval &LI = LIS.getInterval(*I);
578 unsigned PReg = MRI.getSimpleHint(LI.reg);
581 const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg);
582 PReg = RC.getRawAllocationOrder(MF).front();
585 VRM.assignVirt2Phys(LI.reg, PReg);
589 bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
590 LiveIntervals &LIS = getAnalysis<LiveIntervals>();
591 MachineBlockFrequencyInfo &MBFI =
592 getAnalysis<MachineBlockFrequencyInfo>();
594 calculateSpillWeightsAndHints(LIS, MF, getAnalysis<MachineLoopInfo>(), MBFI);
596 VirtRegMap &VRM = getAnalysis<VirtRegMap>();
598 std::unique_ptr<Spiller> VRegSpiller(createInlineSpiller(*this, MF, VRM));
600 MF.getRegInfo().freezeReservedRegs(MF);
602 DEBUG(dbgs() << "PBQP Register Allocating for " << MF.getName() << "\n");
604 // Allocator main loop:
606 // * Map current regalloc problem to a PBQP problem
607 // * Solve the PBQP problem
608 // * Map the solution back to a register allocation
609 // * Spill if necessary
611 // This process is continued till no more spills are generated.
613 // Find the vreg intervals in need of allocation.
614 findVRegIntervalsToAlloc(MF, LIS);
617 const Function &F = *MF.getFunction();
618 std::string FullyQualifiedName =
619 F.getParent()->getModuleIdentifier() + "." + F.getName().str();
622 // If there are non-empty intervals allocate them using pbqp.
623 if (!VRegsToAlloc.empty()) {
625 const TargetSubtargetInfo &Subtarget = *MF.getTarget().getSubtargetImpl();
626 std::unique_ptr<PBQPRAConstraintList> ConstraintsRoot =
627 llvm::make_unique<PBQPRAConstraintList>();
628 ConstraintsRoot->addConstraint(llvm::make_unique<SpillCosts>());
629 ConstraintsRoot->addConstraint(llvm::make_unique<Interference>());
631 ConstraintsRoot->addConstraint(llvm::make_unique<Coalescing>());
632 ConstraintsRoot->addConstraint(Subtarget.getCustomPBQPConstraints());
634 bool PBQPAllocComplete = false;
637 while (!PBQPAllocComplete) {
638 DEBUG(dbgs() << " PBQP Regalloc round " << Round << ":\n");
640 PBQPRAGraph G(PBQPRAGraph::GraphMetadata(MF, LIS, MBFI));
642 ConstraintsRoot->apply(G);
645 if (PBQPDumpGraphs) {
646 std::ostringstream RS;
648 std::string GraphFileName = FullyQualifiedName + "." + RS.str() +
651 raw_fd_ostream OS(GraphFileName, EC, sys::fs::F_Text);
652 DEBUG(dbgs() << "Dumping graph for round " << Round << " to \""
653 << GraphFileName << "\"\n");
658 PBQP::Solution Solution = PBQP::RegAlloc::solve(G);
659 PBQPAllocComplete = mapPBQPToRegAlloc(G, Solution, VRM, *VRegSpiller);
664 // Finalise allocation, allocate empty ranges.
665 finalizeAlloc(MF, LIS, VRM);
666 VRegsToAlloc.clear();
667 EmptyIntervalVRegs.clear();
669 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << VRM << "\n");
674 FunctionPass *llvm::createPBQPRegisterAllocator(char *customPassID) {
675 return new RegAllocPBQP(customPassID);
678 FunctionPass* llvm::createDefaultPBQPRegisterAllocator() {
679 return createPBQPRegisterAllocator();