1 //===-- RegAllocLocal.cpp - A BasicBlock generic register allocator -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This register allocator allocates registers to a basic block at a time,
11 // attempting to keep values in registers and reusing registers as appropriate.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "llvm/BasicBlock.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/IndexedMap.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
38 STATISTIC(NumStores, "Number of stores added");
39 STATISTIC(NumLoads , "Number of loads added");
40 STATISTIC(NumCopies, "Number of copies coalesced");
42 static RegisterRegAlloc
43 localRegAlloc("local", "local register allocator",
44 createLocalRegisterAllocator);
47 class RALocal : public MachineFunctionPass {
50 RALocal() : MachineFunctionPass(&ID), StackSlotForVirtReg(-1) {}
52 const TargetMachine *TM;
54 MachineRegisterInfo *MRI;
55 const TargetRegisterInfo *TRI;
56 const TargetInstrInfo *TII;
58 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
59 // values are spilled.
60 IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
62 // Virt2PhysRegMap - This map contains entries for each virtual register
63 // that is currently available in a physical register.
64 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysRegMap;
66 unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) {
67 return Virt2PhysRegMap[VirtReg];
70 // PhysRegsUsed - This array is effectively a map, containing entries for
71 // each physical register that currently has a value (ie, it is in
72 // Virt2PhysRegMap). The value mapped to is the virtual register
73 // corresponding to the physical register (the inverse of the
74 // Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned
75 // because it is used by a future instruction, and to -2 if it is not
76 // allocatable. If the entry for a physical register is -1, then the
77 // physical register is "not in the map".
79 std::vector<int> PhysRegsUsed;
81 // PhysRegsUseOrder - This contains a list of the physical registers that
82 // currently have a virtual register value in them. This list provides an
83 // ordering of registers, imposing a reallocation order. This list is only
84 // used if all registers are allocated and we have to spill one, in which
85 // case we spill the least recently used register. Entries at the front of
86 // the list are the least recently used registers, entries at the back are
87 // the most recently used.
89 std::vector<unsigned> PhysRegsUseOrder;
91 // Virt2LastUseMap - This maps each virtual register to its last use
92 // (MachineInstr*, operand index pair).
93 IndexedMap<std::pair<MachineInstr*, unsigned>, VirtReg2IndexFunctor>
96 std::pair<MachineInstr*,unsigned>& getVirtRegLastUse(unsigned Reg) {
97 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
98 return Virt2LastUseMap[Reg];
101 // VirtRegModified - This bitset contains information about which virtual
102 // registers need to be spilled back to memory when their registers are
103 // scavenged. If a virtual register has simply been rematerialized, there
104 // is no reason to spill it to memory when we need the register back.
106 BitVector VirtRegModified;
108 // UsedInMultipleBlocks - Tracks whether a particular register is used in
109 // more than one block.
110 BitVector UsedInMultipleBlocks;
112 void markVirtRegModified(unsigned Reg, bool Val = true) {
113 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
114 Reg -= TargetRegisterInfo::FirstVirtualRegister;
116 VirtRegModified.set(Reg);
118 VirtRegModified.reset(Reg);
121 bool isVirtRegModified(unsigned Reg) const {
122 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
123 assert(Reg - TargetRegisterInfo::FirstVirtualRegister <
124 VirtRegModified.size() && "Illegal virtual register!");
125 return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister];
128 void AddToPhysRegsUseOrder(unsigned Reg) {
129 std::vector<unsigned>::iterator It =
130 std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), Reg);
131 if (It != PhysRegsUseOrder.end())
132 PhysRegsUseOrder.erase(It);
133 PhysRegsUseOrder.push_back(Reg);
136 void MarkPhysRegRecentlyUsed(unsigned Reg) {
137 if (PhysRegsUseOrder.empty() ||
138 PhysRegsUseOrder.back() == Reg) return; // Already most recently used
140 for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i) {
141 unsigned RegMatch = PhysRegsUseOrder[i-1]; // remove from middle
142 if (!areRegsEqual(Reg, RegMatch)) continue;
144 PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1);
145 // Add it to the end of the list
146 PhysRegsUseOrder.push_back(RegMatch);
148 return; // Found an exact match, exit early
153 virtual const char *getPassName() const {
154 return "Local Register Allocator";
157 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
158 AU.setPreservesCFG();
159 AU.addRequiredID(PHIEliminationID);
160 AU.addRequiredID(TwoAddressInstructionPassID);
161 MachineFunctionPass::getAnalysisUsage(AU);
165 /// runOnMachineFunction - Register allocate the whole function
166 bool runOnMachineFunction(MachineFunction &Fn);
168 /// AllocateBasicBlock - Register allocate the specified basic block.
169 void AllocateBasicBlock(MachineBasicBlock &MBB);
172 /// areRegsEqual - This method returns true if the specified registers are
173 /// related to each other. To do this, it checks to see if they are equal
174 /// or if the first register is in the alias set of the second register.
176 bool areRegsEqual(unsigned R1, unsigned R2) const {
177 if (R1 == R2) return true;
178 for (const unsigned *AliasSet = TRI->getAliasSet(R2);
179 *AliasSet; ++AliasSet) {
180 if (*AliasSet == R1) return true;
185 /// getStackSpaceFor - This returns the frame index of the specified virtual
186 /// register on the stack, allocating space if necessary.
187 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
189 /// removePhysReg - This method marks the specified physical register as no
190 /// longer being in use.
192 void removePhysReg(unsigned PhysReg);
194 void storeVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
195 unsigned VirtReg, unsigned PhysReg, bool isKill);
197 /// spillVirtReg - This method spills the value specified by PhysReg into
198 /// the virtual register slot specified by VirtReg. It then updates the RA
199 /// data structures to indicate the fact that PhysReg is now available.
201 void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
202 unsigned VirtReg, unsigned PhysReg);
204 /// spillPhysReg - This method spills the specified physical register into
205 /// the virtual register slot associated with it. If OnlyVirtRegs is set to
206 /// true, then the request is ignored if the physical register does not
207 /// contain a virtual register.
209 void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
210 unsigned PhysReg, bool OnlyVirtRegs = false);
212 /// assignVirtToPhysReg - This method updates local state so that we know
213 /// that PhysReg is the proper container for VirtReg now. The physical
214 /// register must not be used for anything else when this is called.
216 void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg);
218 /// isPhysRegAvailable - Return true if the specified physical register is
219 /// free and available for use. This also includes checking to see if
220 /// aliased registers are all free...
222 bool isPhysRegAvailable(unsigned PhysReg) const;
224 /// getFreeReg - Look to see if there is a free register available in the
225 /// specified register class. If not, return 0.
227 unsigned getFreeReg(const TargetRegisterClass *RC);
229 /// getReg - Find a physical register to hold the specified virtual
230 /// register. If all compatible physical registers are used, this method
231 /// spills the last used virtual register to the stack, and uses that
232 /// register. If NoFree is true, that means the caller knows there isn't
233 /// a free register, do not call getFreeReg().
234 unsigned getReg(MachineBasicBlock &MBB, MachineInstr *MI,
235 unsigned VirtReg, bool NoFree = false);
237 /// reloadVirtReg - This method transforms the specified virtual
238 /// register use to refer to a physical register. This method may do this
239 /// in one of several ways: if the register is available in a physical
240 /// register already, it uses that physical register. If the value is not
241 /// in a physical register, and if there are physical registers available,
242 /// it loads it into a register: PhysReg if that is an available physical
243 /// register, otherwise any physical register of the right class.
244 /// If register pressure is high, and it is possible, it tries to fold the
245 /// load of the virtual register into the instruction itself. It avoids
246 /// doing this if register pressure is low to improve the chance that
247 /// subsequent instructions can use the reloaded value. This method
248 /// returns the modified instruction.
250 MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
251 unsigned OpNum, SmallSet<unsigned, 4> &RRegs,
254 /// ComputeLocalLiveness - Computes liveness of registers within a basic
255 /// block, setting the killed/dead flags as appropriate.
256 void ComputeLocalLiveness(MachineBasicBlock& MBB);
258 void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
261 char RALocal::ID = 0;
264 /// getStackSpaceFor - This allocates space for the specified virtual register
265 /// to be held on the stack.
266 int RALocal::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
267 // Find the location Reg would belong...
268 int SS = StackSlotForVirtReg[VirtReg];
270 return SS; // Already has space allocated?
272 // Allocate a new stack object for this spill location...
273 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
277 StackSlotForVirtReg[VirtReg] = FrameIdx;
282 /// removePhysReg - This method marks the specified physical register as no
283 /// longer being in use.
285 void RALocal::removePhysReg(unsigned PhysReg) {
286 PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used
288 std::vector<unsigned>::iterator It =
289 std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), PhysReg);
290 if (It != PhysRegsUseOrder.end())
291 PhysRegsUseOrder.erase(It);
294 /// storeVirtReg - Store a virtual register to its assigned stack slot.
295 void RALocal::storeVirtReg(MachineBasicBlock &MBB,
296 MachineBasicBlock::iterator I,
297 unsigned VirtReg, unsigned PhysReg,
299 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
300 int FrameIndex = getStackSpaceFor(VirtReg, RC);
301 DEBUG(dbgs() << " to stack slot #" << FrameIndex);
302 TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC, TRI);
303 ++NumStores; // Update statistics
306 /// spillVirtReg - This method spills the value specified by PhysReg into the
307 /// virtual register slot specified by VirtReg. It then updates the RA data
308 /// structures to indicate the fact that PhysReg is now available.
310 void RALocal::spillVirtReg(MachineBasicBlock &MBB,
311 MachineBasicBlock::iterator I,
312 unsigned VirtReg, unsigned PhysReg) {
313 assert(VirtReg && "Spilling a physical register is illegal!"
314 " Must not have appropriate kill for the register or use exists beyond"
315 " the intended one.");
316 DEBUG(dbgs() << " Spilling register " << TRI->getName(PhysReg)
317 << " containing %reg" << VirtReg);
319 if (!isVirtRegModified(VirtReg)) {
320 DEBUG(dbgs() << " which has not been modified, so no store necessary!");
321 std::pair<MachineInstr*, unsigned> &LastUse = getVirtRegLastUse(VirtReg);
323 LastUse.first->getOperand(LastUse.second).setIsKill();
325 // Otherwise, there is a virtual register corresponding to this physical
326 // register. We only need to spill it into its stack slot if it has been
328 // If the instruction reads the register that's spilled, (e.g. this can
329 // happen if it is a move to a physical register), then the spill
330 // instruction is not a kill.
331 bool isKill = !(I != MBB.end() && I->readsRegister(PhysReg));
332 storeVirtReg(MBB, I, VirtReg, PhysReg, isKill);
335 getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available
337 DEBUG(dbgs() << '\n');
338 removePhysReg(PhysReg);
342 /// spillPhysReg - This method spills the specified physical register into the
343 /// virtual register slot associated with it. If OnlyVirtRegs is set to true,
344 /// then the request is ignored if the physical register does not contain a
345 /// virtual register.
347 void RALocal::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
348 unsigned PhysReg, bool OnlyVirtRegs) {
349 if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used!
350 assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
351 if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs)
352 spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg);
356 // If the selected register aliases any other registers, we must make
357 // sure that one of the aliases isn't alive.
358 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
359 *AliasSet; ++AliasSet) {
360 if (PhysRegsUsed[*AliasSet] == -1 || // Spill aliased register.
361 PhysRegsUsed[*AliasSet] == -2) // If allocatable.
364 if (PhysRegsUsed[*AliasSet])
365 spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
370 /// assignVirtToPhysReg - This method updates local state so that we know
371 /// that PhysReg is the proper container for VirtReg now. The physical
372 /// register must not be used for anything else when this is called.
374 void RALocal::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
375 assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!");
376 // Update information to note the fact that this register was just used, and
378 PhysRegsUsed[PhysReg] = VirtReg;
379 getVirt2PhysRegMapSlot(VirtReg) = PhysReg;
380 AddToPhysRegsUseOrder(PhysReg); // New use of PhysReg
384 /// isPhysRegAvailable - Return true if the specified physical register is free
385 /// and available for use. This also includes checking to see if aliased
386 /// registers are all free...
388 bool RALocal::isPhysRegAvailable(unsigned PhysReg) const {
389 if (PhysRegsUsed[PhysReg] != -1) return false;
391 // If the selected register aliases any other allocated registers, it is
393 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
394 *AliasSet; ++AliasSet)
395 if (PhysRegsUsed[*AliasSet] >= 0) // Aliased register in use?
396 return false; // Can't use this reg then.
401 /// getFreeReg - Look to see if there is a free register available in the
402 /// specified register class. If not, return 0.
404 unsigned RALocal::getFreeReg(const TargetRegisterClass *RC) {
405 // Get iterators defining the range of registers that are valid to allocate in
406 // this class, which also specifies the preferred allocation order.
407 TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
408 TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
410 for (; RI != RE; ++RI)
411 if (isPhysRegAvailable(*RI)) { // Is reg unused?
412 assert(*RI != 0 && "Cannot use register!");
413 return *RI; // Found an unused register!
419 /// getReg - Find a physical register to hold the specified virtual
420 /// register. If all compatible physical registers are used, this method spills
421 /// the last used virtual register to the stack, and uses that register.
423 unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I,
424 unsigned VirtReg, bool NoFree) {
425 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
427 // First check to see if we have a free register of the requested type...
428 unsigned PhysReg = NoFree ? 0 : getFreeReg(RC);
431 // Assign the register.
432 assignVirtToPhysReg(VirtReg, PhysReg);
436 // If we didn't find an unused register, scavenge one now!
437 assert(!PhysRegsUseOrder.empty() && "No allocated registers??");
439 // Loop over all of the preallocated registers from the least recently used
440 // to the most recently used. When we find one that is capable of holding
441 // our register, use it.
442 for (unsigned i = 0; PhysReg == 0; ++i) {
443 assert(i != PhysRegsUseOrder.size() &&
444 "Couldn't find a register of the appropriate class!");
446 unsigned R = PhysRegsUseOrder[i];
448 // We can only use this register if it holds a virtual register (ie, it
449 // can be spilled). Do not use it if it is an explicitly allocated
450 // physical register!
451 assert(PhysRegsUsed[R] != -1 &&
452 "PhysReg in PhysRegsUseOrder, but is not allocated?");
453 if (PhysRegsUsed[R] && PhysRegsUsed[R] != -2) {
454 // If the current register is compatible, use it.
455 if (RC->contains(R)) {
460 // If one of the registers aliased to the current register is
461 // compatible, use it.
462 for (const unsigned *AliasIt = TRI->getAliasSet(R);
463 *AliasIt; ++AliasIt) {
464 if (!RC->contains(*AliasIt)) continue;
466 // If this is pinned down for some reason, don't use it. For
467 // example, if CL is pinned, and we run across CH, don't use
468 // CH as justification for using scavenging ECX (which will
470 if (PhysRegsUsed[*AliasIt] == 0) continue;
472 // Make sure the register is allocatable. Don't allocate SIL on
474 if (PhysRegsUsed[*AliasIt] == -2) continue;
476 PhysReg = *AliasIt; // Take an aliased register
482 assert(PhysReg && "Physical register not assigned!?!?");
484 // At this point PhysRegsUseOrder[i] is the least recently used register of
485 // compatible register class. Spill it to memory and reap its remains.
486 spillPhysReg(MBB, I, PhysReg);
488 // Now that we know which register we need to assign this to, do it now!
489 assignVirtToPhysReg(VirtReg, PhysReg);
494 /// reloadVirtReg - This method transforms the specified virtual
495 /// register use to refer to a physical register. This method may do this in
496 /// one of several ways: if the register is available in a physical register
497 /// already, it uses that physical register. If the value is not in a physical
498 /// register, and if there are physical registers available, it loads it into a
499 /// register: PhysReg if that is an available physical register, otherwise any
500 /// register. If register pressure is high, and it is possible, it tries to
501 /// fold the load of the virtual register into the instruction itself. It
502 /// avoids doing this if register pressure is low to improve the chance that
503 /// subsequent instructions can use the reloaded value. This method returns
504 /// the modified instruction.
506 MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
508 SmallSet<unsigned, 4> &ReloadedRegs,
510 unsigned VirtReg = MI->getOperand(OpNum).getReg();
511 unsigned SubIdx = MI->getOperand(OpNum).getSubReg();
513 // If the virtual register is already available, just update the instruction
515 if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
517 PR = TRI->getSubReg(PR, SubIdx);
518 MI->getOperand(OpNum).setSubReg(0);
520 MI->getOperand(OpNum).setReg(PR); // Assign the input register
521 if (!MI->isDebugValue()) {
522 // Do not do these for DBG_VALUE as they can affect codegen.
523 MarkPhysRegRecentlyUsed(PR); // Already have this value available!
524 getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
529 // Otherwise, we need to fold it into the current instruction, or reload it.
530 // If we have registers available to hold the value, use them.
531 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
532 // If we already have a PhysReg (this happens when the instruction is a
533 // reg-to-reg copy with a PhysReg destination) use that.
534 if (!PhysReg || !TargetRegisterInfo::isPhysicalRegister(PhysReg) ||
535 !isPhysRegAvailable(PhysReg))
536 PhysReg = getFreeReg(RC);
537 int FrameIndex = getStackSpaceFor(VirtReg, RC);
539 if (PhysReg) { // Register is available, allocate it!
540 assignVirtToPhysReg(VirtReg, PhysReg);
541 } else { // No registers available.
542 // Force some poor hapless value out of the register file to
543 // make room for the new register, and reload it.
544 PhysReg = getReg(MBB, MI, VirtReg, true);
547 markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded
549 DEBUG(dbgs() << " Reloading %reg" << VirtReg << " into "
550 << TRI->getName(PhysReg) << "\n");
552 // Add move instruction(s)
553 TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC, TRI);
554 ++NumLoads; // Update statistics
556 MF->getRegInfo().setPhysRegUsed(PhysReg);
557 // Assign the input register.
559 MI->getOperand(OpNum).setSubReg(0);
560 MI->getOperand(OpNum).setReg(TRI->getSubReg(PhysReg, SubIdx));
562 MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
563 getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
565 if (!ReloadedRegs.insert(PhysReg)) {
567 raw_string_ostream Msg(msg);
568 Msg << "Ran out of registers during register allocation!";
569 if (MI->isInlineAsm()) {
570 Msg << "\nPlease check your inline asm statement for invalid "
574 report_fatal_error(Msg.str());
576 for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
577 *SubRegs; ++SubRegs) {
578 if (ReloadedRegs.insert(*SubRegs)) continue;
581 raw_string_ostream Msg(msg);
582 Msg << "Ran out of registers during register allocation!";
583 if (MI->isInlineAsm()) {
584 Msg << "\nPlease check your inline asm statement for invalid "
588 report_fatal_error(Msg.str());
594 /// isReadModWriteImplicitKill - True if this is an implicit kill for a
595 /// read/mod/write register, i.e. update partial register.
596 static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
597 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
598 MachineOperand &MO = MI->getOperand(i);
599 if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
600 MO.isDef() && !MO.isDead())
606 /// isReadModWriteImplicitDef - True if this is an implicit def for a
607 /// read/mod/write register, i.e. update partial register.
608 static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
609 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
610 MachineOperand &MO = MI->getOperand(i);
611 if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
612 !MO.isDef() && MO.isKill())
618 // precedes - Helper function to determine with MachineInstr A
619 // precedes MachineInstr B within the same MBB.
620 static bool precedes(MachineBasicBlock::iterator A,
621 MachineBasicBlock::iterator B) {
625 MachineBasicBlock::iterator I = A->getParent()->begin();
626 while (I != A->getParent()->end()) {
638 /// ComputeLocalLiveness - Computes liveness of registers within a basic
639 /// block, setting the killed/dead flags as appropriate.
640 void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) {
641 // Keep track of the most recently seen previous use or def of each reg,
642 // so that we can update them with dead/kill markers.
643 DenseMap<unsigned, std::pair<MachineInstr*, unsigned> > LastUseDef;
644 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
646 if (I->isDebugValue())
649 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
650 MachineOperand &MO = I->getOperand(i);
651 // Uses don't trigger any flags, but we need to save
652 // them for later. Also, we have to process these
653 // _before_ processing the defs, since an instr
654 // uses regs before it defs them.
655 if (!MO.isReg() || !MO.getReg() || !MO.isUse())
658 // Ignore helpful kill flags from earlier passes.
661 LastUseDef[MO.getReg()] = std::make_pair(I, i);
663 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) continue;
665 const unsigned *Aliases = TRI->getAliasSet(MO.getReg());
670 DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
671 alias = LastUseDef.find(*Aliases);
673 if (alias != LastUseDef.end() && alias->second.first != I)
674 LastUseDef[*Aliases] = std::make_pair(I, i);
680 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
681 MachineOperand &MO = I->getOperand(i);
682 // Defs others than 2-addr redefs _do_ trigger flag changes:
683 // - A def followed by a def is dead
684 // - A use followed by a def is a kill
685 if (!MO.isReg() || !MO.getReg() || !MO.isDef()) continue;
687 unsigned SubIdx = MO.getSubReg();
688 DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
689 last = LastUseDef.find(MO.getReg());
690 if (last != LastUseDef.end()) {
691 // Check if this is a two address instruction. If so, then
692 // the def does not kill the use.
693 if (last->second.first == I && I->isRegTiedToUseOperand(i))
696 MachineOperand &lastUD =
697 last->second.first->getOperand(last->second.second);
698 if (SubIdx && lastUD.getSubReg() != SubIdx)
699 // Partial re-def, the last def is not dead.
703 // %reg1024:5<def> = op %reg1024, 5
707 lastUD.setIsDead(true);
709 lastUD.setIsKill(true);
712 LastUseDef[MO.getReg()] = std::make_pair(I, i);
716 // Live-out (of the function) registers contain return values of the function,
717 // so we need to make sure they are alive at return time.
718 MachineBasicBlock::iterator Ret = MBB.getFirstTerminator();
719 bool BBEndsInReturn = (Ret != MBB.end() && Ret->getDesc().isReturn());
722 for (MachineRegisterInfo::liveout_iterator
723 I = MF->getRegInfo().liveout_begin(),
724 E = MF->getRegInfo().liveout_end(); I != E; ++I)
725 if (!Ret->readsRegister(*I)) {
726 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
727 LastUseDef[*I] = std::make_pair(Ret, Ret->getNumOperands()-1);
730 // Finally, loop over the final use/def of each reg
731 // in the block and determine if it is dead.
732 for (DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
733 I = LastUseDef.begin(), E = LastUseDef.end(); I != E; ++I) {
734 MachineInstr *MI = I->second.first;
735 unsigned idx = I->second.second;
736 MachineOperand &MO = MI->getOperand(idx);
738 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(MO.getReg());
740 // A crude approximation of "live-out" calculation
741 bool usedOutsideBlock = isPhysReg ? false :
742 UsedInMultipleBlocks.test(MO.getReg() -
743 TargetRegisterInfo::FirstVirtualRegister);
745 // If the machine BB ends in a return instruction, then the value isn't used
746 // outside of the BB.
747 if (!isPhysReg && (!usedOutsideBlock || BBEndsInReturn)) {
748 // DBG_VALUE complicates this: if the only refs of a register outside
749 // this block are DBG_VALUE, we can't keep the reg live just for that,
750 // as it will cause the reg to be spilled at the end of this block when
751 // it wouldn't have been otherwise. Nullify the DBG_VALUEs when that
753 bool UsedByDebugValueOnly = false;
754 for (MachineRegisterInfo::reg_iterator UI = MRI->reg_begin(MO.getReg()),
755 UE = MRI->reg_end(); UI != UE; ++UI) {
757 // - used in another block
758 // - used in the same block before it is defined (loop)
759 if (UI->getParent() == &MBB &&
760 !(MO.isDef() && UI.getOperand().isUse() && precedes(&*UI, MI)))
763 if (UI->isDebugValue()) {
764 UsedByDebugValueOnly = true;
768 // A non-DBG_VALUE use means we can leave DBG_VALUE uses alone.
769 UsedInMultipleBlocks.set(MO.getReg() -
770 TargetRegisterInfo::FirstVirtualRegister);
771 usedOutsideBlock = true;
772 UsedByDebugValueOnly = false;
776 if (UsedByDebugValueOnly)
777 for (MachineRegisterInfo::reg_iterator UI = MRI->reg_begin(MO.getReg()),
778 UE = MRI->reg_end(); UI != UE; ++UI)
779 if (UI->isDebugValue() &&
780 (UI->getParent() != &MBB ||
781 (MO.isDef() && precedes(&*UI, MI))))
782 UI.getOperand().setReg(0U);
785 // Physical registers and those that are not live-out of the block are
786 // killed/dead at their last use/def within this block.
787 if (isPhysReg || !usedOutsideBlock || BBEndsInReturn) {
789 // Don't mark uses that are tied to defs as kills.
790 if (!MI->isRegTiedToDefOperand(idx))
799 void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
800 // loop over each instruction
801 MachineBasicBlock::iterator MII = MBB.begin();
804 const BasicBlock *LBB = MBB.getBasicBlock();
806 dbgs() << "\nStarting RegAlloc of BB: " << LBB->getName();
809 // Add live-in registers as active.
810 for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
811 E = MBB.livein_end(); I != E; ++I) {
813 MF->getRegInfo().setPhysRegUsed(Reg);
814 PhysRegsUsed[Reg] = 0; // It is free and reserved now
815 AddToPhysRegsUseOrder(Reg);
816 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
817 *SubRegs; ++SubRegs) {
818 if (PhysRegsUsed[*SubRegs] == -2) continue;
820 AddToPhysRegsUseOrder(*SubRegs);
821 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
822 MF->getRegInfo().setPhysRegUsed(*SubRegs);
826 ComputeLocalLiveness(MBB);
828 // Otherwise, sequentially allocate each instruction in the MBB.
829 while (MII != MBB.end()) {
830 MachineInstr *MI = MII++;
831 const TargetInstrDesc &TID = MI->getDesc();
833 dbgs() << "\nStarting RegAlloc of: " << *MI;
834 dbgs() << " Regs have values: ";
835 for (unsigned i = 0; i != TRI->getNumRegs(); ++i)
836 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) {
837 if (PhysRegsUsed[i] && isVirtRegModified(PhysRegsUsed[i]))
839 dbgs() << "[" << TRI->getName(i)
840 << ",%reg" << PhysRegsUsed[i] << "] ";
845 // Determine whether this is a copy instruction. The cases where the
846 // source or destination are phys regs are handled specially.
847 unsigned SrcCopyReg, DstCopyReg, SrcCopySubReg, DstCopySubReg;
848 unsigned SrcCopyPhysReg = 0U;
849 bool isCopy = TII->isMoveInstr(*MI, SrcCopyReg, DstCopyReg,
850 SrcCopySubReg, DstCopySubReg) &&
851 SrcCopySubReg == DstCopySubReg;
852 if (isCopy && TargetRegisterInfo::isVirtualRegister(SrcCopyReg))
853 SrcCopyPhysReg = getVirt2PhysRegMapSlot(SrcCopyReg);
855 // Loop over the implicit uses, making sure that they are at the head of the
856 // use order list, so they don't get reallocated.
857 if (TID.ImplicitUses) {
858 for (const unsigned *ImplicitUses = TID.ImplicitUses;
859 *ImplicitUses; ++ImplicitUses)
860 MarkPhysRegRecentlyUsed(*ImplicitUses);
863 SmallVector<unsigned, 8> Kills;
864 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
865 MachineOperand &MO = MI->getOperand(i);
866 if (!MO.isReg() || !MO.isKill()) continue;
868 if (!MO.isImplicit())
869 Kills.push_back(MO.getReg());
870 else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
871 // These are extra physical register kills when a sub-register
872 // is defined (def of a sub-register is a read/mod/write of the
873 // larger registers). Ignore.
874 Kills.push_back(MO.getReg());
877 // If any physical regs are earlyclobber, spill any value they might
878 // have in them, then mark them unallocatable.
879 // If any virtual regs are earlyclobber, allocate them now (before
880 // freeing inputs that are killed).
881 if (MI->isInlineAsm()) {
882 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
883 MachineOperand &MO = MI->getOperand(i);
884 if (!MO.isReg() || !MO.isDef() || !MO.isEarlyClobber() ||
888 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
889 unsigned DestVirtReg = MO.getReg();
890 unsigned DestPhysReg;
892 // If DestVirtReg already has a value, use it.
893 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
894 DestPhysReg = getReg(MBB, MI, DestVirtReg);
895 MF->getRegInfo().setPhysRegUsed(DestPhysReg);
896 markVirtRegModified(DestVirtReg);
897 getVirtRegLastUse(DestVirtReg) =
898 std::make_pair((MachineInstr*)0, 0);
899 DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg)
900 << " to %reg" << DestVirtReg << "\n");
901 if (unsigned DestSubIdx = MO.getSubReg()) {
903 DestPhysReg = TRI->getSubReg(DestPhysReg, DestSubIdx);
905 MO.setReg(DestPhysReg); // Assign the earlyclobber register
907 unsigned Reg = MO.getReg();
908 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
909 // These are extra physical register defs when a sub-register
910 // is defined (def of a sub-register is a read/mod/write of the
911 // larger registers). Ignore.
912 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
914 MF->getRegInfo().setPhysRegUsed(Reg);
915 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
916 PhysRegsUsed[Reg] = 0; // It is free and reserved now
917 AddToPhysRegsUseOrder(Reg);
919 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
920 *SubRegs; ++SubRegs) {
921 if (PhysRegsUsed[*SubRegs] == -2) continue;
922 MF->getRegInfo().setPhysRegUsed(*SubRegs);
923 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
924 AddToPhysRegsUseOrder(*SubRegs);
930 // If a DBG_VALUE says something is located in a spilled register,
931 // change the DBG_VALUE to be undef, which prevents the register
932 // from being reloaded here. Doing that would change the generated
933 // code, unless another use immediately follows this instruction.
934 if (MI->isDebugValue() &&
935 MI->getNumOperands()==3 && MI->getOperand(0).isReg()) {
936 unsigned VirtReg = MI->getOperand(0).getReg();
937 if (VirtReg && TargetRegisterInfo::isVirtualRegister(VirtReg) &&
938 !getVirt2PhysRegMapSlot(VirtReg))
939 MI->getOperand(0).setReg(0U);
942 // Get the used operands into registers. This has the potential to spill
943 // incoming values if we are out of registers. Note that we completely
944 // ignore physical register uses here. We assume that if an explicit
945 // physical register is referenced by the instruction, that it is guaranteed
946 // to be live-in, or the input is badly hosed.
948 SmallSet<unsigned, 4> ReloadedRegs;
949 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
950 MachineOperand &MO = MI->getOperand(i);
951 // here we are looking for only used operands (never def&use)
952 if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
953 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
954 MI = reloadVirtReg(MBB, MI, i, ReloadedRegs,
955 isCopy ? DstCopyReg : 0);
958 // If this instruction is the last user of this register, kill the
959 // value, freeing the register being used, so it doesn't need to be
960 // spilled to memory.
962 for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
963 unsigned VirtReg = Kills[i];
964 unsigned PhysReg = VirtReg;
965 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
966 // If the virtual register was never materialized into a register, it
967 // might not be in the map, but it won't hurt to zero it out anyway.
968 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
969 PhysReg = PhysRegSlot;
971 } else if (PhysRegsUsed[PhysReg] == -2) {
972 // Unallocatable register dead, ignore.
975 assert((!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1) &&
976 "Silently clearing a virtual register?");
979 if (!PhysReg) continue;
981 DEBUG(dbgs() << " Last use of " << TRI->getName(PhysReg)
982 << "[%reg" << VirtReg <<"], removing it from live set\n");
983 removePhysReg(PhysReg);
984 for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
985 *SubRegs; ++SubRegs) {
986 if (PhysRegsUsed[*SubRegs] != -2) {
987 DEBUG(dbgs() << " Last use of "
988 << TRI->getName(*SubRegs) << "[%reg" << VirtReg
989 <<"], removing it from live set\n");
990 removePhysReg(*SubRegs);
995 // Loop over all of the operands of the instruction, spilling registers that
996 // are defined, and marking explicit destinations in the PhysRegsUsed map.
997 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
998 MachineOperand &MO = MI->getOperand(i);
999 if (!MO.isReg() || !MO.isDef() || MO.isImplicit() || !MO.getReg() ||
1000 MO.isEarlyClobber() ||
1001 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1004 unsigned Reg = MO.getReg();
1005 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
1006 // These are extra physical register defs when a sub-register
1007 // is defined (def of a sub-register is a read/mod/write of the
1008 // larger registers). Ignore.
1009 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
1011 MF->getRegInfo().setPhysRegUsed(Reg);
1012 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
1013 PhysRegsUsed[Reg] = 0; // It is free and reserved now
1014 AddToPhysRegsUseOrder(Reg);
1016 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
1017 *SubRegs; ++SubRegs) {
1018 if (PhysRegsUsed[*SubRegs] == -2) continue;
1020 MF->getRegInfo().setPhysRegUsed(*SubRegs);
1021 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
1022 AddToPhysRegsUseOrder(*SubRegs);
1026 // Loop over the implicit defs, spilling them as well.
1027 if (TID.ImplicitDefs) {
1028 for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
1029 *ImplicitDefs; ++ImplicitDefs) {
1030 unsigned Reg = *ImplicitDefs;
1031 if (PhysRegsUsed[Reg] != -2) {
1032 spillPhysReg(MBB, MI, Reg, true);
1033 AddToPhysRegsUseOrder(Reg);
1034 PhysRegsUsed[Reg] = 0; // It is free and reserved now
1036 MF->getRegInfo().setPhysRegUsed(Reg);
1037 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
1038 *SubRegs; ++SubRegs) {
1039 if (PhysRegsUsed[*SubRegs] == -2) continue;
1041 AddToPhysRegsUseOrder(*SubRegs);
1042 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
1043 MF->getRegInfo().setPhysRegUsed(*SubRegs);
1048 SmallVector<unsigned, 8> DeadDefs;
1049 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1050 MachineOperand &MO = MI->getOperand(i);
1051 if (MO.isReg() && MO.isDead())
1052 DeadDefs.push_back(MO.getReg());
1055 // Okay, we have allocated all of the source operands and spilled any values
1056 // that would be destroyed by defs of this instruction. Loop over the
1057 // explicit defs and assign them to a register, spilling incoming values if
1058 // we need to scavenge a register.
1060 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1061 MachineOperand &MO = MI->getOperand(i);
1062 if (!MO.isReg() || !MO.isDef() || !MO.getReg() ||
1063 MO.isEarlyClobber() ||
1064 !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1067 unsigned DestVirtReg = MO.getReg();
1068 unsigned DestPhysReg;
1070 // If DestVirtReg already has a value, use it.
1071 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) {
1072 // If this is a copy try to reuse the input as the output;
1073 // that will make the copy go away.
1074 // If this is a copy, the source reg is a phys reg, and
1075 // that reg is available, use that phys reg for DestPhysReg.
1076 // If this is a copy, the source reg is a virtual reg, and
1077 // the phys reg that was assigned to that virtual reg is now
1078 // available, use that phys reg for DestPhysReg. (If it's now
1079 // available that means this was the last use of the source.)
1081 TargetRegisterInfo::isPhysicalRegister(SrcCopyReg) &&
1082 isPhysRegAvailable(SrcCopyReg)) {
1083 DestPhysReg = SrcCopyReg;
1084 assignVirtToPhysReg(DestVirtReg, DestPhysReg);
1085 } else if (isCopy &&
1086 TargetRegisterInfo::isVirtualRegister(SrcCopyReg) &&
1087 SrcCopyPhysReg && isPhysRegAvailable(SrcCopyPhysReg) &&
1088 MF->getRegInfo().getRegClass(DestVirtReg)->
1089 contains(SrcCopyPhysReg)) {
1090 DestPhysReg = SrcCopyPhysReg;
1091 assignVirtToPhysReg(DestVirtReg, DestPhysReg);
1093 DestPhysReg = getReg(MBB, MI, DestVirtReg);
1095 MF->getRegInfo().setPhysRegUsed(DestPhysReg);
1096 markVirtRegModified(DestVirtReg);
1097 getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
1098 DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg)
1099 << " to %reg" << DestVirtReg << "\n");
1101 if (unsigned DestSubIdx = MO.getSubReg()) {
1103 DestPhysReg = TRI->getSubReg(DestPhysReg, DestSubIdx);
1105 MO.setReg(DestPhysReg); // Assign the output register
1108 // If this instruction defines any registers that are immediately dead,
1111 for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
1112 unsigned VirtReg = DeadDefs[i];
1113 unsigned PhysReg = VirtReg;
1114 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
1115 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
1116 PhysReg = PhysRegSlot;
1117 assert(PhysReg != 0);
1119 } else if (PhysRegsUsed[PhysReg] == -2) {
1120 // Unallocatable register dead, ignore.
1122 } else if (!PhysReg)
1125 DEBUG(dbgs() << " Register " << TRI->getName(PhysReg)
1126 << " [%reg" << VirtReg
1127 << "] is never used, removing it from live set\n");
1128 removePhysReg(PhysReg);
1129 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
1130 *AliasSet; ++AliasSet) {
1131 if (PhysRegsUsed[*AliasSet] != -2) {
1132 DEBUG(dbgs() << " Register " << TRI->getName(*AliasSet)
1133 << " [%reg" << *AliasSet
1134 << "] is never used, removing it from live set\n");
1135 removePhysReg(*AliasSet);
1140 // If this instruction is a call, make sure there are no dirty registers. The
1141 // call might throw an exception, and the landing pad expects to find all
1142 // registers in stack slots.
1144 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
1145 if (PhysRegsUsed[i] <= 0) continue;
1146 unsigned VirtReg = PhysRegsUsed[i];
1147 if (!isVirtRegModified(VirtReg)) continue;
1148 DEBUG(dbgs() << " Storing dirty %reg" << VirtReg);
1149 storeVirtReg(MBB, MI, VirtReg, i, false);
1150 markVirtRegModified(VirtReg, false);
1151 DEBUG(dbgs() << " because the call might throw\n");
1154 // Finally, if this is a noop copy instruction, zap it. (Except that if
1155 // the copy is dead, it must be kept to avoid messing up liveness info for
1156 // the register scavenger. See pr4100.)
1157 if (TII->isMoveInstr(*MI, SrcCopyReg, DstCopyReg,
1158 SrcCopySubReg, DstCopySubReg) &&
1159 SrcCopyReg == DstCopyReg && SrcCopySubReg == DstCopySubReg &&
1166 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
1168 // Spill all physical registers holding virtual registers now.
1169 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
1170 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) {
1171 if (unsigned VirtReg = PhysRegsUsed[i])
1172 spillVirtReg(MBB, MI, VirtReg, i);
1178 // This checking code is very expensive.
1180 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
1181 e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
1182 if (unsigned PR = Virt2PhysRegMap[i]) {
1183 cerr << "Register still mapped: " << i << " -> " << PR << "\n";
1186 assert(AllOk && "Virtual registers still in phys regs?");
1189 // Clear any physical register which appear live at the end of the basic
1190 // block, but which do not hold any virtual registers. e.g., the stack
1192 PhysRegsUseOrder.clear();
1195 /// runOnMachineFunction - Register allocate the whole function
1197 bool RALocal::runOnMachineFunction(MachineFunction &Fn) {
1198 DEBUG(dbgs() << "Machine Function\n");
1200 MRI = &Fn.getRegInfo();
1201 TM = &Fn.getTarget();
1202 TRI = TM->getRegisterInfo();
1203 TII = TM->getInstrInfo();
1205 PhysRegsUsed.assign(TRI->getNumRegs(), -1);
1207 // At various places we want to efficiently check to see whether a register
1208 // is allocatable. To handle this, we mark all unallocatable registers as
1209 // being pinned down, permanently.
1211 BitVector Allocable = TRI->getAllocatableSet(Fn);
1212 for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
1214 PhysRegsUsed[i] = -2; // Mark the reg unallocable.
1217 // initialize the virtual->physical register map to have a 'null'
1218 // mapping for all virtual registers
1219 unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg();
1220 StackSlotForVirtReg.grow(LastVirtReg);
1221 Virt2PhysRegMap.grow(LastVirtReg);
1222 Virt2LastUseMap.grow(LastVirtReg);
1223 VirtRegModified.resize(LastVirtReg+1 -
1224 TargetRegisterInfo::FirstVirtualRegister);
1225 UsedInMultipleBlocks.resize(LastVirtReg+1 -
1226 TargetRegisterInfo::FirstVirtualRegister);
1228 // Loop over all of the basic blocks, eliminating virtual register references
1229 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
1231 AllocateBasicBlock(*MBB);
1233 StackSlotForVirtReg.clear();
1234 PhysRegsUsed.clear();
1235 VirtRegModified.clear();
1236 UsedInMultipleBlocks.clear();
1237 Virt2PhysRegMap.clear();
1238 Virt2LastUseMap.clear();
1242 FunctionPass *llvm::createLocalRegisterAllocator() {
1243 return new RALocal();