1 //===-- RegAllocLocal.cpp - A BasicBlock generic register allocator -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This register allocator allocates registers to a basic block at a time,
11 // attempting to keep values in registers and reusing registers as appropriate.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "llvm/BasicBlock.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/IndexedMap.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
38 STATISTIC(NumStores, "Number of stores added");
39 STATISTIC(NumLoads , "Number of loads added");
41 static RegisterRegAlloc
42 localRegAlloc("local", "local register allocator",
43 createLocalRegisterAllocator);
46 class RALocal : public MachineFunctionPass {
49 RALocal() : MachineFunctionPass(&ID), StackSlotForVirtReg(-1) {}
51 const TargetMachine *TM;
53 const TargetRegisterInfo *TRI;
54 const TargetInstrInfo *TII;
56 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
57 // values are spilled.
58 IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
60 // Virt2PhysRegMap - This map contains entries for each virtual register
61 // that is currently available in a physical register.
62 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysRegMap;
64 unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) {
65 return Virt2PhysRegMap[VirtReg];
68 // PhysRegsUsed - This array is effectively a map, containing entries for
69 // each physical register that currently has a value (ie, it is in
70 // Virt2PhysRegMap). The value mapped to is the virtual register
71 // corresponding to the physical register (the inverse of the
72 // Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned
73 // because it is used by a future instruction, and to -2 if it is not
74 // allocatable. If the entry for a physical register is -1, then the
75 // physical register is "not in the map".
77 std::vector<int> PhysRegsUsed;
79 // PhysRegsUseOrder - This contains a list of the physical registers that
80 // currently have a virtual register value in them. This list provides an
81 // ordering of registers, imposing a reallocation order. This list is only
82 // used if all registers are allocated and we have to spill one, in which
83 // case we spill the least recently used register. Entries at the front of
84 // the list are the least recently used registers, entries at the back are
85 // the most recently used.
87 std::vector<unsigned> PhysRegsUseOrder;
89 // Virt2LastUseMap - This maps each virtual register to its last use
90 // (MachineInstr*, operand index pair).
91 IndexedMap<std::pair<MachineInstr*, unsigned>, VirtReg2IndexFunctor>
94 std::pair<MachineInstr*,unsigned>& getVirtRegLastUse(unsigned Reg) {
95 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
96 return Virt2LastUseMap[Reg];
99 // VirtRegModified - This bitset contains information about which virtual
100 // registers need to be spilled back to memory when their registers are
101 // scavenged. If a virtual register has simply been rematerialized, there
102 // is no reason to spill it to memory when we need the register back.
104 BitVector VirtRegModified;
106 // UsedInMultipleBlocks - Tracks whether a particular register is used in
107 // more than one block.
108 BitVector UsedInMultipleBlocks;
110 void markVirtRegModified(unsigned Reg, bool Val = true) {
111 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
112 Reg -= TargetRegisterInfo::FirstVirtualRegister;
114 VirtRegModified.set(Reg);
116 VirtRegModified.reset(Reg);
119 bool isVirtRegModified(unsigned Reg) const {
120 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
121 assert(Reg - TargetRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
122 && "Illegal virtual register!");
123 return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister];
126 void AddToPhysRegsUseOrder(unsigned Reg) {
127 std::vector<unsigned>::iterator It =
128 std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), Reg);
129 if (It != PhysRegsUseOrder.end())
130 PhysRegsUseOrder.erase(It);
131 PhysRegsUseOrder.push_back(Reg);
134 void MarkPhysRegRecentlyUsed(unsigned Reg) {
135 if (PhysRegsUseOrder.empty() ||
136 PhysRegsUseOrder.back() == Reg) return; // Already most recently used
138 for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i)
139 if (areRegsEqual(Reg, PhysRegsUseOrder[i-1])) {
140 unsigned RegMatch = PhysRegsUseOrder[i-1]; // remove from middle
141 PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1);
142 // Add it to the end of the list
143 PhysRegsUseOrder.push_back(RegMatch);
145 return; // Found an exact match, exit early
150 virtual const char *getPassName() const {
151 return "Local Register Allocator";
154 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
155 AU.setPreservesCFG();
156 AU.addRequiredID(PHIEliminationID);
157 AU.addRequiredID(TwoAddressInstructionPassID);
158 MachineFunctionPass::getAnalysisUsage(AU);
162 /// runOnMachineFunction - Register allocate the whole function
163 bool runOnMachineFunction(MachineFunction &Fn);
165 /// AllocateBasicBlock - Register allocate the specified basic block.
166 void AllocateBasicBlock(MachineBasicBlock &MBB);
169 /// areRegsEqual - This method returns true if the specified registers are
170 /// related to each other. To do this, it checks to see if they are equal
171 /// or if the first register is in the alias set of the second register.
173 bool areRegsEqual(unsigned R1, unsigned R2) const {
174 if (R1 == R2) return true;
175 for (const unsigned *AliasSet = TRI->getAliasSet(R2);
176 *AliasSet; ++AliasSet) {
177 if (*AliasSet == R1) return true;
182 /// getStackSpaceFor - This returns the frame index of the specified virtual
183 /// register on the stack, allocating space if necessary.
184 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
186 /// removePhysReg - This method marks the specified physical register as no
187 /// longer being in use.
189 void removePhysReg(unsigned PhysReg);
191 /// spillVirtReg - This method spills the value specified by PhysReg into
192 /// the virtual register slot specified by VirtReg. It then updates the RA
193 /// data structures to indicate the fact that PhysReg is now available.
195 void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
196 unsigned VirtReg, unsigned PhysReg);
198 /// spillPhysReg - This method spills the specified physical register into
199 /// the virtual register slot associated with it. If OnlyVirtRegs is set to
200 /// true, then the request is ignored if the physical register does not
201 /// contain a virtual register.
203 void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
204 unsigned PhysReg, bool OnlyVirtRegs = false);
206 /// assignVirtToPhysReg - This method updates local state so that we know
207 /// that PhysReg is the proper container for VirtReg now. The physical
208 /// register must not be used for anything else when this is called.
210 void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg);
212 /// isPhysRegAvailable - Return true if the specified physical register is
213 /// free and available for use. This also includes checking to see if
214 /// aliased registers are all free...
216 bool isPhysRegAvailable(unsigned PhysReg) const;
218 /// getFreeReg - Look to see if there is a free register available in the
219 /// specified register class. If not, return 0.
221 unsigned getFreeReg(const TargetRegisterClass *RC);
223 /// getReg - Find a physical register to hold the specified virtual
224 /// register. If all compatible physical registers are used, this method
225 /// spills the last used virtual register to the stack, and uses that
226 /// register. If NoFree is true, that means the caller knows there isn't
227 /// a free register, do not call getFreeReg().
228 unsigned getReg(MachineBasicBlock &MBB, MachineInstr *MI,
229 unsigned VirtReg, bool NoFree = false);
231 /// reloadVirtReg - This method transforms the specified virtual
232 /// register use to refer to a physical register. This method may do this
233 /// in one of several ways: if the register is available in a physical
234 /// register already, it uses that physical register. If the value is not
235 /// in a physical register, and if there are physical registers available,
236 /// it loads it into a register. If register pressure is high, and it is
237 /// possible, it tries to fold the load of the virtual register into the
238 /// instruction itself. It avoids doing this if register pressure is low to
239 /// improve the chance that subsequent instructions can use the reloaded
240 /// value. This method returns the modified instruction.
242 MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
243 unsigned OpNum, SmallSet<unsigned, 4> &RRegs);
245 /// ComputeLocalLiveness - Computes liveness of registers within a basic
246 /// block, setting the killed/dead flags as appropriate.
247 void ComputeLocalLiveness(MachineBasicBlock& MBB);
249 void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
252 char RALocal::ID = 0;
255 /// getStackSpaceFor - This allocates space for the specified virtual register
256 /// to be held on the stack.
257 int RALocal::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
258 // Find the location Reg would belong...
259 int SS = StackSlotForVirtReg[VirtReg];
261 return SS; // Already has space allocated?
263 // Allocate a new stack object for this spill location...
264 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
267 // Assign the slot...
268 StackSlotForVirtReg[VirtReg] = FrameIdx;
273 /// removePhysReg - This method marks the specified physical register as no
274 /// longer being in use.
276 void RALocal::removePhysReg(unsigned PhysReg) {
277 PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used
279 std::vector<unsigned>::iterator It =
280 std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), PhysReg);
281 if (It != PhysRegsUseOrder.end())
282 PhysRegsUseOrder.erase(It);
286 /// spillVirtReg - This method spills the value specified by PhysReg into the
287 /// virtual register slot specified by VirtReg. It then updates the RA data
288 /// structures to indicate the fact that PhysReg is now available.
290 void RALocal::spillVirtReg(MachineBasicBlock &MBB,
291 MachineBasicBlock::iterator I,
292 unsigned VirtReg, unsigned PhysReg) {
293 assert(VirtReg && "Spilling a physical register is illegal!"
294 " Must not have appropriate kill for the register or use exists beyond"
295 " the intended one.");
296 DEBUG(errs() << " Spilling register " << TRI->getName(PhysReg)
297 << " containing %reg" << VirtReg);
299 if (!isVirtRegModified(VirtReg)) {
300 DEBUG(errs() << " which has not been modified, so no store necessary!");
301 std::pair<MachineInstr*, unsigned> &LastUse = getVirtRegLastUse(VirtReg);
303 LastUse.first->getOperand(LastUse.second).setIsKill();
305 // Otherwise, there is a virtual register corresponding to this physical
306 // register. We only need to spill it into its stack slot if it has been
308 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
309 int FrameIndex = getStackSpaceFor(VirtReg, RC);
310 DEBUG(errs() << " to stack slot #" << FrameIndex);
311 // If the instruction reads the register that's spilled, (e.g. this can
312 // happen if it is a move to a physical register), then the spill
313 // instruction is not a kill.
314 bool isKill = !(I != MBB.end() && I->readsRegister(PhysReg));
315 TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC);
316 ++NumStores; // Update statistics
319 getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available
321 DEBUG(errs() << '\n');
322 removePhysReg(PhysReg);
326 /// spillPhysReg - This method spills the specified physical register into the
327 /// virtual register slot associated with it. If OnlyVirtRegs is set to true,
328 /// then the request is ignored if the physical register does not contain a
329 /// virtual register.
331 void RALocal::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
332 unsigned PhysReg, bool OnlyVirtRegs) {
333 if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used!
334 assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
335 if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs)
336 spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg);
338 // If the selected register aliases any other registers, we must make
339 // sure that one of the aliases isn't alive.
340 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
341 *AliasSet; ++AliasSet)
342 if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register.
343 PhysRegsUsed[*AliasSet] != -2) // If allocatable.
344 if (PhysRegsUsed[*AliasSet])
345 spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
350 /// assignVirtToPhysReg - This method updates local state so that we know
351 /// that PhysReg is the proper container for VirtReg now. The physical
352 /// register must not be used for anything else when this is called.
354 void RALocal::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
355 assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!");
356 // Update information to note the fact that this register was just used, and
358 PhysRegsUsed[PhysReg] = VirtReg;
359 getVirt2PhysRegMapSlot(VirtReg) = PhysReg;
360 AddToPhysRegsUseOrder(PhysReg); // New use of PhysReg
364 /// isPhysRegAvailable - Return true if the specified physical register is free
365 /// and available for use. This also includes checking to see if aliased
366 /// registers are all free...
368 bool RALocal::isPhysRegAvailable(unsigned PhysReg) const {
369 if (PhysRegsUsed[PhysReg] != -1) return false;
371 // If the selected register aliases any other allocated registers, it is
373 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
374 *AliasSet; ++AliasSet)
375 if (PhysRegsUsed[*AliasSet] >= 0) // Aliased register in use?
376 return false; // Can't use this reg then.
381 /// getFreeReg - Look to see if there is a free register available in the
382 /// specified register class. If not, return 0.
384 unsigned RALocal::getFreeReg(const TargetRegisterClass *RC) {
385 // Get iterators defining the range of registers that are valid to allocate in
386 // this class, which also specifies the preferred allocation order.
387 TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
388 TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
390 for (; RI != RE; ++RI)
391 if (isPhysRegAvailable(*RI)) { // Is reg unused?
392 assert(*RI != 0 && "Cannot use register!");
393 return *RI; // Found an unused register!
399 /// getReg - Find a physical register to hold the specified virtual
400 /// register. If all compatible physical registers are used, this method spills
401 /// the last used virtual register to the stack, and uses that register.
403 unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I,
404 unsigned VirtReg, bool NoFree) {
405 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
407 // First check to see if we have a free register of the requested type...
408 unsigned PhysReg = NoFree ? 0 : getFreeReg(RC);
410 // If we didn't find an unused register, scavenge one now!
412 assert(!PhysRegsUseOrder.empty() && "No allocated registers??");
414 // Loop over all of the preallocated registers from the least recently used
415 // to the most recently used. When we find one that is capable of holding
416 // our register, use it.
417 for (unsigned i = 0; PhysReg == 0; ++i) {
418 assert(i != PhysRegsUseOrder.size() &&
419 "Couldn't find a register of the appropriate class!");
421 unsigned R = PhysRegsUseOrder[i];
423 // We can only use this register if it holds a virtual register (ie, it
424 // can be spilled). Do not use it if it is an explicitly allocated
425 // physical register!
426 assert(PhysRegsUsed[R] != -1 &&
427 "PhysReg in PhysRegsUseOrder, but is not allocated?");
428 if (PhysRegsUsed[R] && PhysRegsUsed[R] != -2) {
429 // If the current register is compatible, use it.
430 if (RC->contains(R)) {
434 // If one of the registers aliased to the current register is
435 // compatible, use it.
436 for (const unsigned *AliasIt = TRI->getAliasSet(R);
437 *AliasIt; ++AliasIt) {
438 if (RC->contains(*AliasIt) &&
439 // If this is pinned down for some reason, don't use it. For
440 // example, if CL is pinned, and we run across CH, don't use
441 // CH as justification for using scavenging ECX (which will
443 PhysRegsUsed[*AliasIt] != 0 &&
445 // Make sure the register is allocatable. Don't allocate SIL on
447 PhysRegsUsed[*AliasIt] != -2) {
448 PhysReg = *AliasIt; // Take an aliased register
456 assert(PhysReg && "Physical register not assigned!?!?");
458 // At this point PhysRegsUseOrder[i] is the least recently used register of
459 // compatible register class. Spill it to memory and reap its remains.
460 spillPhysReg(MBB, I, PhysReg);
463 // Now that we know which register we need to assign this to, do it now!
464 assignVirtToPhysReg(VirtReg, PhysReg);
469 /// reloadVirtReg - This method transforms the specified virtual
470 /// register use to refer to a physical register. This method may do this in
471 /// one of several ways: if the register is available in a physical register
472 /// already, it uses that physical register. If the value is not in a physical
473 /// register, and if there are physical registers available, it loads it into a
474 /// register. If register pressure is high, and it is possible, it tries to
475 /// fold the load of the virtual register into the instruction itself. It
476 /// avoids doing this if register pressure is low to improve the chance that
477 /// subsequent instructions can use the reloaded value. This method returns the
478 /// modified instruction.
480 MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
482 SmallSet<unsigned, 4> &ReloadedRegs) {
483 unsigned VirtReg = MI->getOperand(OpNum).getReg();
485 // If the virtual register is already available, just update the instruction
487 if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
488 MarkPhysRegRecentlyUsed(PR); // Already have this value available!
489 MI->getOperand(OpNum).setReg(PR); // Assign the input register
490 getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
494 // Otherwise, we need to fold it into the current instruction, or reload it.
495 // If we have registers available to hold the value, use them.
496 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
497 unsigned PhysReg = getFreeReg(RC);
498 int FrameIndex = getStackSpaceFor(VirtReg, RC);
500 if (PhysReg) { // Register is available, allocate it!
501 assignVirtToPhysReg(VirtReg, PhysReg);
502 } else { // No registers available.
503 // Force some poor hapless value out of the register file to
504 // make room for the new register, and reload it.
505 PhysReg = getReg(MBB, MI, VirtReg, true);
508 markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded
510 DEBUG(errs() << " Reloading %reg" << VirtReg << " into "
511 << TRI->getName(PhysReg) << "\n");
513 // Add move instruction(s)
514 TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
515 ++NumLoads; // Update statistics
517 MF->getRegInfo().setPhysRegUsed(PhysReg);
518 MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
519 getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
521 if (!ReloadedRegs.insert(PhysReg)) {
523 raw_string_ostream Msg(msg);
524 Msg << "Ran out of registers during register allocation!";
525 if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
526 Msg << "\nPlease check your inline asm statement for invalid "
530 llvm_report_error(Msg.str());
532 for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
533 *SubRegs; ++SubRegs) {
534 if (!ReloadedRegs.insert(*SubRegs)) {
536 raw_string_ostream Msg(msg);
537 Msg << "Ran out of registers during register allocation!";
538 if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
539 Msg << "\nPlease check your inline asm statement for invalid "
543 llvm_report_error(Msg.str());
550 /// isReadModWriteImplicitKill - True if this is an implicit kill for a
551 /// read/mod/write register, i.e. update partial register.
552 static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
553 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
554 MachineOperand& MO = MI->getOperand(i);
555 if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
556 MO.isDef() && !MO.isDead())
562 /// isReadModWriteImplicitDef - True if this is an implicit def for a
563 /// read/mod/write register, i.e. update partial register.
564 static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
565 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
566 MachineOperand& MO = MI->getOperand(i);
567 if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
568 !MO.isDef() && MO.isKill())
574 // precedes - Helper function to determine with MachineInstr A
575 // precedes MachineInstr B within the same MBB.
576 static bool precedes(MachineBasicBlock::iterator A,
577 MachineBasicBlock::iterator B) {
581 MachineBasicBlock::iterator I = A->getParent()->begin();
582 while (I != A->getParent()->end()) {
594 /// ComputeLocalLiveness - Computes liveness of registers within a basic
595 /// block, setting the killed/dead flags as appropriate.
596 void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) {
597 MachineRegisterInfo& MRI = MBB.getParent()->getRegInfo();
598 // Keep track of the most recently seen previous use or def of each reg,
599 // so that we can update them with dead/kill markers.
600 DenseMap<unsigned, std::pair<MachineInstr*, unsigned> > LastUseDef;
601 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
603 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
604 MachineOperand& MO = I->getOperand(i);
605 // Uses don't trigger any flags, but we need to save
606 // them for later. Also, we have to process these
607 // _before_ processing the defs, since an instr
608 // uses regs before it defs them.
609 if (MO.isReg() && MO.getReg() && MO.isUse()) {
610 LastUseDef[MO.getReg()] = std::make_pair(I, i);
613 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) continue;
615 const unsigned* Aliases = TRI->getAliasSet(MO.getReg());
618 DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
619 alias = LastUseDef.find(*Aliases);
621 if (alias != LastUseDef.end() && alias->second.first != I)
622 LastUseDef[*Aliases] = std::make_pair(I, i);
630 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
631 MachineOperand& MO = I->getOperand(i);
632 // Defs others than 2-addr redefs _do_ trigger flag changes:
633 // - A def followed by a def is dead
634 // - A use followed by a def is a kill
635 if (MO.isReg() && MO.getReg() && MO.isDef()) {
636 DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
637 last = LastUseDef.find(MO.getReg());
638 if (last != LastUseDef.end()) {
639 // Check if this is a two address instruction. If so, then
640 // the def does not kill the use.
641 if (last->second.first == I &&
642 I->isRegTiedToUseOperand(i))
645 MachineOperand& lastUD =
646 last->second.first->getOperand(last->second.second);
648 lastUD.setIsDead(true);
650 lastUD.setIsKill(true);
653 LastUseDef[MO.getReg()] = std::make_pair(I, i);
658 // Live-out (of the function) registers contain return values of the function,
659 // so we need to make sure they are alive at return time.
660 if (!MBB.empty() && MBB.back().getDesc().isReturn()) {
661 MachineInstr* Ret = &MBB.back();
662 for (MachineRegisterInfo::liveout_iterator
663 I = MF->getRegInfo().liveout_begin(),
664 E = MF->getRegInfo().liveout_end(); I != E; ++I)
665 if (!Ret->readsRegister(*I)) {
666 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
667 LastUseDef[*I] = std::make_pair(Ret, Ret->getNumOperands()-1);
671 // Finally, loop over the final use/def of each reg
672 // in the block and determine if it is dead.
673 for (DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
674 I = LastUseDef.begin(), E = LastUseDef.end(); I != E; ++I) {
675 MachineInstr* MI = I->second.first;
676 unsigned idx = I->second.second;
677 MachineOperand& MO = MI->getOperand(idx);
679 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(MO.getReg());
681 // A crude approximation of "live-out" calculation
682 bool usedOutsideBlock = isPhysReg ? false :
683 UsedInMultipleBlocks.test(MO.getReg() -
684 TargetRegisterInfo::FirstVirtualRegister);
685 if (!isPhysReg && !usedOutsideBlock)
686 for (MachineRegisterInfo::reg_iterator UI = MRI.reg_begin(MO.getReg()),
687 UE = MRI.reg_end(); UI != UE; ++UI)
689 // - used in another block
690 // - used in the same block before it is defined (loop)
691 if (UI->getParent() != &MBB ||
692 (MO.isDef() && UI.getOperand().isUse() && precedes(&*UI, MI))) {
693 UsedInMultipleBlocks.set(MO.getReg() -
694 TargetRegisterInfo::FirstVirtualRegister);
695 usedOutsideBlock = true;
699 // Physical registers and those that are not live-out of the block
700 // are killed/dead at their last use/def within this block.
701 if (isPhysReg || !usedOutsideBlock) {
703 // Don't mark uses that are tied to defs as kills.
704 if (!MI->isRegTiedToDefOperand(idx))
712 void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
713 // loop over each instruction
714 MachineBasicBlock::iterator MII = MBB.begin();
717 const BasicBlock *LBB = MBB.getBasicBlock();
719 errs() << "\nStarting RegAlloc of BB: " << LBB->getName();
722 // Add live-in registers as active.
723 for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
724 E = MBB.livein_end(); I != E; ++I) {
726 MF->getRegInfo().setPhysRegUsed(Reg);
727 PhysRegsUsed[Reg] = 0; // It is free and reserved now
728 AddToPhysRegsUseOrder(Reg);
729 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
730 *SubRegs; ++SubRegs) {
731 if (PhysRegsUsed[*SubRegs] != -2) {
732 AddToPhysRegsUseOrder(*SubRegs);
733 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
734 MF->getRegInfo().setPhysRegUsed(*SubRegs);
739 ComputeLocalLiveness(MBB);
741 // Otherwise, sequentially allocate each instruction in the MBB.
742 while (MII != MBB.end()) {
743 MachineInstr *MI = MII++;
744 const TargetInstrDesc &TID = MI->getDesc();
746 errs() << "\nStarting RegAlloc of: " << *MI;
747 errs() << " Regs have values: ";
748 for (unsigned i = 0; i != TRI->getNumRegs(); ++i)
749 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
750 errs() << "[" << TRI->getName(i)
751 << ",%reg" << PhysRegsUsed[i] << "] ";
755 // Loop over the implicit uses, making sure that they are at the head of the
756 // use order list, so they don't get reallocated.
757 if (TID.ImplicitUses) {
758 for (const unsigned *ImplicitUses = TID.ImplicitUses;
759 *ImplicitUses; ++ImplicitUses)
760 MarkPhysRegRecentlyUsed(*ImplicitUses);
763 SmallVector<unsigned, 8> Kills;
764 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
765 MachineOperand& MO = MI->getOperand(i);
766 if (MO.isReg() && MO.isKill()) {
767 if (!MO.isImplicit())
768 Kills.push_back(MO.getReg());
769 else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
770 // These are extra physical register kills when a sub-register
771 // is defined (def of a sub-register is a read/mod/write of the
772 // larger registers). Ignore.
773 Kills.push_back(MO.getReg());
777 // If any physical regs are earlyclobber, spill any value they might
778 // have in them, then mark them unallocatable.
779 // If any virtual regs are earlyclobber, allocate them now (before
780 // freeing inputs that are killed).
781 if (MI->getOpcode()==TargetInstrInfo::INLINEASM) {
782 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
783 MachineOperand& MO = MI->getOperand(i);
784 if (MO.isReg() && MO.isDef() && MO.isEarlyClobber() &&
786 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
787 unsigned DestVirtReg = MO.getReg();
788 unsigned DestPhysReg;
790 // If DestVirtReg already has a value, use it.
791 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
792 DestPhysReg = getReg(MBB, MI, DestVirtReg);
793 MF->getRegInfo().setPhysRegUsed(DestPhysReg);
794 markVirtRegModified(DestVirtReg);
795 getVirtRegLastUse(DestVirtReg) =
796 std::make_pair((MachineInstr*)0, 0);
797 DEBUG(errs() << " Assigning " << TRI->getName(DestPhysReg)
798 << " to %reg" << DestVirtReg << "\n");
799 MO.setReg(DestPhysReg); // Assign the earlyclobber register
801 unsigned Reg = MO.getReg();
802 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
803 // These are extra physical register defs when a sub-register
804 // is defined (def of a sub-register is a read/mod/write of the
805 // larger registers). Ignore.
806 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
808 MF->getRegInfo().setPhysRegUsed(Reg);
809 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
810 PhysRegsUsed[Reg] = 0; // It is free and reserved now
811 AddToPhysRegsUseOrder(Reg);
813 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
814 *SubRegs; ++SubRegs) {
815 if (PhysRegsUsed[*SubRegs] != -2) {
816 MF->getRegInfo().setPhysRegUsed(*SubRegs);
817 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
818 AddToPhysRegsUseOrder(*SubRegs);
826 // Get the used operands into registers. This has the potential to spill
827 // incoming values if we are out of registers. Note that we completely
828 // ignore physical register uses here. We assume that if an explicit
829 // physical register is referenced by the instruction, that it is guaranteed
830 // to be live-in, or the input is badly hosed.
832 SmallSet<unsigned, 4> ReloadedRegs;
833 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
834 MachineOperand& MO = MI->getOperand(i);
835 // here we are looking for only used operands (never def&use)
836 if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
837 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
838 MI = reloadVirtReg(MBB, MI, i, ReloadedRegs);
841 // If this instruction is the last user of this register, kill the
842 // value, freeing the register being used, so it doesn't need to be
843 // spilled to memory.
845 for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
846 unsigned VirtReg = Kills[i];
847 unsigned PhysReg = VirtReg;
848 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
849 // If the virtual register was never materialized into a register, it
850 // might not be in the map, but it won't hurt to zero it out anyway.
851 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
852 PhysReg = PhysRegSlot;
854 } else if (PhysRegsUsed[PhysReg] == -2) {
855 // Unallocatable register dead, ignore.
858 assert((!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1) &&
859 "Silently clearing a virtual register?");
863 DEBUG(errs() << " Last use of " << TRI->getName(PhysReg)
864 << "[%reg" << VirtReg <<"], removing it from live set\n");
865 removePhysReg(PhysReg);
866 for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
867 *SubRegs; ++SubRegs) {
868 if (PhysRegsUsed[*SubRegs] != -2) {
869 DEBUG(errs() << " Last use of "
870 << TRI->getName(*SubRegs) << "[%reg" << VirtReg
871 <<"], removing it from live set\n");
872 removePhysReg(*SubRegs);
878 // Loop over all of the operands of the instruction, spilling registers that
879 // are defined, and marking explicit destinations in the PhysRegsUsed map.
880 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
881 MachineOperand& MO = MI->getOperand(i);
882 if (MO.isReg() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
883 !MO.isEarlyClobber() &&
884 TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
885 unsigned Reg = MO.getReg();
886 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
887 // These are extra physical register defs when a sub-register
888 // is defined (def of a sub-register is a read/mod/write of the
889 // larger registers). Ignore.
890 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
892 MF->getRegInfo().setPhysRegUsed(Reg);
893 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
894 PhysRegsUsed[Reg] = 0; // It is free and reserved now
895 AddToPhysRegsUseOrder(Reg);
897 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
898 *SubRegs; ++SubRegs) {
899 if (PhysRegsUsed[*SubRegs] != -2) {
900 MF->getRegInfo().setPhysRegUsed(*SubRegs);
901 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
902 AddToPhysRegsUseOrder(*SubRegs);
908 // Loop over the implicit defs, spilling them as well.
909 if (TID.ImplicitDefs) {
910 for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
911 *ImplicitDefs; ++ImplicitDefs) {
912 unsigned Reg = *ImplicitDefs;
913 if (PhysRegsUsed[Reg] != -2) {
914 spillPhysReg(MBB, MI, Reg, true);
915 AddToPhysRegsUseOrder(Reg);
916 PhysRegsUsed[Reg] = 0; // It is free and reserved now
918 MF->getRegInfo().setPhysRegUsed(Reg);
919 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
920 *SubRegs; ++SubRegs) {
921 if (PhysRegsUsed[*SubRegs] != -2) {
922 AddToPhysRegsUseOrder(*SubRegs);
923 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
924 MF->getRegInfo().setPhysRegUsed(*SubRegs);
930 SmallVector<unsigned, 8> DeadDefs;
931 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
932 MachineOperand& MO = MI->getOperand(i);
933 if (MO.isReg() && MO.isDead())
934 DeadDefs.push_back(MO.getReg());
937 // Okay, we have allocated all of the source operands and spilled any values
938 // that would be destroyed by defs of this instruction. Loop over the
939 // explicit defs and assign them to a register, spilling incoming values if
940 // we need to scavenge a register.
942 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
943 MachineOperand& MO = MI->getOperand(i);
944 if (MO.isReg() && MO.isDef() && MO.getReg() &&
945 !MO.isEarlyClobber() &&
946 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
947 unsigned DestVirtReg = MO.getReg();
948 unsigned DestPhysReg;
950 // If DestVirtReg already has a value, use it.
951 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
952 DestPhysReg = getReg(MBB, MI, DestVirtReg);
953 MF->getRegInfo().setPhysRegUsed(DestPhysReg);
954 markVirtRegModified(DestVirtReg);
955 getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
956 DEBUG(errs() << " Assigning " << TRI->getName(DestPhysReg)
957 << " to %reg" << DestVirtReg << "\n");
958 MO.setReg(DestPhysReg); // Assign the output register
962 // If this instruction defines any registers that are immediately dead,
965 for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
966 unsigned VirtReg = DeadDefs[i];
967 unsigned PhysReg = VirtReg;
968 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
969 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
970 PhysReg = PhysRegSlot;
971 assert(PhysReg != 0);
973 } else if (PhysRegsUsed[PhysReg] == -2) {
974 // Unallocatable register dead, ignore.
979 DEBUG(errs() << " Register " << TRI->getName(PhysReg)
980 << " [%reg" << VirtReg
981 << "] is never used, removing it from live set\n");
982 removePhysReg(PhysReg);
983 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
984 *AliasSet; ++AliasSet) {
985 if (PhysRegsUsed[*AliasSet] != -2) {
986 DEBUG(errs() << " Register " << TRI->getName(*AliasSet)
987 << " [%reg" << *AliasSet
988 << "] is never used, removing it from live set\n");
989 removePhysReg(*AliasSet);
995 // Finally, if this is a noop copy instruction, zap it. (Except that if
996 // the copy is dead, it must be kept to avoid messing up liveness info for
997 // the register scavenger. See pr4100.)
998 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
999 if (TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
1000 SrcReg == DstReg && DeadDefs.empty())
1004 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
1006 // Spill all physical registers holding virtual registers now.
1007 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
1008 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) {
1009 if (unsigned VirtReg = PhysRegsUsed[i])
1010 spillVirtReg(MBB, MI, VirtReg, i);
1016 // This checking code is very expensive.
1018 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
1019 e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
1020 if (unsigned PR = Virt2PhysRegMap[i]) {
1021 cerr << "Register still mapped: " << i << " -> " << PR << "\n";
1024 assert(AllOk && "Virtual registers still in phys regs?");
1027 // Clear any physical register which appear live at the end of the basic
1028 // block, but which do not hold any virtual registers. e.g., the stack
1030 PhysRegsUseOrder.clear();
1033 /// runOnMachineFunction - Register allocate the whole function
1035 bool RALocal::runOnMachineFunction(MachineFunction &Fn) {
1036 DEBUG(errs() << "Machine Function\n");
1038 TM = &Fn.getTarget();
1039 TRI = TM->getRegisterInfo();
1040 TII = TM->getInstrInfo();
1042 PhysRegsUsed.assign(TRI->getNumRegs(), -1);
1044 // At various places we want to efficiently check to see whether a register
1045 // is allocatable. To handle this, we mark all unallocatable registers as
1046 // being pinned down, permanently.
1048 BitVector Allocable = TRI->getAllocatableSet(Fn);
1049 for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
1051 PhysRegsUsed[i] = -2; // Mark the reg unallocable.
1054 // initialize the virtual->physical register map to have a 'null'
1055 // mapping for all virtual registers
1056 unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg();
1057 StackSlotForVirtReg.grow(LastVirtReg);
1058 Virt2PhysRegMap.grow(LastVirtReg);
1059 Virt2LastUseMap.grow(LastVirtReg);
1060 VirtRegModified.resize(LastVirtReg+1-TargetRegisterInfo::FirstVirtualRegister);
1061 UsedInMultipleBlocks.resize(LastVirtReg+1-TargetRegisterInfo::FirstVirtualRegister);
1063 // Loop over all of the basic blocks, eliminating virtual register references
1064 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
1066 AllocateBasicBlock(*MBB);
1068 StackSlotForVirtReg.clear();
1069 PhysRegsUsed.clear();
1070 VirtRegModified.clear();
1071 UsedInMultipleBlocks.clear();
1072 Virt2PhysRegMap.clear();
1073 Virt2LastUseMap.clear();
1077 FunctionPass *llvm::createLocalRegisterAllocator() {
1078 return new RALocal();