1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "VirtRegMap.h"
16 #include "VirtRegRewriter.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/LiveStackAnalysis.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegAllocRegistry.h"
27 #include "llvm/CodeGen/RegisterCoalescer.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/ADT/EquivalenceClasses.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
48 STATISTIC(NumIters , "Number of iterations performed");
49 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
50 STATISTIC(NumCoalesce, "Number of copies coalesced");
51 STATISTIC(NumDowngrade, "Number of registers downgraded");
54 NewHeuristic("new-spilling-heuristic",
55 cl::desc("Use new spilling heuristic"),
56 cl::init(false), cl::Hidden);
59 PreSplitIntervals("pre-alloc-split",
60 cl::desc("Pre-register allocation live interval splitting"),
61 cl::init(false), cl::Hidden);
64 NewSpillFramework("new-spill-framework",
65 cl::desc("New spilling framework"),
66 cl::init(false), cl::Hidden);
68 static RegisterRegAlloc
69 linearscanRegAlloc("linearscan", "linear scan register allocator",
70 createLinearScanRegisterAllocator);
73 struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass {
75 RALinScan() : MachineFunctionPass(&ID) {}
77 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
78 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
80 /// RelatedRegClasses - This structure is built the first time a function is
81 /// compiled, and keeps track of which register classes have registers that
82 /// belong to multiple classes or have aliases that are in other classes.
83 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
84 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
86 // NextReloadMap - For each register in the map, it maps to the another
87 // register which is defined by a reload from the same stack slot and
88 // both reloads are in the same basic block.
89 DenseMap<unsigned, unsigned> NextReloadMap;
91 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
92 // un-favored for allocation.
93 SmallSet<unsigned, 8> DowngradedRegs;
95 // DowngradeMap - A map from virtual registers to physical registers being
96 // downgraded for the virtual registers.
97 DenseMap<unsigned, unsigned> DowngradeMap;
100 MachineRegisterInfo* mri_;
101 const TargetMachine* tm_;
102 const TargetRegisterInfo* tri_;
103 const TargetInstrInfo* tii_;
104 BitVector allocatableRegs_;
107 const MachineLoopInfo *loopInfo;
109 /// handled_ - Intervals are added to the handled_ set in the order of their
110 /// start value. This is uses for backtracking.
111 std::vector<LiveInterval*> handled_;
113 /// fixed_ - Intervals that correspond to machine registers.
117 /// active_ - Intervals that are currently being processed, and which have a
118 /// live range active for the current point.
119 IntervalPtrs active_;
121 /// inactive_ - Intervals that are currently being processed, but which have
122 /// a hold at the current point.
123 IntervalPtrs inactive_;
125 typedef std::priority_queue<LiveInterval*,
126 SmallVector<LiveInterval*, 64>,
127 greater_ptr<LiveInterval> > IntervalHeap;
128 IntervalHeap unhandled_;
130 /// regUse_ - Tracks register usage.
131 SmallVector<unsigned, 32> regUse_;
132 SmallVector<unsigned, 32> regUseBackUp_;
134 /// vrm_ - Tracks register assignments.
137 std::auto_ptr<VirtRegRewriter> rewriter_;
139 std::auto_ptr<Spiller> spiller_;
142 virtual const char* getPassName() const {
143 return "Linear Scan Register Allocator";
146 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
147 AU.setPreservesCFG();
148 AU.addRequired<LiveIntervals>();
150 AU.addRequiredID(StrongPHIEliminationID);
151 // Make sure PassManager knows which analyses to make available
152 // to coalescing and which analyses coalescing invalidates.
153 AU.addRequiredTransitive<RegisterCoalescer>();
154 if (PreSplitIntervals)
155 AU.addRequiredID(PreAllocSplittingID);
156 AU.addRequired<LiveStacks>();
157 AU.addPreserved<LiveStacks>();
158 AU.addRequired<MachineLoopInfo>();
159 AU.addPreserved<MachineLoopInfo>();
160 AU.addRequired<VirtRegMap>();
161 AU.addPreserved<VirtRegMap>();
162 AU.addPreservedID(MachineDominatorsID);
163 MachineFunctionPass::getAnalysisUsage(AU);
166 /// runOnMachineFunction - register allocate the whole function
167 bool runOnMachineFunction(MachineFunction&);
170 /// linearScan - the linear scan algorithm
173 /// initIntervalSets - initialize the interval sets.
175 void initIntervalSets();
177 /// processActiveIntervals - expire old intervals and move non-overlapping
178 /// ones to the inactive list.
179 void processActiveIntervals(unsigned CurPoint);
181 /// processInactiveIntervals - expire old intervals and move overlapping
182 /// ones to the active list.
183 void processInactiveIntervals(unsigned CurPoint);
185 /// hasNextReloadInterval - Return the next liveinterval that's being
186 /// defined by a reload from the same SS as the specified one.
187 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
189 /// DowngradeRegister - Downgrade a register for allocation.
190 void DowngradeRegister(LiveInterval *li, unsigned Reg);
192 /// UpgradeRegister - Upgrade a register for allocation.
193 void UpgradeRegister(unsigned Reg);
195 /// assignRegOrStackSlotAtInterval - assign a register if one
196 /// is available, or spill.
197 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
199 void updateSpillWeights(std::vector<float> &Weights,
200 unsigned reg, float weight,
201 const TargetRegisterClass *RC);
203 /// findIntervalsToSpill - Determine the intervals to spill for the
204 /// specified interval. It's passed the physical registers whose spill
205 /// weight is the lowest among all the registers whose live intervals
206 /// conflict with the interval.
207 void findIntervalsToSpill(LiveInterval *cur,
208 std::vector<std::pair<unsigned,float> > &Candidates,
210 SmallVector<LiveInterval*, 8> &SpillIntervals);
212 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
213 /// try allocate the definition the same register as the source register
214 /// if the register is not defined during live time of the interval. This
215 /// eliminate a copy. This is used to coalesce copies which were not
216 /// coalesced away before allocation either due to dest and src being in
217 /// different register classes or because the coalescer was overly
219 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
222 /// Register usage / availability tracking helpers.
226 regUse_.resize(tri_->getNumRegs(), 0);
227 regUseBackUp_.resize(tri_->getNumRegs(), 0);
230 void finalizeRegUses() {
232 // Verify all the registers are "freed".
234 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
235 if (regUse_[i] != 0) {
236 errs() << tri_->getName(i) << " is still in use!\n";
244 regUseBackUp_.clear();
247 void addRegUse(unsigned physReg) {
248 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
249 "should be physical register!");
251 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
255 void delRegUse(unsigned physReg) {
256 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
257 "should be physical register!");
258 assert(regUse_[physReg] != 0);
260 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
261 assert(regUse_[*as] != 0);
266 bool isRegAvail(unsigned physReg) const {
267 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
268 "should be physical register!");
269 return regUse_[physReg] == 0;
272 void backUpRegUses() {
273 regUseBackUp_ = regUse_;
276 void restoreRegUses() {
277 regUse_ = regUseBackUp_;
281 /// Register handling helpers.
284 /// getFreePhysReg - return a free physical register for this virtual
285 /// register interval if we have one, otherwise return 0.
286 unsigned getFreePhysReg(LiveInterval* cur);
287 unsigned getFreePhysReg(LiveInterval* cur,
288 const TargetRegisterClass *RC,
289 unsigned MaxInactiveCount,
290 SmallVector<unsigned, 256> &inactiveCounts,
293 /// assignVirt2StackSlot - assigns this virtual register to a
294 /// stack slot. returns the stack slot
295 int assignVirt2StackSlot(unsigned virtReg);
297 void ComputeRelatedRegClasses();
299 template <typename ItTy>
300 void printIntervals(const char* const str, ItTy i, ItTy e) const {
303 errs() << str << " intervals:\n";
305 for (; i != e; ++i) {
306 errs() << "\t" << *i->first << " -> ";
308 unsigned reg = i->first->reg;
309 if (TargetRegisterInfo::isVirtualRegister(reg))
310 reg = vrm_->getPhys(reg);
312 errs() << tri_->getName(reg) << '\n';
317 char RALinScan::ID = 0;
320 static RegisterPass<RALinScan>
321 X("linearscan-regalloc", "Linear Scan Register Allocator");
323 void RALinScan::ComputeRelatedRegClasses() {
324 // First pass, add all reg classes to the union, and determine at least one
325 // reg class that each register is in.
326 bool HasAliases = false;
327 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
328 E = tri_->regclass_end(); RCI != E; ++RCI) {
329 RelatedRegClasses.insert(*RCI);
330 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
332 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
334 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
336 // Already processed this register. Just make sure we know that
337 // multiple register classes share a register.
338 RelatedRegClasses.unionSets(PRC, *RCI);
345 // Second pass, now that we know conservatively what register classes each reg
346 // belongs to, add info about aliases. We don't need to do this for targets
347 // without register aliases.
349 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
350 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
352 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
353 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
356 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
357 /// try allocate the definition the same register as the source register
358 /// if the register is not defined during live time of the interval. This
359 /// eliminate a copy. This is used to coalesce copies which were not
360 /// coalesced away before allocation either due to dest and src being in
361 /// different register classes or because the coalescer was overly
363 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
364 unsigned Preference = vrm_->getRegAllocPref(cur.reg);
365 if ((Preference && Preference == Reg) || !cur.containsOneValue())
368 VNInfo *vni = cur.begin()->valno;
369 if (!vni->def || vni->isUnused() || !vni->isDefAccurate())
371 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
372 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg, PhysReg;
374 !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
377 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
378 if (!vrm_->isAssignedReg(SrcReg))
380 PhysReg = vrm_->getPhys(SrcReg);
385 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
386 if (!RC->contains(PhysReg))
390 if (!li_->conflictsWithPhysRegDef(cur, *vrm_, PhysReg)) {
391 DEBUG(errs() << "Coalescing: " << cur << " -> " << tri_->getName(PhysReg)
393 vrm_->clearVirt(cur.reg);
394 vrm_->assignVirt2Phys(cur.reg, PhysReg);
396 // Remove unnecessary kills since a copy does not clobber the register.
397 if (li_->hasInterval(SrcReg)) {
398 LiveInterval &SrcLI = li_->getInterval(SrcReg);
399 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(cur.reg),
400 E = mri_->reg_end(); I != E; ++I) {
401 MachineOperand &O = I.getOperand();
402 if (!O.isUse() || !O.isKill())
404 MachineInstr *MI = &*I;
405 if (SrcLI.liveAt(li_->getDefIndex(li_->getInstructionIndex(MI))))
417 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
419 mri_ = &fn.getRegInfo();
420 tm_ = &fn.getTarget();
421 tri_ = tm_->getRegisterInfo();
422 tii_ = tm_->getInstrInfo();
423 allocatableRegs_ = tri_->getAllocatableSet(fn);
424 li_ = &getAnalysis<LiveIntervals>();
425 ls_ = &getAnalysis<LiveStacks>();
426 loopInfo = &getAnalysis<MachineLoopInfo>();
428 // We don't run the coalescer here because we have no reason to
429 // interact with it. If the coalescer requires interaction, it
430 // won't do anything. If it doesn't require interaction, we assume
431 // it was run as a separate pass.
433 // If this is the first function compiled, compute the related reg classes.
434 if (RelatedRegClasses.empty())
435 ComputeRelatedRegClasses();
437 // Also resize register usage trackers.
440 vrm_ = &getAnalysis<VirtRegMap>();
441 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
443 if (NewSpillFramework) {
444 spiller_.reset(createSpiller(mf_, li_, ls_, vrm_));
451 // Rewrite spill code and update the PhysRegsUsed set.
452 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
454 assert(unhandled_.empty() && "Unhandled live intervals remain!");
462 NextReloadMap.clear();
463 DowngradedRegs.clear();
464 DowngradeMap.clear();
470 /// initIntervalSets - initialize the interval sets.
472 void RALinScan::initIntervalSets()
474 assert(unhandled_.empty() && fixed_.empty() &&
475 active_.empty() && inactive_.empty() &&
476 "interval sets should be empty on initialization");
478 handled_.reserve(li_->getNumIntervals());
480 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
481 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
482 mri_->setPhysRegUsed(i->second->reg);
483 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
485 unhandled_.push(i->second);
489 void RALinScan::linearScan() {
490 // linear scan algorithm
492 errs() << "********** LINEAR SCAN **********\n"
493 << "********** Function: "
494 << mf_->getFunction()->getName() << '\n';
495 printIntervals("fixed", fixed_.begin(), fixed_.end());
498 while (!unhandled_.empty()) {
499 // pick the interval with the earliest start point
500 LiveInterval* cur = unhandled_.top();
503 DEBUG(errs() << "\n*** CURRENT ***: " << *cur << '\n');
506 processActiveIntervals(cur->beginNumber());
507 processInactiveIntervals(cur->beginNumber());
509 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
510 "Can only allocate virtual registers!");
513 // Allocating a virtual register. try to find a free
514 // physical register or spill an interval (possibly this one) in order to
516 assignRegOrStackSlotAtInterval(cur);
519 printIntervals("active", active_.begin(), active_.end());
520 printIntervals("inactive", inactive_.begin(), inactive_.end());
524 // Expire any remaining active intervals
525 while (!active_.empty()) {
526 IntervalPtr &IP = active_.back();
527 unsigned reg = IP.first->reg;
528 DEBUG(errs() << "\tinterval " << *IP.first << " expired\n");
529 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
530 "Can only allocate virtual registers!");
531 reg = vrm_->getPhys(reg);
536 // Expire any remaining inactive intervals
538 for (IntervalPtrs::reverse_iterator
539 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
540 errs() << "\tinterval " << *i->first << " expired\n";
544 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
545 MachineFunction::iterator EntryMBB = mf_->begin();
546 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
547 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
548 LiveInterval &cur = *i->second;
550 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
553 else if (vrm_->isAssignedReg(cur.reg))
554 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
557 // Ignore splited live intervals.
558 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
561 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
563 const LiveRange &LR = *I;
564 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
565 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
566 if (LiveInMBBs[i] != EntryMBB) {
567 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
568 "Adding a virtual register to livein set?");
569 LiveInMBBs[i]->addLiveIn(Reg);
576 DEBUG(errs() << *vrm_);
578 // Look for physical registers that end up not being allocated even though
579 // register allocator had to spill other registers in its register class.
580 if (ls_->getNumIntervals() == 0)
582 if (!vrm_->FindUnusedRegisters(li_))
586 /// processActiveIntervals - expire old intervals and move non-overlapping ones
587 /// to the inactive list.
588 void RALinScan::processActiveIntervals(unsigned CurPoint)
590 DEBUG(errs() << "\tprocessing active intervals:\n");
592 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
593 LiveInterval *Interval = active_[i].first;
594 LiveInterval::iterator IntervalPos = active_[i].second;
595 unsigned reg = Interval->reg;
597 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
599 if (IntervalPos == Interval->end()) { // Remove expired intervals.
600 DEBUG(errs() << "\t\tinterval " << *Interval << " expired\n");
601 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
602 "Can only allocate virtual registers!");
603 reg = vrm_->getPhys(reg);
606 // Pop off the end of the list.
607 active_[i] = active_.back();
611 } else if (IntervalPos->start > CurPoint) {
612 // Move inactive intervals to inactive list.
613 DEBUG(errs() << "\t\tinterval " << *Interval << " inactive\n");
614 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
615 "Can only allocate virtual registers!");
616 reg = vrm_->getPhys(reg);
619 inactive_.push_back(std::make_pair(Interval, IntervalPos));
621 // Pop off the end of the list.
622 active_[i] = active_.back();
626 // Otherwise, just update the iterator position.
627 active_[i].second = IntervalPos;
632 /// processInactiveIntervals - expire old intervals and move overlapping
633 /// ones to the active list.
634 void RALinScan::processInactiveIntervals(unsigned CurPoint)
636 DEBUG(errs() << "\tprocessing inactive intervals:\n");
638 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
639 LiveInterval *Interval = inactive_[i].first;
640 LiveInterval::iterator IntervalPos = inactive_[i].second;
641 unsigned reg = Interval->reg;
643 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
645 if (IntervalPos == Interval->end()) { // remove expired intervals.
646 DEBUG(errs() << "\t\tinterval " << *Interval << " expired\n");
648 // Pop off the end of the list.
649 inactive_[i] = inactive_.back();
650 inactive_.pop_back();
652 } else if (IntervalPos->start <= CurPoint) {
653 // move re-activated intervals in active list
654 DEBUG(errs() << "\t\tinterval " << *Interval << " active\n");
655 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
656 "Can only allocate virtual registers!");
657 reg = vrm_->getPhys(reg);
660 active_.push_back(std::make_pair(Interval, IntervalPos));
662 // Pop off the end of the list.
663 inactive_[i] = inactive_.back();
664 inactive_.pop_back();
667 // Otherwise, just update the iterator position.
668 inactive_[i].second = IntervalPos;
673 /// updateSpillWeights - updates the spill weights of the specifed physical
674 /// register and its weight.
675 void RALinScan::updateSpillWeights(std::vector<float> &Weights,
676 unsigned reg, float weight,
677 const TargetRegisterClass *RC) {
678 SmallSet<unsigned, 4> Processed;
679 SmallSet<unsigned, 4> SuperAdded;
680 SmallVector<unsigned, 4> Supers;
681 Weights[reg] += weight;
682 Processed.insert(reg);
683 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
684 Weights[*as] += weight;
685 Processed.insert(*as);
686 if (tri_->isSubRegister(*as, reg) &&
687 SuperAdded.insert(*as) &&
689 Supers.push_back(*as);
693 // If the alias is a super-register, and the super-register is in the
694 // register class we are trying to allocate. Then add the weight to all
695 // sub-registers of the super-register even if they are not aliases.
696 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
697 // bl should get the same spill weight otherwise it will be choosen
698 // as a spill candidate since spilling bh doesn't make ebx available.
699 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
700 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
701 if (!Processed.count(*sr))
702 Weights[*sr] += weight;
707 RALinScan::IntervalPtrs::iterator
708 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
709 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
711 if (I->first == LI) return I;
715 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, unsigned Point){
716 for (unsigned i = 0, e = V.size(); i != e; ++i) {
717 RALinScan::IntervalPtr &IP = V[i];
718 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
720 if (I != IP.first->begin()) --I;
725 /// addStackInterval - Create a LiveInterval for stack if the specified live
726 /// interval has been spilled.
727 static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
729 MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
730 int SS = vrm_.getStackSlot(cur->reg);
731 if (SS == VirtRegMap::NO_STACK_SLOT)
734 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
735 LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
738 if (SI.hasAtLeastOneValue())
739 VNI = SI.getValNumInfo(0);
741 VNI = SI.getNextValue(0, 0, false, ls_->getVNInfoAllocator());
743 LiveInterval &RI = li_->getInterval(cur->reg);
744 // FIXME: This may be overly conservative.
745 SI.MergeRangesInAsValue(RI, VNI);
748 /// getConflictWeight - Return the number of conflicts between cur
749 /// live interval and defs and uses of Reg weighted by loop depthes.
751 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
752 MachineRegisterInfo *mri_,
753 const MachineLoopInfo *loopInfo) {
755 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
756 E = mri_->reg_end(); I != E; ++I) {
757 MachineInstr *MI = &*I;
758 if (cur->liveAt(li_->getInstructionIndex(MI))) {
759 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
760 Conflicts += powf(10.0f, (float)loopDepth);
766 /// findIntervalsToSpill - Determine the intervals to spill for the
767 /// specified interval. It's passed the physical registers whose spill
768 /// weight is the lowest among all the registers whose live intervals
769 /// conflict with the interval.
770 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
771 std::vector<std::pair<unsigned,float> > &Candidates,
773 SmallVector<LiveInterval*, 8> &SpillIntervals) {
774 // We have figured out the *best* register to spill. But there are other
775 // registers that are pretty good as well (spill weight within 3%). Spill
776 // the one that has fewest defs and uses that conflict with cur.
777 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
778 SmallVector<LiveInterval*, 8> SLIs[3];
781 errs() << "\tConsidering " << NumCands << " candidates: ";
782 for (unsigned i = 0; i != NumCands; ++i)
783 errs() << tri_->getName(Candidates[i].first) << " ";
787 // Calculate the number of conflicts of each candidate.
788 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
789 unsigned Reg = i->first->reg;
790 unsigned PhysReg = vrm_->getPhys(Reg);
791 if (!cur->overlapsFrom(*i->first, i->second))
793 for (unsigned j = 0; j < NumCands; ++j) {
794 unsigned Candidate = Candidates[j].first;
795 if (tri_->regsOverlap(PhysReg, Candidate)) {
797 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
798 SLIs[j].push_back(i->first);
803 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
804 unsigned Reg = i->first->reg;
805 unsigned PhysReg = vrm_->getPhys(Reg);
806 if (!cur->overlapsFrom(*i->first, i->second-1))
808 for (unsigned j = 0; j < NumCands; ++j) {
809 unsigned Candidate = Candidates[j].first;
810 if (tri_->regsOverlap(PhysReg, Candidate)) {
812 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
813 SLIs[j].push_back(i->first);
818 // Which is the best candidate?
819 unsigned BestCandidate = 0;
820 float MinConflicts = Conflicts[0];
821 for (unsigned i = 1; i != NumCands; ++i) {
822 if (Conflicts[i] < MinConflicts) {
824 MinConflicts = Conflicts[i];
828 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
829 std::back_inserter(SpillIntervals));
833 struct WeightCompare {
834 typedef std::pair<unsigned, float> RegWeightPair;
835 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
836 return LHS.second < RHS.second;
841 static bool weightsAreClose(float w1, float w2) {
845 float diff = w1 - w2;
846 if (diff <= 0.02f) // Within 0.02f
848 return (diff / w2) <= 0.05f; // Within 5%.
851 LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
852 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
853 if (I == NextReloadMap.end())
855 return &li_->getInterval(I->second);
858 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
859 bool isNew = DowngradedRegs.insert(Reg);
860 isNew = isNew; // Silence compiler warning.
861 assert(isNew && "Multiple reloads holding the same register?");
862 DowngradeMap.insert(std::make_pair(li->reg, Reg));
863 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
864 isNew = DowngradedRegs.insert(*AS);
865 isNew = isNew; // Silence compiler warning.
866 assert(isNew && "Multiple reloads holding the same register?");
867 DowngradeMap.insert(std::make_pair(li->reg, *AS));
872 void RALinScan::UpgradeRegister(unsigned Reg) {
874 DowngradedRegs.erase(Reg);
875 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
876 DowngradedRegs.erase(*AS);
882 bool operator()(LiveInterval* A, LiveInterval* B) {
883 return A->beginNumber() < B->beginNumber();
888 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
890 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
891 DEBUG(errs() << "\tallocating current interval: ");
893 // This is an implicitly defined live interval, just assign any register.
894 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
896 unsigned physReg = vrm_->getRegAllocPref(cur->reg);
898 physReg = *RC->allocation_order_begin(*mf_);
899 DEBUG(errs() << tri_->getName(physReg) << '\n');
900 // Note the register is not really in use.
901 vrm_->assignVirt2Phys(cur->reg, physReg);
907 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
908 unsigned StartPosition = cur->beginNumber();
909 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
911 // If start of this live interval is defined by a move instruction and its
912 // source is assigned a physical register that is compatible with the target
913 // register class, then we should try to assign it the same register.
914 // This can happen when the move is from a larger register class to a smaller
915 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
916 if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
917 VNInfo *vni = cur->begin()->valno;
918 if (vni->def && !vni->isUnused() && vni->isDefAccurate()) {
919 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
920 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
922 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
924 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
926 else if (vrm_->isAssignedReg(SrcReg))
927 Reg = vrm_->getPhys(SrcReg);
930 Reg = tri_->getSubReg(Reg, SrcSubReg);
932 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
933 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
934 mri_->setRegAllocationHint(cur->reg, 0, Reg);
940 // For every interval in inactive we overlap with, mark the
941 // register as not free and update spill weights.
942 for (IntervalPtrs::const_iterator i = inactive_.begin(),
943 e = inactive_.end(); i != e; ++i) {
944 unsigned Reg = i->first->reg;
945 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
946 "Can only allocate virtual registers!");
947 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
948 // If this is not in a related reg class to the register we're allocating,
950 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
951 cur->overlapsFrom(*i->first, i->second-1)) {
952 Reg = vrm_->getPhys(Reg);
954 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
958 // Speculatively check to see if we can get a register right now. If not,
959 // we know we won't be able to by adding more constraints. If so, we can
960 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
961 // is very bad (it contains all callee clobbered registers for any functions
962 // with a call), so we want to avoid doing that if possible.
963 unsigned physReg = getFreePhysReg(cur);
964 unsigned BestPhysReg = physReg;
966 // We got a register. However, if it's in the fixed_ list, we might
967 // conflict with it. Check to see if we conflict with it or any of its
969 SmallSet<unsigned, 8> RegAliases;
970 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
971 RegAliases.insert(*AS);
973 bool ConflictsWithFixed = false;
974 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
975 IntervalPtr &IP = fixed_[i];
976 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
977 // Okay, this reg is on the fixed list. Check to see if we actually
979 LiveInterval *I = IP.first;
980 if (I->endNumber() > StartPosition) {
981 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
983 if (II != I->begin() && II->start > StartPosition)
985 if (cur->overlapsFrom(*I, II)) {
986 ConflictsWithFixed = true;
993 // Okay, the register picked by our speculative getFreePhysReg call turned
994 // out to be in use. Actually add all of the conflicting fixed registers to
995 // regUse_ so we can do an accurate query.
996 if (ConflictsWithFixed) {
997 // For every interval in fixed we overlap with, mark the register as not
998 // free and update spill weights.
999 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1000 IntervalPtr &IP = fixed_[i];
1001 LiveInterval *I = IP.first;
1003 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
1004 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1005 I->endNumber() > StartPosition) {
1006 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1008 if (II != I->begin() && II->start > StartPosition)
1010 if (cur->overlapsFrom(*I, II)) {
1011 unsigned reg = I->reg;
1013 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
1018 // Using the newly updated regUse_ object, which includes conflicts in the
1019 // future, see if there are any registers available.
1020 physReg = getFreePhysReg(cur);
1024 // Restore the physical register tracker, removing information about the
1028 // If we find a free register, we are done: assign this virtual to
1029 // the free physical register and add this interval to the active
1032 DEBUG(errs() << tri_->getName(physReg) << '\n');
1033 vrm_->assignVirt2Phys(cur->reg, physReg);
1035 active_.push_back(std::make_pair(cur, cur->begin()));
1036 handled_.push_back(cur);
1038 // "Upgrade" the physical register since it has been allocated.
1039 UpgradeRegister(physReg);
1040 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1041 // "Downgrade" physReg to try to keep physReg from being allocated until
1042 // the next reload from the same SS is allocated.
1043 mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg);
1044 DowngradeRegister(cur, physReg);
1048 DEBUG(errs() << "no free registers\n");
1050 // Compile the spill weights into an array that is better for scanning.
1051 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
1052 for (std::vector<std::pair<unsigned, float> >::iterator
1053 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
1054 updateSpillWeights(SpillWeights, I->first, I->second, RC);
1056 // for each interval in active, update spill weights.
1057 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1059 unsigned reg = i->first->reg;
1060 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1061 "Can only allocate virtual registers!");
1062 reg = vrm_->getPhys(reg);
1063 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
1066 DEBUG(errs() << "\tassigning stack slot at interval "<< *cur << ":\n");
1068 // Find a register to spill.
1069 float minWeight = HUGE_VALF;
1070 unsigned minReg = 0;
1073 std::vector<std::pair<unsigned,float> > RegsWeights;
1074 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1075 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1076 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1078 float regWeight = SpillWeights[reg];
1079 if (minWeight > regWeight)
1081 RegsWeights.push_back(std::make_pair(reg, regWeight));
1084 // If we didn't find a register that is spillable, try aliases?
1086 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1087 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1089 // No need to worry about if the alias register size < regsize of RC.
1090 // We are going to spill all registers that alias it anyway.
1091 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1092 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
1096 // Sort all potential spill candidates by weight.
1097 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare());
1098 minReg = RegsWeights[0].first;
1099 minWeight = RegsWeights[0].second;
1100 if (minWeight == HUGE_VALF) {
1101 // All registers must have inf weight. Just grab one!
1102 minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
1103 if (cur->weight == HUGE_VALF ||
1104 li_->getApproximateInstructionCount(*cur) == 0) {
1105 // Spill a physical register around defs and uses.
1106 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
1107 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1108 // in fixed_. Reset them.
1109 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1110 IntervalPtr &IP = fixed_[i];
1111 LiveInterval *I = IP.first;
1112 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1113 IP.second = I->advanceTo(I->begin(), StartPosition);
1116 DowngradedRegs.clear();
1117 assignRegOrStackSlotAtInterval(cur);
1119 llvm_report_error("Ran out of registers during register allocation!");
1125 // Find up to 3 registers to consider as spill candidates.
1126 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1127 while (LastCandidate > 1) {
1128 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1134 errs() << "\t\tregister(s) with min weight(s): ";
1136 for (unsigned i = 0; i != LastCandidate; ++i)
1137 errs() << tri_->getName(RegsWeights[i].first)
1138 << " (" << RegsWeights[i].second << ")\n";
1141 // If the current has the minimum weight, we need to spill it and
1142 // add any added intervals back to unhandled, and restart
1144 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
1145 DEBUG(errs() << "\t\t\tspilling(c): " << *cur << '\n');
1146 SmallVector<LiveInterval*, 8> spillIs;
1147 std::vector<LiveInterval*> added;
1149 if (!NewSpillFramework) {
1150 added = li_->addIntervalsForSpills(*cur, spillIs, loopInfo, *vrm_);
1152 added = spiller_->spill(cur);
1155 std::sort(added.begin(), added.end(), LISorter());
1156 addStackInterval(cur, ls_, li_, mri_, *vrm_);
1158 return; // Early exit if all spills were folded.
1160 // Merge added with unhandled. Note that we have already sorted
1161 // intervals returned by addIntervalsForSpills by their starting
1163 // This also update the NextReloadMap. That is, it adds mapping from a
1164 // register defined by a reload from SS to the next reload from SS in the
1165 // same basic block.
1166 MachineBasicBlock *LastReloadMBB = 0;
1167 LiveInterval *LastReload = 0;
1168 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1169 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1170 LiveInterval *ReloadLi = added[i];
1171 if (ReloadLi->weight == HUGE_VALF &&
1172 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1173 unsigned ReloadIdx = ReloadLi->beginNumber();
1174 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1175 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1176 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1177 // Last reload of same SS is in the same MBB. We want to try to
1178 // allocate both reloads the same register and make sure the reg
1179 // isn't clobbered in between if at all possible.
1180 assert(LastReload->beginNumber() < ReloadIdx);
1181 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1183 LastReloadMBB = ReloadMBB;
1184 LastReload = ReloadLi;
1185 LastReloadSS = ReloadSS;
1187 unhandled_.push(ReloadLi);
1194 // Push the current interval back to unhandled since we are going
1195 // to re-run at least this iteration. Since we didn't modify it it
1196 // should go back right in the front of the list
1197 unhandled_.push(cur);
1199 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
1200 "did not choose a register to spill?");
1202 // We spill all intervals aliasing the register with
1203 // minimum weight, rollback to the interval with the earliest
1204 // start point and let the linear scan algorithm run again
1205 SmallVector<LiveInterval*, 8> spillIs;
1207 // Determine which intervals have to be spilled.
1208 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1210 // Set of spilled vregs (used later to rollback properly)
1211 SmallSet<unsigned, 8> spilled;
1213 // The earliest start of a Spilled interval indicates up to where
1214 // in handled we need to roll back
1216 LiveInterval *earliestStartInterval = cur;
1218 // Spill live intervals of virtual regs mapped to the physical register we
1219 // want to clear (and its aliases). We only spill those that overlap with the
1220 // current interval as the rest do not affect its allocation. we also keep
1221 // track of the earliest start of all spilled live intervals since this will
1222 // mark our rollback point.
1223 std::vector<LiveInterval*> added;
1224 while (!spillIs.empty()) {
1225 LiveInterval *sli = spillIs.back();
1227 DEBUG(errs() << "\t\t\tspilling(a): " << *sli << '\n');
1228 earliestStartInterval =
1229 (earliestStartInterval->beginNumber() < sli->beginNumber()) ?
1230 earliestStartInterval : sli;
1232 std::vector<LiveInterval*> newIs;
1233 if (!NewSpillFramework) {
1234 newIs = li_->addIntervalsForSpills(*sli, spillIs, loopInfo, *vrm_);
1236 newIs = spiller_->spill(sli);
1238 addStackInterval(sli, ls_, li_, mri_, *vrm_);
1239 std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
1240 spilled.insert(sli->reg);
1243 unsigned earliestStart = earliestStartInterval->beginNumber();
1245 DEBUG(errs() << "\t\trolling back to: " << earliestStart << '\n');
1247 // Scan handled in reverse order up to the earliest start of a
1248 // spilled live interval and undo each one, restoring the state of
1250 while (!handled_.empty()) {
1251 LiveInterval* i = handled_.back();
1252 // If this interval starts before t we are done.
1253 if (i->beginNumber() < earliestStart)
1255 DEBUG(errs() << "\t\t\tundo changes for: " << *i << '\n');
1256 handled_.pop_back();
1258 // When undoing a live interval allocation we must know if it is active or
1259 // inactive to properly update regUse_ and the VirtRegMap.
1260 IntervalPtrs::iterator it;
1261 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
1263 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1264 if (!spilled.count(i->reg))
1266 delRegUse(vrm_->getPhys(i->reg));
1267 vrm_->clearVirt(i->reg);
1268 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
1269 inactive_.erase(it);
1270 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1271 if (!spilled.count(i->reg))
1273 vrm_->clearVirt(i->reg);
1275 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
1276 "Can only allocate virtual registers!");
1277 vrm_->clearVirt(i->reg);
1281 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1282 if (ii == DowngradeMap.end())
1283 // It interval has a preference, it must be defined by a copy. Clear the
1284 // preference now since the source interval allocation may have been
1286 mri_->setRegAllocationHint(i->reg, 0, 0);
1288 UpgradeRegister(ii->second);
1292 // Rewind the iterators in the active, inactive, and fixed lists back to the
1293 // point we reverted to.
1294 RevertVectorIteratorsTo(active_, earliestStart);
1295 RevertVectorIteratorsTo(inactive_, earliestStart);
1296 RevertVectorIteratorsTo(fixed_, earliestStart);
1298 // Scan the rest and undo each interval that expired after t and
1299 // insert it in active (the next iteration of the algorithm will
1300 // put it in inactive if required)
1301 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1302 LiveInterval *HI = handled_[i];
1303 if (!HI->expiredAt(earliestStart) &&
1304 HI->expiredAt(cur->beginNumber())) {
1305 DEBUG(errs() << "\t\t\tundo changes for: " << *HI << '\n');
1306 active_.push_back(std::make_pair(HI, HI->begin()));
1307 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1308 addRegUse(vrm_->getPhys(HI->reg));
1312 // Merge added with unhandled.
1313 // This also update the NextReloadMap. That is, it adds mapping from a
1314 // register defined by a reload from SS to the next reload from SS in the
1315 // same basic block.
1316 MachineBasicBlock *LastReloadMBB = 0;
1317 LiveInterval *LastReload = 0;
1318 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1319 std::sort(added.begin(), added.end(), LISorter());
1320 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1321 LiveInterval *ReloadLi = added[i];
1322 if (ReloadLi->weight == HUGE_VALF &&
1323 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1324 unsigned ReloadIdx = ReloadLi->beginNumber();
1325 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1326 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1327 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1328 // Last reload of same SS is in the same MBB. We want to try to
1329 // allocate both reloads the same register and make sure the reg
1330 // isn't clobbered in between if at all possible.
1331 assert(LastReload->beginNumber() < ReloadIdx);
1332 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1334 LastReloadMBB = ReloadMBB;
1335 LastReload = ReloadLi;
1336 LastReloadSS = ReloadSS;
1338 unhandled_.push(ReloadLi);
1342 unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
1343 const TargetRegisterClass *RC,
1344 unsigned MaxInactiveCount,
1345 SmallVector<unsigned, 256> &inactiveCounts,
1347 unsigned FreeReg = 0;
1348 unsigned FreeRegInactiveCount = 0;
1350 std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(cur->reg);
1351 // Resolve second part of the hint (if possible) given the current allocation.
1352 unsigned physReg = Hint.second;
1354 TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
1355 physReg = vrm_->getPhys(physReg);
1357 TargetRegisterClass::iterator I, E;
1358 tie(I, E) = tri_->getAllocationOrder(RC, Hint.first, physReg, *mf_);
1359 assert(I != E && "No allocatable register in this register class!");
1361 // Scan for the first available register.
1362 for (; I != E; ++I) {
1364 // Ignore "downgraded" registers.
1365 if (SkipDGRegs && DowngradedRegs.count(Reg))
1367 if (isRegAvail(Reg)) {
1369 if (FreeReg < inactiveCounts.size())
1370 FreeRegInactiveCount = inactiveCounts[FreeReg];
1372 FreeRegInactiveCount = 0;
1377 // If there are no free regs, or if this reg has the max inactive count,
1378 // return this register.
1379 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount)
1382 // Continue scanning the registers, looking for the one with the highest
1383 // inactive count. Alkis found that this reduced register pressure very
1384 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1386 for (; I != E; ++I) {
1388 // Ignore "downgraded" registers.
1389 if (SkipDGRegs && DowngradedRegs.count(Reg))
1391 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1392 FreeRegInactiveCount < inactiveCounts[Reg]) {
1394 FreeRegInactiveCount = inactiveCounts[Reg];
1395 if (FreeRegInactiveCount == MaxInactiveCount)
1396 break; // We found the one with the max inactive count.
1403 /// getFreePhysReg - return a free physical register for this virtual register
1404 /// interval if we have one, otherwise return 0.
1405 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1406 SmallVector<unsigned, 256> inactiveCounts;
1407 unsigned MaxInactiveCount = 0;
1409 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1410 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1412 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1414 unsigned reg = i->first->reg;
1415 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1416 "Can only allocate virtual registers!");
1418 // If this is not in a related reg class to the register we're allocating,
1420 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1421 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1422 reg = vrm_->getPhys(reg);
1423 if (inactiveCounts.size() <= reg)
1424 inactiveCounts.resize(reg+1);
1425 ++inactiveCounts[reg];
1426 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1430 // If copy coalescer has assigned a "preferred" register, check if it's
1432 unsigned Preference = vrm_->getRegAllocPref(cur->reg);
1434 DEBUG(errs() << "(preferred: " << tri_->getName(Preference) << ") ");
1435 if (isRegAvail(Preference) &&
1436 RC->contains(Preference))
1440 if (!DowngradedRegs.empty()) {
1441 unsigned FreeReg = getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts,
1446 return getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts, false);
1449 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1450 return new RALinScan();