1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "VirtRegMap.h"
16 #include "VirtRegRewriter.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/CalcSpillWeights.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/LiveStackAnalysis.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/RegAllocRegistry.h"
28 #include "llvm/CodeGen/RegisterCoalescer.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/ADT/EquivalenceClasses.h"
34 #include "llvm/ADT/SmallSet.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/ADT/STLExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
48 STATISTIC(NumIters , "Number of iterations performed");
49 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
50 STATISTIC(NumCoalesce, "Number of copies coalesced");
51 STATISTIC(NumDowngrade, "Number of registers downgraded");
54 NewHeuristic("new-spilling-heuristic",
55 cl::desc("Use new spilling heuristic"),
56 cl::init(false), cl::Hidden);
59 PreSplitIntervals("pre-alloc-split",
60 cl::desc("Pre-register allocation live interval splitting"),
61 cl::init(false), cl::Hidden);
64 TrivCoalesceEnds("trivial-coalesce-ends",
65 cl::desc("Attempt trivial coalescing of interval ends"),
66 cl::init(false), cl::Hidden);
68 static RegisterRegAlloc
69 linearscanRegAlloc("linearscan", "linear scan register allocator",
70 createLinearScanRegisterAllocator);
73 // When we allocate a register, add it to a fixed-size queue of
74 // registers to skip in subsequent allocations. This trades a small
75 // amount of register pressure and increased spills for flexibility in
76 // the post-pass scheduler.
78 // Note that in a the number of registers used for reloading spills
79 // will be one greater than the value of this option.
81 // One big limitation of this is that it doesn't differentiate between
82 // different register classes. So on x86-64, if there is xmm register
83 // pressure, it can caused fewer GPRs to be held in the queue.
84 static cl::opt<unsigned>
85 NumRecentlyUsedRegs("linearscan-skip-count",
86 cl::desc("Number of registers for linearscan to remember"
91 struct RALinScan : public MachineFunctionPass {
93 RALinScan() : MachineFunctionPass(ID) {
94 // Initialize the queue to record recently-used registers.
95 if (NumRecentlyUsedRegs > 0)
96 RecentRegs.resize(NumRecentlyUsedRegs, 0);
97 RecentNext = RecentRegs.begin();
100 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
101 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
103 /// RelatedRegClasses - This structure is built the first time a function is
104 /// compiled, and keeps track of which register classes have registers that
105 /// belong to multiple classes or have aliases that are in other classes.
106 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
107 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
109 // NextReloadMap - For each register in the map, it maps to the another
110 // register which is defined by a reload from the same stack slot and
111 // both reloads are in the same basic block.
112 DenseMap<unsigned, unsigned> NextReloadMap;
114 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
115 // un-favored for allocation.
116 SmallSet<unsigned, 8> DowngradedRegs;
118 // DowngradeMap - A map from virtual registers to physical registers being
119 // downgraded for the virtual registers.
120 DenseMap<unsigned, unsigned> DowngradeMap;
122 MachineFunction* mf_;
123 MachineRegisterInfo* mri_;
124 const TargetMachine* tm_;
125 const TargetRegisterInfo* tri_;
126 const TargetInstrInfo* tii_;
127 BitVector allocatableRegs_;
128 BitVector reservedRegs_;
131 MachineLoopInfo *loopInfo;
133 /// handled_ - Intervals are added to the handled_ set in the order of their
134 /// start value. This is uses for backtracking.
135 std::vector<LiveInterval*> handled_;
137 /// fixed_ - Intervals that correspond to machine registers.
141 /// active_ - Intervals that are currently being processed, and which have a
142 /// live range active for the current point.
143 IntervalPtrs active_;
145 /// inactive_ - Intervals that are currently being processed, but which have
146 /// a hold at the current point.
147 IntervalPtrs inactive_;
149 typedef std::priority_queue<LiveInterval*,
150 SmallVector<LiveInterval*, 64>,
151 greater_ptr<LiveInterval> > IntervalHeap;
152 IntervalHeap unhandled_;
154 /// regUse_ - Tracks register usage.
155 SmallVector<unsigned, 32> regUse_;
156 SmallVector<unsigned, 32> regUseBackUp_;
158 /// vrm_ - Tracks register assignments.
161 std::auto_ptr<VirtRegRewriter> rewriter_;
163 std::auto_ptr<Spiller> spiller_;
165 // The queue of recently-used registers.
166 SmallVector<unsigned, 4> RecentRegs;
167 SmallVector<unsigned, 4>::iterator RecentNext;
169 // Record that we just picked this register.
170 void recordRecentlyUsed(unsigned reg) {
171 assert(reg != 0 && "Recently used register is NOREG!");
172 if (!RecentRegs.empty()) {
174 if (RecentNext == RecentRegs.end())
175 RecentNext = RecentRegs.begin();
180 virtual const char* getPassName() const {
181 return "Linear Scan Register Allocator";
184 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
185 AU.setPreservesCFG();
186 AU.addRequired<LiveIntervals>();
187 AU.addPreserved<SlotIndexes>();
189 AU.addRequiredID(StrongPHIEliminationID);
190 // Make sure PassManager knows which analyses to make available
191 // to coalescing and which analyses coalescing invalidates.
192 AU.addRequiredTransitive<RegisterCoalescer>();
193 AU.addRequired<CalculateSpillWeights>();
194 if (PreSplitIntervals)
195 AU.addRequiredID(PreAllocSplittingID);
196 AU.addRequired<LiveStacks>();
197 AU.addPreserved<LiveStacks>();
198 AU.addRequired<MachineLoopInfo>();
199 AU.addPreserved<MachineLoopInfo>();
200 AU.addRequired<VirtRegMap>();
201 AU.addPreserved<VirtRegMap>();
202 AU.addPreservedID(MachineDominatorsID);
203 MachineFunctionPass::getAnalysisUsage(AU);
206 /// runOnMachineFunction - register allocate the whole function
207 bool runOnMachineFunction(MachineFunction&);
209 // Determine if we skip this register due to its being recently used.
210 bool isRecentlyUsed(unsigned reg) const {
211 return std::find(RecentRegs.begin(), RecentRegs.end(), reg) !=
216 /// linearScan - the linear scan algorithm
219 /// initIntervalSets - initialize the interval sets.
221 void initIntervalSets();
223 /// processActiveIntervals - expire old intervals and move non-overlapping
224 /// ones to the inactive list.
225 void processActiveIntervals(SlotIndex CurPoint);
227 /// processInactiveIntervals - expire old intervals and move overlapping
228 /// ones to the active list.
229 void processInactiveIntervals(SlotIndex CurPoint);
231 /// hasNextReloadInterval - Return the next liveinterval that's being
232 /// defined by a reload from the same SS as the specified one.
233 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
235 /// DowngradeRegister - Downgrade a register for allocation.
236 void DowngradeRegister(LiveInterval *li, unsigned Reg);
238 /// UpgradeRegister - Upgrade a register for allocation.
239 void UpgradeRegister(unsigned Reg);
241 /// assignRegOrStackSlotAtInterval - assign a register if one
242 /// is available, or spill.
243 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
245 void updateSpillWeights(std::vector<float> &Weights,
246 unsigned reg, float weight,
247 const TargetRegisterClass *RC);
249 /// findIntervalsToSpill - Determine the intervals to spill for the
250 /// specified interval. It's passed the physical registers whose spill
251 /// weight is the lowest among all the registers whose live intervals
252 /// conflict with the interval.
253 void findIntervalsToSpill(LiveInterval *cur,
254 std::vector<std::pair<unsigned,float> > &Candidates,
256 SmallVector<LiveInterval*, 8> &SpillIntervals);
258 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
259 /// try to allocate the definition to the same register as the source,
260 /// if the register is not defined during the life time of the interval.
261 /// This eliminates a copy, and is used to coalesce copies which were not
262 /// coalesced away before allocation either due to dest and src being in
263 /// different register classes or because the coalescer was overly
265 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
268 /// Register usage / availability tracking helpers.
272 regUse_.resize(tri_->getNumRegs(), 0);
273 regUseBackUp_.resize(tri_->getNumRegs(), 0);
276 void finalizeRegUses() {
278 // Verify all the registers are "freed".
280 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
281 if (regUse_[i] != 0) {
282 dbgs() << tri_->getName(i) << " is still in use!\n";
290 regUseBackUp_.clear();
293 void addRegUse(unsigned physReg) {
294 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
295 "should be physical register!");
297 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
301 void delRegUse(unsigned physReg) {
302 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
303 "should be physical register!");
304 assert(regUse_[physReg] != 0);
306 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
307 assert(regUse_[*as] != 0);
312 bool isRegAvail(unsigned physReg) const {
313 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
314 "should be physical register!");
315 return regUse_[physReg] == 0;
318 void backUpRegUses() {
319 regUseBackUp_ = regUse_;
322 void restoreRegUses() {
323 regUse_ = regUseBackUp_;
327 /// Register handling helpers.
330 /// getFreePhysReg - return a free physical register for this virtual
331 /// register interval if we have one, otherwise return 0.
332 unsigned getFreePhysReg(LiveInterval* cur);
333 unsigned getFreePhysReg(LiveInterval* cur,
334 const TargetRegisterClass *RC,
335 unsigned MaxInactiveCount,
336 SmallVector<unsigned, 256> &inactiveCounts,
339 /// getFirstNonReservedPhysReg - return the first non-reserved physical
340 /// register in the register class.
341 unsigned getFirstNonReservedPhysReg(const TargetRegisterClass *RC) {
342 TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_);
343 TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_);
344 while (i != aoe && reservedRegs_.test(*i))
346 assert(i != aoe && "All registers reserved?!");
350 void ComputeRelatedRegClasses();
352 template <typename ItTy>
353 void printIntervals(const char* const str, ItTy i, ItTy e) const {
356 dbgs() << str << " intervals:\n";
358 for (; i != e; ++i) {
359 dbgs() << "\t" << *i->first << " -> ";
361 unsigned reg = i->first->reg;
362 if (TargetRegisterInfo::isVirtualRegister(reg))
363 reg = vrm_->getPhys(reg);
365 dbgs() << tri_->getName(reg) << '\n';
370 char RALinScan::ID = 0;
373 INITIALIZE_PASS(RALinScan, "linearscan-regalloc",
374 "Linear Scan Register Allocator", false, false);
376 void RALinScan::ComputeRelatedRegClasses() {
377 // First pass, add all reg classes to the union, and determine at least one
378 // reg class that each register is in.
379 bool HasAliases = false;
380 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
381 E = tri_->regclass_end(); RCI != E; ++RCI) {
382 RelatedRegClasses.insert(*RCI);
383 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
385 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
387 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
389 // Already processed this register. Just make sure we know that
390 // multiple register classes share a register.
391 RelatedRegClasses.unionSets(PRC, *RCI);
398 // Second pass, now that we know conservatively what register classes each reg
399 // belongs to, add info about aliases. We don't need to do this for targets
400 // without register aliases.
402 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
403 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
405 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
406 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
409 /// attemptTrivialCoalescing - If a simple interval is defined by a copy, try
410 /// allocate the definition the same register as the source register if the
411 /// register is not defined during live time of the interval. If the interval is
412 /// killed by a copy, try to use the destination register. This eliminates a
413 /// copy. This is used to coalesce copies which were not coalesced away before
414 /// allocation either due to dest and src being in different register classes or
415 /// because the coalescer was overly conservative.
416 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
417 unsigned Preference = vrm_->getRegAllocPref(cur.reg);
418 if ((Preference && Preference == Reg) || !cur.containsOneValue())
421 // We cannot handle complicated live ranges. Simple linear stuff only.
422 if (cur.ranges.size() != 1)
425 const LiveRange &range = cur.ranges.front();
427 VNInfo *vni = range.valno;
433 MachineInstr *CopyMI;
434 if (vni->def != SlotIndex() && vni->isDefAccurate() &&
435 (CopyMI = li_->getInstructionFromIndex(vni->def)) && CopyMI->isCopy())
436 // Defined by a copy, try to extend SrcReg forward
437 CandReg = CopyMI->getOperand(1).getReg();
438 else if (TrivCoalesceEnds &&
439 (CopyMI = li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
440 CopyMI->isCopy() && cur.reg == CopyMI->getOperand(1).getReg())
441 // Only used by a copy, try to extend DstReg backwards
442 CandReg = CopyMI->getOperand(0).getReg();
447 if (TargetRegisterInfo::isVirtualRegister(CandReg)) {
448 if (!vrm_->isAssignedReg(CandReg))
450 CandReg = vrm_->getPhys(CandReg);
455 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
456 if (!RC->contains(CandReg))
459 if (li_->conflictsWithPhysReg(cur, *vrm_, CandReg))
463 DEBUG(dbgs() << "Coalescing: " << cur << " -> " << tri_->getName(CandReg)
465 vrm_->clearVirt(cur.reg);
466 vrm_->assignVirt2Phys(cur.reg, CandReg);
472 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
474 mri_ = &fn.getRegInfo();
475 tm_ = &fn.getTarget();
476 tri_ = tm_->getRegisterInfo();
477 tii_ = tm_->getInstrInfo();
478 allocatableRegs_ = tri_->getAllocatableSet(fn);
479 reservedRegs_ = tri_->getReservedRegs(fn);
480 li_ = &getAnalysis<LiveIntervals>();
481 ls_ = &getAnalysis<LiveStacks>();
482 loopInfo = &getAnalysis<MachineLoopInfo>();
484 // We don't run the coalescer here because we have no reason to
485 // interact with it. If the coalescer requires interaction, it
486 // won't do anything. If it doesn't require interaction, we assume
487 // it was run as a separate pass.
489 // If this is the first function compiled, compute the related reg classes.
490 if (RelatedRegClasses.empty())
491 ComputeRelatedRegClasses();
493 // Also resize register usage trackers.
496 vrm_ = &getAnalysis<VirtRegMap>();
497 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
499 spiller_.reset(createSpiller(*this, *mf_, *vrm_));
505 // Rewrite spill code and update the PhysRegsUsed set.
506 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
508 assert(unhandled_.empty() && "Unhandled live intervals remain!");
516 NextReloadMap.clear();
517 DowngradedRegs.clear();
518 DowngradeMap.clear();
524 /// initIntervalSets - initialize the interval sets.
526 void RALinScan::initIntervalSets()
528 assert(unhandled_.empty() && fixed_.empty() &&
529 active_.empty() && inactive_.empty() &&
530 "interval sets should be empty on initialization");
532 handled_.reserve(li_->getNumIntervals());
534 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
535 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
536 if (!i->second->empty()) {
537 mri_->setPhysRegUsed(i->second->reg);
538 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
541 if (i->second->empty()) {
542 assignRegOrStackSlotAtInterval(i->second);
545 unhandled_.push(i->second);
550 void RALinScan::linearScan() {
551 // linear scan algorithm
553 dbgs() << "********** LINEAR SCAN **********\n"
554 << "********** Function: "
555 << mf_->getFunction()->getName() << '\n';
556 printIntervals("fixed", fixed_.begin(), fixed_.end());
559 while (!unhandled_.empty()) {
560 // pick the interval with the earliest start point
561 LiveInterval* cur = unhandled_.top();
564 DEBUG(dbgs() << "\n*** CURRENT ***: " << *cur << '\n');
566 assert(!cur->empty() && "Empty interval in unhandled set.");
568 processActiveIntervals(cur->beginIndex());
569 processInactiveIntervals(cur->beginIndex());
571 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
572 "Can only allocate virtual registers!");
574 // Allocating a virtual register. try to find a free
575 // physical register or spill an interval (possibly this one) in order to
577 assignRegOrStackSlotAtInterval(cur);
580 printIntervals("active", active_.begin(), active_.end());
581 printIntervals("inactive", inactive_.begin(), inactive_.end());
585 // Expire any remaining active intervals
586 while (!active_.empty()) {
587 IntervalPtr &IP = active_.back();
588 unsigned reg = IP.first->reg;
589 DEBUG(dbgs() << "\tinterval " << *IP.first << " expired\n");
590 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
591 "Can only allocate virtual registers!");
592 reg = vrm_->getPhys(reg);
597 // Expire any remaining inactive intervals
599 for (IntervalPtrs::reverse_iterator
600 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
601 dbgs() << "\tinterval " << *i->first << " expired\n";
605 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
606 MachineFunction::iterator EntryMBB = mf_->begin();
607 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
608 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
609 LiveInterval &cur = *i->second;
611 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
614 else if (vrm_->isAssignedReg(cur.reg))
615 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
618 // Ignore splited live intervals.
619 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
622 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
624 const LiveRange &LR = *I;
625 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
626 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
627 if (LiveInMBBs[i] != EntryMBB) {
628 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
629 "Adding a virtual register to livein set?");
630 LiveInMBBs[i]->addLiveIn(Reg);
637 DEBUG(dbgs() << *vrm_);
639 // Look for physical registers that end up not being allocated even though
640 // register allocator had to spill other registers in its register class.
641 if (ls_->getNumIntervals() == 0)
643 if (!vrm_->FindUnusedRegisters(li_))
647 /// processActiveIntervals - expire old intervals and move non-overlapping ones
648 /// to the inactive list.
649 void RALinScan::processActiveIntervals(SlotIndex CurPoint)
651 DEBUG(dbgs() << "\tprocessing active intervals:\n");
653 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
654 LiveInterval *Interval = active_[i].first;
655 LiveInterval::iterator IntervalPos = active_[i].second;
656 unsigned reg = Interval->reg;
658 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
660 if (IntervalPos == Interval->end()) { // Remove expired intervals.
661 DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
662 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
663 "Can only allocate virtual registers!");
664 reg = vrm_->getPhys(reg);
667 // Pop off the end of the list.
668 active_[i] = active_.back();
672 } else if (IntervalPos->start > CurPoint) {
673 // Move inactive intervals to inactive list.
674 DEBUG(dbgs() << "\t\tinterval " << *Interval << " inactive\n");
675 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
676 "Can only allocate virtual registers!");
677 reg = vrm_->getPhys(reg);
680 inactive_.push_back(std::make_pair(Interval, IntervalPos));
682 // Pop off the end of the list.
683 active_[i] = active_.back();
687 // Otherwise, just update the iterator position.
688 active_[i].second = IntervalPos;
693 /// processInactiveIntervals - expire old intervals and move overlapping
694 /// ones to the active list.
695 void RALinScan::processInactiveIntervals(SlotIndex CurPoint)
697 DEBUG(dbgs() << "\tprocessing inactive intervals:\n");
699 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
700 LiveInterval *Interval = inactive_[i].first;
701 LiveInterval::iterator IntervalPos = inactive_[i].second;
702 unsigned reg = Interval->reg;
704 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
706 if (IntervalPos == Interval->end()) { // remove expired intervals.
707 DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
709 // Pop off the end of the list.
710 inactive_[i] = inactive_.back();
711 inactive_.pop_back();
713 } else if (IntervalPos->start <= CurPoint) {
714 // move re-activated intervals in active list
715 DEBUG(dbgs() << "\t\tinterval " << *Interval << " active\n");
716 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
717 "Can only allocate virtual registers!");
718 reg = vrm_->getPhys(reg);
721 active_.push_back(std::make_pair(Interval, IntervalPos));
723 // Pop off the end of the list.
724 inactive_[i] = inactive_.back();
725 inactive_.pop_back();
728 // Otherwise, just update the iterator position.
729 inactive_[i].second = IntervalPos;
734 /// updateSpillWeights - updates the spill weights of the specifed physical
735 /// register and its weight.
736 void RALinScan::updateSpillWeights(std::vector<float> &Weights,
737 unsigned reg, float weight,
738 const TargetRegisterClass *RC) {
739 SmallSet<unsigned, 4> Processed;
740 SmallSet<unsigned, 4> SuperAdded;
741 SmallVector<unsigned, 4> Supers;
742 Weights[reg] += weight;
743 Processed.insert(reg);
744 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
745 Weights[*as] += weight;
746 Processed.insert(*as);
747 if (tri_->isSubRegister(*as, reg) &&
748 SuperAdded.insert(*as) &&
750 Supers.push_back(*as);
754 // If the alias is a super-register, and the super-register is in the
755 // register class we are trying to allocate. Then add the weight to all
756 // sub-registers of the super-register even if they are not aliases.
757 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
758 // bl should get the same spill weight otherwise it will be choosen
759 // as a spill candidate since spilling bh doesn't make ebx available.
760 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
761 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
762 if (!Processed.count(*sr))
763 Weights[*sr] += weight;
768 RALinScan::IntervalPtrs::iterator
769 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
770 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
772 if (I->first == LI) return I;
776 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V,
778 for (unsigned i = 0, e = V.size(); i != e; ++i) {
779 RALinScan::IntervalPtr &IP = V[i];
780 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
782 if (I != IP.first->begin()) --I;
787 /// addStackInterval - Create a LiveInterval for stack if the specified live
788 /// interval has been spilled.
789 static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
791 MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
792 int SS = vrm_.getStackSlot(cur->reg);
793 if (SS == VirtRegMap::NO_STACK_SLOT)
796 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
797 LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
800 if (SI.hasAtLeastOneValue())
801 VNI = SI.getValNumInfo(0);
803 VNI = SI.getNextValue(SlotIndex(), 0, false,
804 ls_->getVNInfoAllocator());
806 LiveInterval &RI = li_->getInterval(cur->reg);
807 // FIXME: This may be overly conservative.
808 SI.MergeRangesInAsValue(RI, VNI);
811 /// getConflictWeight - Return the number of conflicts between cur
812 /// live interval and defs and uses of Reg weighted by loop depthes.
814 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
815 MachineRegisterInfo *mri_,
816 MachineLoopInfo *loopInfo) {
818 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
819 E = mri_->reg_end(); I != E; ++I) {
820 MachineInstr *MI = &*I;
821 if (cur->liveAt(li_->getInstructionIndex(MI))) {
822 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
823 Conflicts += std::pow(10.0f, (float)loopDepth);
829 /// findIntervalsToSpill - Determine the intervals to spill for the
830 /// specified interval. It's passed the physical registers whose spill
831 /// weight is the lowest among all the registers whose live intervals
832 /// conflict with the interval.
833 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
834 std::vector<std::pair<unsigned,float> > &Candidates,
836 SmallVector<LiveInterval*, 8> &SpillIntervals) {
837 // We have figured out the *best* register to spill. But there are other
838 // registers that are pretty good as well (spill weight within 3%). Spill
839 // the one that has fewest defs and uses that conflict with cur.
840 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
841 SmallVector<LiveInterval*, 8> SLIs[3];
844 dbgs() << "\tConsidering " << NumCands << " candidates: ";
845 for (unsigned i = 0; i != NumCands; ++i)
846 dbgs() << tri_->getName(Candidates[i].first) << " ";
850 // Calculate the number of conflicts of each candidate.
851 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
852 unsigned Reg = i->first->reg;
853 unsigned PhysReg = vrm_->getPhys(Reg);
854 if (!cur->overlapsFrom(*i->first, i->second))
856 for (unsigned j = 0; j < NumCands; ++j) {
857 unsigned Candidate = Candidates[j].first;
858 if (tri_->regsOverlap(PhysReg, Candidate)) {
860 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
861 SLIs[j].push_back(i->first);
866 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
867 unsigned Reg = i->first->reg;
868 unsigned PhysReg = vrm_->getPhys(Reg);
869 if (!cur->overlapsFrom(*i->first, i->second-1))
871 for (unsigned j = 0; j < NumCands; ++j) {
872 unsigned Candidate = Candidates[j].first;
873 if (tri_->regsOverlap(PhysReg, Candidate)) {
875 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
876 SLIs[j].push_back(i->first);
881 // Which is the best candidate?
882 unsigned BestCandidate = 0;
883 float MinConflicts = Conflicts[0];
884 for (unsigned i = 1; i != NumCands; ++i) {
885 if (Conflicts[i] < MinConflicts) {
887 MinConflicts = Conflicts[i];
891 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
892 std::back_inserter(SpillIntervals));
896 struct WeightCompare {
898 const RALinScan &Allocator;
901 WeightCompare(const RALinScan &Alloc) : Allocator(Alloc) {}
903 typedef std::pair<unsigned, float> RegWeightPair;
904 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
905 return LHS.second < RHS.second && !Allocator.isRecentlyUsed(LHS.first);
910 static bool weightsAreClose(float w1, float w2) {
914 float diff = w1 - w2;
915 if (diff <= 0.02f) // Within 0.02f
917 return (diff / w2) <= 0.05f; // Within 5%.
920 LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
921 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
922 if (I == NextReloadMap.end())
924 return &li_->getInterval(I->second);
927 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
928 bool isNew = DowngradedRegs.insert(Reg);
929 isNew = isNew; // Silence compiler warning.
930 assert(isNew && "Multiple reloads holding the same register?");
931 DowngradeMap.insert(std::make_pair(li->reg, Reg));
932 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
933 isNew = DowngradedRegs.insert(*AS);
934 isNew = isNew; // Silence compiler warning.
935 assert(isNew && "Multiple reloads holding the same register?");
936 DowngradeMap.insert(std::make_pair(li->reg, *AS));
941 void RALinScan::UpgradeRegister(unsigned Reg) {
943 DowngradedRegs.erase(Reg);
944 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
945 DowngradedRegs.erase(*AS);
951 bool operator()(LiveInterval* A, LiveInterval* B) {
952 return A->beginIndex() < B->beginIndex();
957 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
959 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
960 DEBUG(dbgs() << "\tallocating current interval: ");
962 // This is an implicitly defined live interval, just assign any register.
963 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
965 unsigned physReg = vrm_->getRegAllocPref(cur->reg);
967 physReg = getFirstNonReservedPhysReg(RC);
968 DEBUG(dbgs() << tri_->getName(physReg) << '\n');
969 // Note the register is not really in use.
970 vrm_->assignVirt2Phys(cur->reg, physReg);
976 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
977 SlotIndex StartPosition = cur->beginIndex();
978 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
980 // If start of this live interval is defined by a move instruction and its
981 // source is assigned a physical register that is compatible with the target
982 // register class, then we should try to assign it the same register.
983 // This can happen when the move is from a larger register class to a smaller
984 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
985 if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
986 VNInfo *vni = cur->begin()->valno;
987 if ((vni->def != SlotIndex()) && !vni->isUnused() &&
988 vni->isDefAccurate()) {
989 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
990 if (CopyMI && CopyMI->isCopy()) {
991 unsigned DstSubReg = CopyMI->getOperand(0).getSubReg();
992 unsigned SrcReg = CopyMI->getOperand(1).getReg();
993 unsigned SrcSubReg = CopyMI->getOperand(1).getSubReg();
995 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
997 else if (vrm_->isAssignedReg(SrcReg))
998 Reg = vrm_->getPhys(SrcReg);
1001 Reg = tri_->getSubReg(Reg, SrcSubReg);
1003 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
1004 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
1005 mri_->setRegAllocationHint(cur->reg, 0, Reg);
1011 // For every interval in inactive we overlap with, mark the
1012 // register as not free and update spill weights.
1013 for (IntervalPtrs::const_iterator i = inactive_.begin(),
1014 e = inactive_.end(); i != e; ++i) {
1015 unsigned Reg = i->first->reg;
1016 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
1017 "Can only allocate virtual registers!");
1018 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
1019 // If this is not in a related reg class to the register we're allocating,
1021 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1022 cur->overlapsFrom(*i->first, i->second-1)) {
1023 Reg = vrm_->getPhys(Reg);
1025 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
1029 // Speculatively check to see if we can get a register right now. If not,
1030 // we know we won't be able to by adding more constraints. If so, we can
1031 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
1032 // is very bad (it contains all callee clobbered registers for any functions
1033 // with a call), so we want to avoid doing that if possible.
1034 unsigned physReg = getFreePhysReg(cur);
1035 unsigned BestPhysReg = physReg;
1037 // We got a register. However, if it's in the fixed_ list, we might
1038 // conflict with it. Check to see if we conflict with it or any of its
1040 SmallSet<unsigned, 8> RegAliases;
1041 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
1042 RegAliases.insert(*AS);
1044 bool ConflictsWithFixed = false;
1045 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1046 IntervalPtr &IP = fixed_[i];
1047 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
1048 // Okay, this reg is on the fixed list. Check to see if we actually
1050 LiveInterval *I = IP.first;
1051 if (I->endIndex() > StartPosition) {
1052 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1054 if (II != I->begin() && II->start > StartPosition)
1056 if (cur->overlapsFrom(*I, II)) {
1057 ConflictsWithFixed = true;
1064 // Okay, the register picked by our speculative getFreePhysReg call turned
1065 // out to be in use. Actually add all of the conflicting fixed registers to
1066 // regUse_ so we can do an accurate query.
1067 if (ConflictsWithFixed) {
1068 // For every interval in fixed we overlap with, mark the register as not
1069 // free and update spill weights.
1070 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1071 IntervalPtr &IP = fixed_[i];
1072 LiveInterval *I = IP.first;
1074 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
1075 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1076 I->endIndex() > StartPosition) {
1077 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1079 if (II != I->begin() && II->start > StartPosition)
1081 if (cur->overlapsFrom(*I, II)) {
1082 unsigned reg = I->reg;
1084 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
1089 // Using the newly updated regUse_ object, which includes conflicts in the
1090 // future, see if there are any registers available.
1091 physReg = getFreePhysReg(cur);
1095 // Restore the physical register tracker, removing information about the
1099 // If we find a free register, we are done: assign this virtual to
1100 // the free physical register and add this interval to the active
1103 DEBUG(dbgs() << tri_->getName(physReg) << '\n');
1104 vrm_->assignVirt2Phys(cur->reg, physReg);
1106 active_.push_back(std::make_pair(cur, cur->begin()));
1107 handled_.push_back(cur);
1109 // "Upgrade" the physical register since it has been allocated.
1110 UpgradeRegister(physReg);
1111 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1112 // "Downgrade" physReg to try to keep physReg from being allocated until
1113 // the next reload from the same SS is allocated.
1114 mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg);
1115 DowngradeRegister(cur, physReg);
1119 DEBUG(dbgs() << "no free registers\n");
1121 // Compile the spill weights into an array that is better for scanning.
1122 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
1123 for (std::vector<std::pair<unsigned, float> >::iterator
1124 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
1125 updateSpillWeights(SpillWeights, I->first, I->second, RC);
1127 // for each interval in active, update spill weights.
1128 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1130 unsigned reg = i->first->reg;
1131 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1132 "Can only allocate virtual registers!");
1133 reg = vrm_->getPhys(reg);
1134 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
1137 DEBUG(dbgs() << "\tassigning stack slot at interval "<< *cur << ":\n");
1139 // Find a register to spill.
1140 float minWeight = HUGE_VALF;
1141 unsigned minReg = 0;
1144 std::vector<std::pair<unsigned,float> > RegsWeights;
1145 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1146 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1147 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1149 float regWeight = SpillWeights[reg];
1150 // Don't even consider reserved regs.
1151 if (reservedRegs_.test(reg))
1153 // Skip recently allocated registers and reserved registers.
1154 if (minWeight > regWeight && !isRecentlyUsed(reg))
1156 RegsWeights.push_back(std::make_pair(reg, regWeight));
1159 // If we didn't find a register that is spillable, try aliases?
1161 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1162 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1164 if (reservedRegs_.test(reg))
1166 // No need to worry about if the alias register size < regsize of RC.
1167 // We are going to spill all registers that alias it anyway.
1168 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1169 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
1173 // Sort all potential spill candidates by weight.
1174 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare(*this));
1175 minReg = RegsWeights[0].first;
1176 minWeight = RegsWeights[0].second;
1177 if (minWeight == HUGE_VALF) {
1178 // All registers must have inf weight. Just grab one!
1179 minReg = BestPhysReg ? BestPhysReg : getFirstNonReservedPhysReg(RC);
1180 if (cur->weight == HUGE_VALF ||
1181 li_->getApproximateInstructionCount(*cur) == 0) {
1182 // Spill a physical register around defs and uses.
1183 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
1184 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1185 // in fixed_. Reset them.
1186 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1187 IntervalPtr &IP = fixed_[i];
1188 LiveInterval *I = IP.first;
1189 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1190 IP.second = I->advanceTo(I->begin(), StartPosition);
1193 DowngradedRegs.clear();
1194 assignRegOrStackSlotAtInterval(cur);
1196 assert(false && "Ran out of registers during register allocation!");
1197 report_fatal_error("Ran out of registers during register allocation!");
1203 // Find up to 3 registers to consider as spill candidates.
1204 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1205 while (LastCandidate > 1) {
1206 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1212 dbgs() << "\t\tregister(s) with min weight(s): ";
1214 for (unsigned i = 0; i != LastCandidate; ++i)
1215 dbgs() << tri_->getName(RegsWeights[i].first)
1216 << " (" << RegsWeights[i].second << ")\n";
1219 // If the current has the minimum weight, we need to spill it and
1220 // add any added intervals back to unhandled, and restart
1222 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
1223 DEBUG(dbgs() << "\t\t\tspilling(c): " << *cur << '\n');
1224 SmallVector<LiveInterval*, 8> spillIs, added;
1225 spiller_->spill(cur, added, spillIs);
1227 std::sort(added.begin(), added.end(), LISorter());
1228 addStackInterval(cur, ls_, li_, mri_, *vrm_);
1230 return; // Early exit if all spills were folded.
1232 // Merge added with unhandled. Note that we have already sorted
1233 // intervals returned by addIntervalsForSpills by their starting
1235 // This also update the NextReloadMap. That is, it adds mapping from a
1236 // register defined by a reload from SS to the next reload from SS in the
1237 // same basic block.
1238 MachineBasicBlock *LastReloadMBB = 0;
1239 LiveInterval *LastReload = 0;
1240 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1241 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1242 LiveInterval *ReloadLi = added[i];
1243 if (ReloadLi->weight == HUGE_VALF &&
1244 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1245 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1246 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1247 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1248 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1249 // Last reload of same SS is in the same MBB. We want to try to
1250 // allocate both reloads the same register and make sure the reg
1251 // isn't clobbered in between if at all possible.
1252 assert(LastReload->beginIndex() < ReloadIdx);
1253 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1255 LastReloadMBB = ReloadMBB;
1256 LastReload = ReloadLi;
1257 LastReloadSS = ReloadSS;
1259 unhandled_.push(ReloadLi);
1266 // Push the current interval back to unhandled since we are going
1267 // to re-run at least this iteration. Since we didn't modify it it
1268 // should go back right in the front of the list
1269 unhandled_.push(cur);
1271 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
1272 "did not choose a register to spill?");
1274 // We spill all intervals aliasing the register with
1275 // minimum weight, rollback to the interval with the earliest
1276 // start point and let the linear scan algorithm run again
1277 SmallVector<LiveInterval*, 8> spillIs;
1279 // Determine which intervals have to be spilled.
1280 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1282 // Set of spilled vregs (used later to rollback properly)
1283 SmallSet<unsigned, 8> spilled;
1285 // The earliest start of a Spilled interval indicates up to where
1286 // in handled we need to roll back
1287 assert(!spillIs.empty() && "No spill intervals?");
1288 SlotIndex earliestStart = spillIs[0]->beginIndex();
1290 // Spill live intervals of virtual regs mapped to the physical register we
1291 // want to clear (and its aliases). We only spill those that overlap with the
1292 // current interval as the rest do not affect its allocation. we also keep
1293 // track of the earliest start of all spilled live intervals since this will
1294 // mark our rollback point.
1295 SmallVector<LiveInterval*, 8> added;
1296 while (!spillIs.empty()) {
1297 LiveInterval *sli = spillIs.back();
1299 DEBUG(dbgs() << "\t\t\tspilling(a): " << *sli << '\n');
1300 if (sli->beginIndex() < earliestStart)
1301 earliestStart = sli->beginIndex();
1302 spiller_->spill(sli, added, spillIs);
1303 addStackInterval(sli, ls_, li_, mri_, *vrm_);
1304 spilled.insert(sli->reg);
1307 // Include any added intervals in earliestStart.
1308 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1309 SlotIndex SI = added[i]->beginIndex();
1310 if (SI < earliestStart)
1314 DEBUG(dbgs() << "\t\trolling back to: " << earliestStart << '\n');
1316 // Scan handled in reverse order up to the earliest start of a
1317 // spilled live interval and undo each one, restoring the state of
1319 while (!handled_.empty()) {
1320 LiveInterval* i = handled_.back();
1321 // If this interval starts before t we are done.
1322 if (!i->empty() && i->beginIndex() < earliestStart)
1324 DEBUG(dbgs() << "\t\t\tundo changes for: " << *i << '\n');
1325 handled_.pop_back();
1327 // When undoing a live interval allocation we must know if it is active or
1328 // inactive to properly update regUse_ and the VirtRegMap.
1329 IntervalPtrs::iterator it;
1330 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
1332 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1333 if (!spilled.count(i->reg))
1335 delRegUse(vrm_->getPhys(i->reg));
1336 vrm_->clearVirt(i->reg);
1337 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
1338 inactive_.erase(it);
1339 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1340 if (!spilled.count(i->reg))
1342 vrm_->clearVirt(i->reg);
1344 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
1345 "Can only allocate virtual registers!");
1346 vrm_->clearVirt(i->reg);
1350 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1351 if (ii == DowngradeMap.end())
1352 // It interval has a preference, it must be defined by a copy. Clear the
1353 // preference now since the source interval allocation may have been
1355 mri_->setRegAllocationHint(i->reg, 0, 0);
1357 UpgradeRegister(ii->second);
1361 // Rewind the iterators in the active, inactive, and fixed lists back to the
1362 // point we reverted to.
1363 RevertVectorIteratorsTo(active_, earliestStart);
1364 RevertVectorIteratorsTo(inactive_, earliestStart);
1365 RevertVectorIteratorsTo(fixed_, earliestStart);
1367 // Scan the rest and undo each interval that expired after t and
1368 // insert it in active (the next iteration of the algorithm will
1369 // put it in inactive if required)
1370 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1371 LiveInterval *HI = handled_[i];
1372 if (!HI->expiredAt(earliestStart) &&
1373 HI->expiredAt(cur->beginIndex())) {
1374 DEBUG(dbgs() << "\t\t\tundo changes for: " << *HI << '\n');
1375 active_.push_back(std::make_pair(HI, HI->begin()));
1376 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1377 addRegUse(vrm_->getPhys(HI->reg));
1381 // Merge added with unhandled.
1382 // This also update the NextReloadMap. That is, it adds mapping from a
1383 // register defined by a reload from SS to the next reload from SS in the
1384 // same basic block.
1385 MachineBasicBlock *LastReloadMBB = 0;
1386 LiveInterval *LastReload = 0;
1387 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1388 std::sort(added.begin(), added.end(), LISorter());
1389 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1390 LiveInterval *ReloadLi = added[i];
1391 if (ReloadLi->weight == HUGE_VALF &&
1392 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1393 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1394 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1395 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1396 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1397 // Last reload of same SS is in the same MBB. We want to try to
1398 // allocate both reloads the same register and make sure the reg
1399 // isn't clobbered in between if at all possible.
1400 assert(LastReload->beginIndex() < ReloadIdx);
1401 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1403 LastReloadMBB = ReloadMBB;
1404 LastReload = ReloadLi;
1405 LastReloadSS = ReloadSS;
1407 unhandled_.push(ReloadLi);
1411 unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
1412 const TargetRegisterClass *RC,
1413 unsigned MaxInactiveCount,
1414 SmallVector<unsigned, 256> &inactiveCounts,
1416 unsigned FreeReg = 0;
1417 unsigned FreeRegInactiveCount = 0;
1419 std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(cur->reg);
1420 // Resolve second part of the hint (if possible) given the current allocation.
1421 unsigned physReg = Hint.second;
1423 TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
1424 physReg = vrm_->getPhys(physReg);
1426 TargetRegisterClass::iterator I, E;
1427 tie(I, E) = tri_->getAllocationOrder(RC, Hint.first, physReg, *mf_);
1428 assert(I != E && "No allocatable register in this register class!");
1430 // Scan for the first available register.
1431 for (; I != E; ++I) {
1433 // Ignore "downgraded" registers.
1434 if (SkipDGRegs && DowngradedRegs.count(Reg))
1436 // Skip reserved registers.
1437 if (reservedRegs_.test(Reg))
1439 // Skip recently allocated registers.
1440 if (isRegAvail(Reg) && !isRecentlyUsed(Reg)) {
1442 if (FreeReg < inactiveCounts.size())
1443 FreeRegInactiveCount = inactiveCounts[FreeReg];
1445 FreeRegInactiveCount = 0;
1450 // If there are no free regs, or if this reg has the max inactive count,
1451 // return this register.
1452 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) {
1453 // Remember what register we picked so we can skip it next time.
1454 if (FreeReg != 0) recordRecentlyUsed(FreeReg);
1458 // Continue scanning the registers, looking for the one with the highest
1459 // inactive count. Alkis found that this reduced register pressure very
1460 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1462 for (; I != E; ++I) {
1464 // Ignore "downgraded" registers.
1465 if (SkipDGRegs && DowngradedRegs.count(Reg))
1467 // Skip reserved registers.
1468 if (reservedRegs_.test(Reg))
1470 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1471 FreeRegInactiveCount < inactiveCounts[Reg] && !isRecentlyUsed(Reg)) {
1473 FreeRegInactiveCount = inactiveCounts[Reg];
1474 if (FreeRegInactiveCount == MaxInactiveCount)
1475 break; // We found the one with the max inactive count.
1479 // Remember what register we picked so we can skip it next time.
1480 recordRecentlyUsed(FreeReg);
1485 /// getFreePhysReg - return a free physical register for this virtual register
1486 /// interval if we have one, otherwise return 0.
1487 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1488 SmallVector<unsigned, 256> inactiveCounts;
1489 unsigned MaxInactiveCount = 0;
1491 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1492 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1494 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1496 unsigned reg = i->first->reg;
1497 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1498 "Can only allocate virtual registers!");
1500 // If this is not in a related reg class to the register we're allocating,
1502 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1503 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1504 reg = vrm_->getPhys(reg);
1505 if (inactiveCounts.size() <= reg)
1506 inactiveCounts.resize(reg+1);
1507 ++inactiveCounts[reg];
1508 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1512 // If copy coalescer has assigned a "preferred" register, check if it's
1514 unsigned Preference = vrm_->getRegAllocPref(cur->reg);
1516 DEBUG(dbgs() << "(preferred: " << tri_->getName(Preference) << ") ");
1517 if (isRegAvail(Preference) &&
1518 RC->contains(Preference))
1522 if (!DowngradedRegs.empty()) {
1523 unsigned FreeReg = getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts,
1528 return getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts, false);
1531 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1532 return new RALinScan();