1 //===-- RegAllocFast.cpp - A fast register allocator for debug code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This register allocator allocates registers to a basic block at a time,
11 // attempting to keep values in registers and reusing registers as appropriate.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "llvm/BasicBlock.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/CodeGen/RegAllocRegistry.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/IndexedMap.h"
32 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
39 STATISTIC(NumStores, "Number of stores added");
40 STATISTIC(NumLoads , "Number of loads added");
41 STATISTIC(NumCopies, "Number of copies coalesced");
43 static RegisterRegAlloc
44 fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
47 class RAFast : public MachineFunctionPass {
50 RAFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1),
51 isBulkSpilling(false) {}
53 const TargetMachine *TM;
55 MachineRegisterInfo *MRI;
56 const TargetRegisterInfo *TRI;
57 const TargetInstrInfo *TII;
59 // Basic block currently being allocated.
60 MachineBasicBlock *MBB;
62 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
63 // values are spilled.
64 IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
66 // Everything we know about a live virtual register.
68 MachineInstr *LastUse; // Last instr to use reg.
69 unsigned PhysReg; // Currently held here.
70 unsigned short LastOpNum; // OpNum on LastUse.
71 bool Dirty; // Register needs spill.
73 LiveReg(unsigned p=0) : LastUse(0), PhysReg(p), LastOpNum(0),
77 typedef DenseMap<unsigned, LiveReg> LiveRegMap;
78 typedef LiveRegMap::value_type LiveRegEntry;
80 // LiveVirtRegs - This map contains entries for each virtual register
81 // that is currently available in a physical register.
82 LiveRegMap LiveVirtRegs;
84 DenseMap<unsigned, MachineInstr *> LiveDbgValueMap;
86 // RegState - Track the state of a physical register.
88 // A disabled register is not available for allocation, but an alias may
89 // be in use. A register can only be moved out of the disabled state if
90 // all aliases are disabled.
93 // A free register is not currently in use and can be allocated
94 // immediately without checking aliases.
97 // A reserved register has been assigned expolicitly (e.g., setting up a
98 // call parameter), and it remains reserved until it is used.
101 // A register state may also be a virtual register number, indication that
102 // the physical register is currently allocated to a virtual register. In
103 // that case, LiveVirtRegs contains the inverse mapping.
106 // PhysRegState - One of the RegState enums, or a virtreg.
107 std::vector<unsigned> PhysRegState;
109 // UsedInInstr - BitVector of physregs that are used in the current
110 // instruction, and so cannot be allocated.
111 BitVector UsedInInstr;
113 // Allocatable - vector of allocatable physical registers.
114 BitVector Allocatable;
116 // Reserved - vector of reserved physical registers.
119 // SkippedInstrs - Descriptors of instructions whose clobber list was
120 // ignored because all registers were spilled. It is still necessary to
121 // mark all the clobbered registers as used by the function.
122 SmallPtrSet<const TargetInstrDesc*, 4> SkippedInstrs;
124 // isBulkSpilling - This flag is set when LiveRegMap will be cleared
125 // completely after spilling all live registers. LiveRegMap entries should
132 spillImpossible = ~0u
135 virtual const char *getPassName() const {
136 return "Fast Register Allocator";
139 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
140 AU.setPreservesCFG();
141 AU.addRequiredID(PHIEliminationID);
142 AU.addRequiredID(TwoAddressInstructionPassID);
143 MachineFunctionPass::getAnalysisUsage(AU);
147 bool runOnMachineFunction(MachineFunction &Fn);
148 void AllocateBasicBlock();
149 void handleThroughOperands(MachineInstr *MI,
150 SmallVectorImpl<unsigned> &VirtDead);
151 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
152 bool isLastUseOfLocalReg(MachineOperand&);
154 void addKillFlag(const LiveReg&);
155 void killVirtReg(LiveRegMap::iterator);
156 void killVirtReg(unsigned VirtReg);
157 void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator);
158 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
160 void usePhysReg(MachineOperand&);
161 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
162 unsigned calcSpillCost(unsigned PhysReg) const;
163 void assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg);
164 void allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint);
165 LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum,
166 unsigned VirtReg, unsigned Hint);
167 LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum,
168 unsigned VirtReg, unsigned Hint);
169 void spillAll(MachineInstr *MI);
170 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
175 /// getStackSpaceFor - This allocates space for the specified virtual register
176 /// to be held on the stack.
177 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
178 // Find the location Reg would belong...
179 int SS = StackSlotForVirtReg[VirtReg];
181 return SS; // Already has space allocated?
183 // Allocate a new stack object for this spill location...
184 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
188 StackSlotForVirtReg[VirtReg] = FrameIdx;
192 /// isLastUseOfLocalReg - Return true if MO is the only remaining reference to
193 /// its virtual register, and it is guaranteed to be a block-local register.
195 bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) {
196 // Check for non-debug uses or defs following MO.
197 // This is the most likely way to fail - fast path it.
198 MachineOperand *Next = &MO;
199 while ((Next = Next->getNextOperandForReg()))
200 if (!Next->isDebug())
203 // If the register has ever been spilled or reloaded, we conservatively assume
204 // it is a global register used in multiple blocks.
205 if (StackSlotForVirtReg[MO.getReg()] != -1)
208 // Check that the use/def chain has exactly one operand - MO.
209 return &MRI->reg_nodbg_begin(MO.getReg()).getOperand() == &MO;
212 /// addKillFlag - Set kill flags on last use of a virtual register.
213 void RAFast::addKillFlag(const LiveReg &LR) {
214 if (!LR.LastUse) return;
215 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
216 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
217 if (MO.getReg() == LR.PhysReg)
220 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true);
224 /// killVirtReg - Mark virtreg as no longer available.
225 void RAFast::killVirtReg(LiveRegMap::iterator LRI) {
226 addKillFlag(LRI->second);
227 const LiveReg &LR = LRI->second;
228 assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
229 PhysRegState[LR.PhysReg] = regFree;
230 // Erase from LiveVirtRegs unless we're spilling in bulk.
232 LiveVirtRegs.erase(LRI);
235 /// killVirtReg - Mark virtreg as no longer available.
236 void RAFast::killVirtReg(unsigned VirtReg) {
237 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
238 "killVirtReg needs a virtual register");
239 LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg);
240 if (LRI != LiveVirtRegs.end())
244 /// spillVirtReg - This method spills the value specified by VirtReg into the
245 /// corresponding stack slot if needed.
246 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {
247 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
248 "Spilling a physical register is illegal!");
249 LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg);
250 assert(LRI != LiveVirtRegs.end() && "Spilling unmapped virtual register");
251 spillVirtReg(MI, LRI);
254 /// spillVirtReg - Do the actual work of spilling.
255 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
256 LiveRegMap::iterator LRI) {
257 LiveReg &LR = LRI->second;
258 assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
261 // If this physreg is used by the instruction, we want to kill it on the
262 // instruction, not on the spill.
263 bool SpillKill = LR.LastUse != MI;
265 DEBUG(dbgs() << "Spilling %reg" << LRI->first
266 << " in " << TRI->getName(LR.PhysReg));
267 const TargetRegisterClass *RC = MRI->getRegClass(LRI->first);
268 int FI = getStackSpaceFor(LRI->first, RC);
269 DEBUG(dbgs() << " to stack slot #" << FI << "\n");
270 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
271 ++NumStores; // Update statistics
273 // If this register is used by DBG_VALUE then insert new DBG_VALUE to
274 // identify spilled location as the place to find corresponding variable's
276 if (MachineInstr *DBG = LiveDbgValueMap.lookup(LRI->first)) {
277 const MDNode *MDPtr =
278 DBG->getOperand(DBG->getNumOperands()-1).getMetadata();
280 if (DBG->getOperand(1).isImm())
281 Offset = DBG->getOperand(1).getImm();
283 if (MI == MBB->end()) {
284 // If MI is at basic block end then use last instruction's location.
285 MachineBasicBlock::iterator EI = MI;
286 DL = (--EI)->getDebugLoc();
289 DL = MI->getDebugLoc();
290 if (MachineInstr *NewDV =
291 TII->emitFrameIndexDebugValue(*MF, FI, Offset, MDPtr, DL)) {
292 MachineBasicBlock *MBB = DBG->getParent();
293 MBB->insert(MI, NewDV);
294 DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV);
295 LiveDbgValueMap[LRI->first] = NewDV;
299 LR.LastUse = 0; // Don't kill register again
304 /// spillAll - Spill all dirty virtregs without killing them.
305 void RAFast::spillAll(MachineInstr *MI) {
306 if (LiveVirtRegs.empty()) return;
307 isBulkSpilling = true;
308 // The LiveRegMap is keyed by an unsigned (the virtreg number), so the order
309 // of spilling here is deterministic, if arbitrary.
310 for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end();
313 LiveVirtRegs.clear();
314 isBulkSpilling = false;
317 /// usePhysReg - Handle the direct use of a physical register.
318 /// Check that the register is not used by a virtreg.
319 /// Kill the physreg, marking it free.
320 /// This may add implicit kills to MO->getParent() and invalidate MO.
321 void RAFast::usePhysReg(MachineOperand &MO) {
322 unsigned PhysReg = MO.getReg();
323 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
324 "Bad usePhysReg operand");
326 switch (PhysRegState[PhysReg]) {
330 PhysRegState[PhysReg] = regFree;
333 UsedInInstr.set(PhysReg);
337 // The physreg was allocated to a virtual register. That means to value we
338 // wanted has been clobbered.
339 llvm_unreachable("Instruction uses an allocated register");
342 // Maybe a superregister is reserved?
343 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
344 unsigned Alias = *AS; ++AS) {
345 switch (PhysRegState[Alias]) {
349 assert(TRI->isSuperRegister(PhysReg, Alias) &&
350 "Instruction is not using a subregister of a reserved register");
351 // Leave the superregister in the working set.
352 PhysRegState[Alias] = regFree;
353 UsedInInstr.set(Alias);
354 MO.getParent()->addRegisterKilled(Alias, TRI, true);
357 if (TRI->isSuperRegister(PhysReg, Alias)) {
358 // Leave the superregister in the working set.
359 UsedInInstr.set(Alias);
360 MO.getParent()->addRegisterKilled(Alias, TRI, true);
363 // Some other alias was in the working set - clear it.
364 PhysRegState[Alias] = regDisabled;
367 llvm_unreachable("Instruction uses an alias of an allocated register");
371 // All aliases are disabled, bring register into working set.
372 PhysRegState[PhysReg] = regFree;
373 UsedInInstr.set(PhysReg);
377 /// definePhysReg - Mark PhysReg as reserved or free after spilling any
378 /// virtregs. This is very similar to defineVirtReg except the physreg is
379 /// reserved instead of allocated.
380 void RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg,
382 UsedInInstr.set(PhysReg);
383 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
387 spillVirtReg(MI, VirtReg);
391 PhysRegState[PhysReg] = NewState;
395 // This is a disabled register, disable all aliases.
396 PhysRegState[PhysReg] = NewState;
397 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
398 unsigned Alias = *AS; ++AS) {
399 UsedInInstr.set(Alias);
400 switch (unsigned VirtReg = PhysRegState[Alias]) {
404 spillVirtReg(MI, VirtReg);
408 PhysRegState[Alias] = regDisabled;
409 if (TRI->isSuperRegister(PhysReg, Alias))
417 // calcSpillCost - Return the cost of spilling clearing out PhysReg and
418 // aliases so it is free for allocation.
419 // Returns 0 when PhysReg is free or disabled with all aliases disabled - it
420 // can be allocated directly.
421 // Returns spillImpossible when PhysReg or an alias can't be spilled.
422 unsigned RAFast::calcSpillCost(unsigned PhysReg) const {
423 if (UsedInInstr.test(PhysReg))
424 return spillImpossible;
425 switch (unsigned VirtReg = PhysRegState[PhysReg]) {
431 return spillImpossible;
433 return LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean;
436 // This is a disabled register, add up const of aliases.
438 for (const unsigned *AS = TRI->getAliasSet(PhysReg);
439 unsigned Alias = *AS; ++AS) {
440 if (UsedInInstr.test(Alias))
441 return spillImpossible;
442 switch (unsigned VirtReg = PhysRegState[Alias]) {
449 return spillImpossible;
451 Cost += LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean;
459 /// assignVirtToPhysReg - This method updates local state so that we know
460 /// that PhysReg is the proper container for VirtReg now. The physical
461 /// register must not be used for anything else when this is called.
463 void RAFast::assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg) {
464 DEBUG(dbgs() << "Assigning %reg" << LRE.first << " to "
465 << TRI->getName(PhysReg) << "\n");
466 PhysRegState[PhysReg] = LRE.first;
467 assert(!LRE.second.PhysReg && "Already assigned a physreg");
468 LRE.second.PhysReg = PhysReg;
471 /// allocVirtReg - Allocate a physical register for VirtReg.
472 void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) {
473 const unsigned VirtReg = LRE.first;
475 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
476 "Can only allocate virtual registers");
478 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
480 // Ignore invalid hints.
481 if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
482 !RC->contains(Hint) || !Allocatable.test(Hint)))
485 // Take hint when possible.
487 switch(calcSpillCost(Hint)) {
489 definePhysReg(MI, Hint, regFree);
492 return assignVirtToPhysReg(LRE, Hint);
493 case spillImpossible:
498 TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF);
499 TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF);
501 // First try to find a completely free register.
502 for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
503 unsigned PhysReg = *I;
504 if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg))
505 return assignVirtToPhysReg(LRE, PhysReg);
508 DEBUG(dbgs() << "Allocating %reg" << VirtReg << " from " << RC->getName()
511 unsigned BestReg = 0, BestCost = spillImpossible;
512 for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
513 unsigned Cost = calcSpillCost(*I);
514 // Cost is 0 when all aliases are already disabled.
516 return assignVirtToPhysReg(LRE, *I);
518 BestReg = *I, BestCost = Cost;
522 definePhysReg(MI, BestReg, regFree);
523 return assignVirtToPhysReg(LRE, BestReg);
526 // Nothing we can do.
528 raw_string_ostream Msg(msg);
529 Msg << "Ran out of registers during register allocation!";
530 if (MI->isInlineAsm()) {
531 Msg << "\nPlease check your inline asm statement for "
532 << "invalid constraints:\n";
535 report_fatal_error(Msg.str());
538 /// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
539 RAFast::LiveRegMap::iterator
540 RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum,
541 unsigned VirtReg, unsigned Hint) {
542 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
543 "Not a virtual register");
544 LiveRegMap::iterator LRI;
546 tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
547 LiveReg &LR = LRI->second;
549 // If there is no hint, peek at the only use of this register.
550 if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
551 MRI->hasOneNonDBGUse(VirtReg)) {
552 const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg);
553 // It's a copy, use the destination register as a hint.
554 if (UseMI.isCopyLike())
555 Hint = UseMI.getOperand(0).getReg();
557 allocVirtReg(MI, *LRI, Hint);
558 } else if (LR.LastUse) {
559 // Redefining a live register - kill at the last use, unless it is this
560 // instruction defining VirtReg multiple times.
561 if (LR.LastUse != MI || LR.LastUse->getOperand(LR.LastOpNum).isUse())
564 assert(LR.PhysReg && "Register not assigned");
566 LR.LastOpNum = OpNum;
568 UsedInInstr.set(LR.PhysReg);
572 /// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
573 RAFast::LiveRegMap::iterator
574 RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum,
575 unsigned VirtReg, unsigned Hint) {
576 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
577 "Not a virtual register");
578 LiveRegMap::iterator LRI;
580 tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
581 LiveReg &LR = LRI->second;
582 MachineOperand &MO = MI->getOperand(OpNum);
584 allocVirtReg(MI, *LRI, Hint);
585 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
586 int FrameIndex = getStackSpaceFor(VirtReg, RC);
587 DEBUG(dbgs() << "Reloading %reg" << VirtReg << " into "
588 << TRI->getName(LR.PhysReg) << "\n");
589 TII->loadRegFromStackSlot(*MBB, MI, LR.PhysReg, FrameIndex, RC, TRI);
591 } else if (LR.Dirty) {
592 if (isLastUseOfLocalReg(MO)) {
593 DEBUG(dbgs() << "Killing last use: " << MO << "\n");
598 } else if (MO.isKill()) {
599 DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n");
601 } else if (MO.isDead()) {
602 DEBUG(dbgs() << "Clearing dubious dead: " << MO << "\n");
605 } else if (MO.isKill()) {
606 // We must remove kill flags from uses of reloaded registers because the
607 // register would be killed immediately, and there might be a second use:
608 // %foo = OR %x<kill>, %x
609 // This would cause a second reload of %x into a different register.
610 DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n");
612 } else if (MO.isDead()) {
613 DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n");
616 assert(LR.PhysReg && "Register not assigned");
618 LR.LastOpNum = OpNum;
619 UsedInInstr.set(LR.PhysReg);
623 // setPhysReg - Change operand OpNum in MI the refer the PhysReg, considering
624 // subregs. This may invalidate any operand pointers.
625 // Return true if the operand kills its register.
626 bool RAFast::setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) {
627 MachineOperand &MO = MI->getOperand(OpNum);
628 if (!MO.getSubReg()) {
630 return MO.isKill() || MO.isDead();
633 // Handle subregister index.
634 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
637 // A kill flag implies killing the full register. Add corresponding super
640 MI->addRegisterKilled(PhysReg, TRI, true);
646 // Handle special instruction operand like early clobbers and tied ops when
647 // there are additional physreg defines.
648 void RAFast::handleThroughOperands(MachineInstr *MI,
649 SmallVectorImpl<unsigned> &VirtDead) {
650 DEBUG(dbgs() << "Scanning for through registers:");
651 SmallSet<unsigned, 8> ThroughRegs;
652 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
653 MachineOperand &MO = MI->getOperand(i);
654 if (!MO.isReg()) continue;
655 unsigned Reg = MO.getReg();
656 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
657 if (MO.isEarlyClobber() || MI->isRegTiedToDefOperand(i) ||
658 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) {
659 if (ThroughRegs.insert(Reg))
660 DEBUG(dbgs() << " %reg" << Reg);
664 // If any physreg defines collide with preallocated through registers,
665 // we must spill and reallocate.
666 DEBUG(dbgs() << "\nChecking for physdef collisions.\n");
667 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
668 MachineOperand &MO = MI->getOperand(i);
669 if (!MO.isReg() || !MO.isDef()) continue;
670 unsigned Reg = MO.getReg();
671 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
672 UsedInInstr.set(Reg);
673 if (ThroughRegs.count(PhysRegState[Reg]))
674 definePhysReg(MI, Reg, regFree);
675 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
676 UsedInInstr.set(*AS);
677 if (ThroughRegs.count(PhysRegState[*AS]))
678 definePhysReg(MI, *AS, regFree);
682 SmallVector<unsigned, 8> PartialDefs;
683 DEBUG(dbgs() << "Allocating tied uses and early clobbers.\n");
684 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
685 MachineOperand &MO = MI->getOperand(i);
686 if (!MO.isReg()) continue;
687 unsigned Reg = MO.getReg();
688 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
691 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
692 DEBUG(dbgs() << "Operand " << i << "("<< MO << ") is tied to operand "
694 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
695 unsigned PhysReg = LRI->second.PhysReg;
696 setPhysReg(MI, i, PhysReg);
697 // Note: we don't update the def operand yet. That would cause the normal
698 // def-scan to attempt spilling.
699 } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) {
700 DEBUG(dbgs() << "Partial redefine: " << MO << "\n");
701 // Reload the register, but don't assign to the operand just yet.
702 // That would confuse the later phys-def processing pass.
703 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
704 PartialDefs.push_back(LRI->second.PhysReg);
705 } else if (MO.isEarlyClobber()) {
706 // Note: defineVirtReg may invalidate MO.
707 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);
708 unsigned PhysReg = LRI->second.PhysReg;
709 if (setPhysReg(MI, i, PhysReg))
710 VirtDead.push_back(Reg);
714 // Restore UsedInInstr to a state usable for allocating normal virtual uses.
715 UsedInInstr = Reserved;
716 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
717 MachineOperand &MO = MI->getOperand(i);
718 if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;
719 unsigned Reg = MO.getReg();
720 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
721 UsedInInstr.set(Reg);
722 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
723 UsedInInstr.set(*AS);
726 // Also mark PartialDefs as used to avoid reallocation.
727 for (unsigned i = 0, e = PartialDefs.size(); i != e; ++i)
728 UsedInInstr.set(PartialDefs[i]);
731 void RAFast::AllocateBasicBlock() {
732 DEBUG(dbgs() << "\nAllocating " << *MBB);
734 PhysRegState.assign(TRI->getNumRegs(), regDisabled);
735 assert(LiveVirtRegs.empty() && "Mapping not cleared form last block?");
737 MachineBasicBlock::iterator MII = MBB->begin();
739 // Add live-in registers as live.
740 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
741 E = MBB->livein_end(); I != E; ++I)
742 if (Allocatable.test(*I))
743 definePhysReg(MII, *I, regReserved);
745 SmallVector<unsigned, 8> VirtDead;
746 SmallVector<MachineInstr*, 32> Coalesced;
748 // Otherwise, sequentially allocate each instruction in the MBB.
749 while (MII != MBB->end()) {
750 MachineInstr *MI = MII++;
751 const TargetInstrDesc &TID = MI->getDesc();
753 dbgs() << "\n>> " << *MI << "Regs:";
754 for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
755 if (PhysRegState[Reg] == regDisabled) continue;
756 dbgs() << " " << TRI->getName(Reg);
757 switch(PhysRegState[Reg]) {
764 dbgs() << "=%reg" << PhysRegState[Reg];
765 if (LiveVirtRegs[PhysRegState[Reg]].Dirty)
767 assert(LiveVirtRegs[PhysRegState[Reg]].PhysReg == Reg &&
773 // Check that LiveVirtRegs is the inverse.
774 for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
775 e = LiveVirtRegs.end(); i != e; ++i) {
776 assert(TargetRegisterInfo::isVirtualRegister(i->first) &&
778 assert(TargetRegisterInfo::isPhysicalRegister(i->second.PhysReg) &&
780 assert(PhysRegState[i->second.PhysReg] == i->first &&
785 // Debug values are not allowed to change codegen in any way.
786 if (MI->isDebugValue()) {
787 bool ScanDbgValue = true;
788 while (ScanDbgValue) {
789 ScanDbgValue = false;
790 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
791 MachineOperand &MO = MI->getOperand(i);
792 if (!MO.isReg()) continue;
793 unsigned Reg = MO.getReg();
794 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
795 LiveDbgValueMap[Reg] = MI;
796 LiveRegMap::iterator LRI = LiveVirtRegs.find(Reg);
797 if (LRI != LiveVirtRegs.end())
798 setPhysReg(MI, i, LRI->second.PhysReg);
800 int SS = StackSlotForVirtReg[Reg];
802 // We can't allocate a physreg for a DebugValue, sorry!
805 // Modify DBG_VALUE now that the value is in a spill slot.
806 int64_t Offset = MI->getOperand(1).getImm();
807 const MDNode *MDPtr =
808 MI->getOperand(MI->getNumOperands()-1).getMetadata();
809 DebugLoc DL = MI->getDebugLoc();
810 if (MachineInstr *NewDV =
811 TII->emitFrameIndexDebugValue(*MF, SS, Offset, MDPtr, DL)) {
812 DEBUG(dbgs() << "Modifying debug info due to spill:" <<
814 MachineBasicBlock *MBB = MI->getParent();
815 MBB->insert(MBB->erase(MI), NewDV);
816 // Scan NewDV operands from the beginning.
821 // We can't allocate a physreg for a DebugValue; sorry!
831 // If this is a copy, we may be able to coalesce.
832 unsigned CopySrc = 0, CopyDst = 0, CopySrcSub = 0, CopyDstSub = 0;
834 CopyDst = MI->getOperand(0).getReg();
835 CopySrc = MI->getOperand(1).getReg();
836 CopyDstSub = MI->getOperand(0).getSubReg();
837 CopySrcSub = MI->getOperand(1).getSubReg();
840 // Track registers used by instruction.
841 UsedInInstr = Reserved;
844 // Mark physreg uses and early clobbers as used.
845 // Find the end of the virtreg operands
846 unsigned VirtOpEnd = 0;
847 bool hasTiedOps = false;
848 bool hasEarlyClobbers = false;
849 bool hasPartialRedefs = false;
850 bool hasPhysDefs = false;
851 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
852 MachineOperand &MO = MI->getOperand(i);
853 if (!MO.isReg()) continue;
854 unsigned Reg = MO.getReg();
856 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
859 hasTiedOps = hasTiedOps ||
860 TID.getOperandConstraint(i, TOI::TIED_TO) != -1;
862 if (MO.isEarlyClobber())
863 hasEarlyClobbers = true;
864 if (MO.getSubReg() && MI->readsVirtualRegister(Reg))
865 hasPartialRedefs = true;
869 if (!Allocatable.test(Reg)) continue;
872 } else if (MO.isEarlyClobber()) {
873 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
874 regFree : regReserved);
875 hasEarlyClobbers = true;
880 // The instruction may have virtual register operands that must be allocated
881 // the same register at use-time and def-time: early clobbers and tied
882 // operands. If there are also physical defs, these registers must avoid
883 // both physical defs and uses, making them more constrained than normal
885 // Similarly, if there are multiple defs and tied operands, we must make
886 // sure the same register is allocated to uses and defs.
887 // We didn't detect inline asm tied operands above, so just make this extra
888 // pass for all inline asm.
889 if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs ||
890 (hasTiedOps && (hasPhysDefs || TID.getNumDefs() > 1))) {
891 handleThroughOperands(MI, VirtDead);
892 // Don't attempt coalescing when we have funny stuff going on.
894 // Pretend we have early clobbers so the use operands get marked below.
895 // This is not necessary for the common case of a single tied use.
896 hasEarlyClobbers = true;
900 // Allocate virtreg uses.
901 for (unsigned i = 0; i != VirtOpEnd; ++i) {
902 MachineOperand &MO = MI->getOperand(i);
903 if (!MO.isReg()) continue;
904 unsigned Reg = MO.getReg();
905 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
907 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, CopyDst);
908 unsigned PhysReg = LRI->second.PhysReg;
909 CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0;
910 if (setPhysReg(MI, i, PhysReg))
915 MRI->addPhysRegsUsed(UsedInInstr);
917 // Track registers defined by instruction - early clobbers and tied uses at
919 UsedInInstr = Reserved;
920 if (hasEarlyClobbers) {
921 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
922 MachineOperand &MO = MI->getOperand(i);
923 if (!MO.isReg()) continue;
924 unsigned Reg = MO.getReg();
925 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
926 // Look for physreg defs and tied uses.
927 if (!MO.isDef() && !MI->isRegTiedToDefOperand(i)) continue;
928 UsedInInstr.set(Reg);
929 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
930 UsedInInstr.set(*AS);
934 unsigned DefOpEnd = MI->getNumOperands();
936 // Spill all virtregs before a call. This serves two purposes: 1. If an
937 // exception is thrown, the landing pad is going to expect to find
938 // registers in their spill slots, and 2. we don't have to wade through
939 // all the <imp-def> operands on the call instruction.
940 DefOpEnd = VirtOpEnd;
941 DEBUG(dbgs() << " Spilling remaining registers before call.\n");
944 // The imp-defs are skipped below, but we still need to mark those
945 // registers as used by the function.
946 SkippedInstrs.insert(&TID);
950 // Allocate defs and collect dead defs.
951 for (unsigned i = 0; i != DefOpEnd; ++i) {
952 MachineOperand &MO = MI->getOperand(i);
953 if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
955 unsigned Reg = MO.getReg();
957 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
958 if (!Allocatable.test(Reg)) continue;
959 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
960 regFree : regReserved);
963 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, CopySrc);
964 unsigned PhysReg = LRI->second.PhysReg;
965 if (setPhysReg(MI, i, PhysReg)) {
966 VirtDead.push_back(Reg);
967 CopyDst = 0; // cancel coalescing;
969 CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0;
972 // Kill dead defs after the scan to ensure that multiple defs of the same
973 // register are allocated identically. We didn't need to do this for uses
974 // because we are crerating our own kill flags, and they are always at the
976 for (unsigned i = 0, e = VirtDead.size(); i != e; ++i)
977 killVirtReg(VirtDead[i]);
980 MRI->addPhysRegsUsed(UsedInInstr);
982 if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) {
983 DEBUG(dbgs() << "-- coalescing: " << *MI);
984 Coalesced.push_back(MI);
986 DEBUG(dbgs() << "<< " << *MI);
990 // Spill all physical registers holding virtual registers now.
991 DEBUG(dbgs() << "Spilling live registers at end of block.\n");
992 spillAll(MBB->getFirstTerminator());
994 // Erase all the coalesced copies. We are delaying it until now because
995 // LiveVirtRegs might refer to the instrs.
996 for (unsigned i = 0, e = Coalesced.size(); i != e; ++i)
997 MBB->erase(Coalesced[i]);
998 NumCopies += Coalesced.size();
1003 /// runOnMachineFunction - Register allocate the whole function
1005 bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
1006 DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n"
1007 << "********** Function: "
1008 << ((Value*)Fn.getFunction())->getName() << '\n');
1010 MRI = &MF->getRegInfo();
1011 TM = &Fn.getTarget();
1012 TRI = TM->getRegisterInfo();
1013 TII = TM->getInstrInfo();
1015 UsedInInstr.resize(TRI->getNumRegs());
1016 Allocatable = TRI->getAllocatableSet(*MF);
1017 Reserved = TRI->getReservedRegs(*MF);
1019 // initialize the virtual->physical register map to have a 'null'
1020 // mapping for all virtual registers
1021 unsigned LastVirtReg = MRI->getLastVirtReg();
1022 StackSlotForVirtReg.grow(LastVirtReg);
1024 // Loop over all of the basic blocks, eliminating virtual register references
1025 for (MachineFunction::iterator MBBi = Fn.begin(), MBBe = Fn.end();
1026 MBBi != MBBe; ++MBBi) {
1028 AllocateBasicBlock();
1031 // Make sure the set of used physregs is closed under subreg operations.
1032 MRI->closePhysRegsUsed(*TRI);
1034 // Add the clobber lists for all the instructions we skipped earlier.
1035 for (SmallPtrSet<const TargetInstrDesc*, 4>::const_iterator
1036 I = SkippedInstrs.begin(), E = SkippedInstrs.end(); I != E; ++I)
1037 if (const unsigned *Defs = (*I)->getImplicitDefs())
1039 MRI->setPhysRegUsed(*Defs++);
1041 SkippedInstrs.clear();
1042 StackSlotForVirtReg.clear();
1043 LiveDbgValueMap.clear();
1047 FunctionPass *llvm::createFastRegisterAllocator() {
1048 return new RAFast();