1 //===-- PreAllocSplitting.cpp - Pre-allocation Interval Spltting Pass. ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the machine instruction level pre-register allocation
11 // live interval splitting pass. It finds live interval barriers, i.e.
12 // instructions which will kill all physical registers in certain register
13 // classes, and split all live intervals which cross the barrier.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "pre-alloc-split"
18 #include "VirtRegMap.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/LiveStackAnalysis.h"
21 #include "llvm/CodeGen/MachineDominators.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/RegisterCoalescer.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/ADT/DenseMap.h"
36 #include "llvm/ADT/DepthFirstIterator.h"
37 #include "llvm/ADT/SmallPtrSet.h"
38 #include "llvm/ADT/Statistic.h"
41 static cl::opt<int> PreSplitLimit("pre-split-limit", cl::init(-1), cl::Hidden);
42 static cl::opt<int> DeadSplitLimit("dead-split-limit", cl::init(-1), cl::Hidden);
43 static cl::opt<int> RestoreFoldLimit("restore-fold-limit", cl::init(-1), cl::Hidden);
45 STATISTIC(NumSplits, "Number of intervals split");
46 STATISTIC(NumRemats, "Number of intervals split by rematerialization");
47 STATISTIC(NumFolds, "Number of intervals split with spill folding");
48 STATISTIC(NumRestoreFolds, "Number of intervals split with restore folding");
49 STATISTIC(NumRenumbers, "Number of intervals renumbered into new registers");
50 STATISTIC(NumDeadSpills, "Number of dead spills removed");
53 class VISIBILITY_HIDDEN PreAllocSplitting : public MachineFunctionPass {
54 MachineFunction *CurrMF;
55 const TargetMachine *TM;
56 const TargetInstrInfo *TII;
57 const TargetRegisterInfo* TRI;
58 MachineFrameInfo *MFI;
59 MachineRegisterInfo *MRI;
64 // Barrier - Current barrier being processed.
65 MachineInstr *Barrier;
67 // BarrierMBB - Basic block where the barrier resides in.
68 MachineBasicBlock *BarrierMBB;
70 // Barrier - Current barrier index.
73 // CurrLI - Current live interval being split.
76 // CurrSLI - Current stack slot live interval.
77 LiveInterval *CurrSLI;
79 // CurrSValNo - Current val# for the stack slot live interval.
82 // IntervalSSMap - A map from live interval to spill slots.
83 DenseMap<unsigned, int> IntervalSSMap;
85 // Def2SpillMap - A map from a def instruction index to spill index.
86 DenseMap<LiveIndex, LiveIndex> Def2SpillMap;
90 PreAllocSplitting() : MachineFunctionPass(&ID) {}
92 virtual bool runOnMachineFunction(MachineFunction &MF);
94 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
96 AU.addRequired<LiveIntervals>();
97 AU.addPreserved<LiveIntervals>();
98 AU.addRequired<LiveStacks>();
99 AU.addPreserved<LiveStacks>();
100 AU.addPreserved<RegisterCoalescer>();
102 AU.addPreservedID(StrongPHIEliminationID);
104 AU.addPreservedID(PHIEliminationID);
105 AU.addRequired<MachineDominatorTree>();
106 AU.addRequired<MachineLoopInfo>();
107 AU.addRequired<VirtRegMap>();
108 AU.addPreserved<MachineDominatorTree>();
109 AU.addPreserved<MachineLoopInfo>();
110 AU.addPreserved<VirtRegMap>();
111 MachineFunctionPass::getAnalysisUsage(AU);
114 virtual void releaseMemory() {
115 IntervalSSMap.clear();
116 Def2SpillMap.clear();
119 virtual const char *getPassName() const {
120 return "Pre-Register Allocaton Live Interval Splitting";
123 /// print - Implement the dump method.
124 virtual void print(raw_ostream &O, const Module* M = 0) const {
130 MachineBasicBlock::iterator
131 findNextEmptySlot(MachineBasicBlock*, MachineInstr*,
134 MachineBasicBlock::iterator
135 findSpillPoint(MachineBasicBlock*, MachineInstr*, MachineInstr*,
136 SmallPtrSet<MachineInstr*, 4>&, LiveIndex&);
138 MachineBasicBlock::iterator
139 findRestorePoint(MachineBasicBlock*, MachineInstr*, LiveIndex,
140 SmallPtrSet<MachineInstr*, 4>&, LiveIndex&);
142 int CreateSpillStackSlot(unsigned, const TargetRegisterClass *);
144 bool IsAvailableInStack(MachineBasicBlock*, unsigned,
145 LiveIndex, LiveIndex,
146 LiveIndex&, int&) const;
148 void UpdateSpillSlotInterval(VNInfo*, LiveIndex, LiveIndex);
150 bool SplitRegLiveInterval(LiveInterval*);
152 bool SplitRegLiveIntervals(const TargetRegisterClass **,
153 SmallPtrSet<LiveInterval*, 8>&);
155 bool createsNewJoin(LiveRange* LR, MachineBasicBlock* DefMBB,
156 MachineBasicBlock* BarrierMBB);
157 bool Rematerialize(unsigned vreg, VNInfo* ValNo,
159 MachineBasicBlock::iterator RestorePt,
160 LiveIndex RestoreIdx,
161 SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
162 MachineInstr* FoldSpill(unsigned vreg, const TargetRegisterClass* RC,
164 MachineInstr* Barrier,
165 MachineBasicBlock* MBB,
167 SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
168 MachineInstr* FoldRestore(unsigned vreg,
169 const TargetRegisterClass* RC,
170 MachineInstr* Barrier,
171 MachineBasicBlock* MBB,
173 SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
174 void RenumberValno(VNInfo* VN);
175 void ReconstructLiveInterval(LiveInterval* LI);
176 bool removeDeadSpills(SmallPtrSet<LiveInterval*, 8>& split);
177 unsigned getNumberOfNonSpills(SmallPtrSet<MachineInstr*, 4>& MIs,
178 unsigned Reg, int FrameIndex, bool& TwoAddr);
179 VNInfo* PerformPHIConstruction(MachineBasicBlock::iterator Use,
180 MachineBasicBlock* MBB, LiveInterval* LI,
181 SmallPtrSet<MachineInstr*, 4>& Visited,
182 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
183 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
184 DenseMap<MachineInstr*, VNInfo*>& NewVNs,
185 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
186 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
187 bool IsTopLevel, bool IsIntraBlock);
188 VNInfo* PerformPHIConstructionFallBack(MachineBasicBlock::iterator Use,
189 MachineBasicBlock* MBB, LiveInterval* LI,
190 SmallPtrSet<MachineInstr*, 4>& Visited,
191 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
192 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
193 DenseMap<MachineInstr*, VNInfo*>& NewVNs,
194 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
195 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
196 bool IsTopLevel, bool IsIntraBlock);
198 } // end anonymous namespace
200 char PreAllocSplitting::ID = 0;
202 static RegisterPass<PreAllocSplitting>
203 X("pre-alloc-splitting", "Pre-Register Allocation Live Interval Splitting");
205 const PassInfo *const llvm::PreAllocSplittingID = &X;
208 /// findNextEmptySlot - Find a gap after the given machine instruction in the
209 /// instruction index map. If there isn't one, return end().
210 MachineBasicBlock::iterator
211 PreAllocSplitting::findNextEmptySlot(MachineBasicBlock *MBB, MachineInstr *MI,
212 LiveIndex &SpotIndex) {
213 MachineBasicBlock::iterator MII = MI;
214 if (++MII != MBB->end()) {
216 LIs->findGapBeforeInstr(LIs->getInstructionIndex(MII));
217 if (Index != LiveIndex()) {
225 /// findSpillPoint - Find a gap as far away from the given MI that's suitable
226 /// for spilling the current live interval. The index must be before any
227 /// defs and uses of the live interval register in the mbb. Return begin() if
229 MachineBasicBlock::iterator
230 PreAllocSplitting::findSpillPoint(MachineBasicBlock *MBB, MachineInstr *MI,
232 SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
233 LiveIndex &SpillIndex) {
234 MachineBasicBlock::iterator Pt = MBB->begin();
236 MachineBasicBlock::iterator MII = MI;
237 MachineBasicBlock::iterator EndPt = DefMI
238 ? MachineBasicBlock::iterator(DefMI) : MBB->begin();
240 while (MII != EndPt && !RefsInMBB.count(MII) &&
241 MII->getOpcode() != TRI->getCallFrameSetupOpcode())
243 if (MII == EndPt || RefsInMBB.count(MII)) return Pt;
245 while (MII != EndPt && !RefsInMBB.count(MII)) {
246 LiveIndex Index = LIs->getInstructionIndex(MII);
248 // We can't insert the spill between the barrier (a call), and its
249 // corresponding call frame setup.
250 if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode()) {
251 while (MII->getOpcode() != TRI->getCallFrameSetupOpcode()) {
258 } else if (LIs->hasGapBeforeInstr(Index)) {
260 SpillIndex = LIs->findGapBeforeInstr(Index, true);
263 if (RefsInMBB.count(MII))
273 /// findRestorePoint - Find a gap in the instruction index map that's suitable
274 /// for restoring the current live interval value. The index must be before any
275 /// uses of the live interval register in the mbb. Return end() if none is
277 MachineBasicBlock::iterator
278 PreAllocSplitting::findRestorePoint(MachineBasicBlock *MBB, MachineInstr *MI,
280 SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
281 LiveIndex &RestoreIndex) {
282 // FIXME: Allow spill to be inserted to the beginning of the mbb. Update mbb
283 // begin index accordingly.
284 MachineBasicBlock::iterator Pt = MBB->end();
285 MachineBasicBlock::iterator EndPt = MBB->getFirstTerminator();
287 // We start at the call, so walk forward until we find the call frame teardown
288 // since we can't insert restores before that. Bail if we encounter a use
290 MachineBasicBlock::iterator MII = MI;
291 if (MII == EndPt) return Pt;
293 while (MII != EndPt && !RefsInMBB.count(MII) &&
294 MII->getOpcode() != TRI->getCallFrameDestroyOpcode())
296 if (MII == EndPt || RefsInMBB.count(MII)) return Pt;
299 // FIXME: Limit the number of instructions to examine to reduce
301 while (MII != EndPt) {
302 LiveIndex Index = LIs->getInstructionIndex(MII);
305 LiveIndex Gap = LIs->findGapBeforeInstr(Index);
307 // We can't insert a restore between the barrier (a call) and its
308 // corresponding call frame teardown.
309 if (MII->getOpcode() == TRI->getCallFrameSetupOpcode()) {
311 if (MII == EndPt || RefsInMBB.count(MII)) return Pt;
313 } while (MII->getOpcode() != TRI->getCallFrameDestroyOpcode());
314 } else if (Gap != LiveIndex()) {
319 if (RefsInMBB.count(MII))
328 /// CreateSpillStackSlot - Create a stack slot for the live interval being
329 /// split. If the live interval was previously split, just reuse the same
331 int PreAllocSplitting::CreateSpillStackSlot(unsigned Reg,
332 const TargetRegisterClass *RC) {
334 DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(Reg);
335 if (I != IntervalSSMap.end()) {
338 SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
339 IntervalSSMap[Reg] = SS;
342 // Create live interval for stack slot.
343 CurrSLI = &LSs->getOrCreateInterval(SS, RC);
344 if (CurrSLI->hasAtLeastOneValue())
345 CurrSValNo = CurrSLI->getValNumInfo(0);
347 CurrSValNo = CurrSLI->getNextValue(LiveIndex(), 0, false,
348 LSs->getVNInfoAllocator());
352 /// IsAvailableInStack - Return true if register is available in a split stack
353 /// slot at the specified index.
355 PreAllocSplitting::IsAvailableInStack(MachineBasicBlock *DefMBB,
356 unsigned Reg, LiveIndex DefIndex,
357 LiveIndex RestoreIndex,
358 LiveIndex &SpillIndex,
363 DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(Reg);
364 if (I == IntervalSSMap.end())
366 DenseMap<LiveIndex, LiveIndex>::iterator
367 II = Def2SpillMap.find(DefIndex);
368 if (II == Def2SpillMap.end())
371 // If last spill of def is in the same mbb as barrier mbb (where restore will
372 // be), make sure it's not below the intended restore index.
373 // FIXME: Undo the previous spill?
374 assert(LIs->getMBBFromIndex(II->second) == DefMBB);
375 if (DefMBB == BarrierMBB && II->second >= RestoreIndex)
379 SpillIndex = II->second;
383 /// UpdateSpillSlotInterval - Given the specified val# of the register live
384 /// interval being split, and the spill and restore indicies, update the live
385 /// interval of the spill stack slot.
387 PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, LiveIndex SpillIndex,
388 LiveIndex RestoreIndex) {
389 assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB &&
390 "Expect restore in the barrier mbb");
392 MachineBasicBlock *MBB = LIs->getMBBFromIndex(SpillIndex);
393 if (MBB == BarrierMBB) {
394 // Intra-block spill + restore. We are done.
395 LiveRange SLR(SpillIndex, RestoreIndex, CurrSValNo);
396 CurrSLI->addRange(SLR);
400 SmallPtrSet<MachineBasicBlock*, 4> Processed;
401 LiveIndex EndIdx = LIs->getMBBEndIdx(MBB);
402 LiveRange SLR(SpillIndex, LIs->getNextSlot(EndIdx), CurrSValNo);
403 CurrSLI->addRange(SLR);
404 Processed.insert(MBB);
406 // Start from the spill mbb, figure out the extend of the spill slot's
408 SmallVector<MachineBasicBlock*, 4> WorkList;
409 const LiveRange *LR = CurrLI->getLiveRangeContaining(SpillIndex);
410 if (LR->end > EndIdx)
411 // If live range extend beyond end of mbb, add successors to work list.
412 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
413 SE = MBB->succ_end(); SI != SE; ++SI)
414 WorkList.push_back(*SI);
416 while (!WorkList.empty()) {
417 MachineBasicBlock *MBB = WorkList.back();
419 if (Processed.count(MBB))
421 LiveIndex Idx = LIs->getMBBStartIdx(MBB);
422 LR = CurrLI->getLiveRangeContaining(Idx);
423 if (LR && LR->valno == ValNo) {
424 EndIdx = LIs->getMBBEndIdx(MBB);
425 if (Idx <= RestoreIndex && RestoreIndex < EndIdx) {
426 // Spill slot live interval stops at the restore.
427 LiveRange SLR(Idx, RestoreIndex, CurrSValNo);
428 CurrSLI->addRange(SLR);
429 } else if (LR->end > EndIdx) {
430 // Live range extends beyond end of mbb, process successors.
431 LiveRange SLR(Idx, LIs->getNextIndex(EndIdx), CurrSValNo);
432 CurrSLI->addRange(SLR);
433 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
434 SE = MBB->succ_end(); SI != SE; ++SI)
435 WorkList.push_back(*SI);
437 LiveRange SLR(Idx, LR->end, CurrSValNo);
438 CurrSLI->addRange(SLR);
440 Processed.insert(MBB);
445 /// PerformPHIConstruction - From properly set up use and def lists, use a PHI
446 /// construction algorithm to compute the ranges and valnos for an interval.
448 PreAllocSplitting::PerformPHIConstruction(MachineBasicBlock::iterator UseI,
449 MachineBasicBlock* MBB, LiveInterval* LI,
450 SmallPtrSet<MachineInstr*, 4>& Visited,
451 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
452 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
453 DenseMap<MachineInstr*, VNInfo*>& NewVNs,
454 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
455 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
456 bool IsTopLevel, bool IsIntraBlock) {
457 // Return memoized result if it's available.
458 if (IsTopLevel && Visited.count(UseI) && NewVNs.count(UseI))
460 else if (!IsTopLevel && IsIntraBlock && NewVNs.count(UseI))
462 else if (!IsIntraBlock && LiveOut.count(MBB))
465 // Check if our block contains any uses or defs.
466 bool ContainsDefs = Defs.count(MBB);
467 bool ContainsUses = Uses.count(MBB);
471 // Enumerate the cases of use/def contaning blocks.
472 if (!ContainsDefs && !ContainsUses) {
473 return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs, Uses,
474 NewVNs, LiveOut, Phis,
475 IsTopLevel, IsIntraBlock);
476 } else if (ContainsDefs && !ContainsUses) {
477 SmallPtrSet<MachineInstr*, 2>& BlockDefs = Defs[MBB];
479 // Search for the def in this block. If we don't find it before the
480 // instruction we care about, go to the fallback case. Note that that
481 // should never happen: this cannot be intrablock, so use should
482 // always be an end() iterator.
483 assert(UseI == MBB->end() && "No use marked in intrablock");
485 MachineBasicBlock::iterator Walker = UseI;
487 while (Walker != MBB->begin()) {
488 if (BlockDefs.count(Walker))
493 // Once we've found it, extend its VNInfo to our instruction.
494 LiveIndex DefIndex = LIs->getInstructionIndex(Walker);
495 DefIndex = LIs->getDefIndex(DefIndex);
496 LiveIndex EndIndex = LIs->getMBBEndIdx(MBB);
498 RetVNI = NewVNs[Walker];
499 LI->addRange(LiveRange(DefIndex, LIs->getNextSlot(EndIndex), RetVNI));
500 } else if (!ContainsDefs && ContainsUses) {
501 SmallPtrSet<MachineInstr*, 2>& BlockUses = Uses[MBB];
503 // Search for the use in this block that precedes the instruction we care
504 // about, going to the fallback case if we don't find it.
505 if (UseI == MBB->begin())
506 return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs,
507 Uses, NewVNs, LiveOut, Phis,
508 IsTopLevel, IsIntraBlock);
510 MachineBasicBlock::iterator Walker = UseI;
513 while (Walker != MBB->begin()) {
514 if (BlockUses.count(Walker)) {
521 // Must check begin() too.
523 if (BlockUses.count(Walker))
526 return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs,
527 Uses, NewVNs, LiveOut, Phis,
528 IsTopLevel, IsIntraBlock);
531 LiveIndex UseIndex = LIs->getInstructionIndex(Walker);
532 UseIndex = LIs->getUseIndex(UseIndex);
535 EndIndex = LIs->getInstructionIndex(UseI);
536 EndIndex = LIs->getUseIndex(EndIndex);
538 EndIndex = LIs->getMBBEndIdx(MBB);
540 // Now, recursively phi construct the VNInfo for the use we found,
541 // and then extend it to include the instruction we care about
542 RetVNI = PerformPHIConstruction(Walker, MBB, LI, Visited, Defs, Uses,
543 NewVNs, LiveOut, Phis, false, true);
545 LI->addRange(LiveRange(UseIndex, LIs->getNextSlot(EndIndex), RetVNI));
547 // FIXME: Need to set kills properly for inter-block stuff.
548 if (RetVNI->isKill(UseIndex)) RetVNI->removeKill(UseIndex);
550 RetVNI->addKill(EndIndex);
551 } else if (ContainsDefs && ContainsUses) {
552 SmallPtrSet<MachineInstr*, 2>& BlockDefs = Defs[MBB];
553 SmallPtrSet<MachineInstr*, 2>& BlockUses = Uses[MBB];
555 // This case is basically a merging of the two preceding case, with the
556 // special note that checking for defs must take precedence over checking
557 // for uses, because of two-address instructions.
559 if (UseI == MBB->begin())
560 return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs, Uses,
561 NewVNs, LiveOut, Phis,
562 IsTopLevel, IsIntraBlock);
564 MachineBasicBlock::iterator Walker = UseI;
566 bool foundDef = false;
567 bool foundUse = false;
568 while (Walker != MBB->begin()) {
569 if (BlockDefs.count(Walker)) {
572 } else if (BlockUses.count(Walker)) {
579 // Must check begin() too.
580 if (!foundDef && !foundUse) {
581 if (BlockDefs.count(Walker))
583 else if (BlockUses.count(Walker))
586 return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs,
587 Uses, NewVNs, LiveOut, Phis,
588 IsTopLevel, IsIntraBlock);
591 LiveIndex StartIndex = LIs->getInstructionIndex(Walker);
592 StartIndex = foundDef ? LIs->getDefIndex(StartIndex) :
593 LIs->getUseIndex(StartIndex);
596 EndIndex = LIs->getInstructionIndex(UseI);
597 EndIndex = LIs->getUseIndex(EndIndex);
599 EndIndex = LIs->getMBBEndIdx(MBB);
602 RetVNI = NewVNs[Walker];
604 RetVNI = PerformPHIConstruction(Walker, MBB, LI, Visited, Defs, Uses,
605 NewVNs, LiveOut, Phis, false, true);
607 LI->addRange(LiveRange(StartIndex, LIs->getNextSlot(EndIndex), RetVNI));
609 if (foundUse && RetVNI->isKill(StartIndex))
610 RetVNI->removeKill(StartIndex);
612 RetVNI->addKill(EndIndex);
616 // Memoize results so we don't have to recompute them.
617 if (!IsIntraBlock) LiveOut[MBB] = RetVNI;
619 if (!NewVNs.count(UseI))
620 NewVNs[UseI] = RetVNI;
621 Visited.insert(UseI);
627 /// PerformPHIConstructionFallBack - PerformPHIConstruction fall back path.
630 PreAllocSplitting::PerformPHIConstructionFallBack(MachineBasicBlock::iterator UseI,
631 MachineBasicBlock* MBB, LiveInterval* LI,
632 SmallPtrSet<MachineInstr*, 4>& Visited,
633 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
634 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
635 DenseMap<MachineInstr*, VNInfo*>& NewVNs,
636 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
637 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
638 bool IsTopLevel, bool IsIntraBlock) {
639 // NOTE: Because this is the fallback case from other cases, we do NOT
640 // assume that we are not intrablock here.
641 if (Phis.count(MBB)) return Phis[MBB];
643 LiveIndex StartIndex = LIs->getMBBStartIdx(MBB);
644 VNInfo *RetVNI = Phis[MBB] =
645 LI->getNextValue(LiveIndex(), /*FIXME*/ 0, false,
646 LIs->getVNInfoAllocator());
648 if (!IsIntraBlock) LiveOut[MBB] = RetVNI;
650 // If there are no uses or defs between our starting point and the
651 // beginning of the block, then recursive perform phi construction
652 // on our predecessors.
653 DenseMap<MachineBasicBlock*, VNInfo*> IncomingVNs;
654 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
655 PE = MBB->pred_end(); PI != PE; ++PI) {
656 VNInfo* Incoming = PerformPHIConstruction((*PI)->end(), *PI, LI,
657 Visited, Defs, Uses, NewVNs,
658 LiveOut, Phis, false, false);
660 IncomingVNs[*PI] = Incoming;
663 if (MBB->pred_size() == 1 && !RetVNI->hasPHIKill()) {
664 VNInfo* OldVN = RetVNI;
665 VNInfo* NewVN = IncomingVNs.begin()->second;
666 VNInfo* MergedVN = LI->MergeValueNumberInto(OldVN, NewVN);
667 if (MergedVN == OldVN) std::swap(OldVN, NewVN);
669 for (DenseMap<MachineBasicBlock*, VNInfo*>::iterator LOI = LiveOut.begin(),
670 LOE = LiveOut.end(); LOI != LOE; ++LOI)
671 if (LOI->second == OldVN)
672 LOI->second = MergedVN;
673 for (DenseMap<MachineInstr*, VNInfo*>::iterator NVI = NewVNs.begin(),
674 NVE = NewVNs.end(); NVI != NVE; ++NVI)
675 if (NVI->second == OldVN)
676 NVI->second = MergedVN;
677 for (DenseMap<MachineBasicBlock*, VNInfo*>::iterator PI = Phis.begin(),
678 PE = Phis.end(); PI != PE; ++PI)
679 if (PI->second == OldVN)
680 PI->second = MergedVN;
683 // Otherwise, merge the incoming VNInfos with a phi join. Create a new
684 // VNInfo to represent the joined value.
685 for (DenseMap<MachineBasicBlock*, VNInfo*>::iterator I =
686 IncomingVNs.begin(), E = IncomingVNs.end(); I != E; ++I) {
687 I->second->setHasPHIKill(true);
688 LiveIndex KillIndex = LIs->getMBBEndIdx(I->first);
689 if (!I->second->isKill(KillIndex))
690 I->second->addKill(KillIndex);
696 EndIndex = LIs->getInstructionIndex(UseI);
697 EndIndex = LIs->getUseIndex(EndIndex);
699 EndIndex = LIs->getMBBEndIdx(MBB);
700 LI->addRange(LiveRange(StartIndex, LIs->getNextSlot(EndIndex), RetVNI));
702 RetVNI->addKill(EndIndex);
704 // Memoize results so we don't have to recompute them.
706 LiveOut[MBB] = RetVNI;
708 if (!NewVNs.count(UseI))
709 NewVNs[UseI] = RetVNI;
710 Visited.insert(UseI);
716 /// ReconstructLiveInterval - Recompute a live interval from scratch.
717 void PreAllocSplitting::ReconstructLiveInterval(LiveInterval* LI) {
718 BumpPtrAllocator& Alloc = LIs->getVNInfoAllocator();
720 // Clear the old ranges and valnos;
723 // Cache the uses and defs of the register
724 typedef DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> > RegMap;
727 // Keep track of the new VNs we're creating.
728 DenseMap<MachineInstr*, VNInfo*> NewVNs;
729 SmallPtrSet<VNInfo*, 2> PhiVNs;
731 // Cache defs, and create a new VNInfo for each def.
732 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg),
733 DE = MRI->def_end(); DI != DE; ++DI) {
734 Defs[(*DI).getParent()].insert(&*DI);
736 LiveIndex DefIdx = LIs->getInstructionIndex(&*DI);
737 DefIdx = LIs->getDefIndex(DefIdx);
739 assert(DI->getOpcode() != TargetInstrInfo::PHI &&
740 "Following NewVN isPHIDef flag incorrect. Fix me!");
741 VNInfo* NewVN = LI->getNextValue(DefIdx, 0, true, Alloc);
743 // If the def is a move, set the copy field.
744 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
745 if (TII->isMoveInstr(*DI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
746 if (DstReg == LI->reg)
747 NewVN->setCopy(&*DI);
749 NewVNs[&*DI] = NewVN;
752 // Cache uses as a separate pass from actually processing them.
753 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(LI->reg),
754 UE = MRI->use_end(); UI != UE; ++UI)
755 Uses[(*UI).getParent()].insert(&*UI);
757 // Now, actually process every use and use a phi construction algorithm
758 // to walk from it to its reaching definitions, building VNInfos along
760 DenseMap<MachineBasicBlock*, VNInfo*> LiveOut;
761 DenseMap<MachineBasicBlock*, VNInfo*> Phis;
762 SmallPtrSet<MachineInstr*, 4> Visited;
763 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(LI->reg),
764 UE = MRI->use_end(); UI != UE; ++UI) {
765 PerformPHIConstruction(&*UI, UI->getParent(), LI, Visited, Defs,
766 Uses, NewVNs, LiveOut, Phis, true, true);
769 // Add ranges for dead defs
770 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg),
771 DE = MRI->def_end(); DI != DE; ++DI) {
772 LiveIndex DefIdx = LIs->getInstructionIndex(&*DI);
773 DefIdx = LIs->getDefIndex(DefIdx);
775 if (LI->liveAt(DefIdx)) continue;
777 VNInfo* DeadVN = NewVNs[&*DI];
778 LI->addRange(LiveRange(DefIdx, LIs->getNextSlot(DefIdx), DeadVN));
779 DeadVN->addKill(DefIdx);
782 // Update kill markers.
783 for (LiveInterval::vni_iterator VI = LI->vni_begin(), VE = LI->vni_end();
786 for (unsigned i = 0, e = VNI->kills.size(); i != e; ++i) {
787 LiveIndex KillIdx = VNI->kills[i];
788 if (KillIdx.isPHIIndex())
790 MachineInstr *KillMI = LIs->getInstructionFromIndex(KillIdx);
792 MachineOperand *KillMO = KillMI->findRegisterUseOperand(CurrLI->reg);
794 // It could be a dead def.
801 /// RenumberValno - Split the given valno out into a new vreg, allowing it to
802 /// be allocated to a different register. This function creates a new vreg,
803 /// copies the valno and its live ranges over to the new vreg's interval,
804 /// removes them from the old interval, and rewrites all uses and defs of
805 /// the original reg to the new vreg within those ranges.
806 void PreAllocSplitting::RenumberValno(VNInfo* VN) {
807 SmallVector<VNInfo*, 4> Stack;
808 SmallVector<VNInfo*, 4> VNsToCopy;
811 // Walk through and copy the valno we care about, and any other valnos
812 // that are two-address redefinitions of the one we care about. These
813 // will need to be rewritten as well. We also check for safety of the
814 // renumbering here, by making sure that none of the valno involved has
816 while (!Stack.empty()) {
817 VNInfo* OldVN = Stack.back();
820 // Bail out if we ever encounter a valno that has a PHI kill. We can't
822 if (OldVN->hasPHIKill()) return;
824 VNsToCopy.push_back(OldVN);
826 // Locate two-address redefinitions
827 for (VNInfo::KillSet::iterator KI = OldVN->kills.begin(),
828 KE = OldVN->kills.end(); KI != KE; ++KI) {
829 assert(!KI->isPHIIndex() &&
830 "VN previously reported having no PHI kills.");
831 MachineInstr* MI = LIs->getInstructionFromIndex(*KI);
832 unsigned DefIdx = MI->findRegisterDefOperandIdx(CurrLI->reg);
833 if (DefIdx == ~0U) continue;
834 if (MI->isRegTiedToUseOperand(DefIdx)) {
836 CurrLI->findDefinedVNInfoForRegInt(LIs->getDefIndex(*KI));
837 if (NextVN == OldVN) continue;
838 Stack.push_back(NextVN);
843 // Create the new vreg
844 unsigned NewVReg = MRI->createVirtualRegister(MRI->getRegClass(CurrLI->reg));
846 // Create the new live interval
847 LiveInterval& NewLI = LIs->getOrCreateInterval(NewVReg);
849 for (SmallVector<VNInfo*, 4>::iterator OI = VNsToCopy.begin(), OE =
850 VNsToCopy.end(); OI != OE; ++OI) {
853 // Copy the valno over
854 VNInfo* NewVN = NewLI.createValueCopy(OldVN, LIs->getVNInfoAllocator());
855 NewLI.MergeValueInAsValue(*CurrLI, OldVN, NewVN);
857 // Remove the valno from the old interval
858 CurrLI->removeValNo(OldVN);
861 // Rewrite defs and uses. This is done in two stages to avoid invalidating
863 SmallVector<std::pair<MachineInstr*, unsigned>, 8> OpsToChange;
865 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg),
866 E = MRI->reg_end(); I != E; ++I) {
867 MachineOperand& MO = I.getOperand();
868 LiveIndex InstrIdx = LIs->getInstructionIndex(&*I);
870 if ((MO.isUse() && NewLI.liveAt(LIs->getUseIndex(InstrIdx))) ||
871 (MO.isDef() && NewLI.liveAt(LIs->getDefIndex(InstrIdx))))
872 OpsToChange.push_back(std::make_pair(&*I, I.getOperandNo()));
875 for (SmallVector<std::pair<MachineInstr*, unsigned>, 8>::iterator I =
876 OpsToChange.begin(), E = OpsToChange.end(); I != E; ++I) {
877 MachineInstr* Inst = I->first;
878 unsigned OpIdx = I->second;
879 MachineOperand& MO = Inst->getOperand(OpIdx);
883 // Grow the VirtRegMap, since we've created a new vreg.
886 // The renumbered vreg shares a stack slot with the old register.
887 if (IntervalSSMap.count(CurrLI->reg))
888 IntervalSSMap[NewVReg] = IntervalSSMap[CurrLI->reg];
893 bool PreAllocSplitting::Rematerialize(unsigned VReg, VNInfo* ValNo,
895 MachineBasicBlock::iterator RestorePt,
896 LiveIndex RestoreIdx,
897 SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
898 MachineBasicBlock& MBB = *RestorePt->getParent();
900 MachineBasicBlock::iterator KillPt = BarrierMBB->end();
902 if (!ValNo->isDefAccurate() || DefMI->getParent() == BarrierMBB)
903 KillPt = findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB, KillIdx);
905 KillPt = findNextEmptySlot(DefMI->getParent(), DefMI, KillIdx);
907 if (KillPt == DefMI->getParent()->end())
910 TII->reMaterialize(MBB, RestorePt, VReg, 0, DefMI);
911 LIs->InsertMachineInstrInMaps(prior(RestorePt), RestoreIdx);
913 ReconstructLiveInterval(CurrLI);
914 LiveIndex RematIdx = LIs->getInstructionIndex(prior(RestorePt));
915 RematIdx = LIs->getDefIndex(RematIdx);
916 RenumberValno(CurrLI->findDefinedVNInfoForRegInt(RematIdx));
923 MachineInstr* PreAllocSplitting::FoldSpill(unsigned vreg,
924 const TargetRegisterClass* RC,
926 MachineInstr* Barrier,
927 MachineBasicBlock* MBB,
929 SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
930 MachineBasicBlock::iterator Pt = MBB->begin();
932 // Go top down if RefsInMBB is empty.
933 if (RefsInMBB.empty())
936 MachineBasicBlock::iterator FoldPt = Barrier;
937 while (&*FoldPt != DefMI && FoldPt != MBB->begin() &&
938 !RefsInMBB.count(FoldPt))
941 int OpIdx = FoldPt->findRegisterDefOperandIdx(vreg, false);
945 SmallVector<unsigned, 1> Ops;
946 Ops.push_back(OpIdx);
948 if (!TII->canFoldMemoryOperand(FoldPt, Ops))
951 DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(vreg);
952 if (I != IntervalSSMap.end()) {
955 SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
958 MachineInstr* FMI = TII->foldMemoryOperand(*MBB->getParent(),
962 LIs->ReplaceMachineInstrInMaps(FoldPt, FMI);
963 FMI = MBB->insert(MBB->erase(FoldPt), FMI);
966 IntervalSSMap[vreg] = SS;
967 CurrSLI = &LSs->getOrCreateInterval(SS, RC);
968 if (CurrSLI->hasAtLeastOneValue())
969 CurrSValNo = CurrSLI->getValNumInfo(0);
971 CurrSValNo = CurrSLI->getNextValue(LiveIndex(), 0, false,
972 LSs->getVNInfoAllocator());
978 MachineInstr* PreAllocSplitting::FoldRestore(unsigned vreg,
979 const TargetRegisterClass* RC,
980 MachineInstr* Barrier,
981 MachineBasicBlock* MBB,
983 SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
984 if ((int)RestoreFoldLimit != -1 && RestoreFoldLimit == (int)NumRestoreFolds)
987 // Go top down if RefsInMBB is empty.
988 if (RefsInMBB.empty())
991 // Can't fold a restore between a call stack setup and teardown.
992 MachineBasicBlock::iterator FoldPt = Barrier;
994 // Advance from barrier to call frame teardown.
995 while (FoldPt != MBB->getFirstTerminator() &&
996 FoldPt->getOpcode() != TRI->getCallFrameDestroyOpcode()) {
997 if (RefsInMBB.count(FoldPt))
1003 if (FoldPt == MBB->getFirstTerminator())
1008 // Now find the restore point.
1009 while (FoldPt != MBB->getFirstTerminator() && !RefsInMBB.count(FoldPt)) {
1010 if (FoldPt->getOpcode() == TRI->getCallFrameSetupOpcode()) {
1011 while (FoldPt != MBB->getFirstTerminator() &&
1012 FoldPt->getOpcode() != TRI->getCallFrameDestroyOpcode()) {
1013 if (RefsInMBB.count(FoldPt))
1019 if (FoldPt == MBB->getFirstTerminator())
1026 if (FoldPt == MBB->getFirstTerminator())
1029 int OpIdx = FoldPt->findRegisterUseOperandIdx(vreg, true);
1033 SmallVector<unsigned, 1> Ops;
1034 Ops.push_back(OpIdx);
1036 if (!TII->canFoldMemoryOperand(FoldPt, Ops))
1039 MachineInstr* FMI = TII->foldMemoryOperand(*MBB->getParent(),
1043 LIs->ReplaceMachineInstrInMaps(FoldPt, FMI);
1044 FMI = MBB->insert(MBB->erase(FoldPt), FMI);
1051 /// SplitRegLiveInterval - Split (spill and restore) the given live interval
1052 /// so it would not cross the barrier that's being processed. Shrink wrap
1053 /// (minimize) the live interval to the last uses.
1054 bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
1057 // Find live range where current interval cross the barrier.
1058 LiveInterval::iterator LR =
1059 CurrLI->FindLiveRangeContaining(LIs->getUseIndex(BarrierIdx));
1060 VNInfo *ValNo = LR->valno;
1062 assert(!ValNo->isUnused() && "Val# is defined by a dead def?");
1064 MachineInstr *DefMI = ValNo->isDefAccurate()
1065 ? LIs->getInstructionFromIndex(ValNo->def) : NULL;
1067 // If this would create a new join point, do not split.
1068 if (DefMI && createsNewJoin(LR, DefMI->getParent(), Barrier->getParent()))
1071 // Find all references in the barrier mbb.
1072 SmallPtrSet<MachineInstr*, 4> RefsInMBB;
1073 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg),
1074 E = MRI->reg_end(); I != E; ++I) {
1075 MachineInstr *RefMI = &*I;
1076 if (RefMI->getParent() == BarrierMBB)
1077 RefsInMBB.insert(RefMI);
1080 // Find a point to restore the value after the barrier.
1081 LiveIndex RestoreIndex;
1082 MachineBasicBlock::iterator RestorePt =
1083 findRestorePoint(BarrierMBB, Barrier, LR->end, RefsInMBB, RestoreIndex);
1084 if (RestorePt == BarrierMBB->end())
1087 if (DefMI && LIs->isReMaterializable(*LI, ValNo, DefMI))
1088 if (Rematerialize(LI->reg, ValNo, DefMI, RestorePt,
1089 RestoreIndex, RefsInMBB))
1092 // Add a spill either before the barrier or after the definition.
1093 MachineBasicBlock *DefMBB = DefMI ? DefMI->getParent() : NULL;
1094 const TargetRegisterClass *RC = MRI->getRegClass(CurrLI->reg);
1095 LiveIndex SpillIndex;
1096 MachineInstr *SpillMI = NULL;
1098 if (!ValNo->isDefAccurate()) {
1099 // If we don't know where the def is we must split just before the barrier.
1100 if ((SpillMI = FoldSpill(LI->reg, RC, 0, Barrier,
1101 BarrierMBB, SS, RefsInMBB))) {
1102 SpillIndex = LIs->getInstructionIndex(SpillMI);
1104 MachineBasicBlock::iterator SpillPt =
1105 findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB, SpillIndex);
1106 if (SpillPt == BarrierMBB->begin())
1107 return false; // No gap to insert spill.
1110 SS = CreateSpillStackSlot(CurrLI->reg, RC);
1111 TII->storeRegToStackSlot(*BarrierMBB, SpillPt, CurrLI->reg, true, SS, RC);
1112 SpillMI = prior(SpillPt);
1113 LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
1115 } else if (!IsAvailableInStack(DefMBB, CurrLI->reg, ValNo->def,
1116 RestoreIndex, SpillIndex, SS)) {
1117 // If it's already split, just restore the value. There is no need to spill
1120 return false; // Def is dead. Do nothing.
1122 if ((SpillMI = FoldSpill(LI->reg, RC, DefMI, Barrier,
1123 BarrierMBB, SS, RefsInMBB))) {
1124 SpillIndex = LIs->getInstructionIndex(SpillMI);
1126 // Check if it's possible to insert a spill after the def MI.
1127 MachineBasicBlock::iterator SpillPt;
1128 if (DefMBB == BarrierMBB) {
1129 // Add spill after the def and the last use before the barrier.
1130 SpillPt = findSpillPoint(BarrierMBB, Barrier, DefMI,
1131 RefsInMBB, SpillIndex);
1132 if (SpillPt == DefMBB->begin())
1133 return false; // No gap to insert spill.
1135 SpillPt = findNextEmptySlot(DefMBB, DefMI, SpillIndex);
1136 if (SpillPt == DefMBB->end())
1137 return false; // No gap to insert spill.
1140 SS = CreateSpillStackSlot(CurrLI->reg, RC);
1141 TII->storeRegToStackSlot(*DefMBB, SpillPt, CurrLI->reg, false, SS, RC);
1142 SpillMI = prior(SpillPt);
1143 LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
1147 // Remember def instruction index to spill index mapping.
1148 if (DefMI && SpillMI)
1149 Def2SpillMap[ValNo->def] = SpillIndex;
1152 bool FoldedRestore = false;
1153 if (MachineInstr* LMI = FoldRestore(CurrLI->reg, RC, Barrier,
1154 BarrierMBB, SS, RefsInMBB)) {
1156 RestoreIndex = LIs->getInstructionIndex(RestorePt);
1157 FoldedRestore = true;
1159 TII->loadRegFromStackSlot(*BarrierMBB, RestorePt, CurrLI->reg, SS, RC);
1160 MachineInstr *LoadMI = prior(RestorePt);
1161 LIs->InsertMachineInstrInMaps(LoadMI, RestoreIndex);
1164 // Update spill stack slot live interval.
1165 UpdateSpillSlotInterval(ValNo, LIs->getNextSlot(LIs->getUseIndex(SpillIndex)),
1166 LIs->getDefIndex(RestoreIndex));
1168 ReconstructLiveInterval(CurrLI);
1170 if (!FoldedRestore) {
1171 LiveIndex RestoreIdx = LIs->getInstructionIndex(prior(RestorePt));
1172 RestoreIdx = LIs->getDefIndex(RestoreIdx);
1173 RenumberValno(CurrLI->findDefinedVNInfoForRegInt(RestoreIdx));
1180 /// SplitRegLiveIntervals - Split all register live intervals that cross the
1181 /// barrier that's being processed.
1183 PreAllocSplitting::SplitRegLiveIntervals(const TargetRegisterClass **RCs,
1184 SmallPtrSet<LiveInterval*, 8>& Split) {
1185 // First find all the virtual registers whose live intervals are intercepted
1186 // by the current barrier.
1187 SmallVector<LiveInterval*, 8> Intervals;
1188 for (const TargetRegisterClass **RC = RCs; *RC; ++RC) {
1189 // FIXME: If it's not safe to move any instruction that defines the barrier
1190 // register class, then it means there are some special dependencies which
1191 // codegen is not modelling. Ignore these barriers for now.
1192 if (!TII->isSafeToMoveRegClassDefs(*RC))
1194 std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
1195 for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
1196 unsigned Reg = VRs[i];
1197 if (!LIs->hasInterval(Reg))
1199 LiveInterval *LI = &LIs->getInterval(Reg);
1200 if (LI->liveAt(BarrierIdx) && !Barrier->readsRegister(Reg))
1201 // Virtual register live interval is intercepted by the barrier. We
1202 // should split and shrink wrap its interval if possible.
1203 Intervals.push_back(LI);
1207 // Process the affected live intervals.
1208 bool Change = false;
1209 while (!Intervals.empty()) {
1210 if (PreSplitLimit != -1 && (int)NumSplits == PreSplitLimit)
1212 LiveInterval *LI = Intervals.back();
1213 Intervals.pop_back();
1214 bool result = SplitRegLiveInterval(LI);
1215 if (result) Split.insert(LI);
1222 unsigned PreAllocSplitting::getNumberOfNonSpills(
1223 SmallPtrSet<MachineInstr*, 4>& MIs,
1224 unsigned Reg, int FrameIndex,
1225 bool& FeedsTwoAddr) {
1226 unsigned NonSpills = 0;
1227 for (SmallPtrSet<MachineInstr*, 4>::iterator UI = MIs.begin(), UE = MIs.end();
1229 int StoreFrameIndex;
1230 unsigned StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
1231 if (StoreVReg != Reg || StoreFrameIndex != FrameIndex)
1234 int DefIdx = (*UI)->findRegisterDefOperandIdx(Reg);
1235 if (DefIdx != -1 && (*UI)->isRegTiedToUseOperand(DefIdx))
1236 FeedsTwoAddr = true;
1242 /// removeDeadSpills - After doing splitting, filter through all intervals we've
1243 /// split, and see if any of the spills are unnecessary. If so, remove them.
1244 bool PreAllocSplitting::removeDeadSpills(SmallPtrSet<LiveInterval*, 8>& split) {
1245 bool changed = false;
1247 // Walk over all of the live intervals that were touched by the splitter,
1248 // and see if we can do any DCE and/or folding.
1249 for (SmallPtrSet<LiveInterval*, 8>::iterator LI = split.begin(),
1250 LE = split.end(); LI != LE; ++LI) {
1251 DenseMap<VNInfo*, SmallPtrSet<MachineInstr*, 4> > VNUseCount;
1253 // First, collect all the uses of the vreg, and sort them by their
1254 // reaching definition (VNInfo).
1255 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin((*LI)->reg),
1256 UE = MRI->use_end(); UI != UE; ++UI) {
1257 LiveIndex index = LIs->getInstructionIndex(&*UI);
1258 index = LIs->getUseIndex(index);
1260 const LiveRange* LR = (*LI)->getLiveRangeContaining(index);
1261 VNUseCount[LR->valno].insert(&*UI);
1264 // Now, take the definitions (VNInfo's) one at a time and try to DCE
1265 // and/or fold them away.
1266 for (LiveInterval::vni_iterator VI = (*LI)->vni_begin(),
1267 VE = (*LI)->vni_end(); VI != VE; ++VI) {
1269 if (DeadSplitLimit != -1 && (int)NumDeadSpills == DeadSplitLimit)
1272 VNInfo* CurrVN = *VI;
1274 // We don't currently try to handle definitions with PHI kills, because
1275 // it would involve processing more than one VNInfo at once.
1276 if (CurrVN->hasPHIKill()) continue;
1278 // We also don't try to handle the results of PHI joins, since there's
1279 // no defining instruction to analyze.
1280 if (!CurrVN->isDefAccurate() || CurrVN->isUnused()) continue;
1282 // We're only interested in eliminating cruft introduced by the splitter,
1283 // is of the form load-use or load-use-store. First, check that the
1284 // definition is a load, and remember what stack slot we loaded it from.
1285 MachineInstr* DefMI = LIs->getInstructionFromIndex(CurrVN->def);
1287 if (!TII->isLoadFromStackSlot(DefMI, FrameIndex)) continue;
1289 // If the definition has no uses at all, just DCE it.
1290 if (VNUseCount[CurrVN].size() == 0) {
1291 LIs->RemoveMachineInstrFromMaps(DefMI);
1292 (*LI)->removeValNo(CurrVN);
1293 DefMI->eraseFromParent();
1294 VNUseCount.erase(CurrVN);
1300 // Second, get the number of non-store uses of the definition, as well as
1301 // a flag indicating whether it feeds into a later two-address definition.
1302 bool FeedsTwoAddr = false;
1303 unsigned NonSpillCount = getNumberOfNonSpills(VNUseCount[CurrVN],
1304 (*LI)->reg, FrameIndex,
1307 // If there's one non-store use and it doesn't feed a two-addr, then
1308 // this is a load-use-store case that we can try to fold.
1309 if (NonSpillCount == 1 && !FeedsTwoAddr) {
1310 // Start by finding the non-store use MachineInstr.
1311 SmallPtrSet<MachineInstr*, 4>::iterator UI = VNUseCount[CurrVN].begin();
1312 int StoreFrameIndex;
1313 unsigned StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
1314 while (UI != VNUseCount[CurrVN].end() &&
1315 (StoreVReg == (*LI)->reg && StoreFrameIndex == FrameIndex)) {
1317 if (UI != VNUseCount[CurrVN].end())
1318 StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex);
1320 if (UI == VNUseCount[CurrVN].end()) continue;
1322 MachineInstr* use = *UI;
1324 // Attempt to fold it away!
1325 int OpIdx = use->findRegisterUseOperandIdx((*LI)->reg, false);
1326 if (OpIdx == -1) continue;
1327 SmallVector<unsigned, 1> Ops;
1328 Ops.push_back(OpIdx);
1329 if (!TII->canFoldMemoryOperand(use, Ops)) continue;
1331 MachineInstr* NewMI =
1332 TII->foldMemoryOperand(*use->getParent()->getParent(),
1333 use, Ops, FrameIndex);
1335 if (!NewMI) continue;
1337 // Update relevant analyses.
1338 LIs->RemoveMachineInstrFromMaps(DefMI);
1339 LIs->ReplaceMachineInstrInMaps(use, NewMI);
1340 (*LI)->removeValNo(CurrVN);
1342 DefMI->eraseFromParent();
1343 MachineBasicBlock* MBB = use->getParent();
1344 NewMI = MBB->insert(MBB->erase(use), NewMI);
1345 VNUseCount[CurrVN].erase(use);
1347 // Remove deleted instructions. Note that we need to remove them from
1348 // the VNInfo->use map as well, just to be safe.
1349 for (SmallPtrSet<MachineInstr*, 4>::iterator II =
1350 VNUseCount[CurrVN].begin(), IE = VNUseCount[CurrVN].end();
1352 for (DenseMap<VNInfo*, SmallPtrSet<MachineInstr*, 4> >::iterator
1353 VNI = VNUseCount.begin(), VNE = VNUseCount.end(); VNI != VNE;
1355 if (VNI->first != CurrVN)
1356 VNI->second.erase(*II);
1357 LIs->RemoveMachineInstrFromMaps(*II);
1358 (*II)->eraseFromParent();
1361 VNUseCount.erase(CurrVN);
1363 for (DenseMap<VNInfo*, SmallPtrSet<MachineInstr*, 4> >::iterator
1364 VI = VNUseCount.begin(), VE = VNUseCount.end(); VI != VE; ++VI)
1365 if (VI->second.erase(use))
1366 VI->second.insert(NewMI);
1373 // If there's more than one non-store instruction, we can't profitably
1374 // fold it, so bail.
1375 if (NonSpillCount) continue;
1377 // Otherwise, this is a load-store case, so DCE them.
1378 for (SmallPtrSet<MachineInstr*, 4>::iterator UI =
1379 VNUseCount[CurrVN].begin(), UE = VNUseCount[CurrVN].end();
1381 LIs->RemoveMachineInstrFromMaps(*UI);
1382 (*UI)->eraseFromParent();
1385 VNUseCount.erase(CurrVN);
1387 LIs->RemoveMachineInstrFromMaps(DefMI);
1388 (*LI)->removeValNo(CurrVN);
1389 DefMI->eraseFromParent();
1398 bool PreAllocSplitting::createsNewJoin(LiveRange* LR,
1399 MachineBasicBlock* DefMBB,
1400 MachineBasicBlock* BarrierMBB) {
1401 if (DefMBB == BarrierMBB)
1404 if (LR->valno->hasPHIKill())
1407 LiveIndex MBBEnd = LIs->getMBBEndIdx(BarrierMBB);
1408 if (LR->end < MBBEnd)
1411 MachineLoopInfo& MLI = getAnalysis<MachineLoopInfo>();
1412 if (MLI.getLoopFor(DefMBB) != MLI.getLoopFor(BarrierMBB))
1415 MachineDominatorTree& MDT = getAnalysis<MachineDominatorTree>();
1416 SmallPtrSet<MachineBasicBlock*, 4> Visited;
1417 typedef std::pair<MachineBasicBlock*,
1418 MachineBasicBlock::succ_iterator> ItPair;
1419 SmallVector<ItPair, 4> Stack;
1420 Stack.push_back(std::make_pair(BarrierMBB, BarrierMBB->succ_begin()));
1422 while (!Stack.empty()) {
1423 ItPair P = Stack.back();
1426 MachineBasicBlock* PredMBB = P.first;
1427 MachineBasicBlock::succ_iterator S = P.second;
1429 if (S == PredMBB->succ_end())
1431 else if (Visited.count(*S)) {
1432 Stack.push_back(std::make_pair(PredMBB, ++S));
1435 Stack.push_back(std::make_pair(PredMBB, S+1));
1437 MachineBasicBlock* MBB = *S;
1438 Visited.insert(MBB);
1440 if (MBB == BarrierMBB)
1443 MachineDomTreeNode* DefMDTN = MDT.getNode(DefMBB);
1444 MachineDomTreeNode* BarrierMDTN = MDT.getNode(BarrierMBB);
1445 MachineDomTreeNode* MDTN = MDT.getNode(MBB)->getIDom();
1447 if (MDTN == DefMDTN)
1449 else if (MDTN == BarrierMDTN)
1451 MDTN = MDTN->getIDom();
1454 MBBEnd = LIs->getMBBEndIdx(MBB);
1455 if (LR->end > MBBEnd)
1456 Stack.push_back(std::make_pair(MBB, MBB->succ_begin()));
1463 bool PreAllocSplitting::runOnMachineFunction(MachineFunction &MF) {
1465 TM = &MF.getTarget();
1466 TRI = TM->getRegisterInfo();
1467 TII = TM->getInstrInfo();
1468 MFI = MF.getFrameInfo();
1469 MRI = &MF.getRegInfo();
1470 LIs = &getAnalysis<LiveIntervals>();
1471 LSs = &getAnalysis<LiveStacks>();
1472 VRM = &getAnalysis<VirtRegMap>();
1474 bool MadeChange = false;
1476 // Make sure blocks are numbered in order.
1477 MF.RenumberBlocks();
1479 MachineBasicBlock *Entry = MF.begin();
1480 SmallPtrSet<MachineBasicBlock*,16> Visited;
1482 SmallPtrSet<LiveInterval*, 8> Split;
1484 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
1485 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
1488 for (MachineBasicBlock::iterator I = BarrierMBB->begin(),
1489 E = BarrierMBB->end(); I != E; ++I) {
1491 const TargetRegisterClass **BarrierRCs =
1492 Barrier->getDesc().getRegClassBarriers();
1495 BarrierIdx = LIs->getInstructionIndex(Barrier);
1496 MadeChange |= SplitRegLiveIntervals(BarrierRCs, Split);
1500 MadeChange |= removeDeadSpills(Split);