1 //===----- SchedulePostRAList.cpp - list scheduler ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a top-down list scheduler, using standard algorithms.
11 // The basic approach uses a priority queue of available nodes to schedule.
12 // One at a time, nodes are taken from the priority queue (thus in priority
13 // order), checked for legality to schedule, and emitted if legal.
15 // Nodes may not be legal to schedule either due to structural hazards (e.g.
16 // pipeline or resource constraints) or because an input to the instruction has
17 // not completed execution.
19 //===----------------------------------------------------------------------===//
21 #define DEBUG_TYPE "post-RA-sched"
22 #include "AntiDepBreaker.h"
23 #include "AggressiveAntiDepBreaker.h"
24 #include "CriticalAntiDepBreaker.h"
25 #include "RegisterClassInfo.h"
26 #include "ScheduleDAGInstrs.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/CodeGen/LatencyPriorityQueue.h"
29 #include "llvm/CodeGen/SchedulerRegistry.h"
30 #include "llvm/CodeGen/MachineDominators.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineLoopInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
36 #include "llvm/Analysis/AliasAnalysis.h"
37 #include "llvm/Target/TargetLowering.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetSubtargetInfo.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/raw_ostream.h"
46 #include "llvm/ADT/BitVector.h"
47 #include "llvm/ADT/Statistic.h"
50 STATISTIC(NumNoops, "Number of noops inserted");
51 STATISTIC(NumStalls, "Number of pipeline stalls");
52 STATISTIC(NumFixedAnti, "Number of fixed anti-dependencies");
54 // Post-RA scheduling is enabled with
55 // TargetSubtargetInfo.enablePostRAScheduler(). This flag can be used to
56 // override the target.
58 EnablePostRAScheduler("post-RA-scheduler",
59 cl::desc("Enable scheduling after register allocation"),
60 cl::init(false), cl::Hidden);
61 static cl::opt<std::string>
62 EnableAntiDepBreaking("break-anti-dependencies",
63 cl::desc("Break post-RA scheduling anti-dependencies: "
64 "\"critical\", \"all\", or \"none\""),
65 cl::init("none"), cl::Hidden);
67 // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
69 DebugDiv("postra-sched-debugdiv",
70 cl::desc("Debug control MBBs that are scheduled"),
71 cl::init(0), cl::Hidden);
73 DebugMod("postra-sched-debugmod",
74 cl::desc("Debug control MBBs that are scheduled"),
75 cl::init(0), cl::Hidden);
77 AntiDepBreaker::~AntiDepBreaker() { }
80 class PostRAScheduler : public MachineFunctionPass {
82 const TargetInstrInfo *TII;
83 RegisterClassInfo RegClassInfo;
87 PostRAScheduler() : MachineFunctionPass(ID) {}
89 void getAnalysisUsage(AnalysisUsage &AU) const {
91 AU.addRequired<AliasAnalysis>();
92 AU.addRequired<TargetPassConfig>();
93 AU.addRequired<MachineDominatorTree>();
94 AU.addPreserved<MachineDominatorTree>();
95 AU.addRequired<MachineLoopInfo>();
96 AU.addPreserved<MachineLoopInfo>();
97 MachineFunctionPass::getAnalysisUsage(AU);
100 bool runOnMachineFunction(MachineFunction &Fn);
102 char PostRAScheduler::ID = 0;
104 class SchedulePostRATDList : public ScheduleDAGInstrs {
105 /// AvailableQueue - The priority queue to use for the available SUnits.
107 LatencyPriorityQueue AvailableQueue;
109 /// PendingQueue - This contains all of the instructions whose operands have
110 /// been issued, but their results are not ready yet (due to the latency of
111 /// the operation). Once the operands becomes available, the instruction is
112 /// added to the AvailableQueue.
113 std::vector<SUnit*> PendingQueue;
115 /// Topo - A topological ordering for SUnits.
116 ScheduleDAGTopologicalSort Topo;
118 /// HazardRec - The hazard recognizer to use.
119 ScheduleHazardRecognizer *HazardRec;
121 /// AntiDepBreak - Anti-dependence breaking object, or NULL if none
122 AntiDepBreaker *AntiDepBreak;
124 /// AA - AliasAnalysis for making memory reference queries.
127 /// KillIndices - The index of the most recent kill (proceding bottom-up),
128 /// or ~0u if the register is not live.
129 std::vector<unsigned> KillIndices;
132 SchedulePostRATDList(
133 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
134 AliasAnalysis *AA, const RegisterClassInfo&,
135 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
136 SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs);
138 ~SchedulePostRATDList();
140 /// StartBlock - Initialize register live-range state for scheduling in
143 void StartBlock(MachineBasicBlock *BB);
145 /// Schedule - Schedule the instruction range using list scheduling.
149 /// Observe - Update liveness information to account for the current
150 /// instruction, which will not be scheduled.
152 void Observe(MachineInstr *MI, unsigned Count);
154 /// FinishBlock - Clean up register live-range state.
158 /// FixupKills - Fix register kill flags that have been made
159 /// invalid due to scheduling
161 void FixupKills(MachineBasicBlock *MBB);
164 void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
165 void ReleaseSuccessors(SUnit *SU);
166 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
167 void ListScheduleTopDown();
168 void StartBlockForKills(MachineBasicBlock *BB);
170 // ToggleKillFlag - Toggle a register operand kill flag. Other
171 // adjustments may be made to the instruction if necessary. Return
172 // true if the operand has been deleted, false if not.
173 bool ToggleKillFlag(MachineInstr *MI, MachineOperand &MO);
177 char &llvm::PostRASchedulerID = PostRAScheduler::ID;
179 INITIALIZE_PASS(PostRAScheduler, "post-RA-sched",
180 "Post RA top-down list latency scheduler", false, false)
182 SchedulePostRATDList::SchedulePostRATDList(
183 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
184 AliasAnalysis *AA, const RegisterClassInfo &RCI,
185 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
186 SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs)
187 : ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), Topo(SUnits), AA(AA),
188 KillIndices(TRI->getNumRegs())
190 const TargetMachine &TM = MF.getTarget();
191 const InstrItineraryData *InstrItins = TM.getInstrItineraryData();
193 TM.getInstrInfo()->CreateTargetPostRAHazardRecognizer(InstrItins, this);
195 ((AntiDepMode == TargetSubtargetInfo::ANTIDEP_ALL) ?
196 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) :
197 ((AntiDepMode == TargetSubtargetInfo::ANTIDEP_CRITICAL) ?
198 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : NULL));
201 SchedulePostRATDList::~SchedulePostRATDList() {
206 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
207 TII = Fn.getTarget().getInstrInfo();
208 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
209 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
210 AliasAnalysis *AA = &getAnalysis<AliasAnalysis>();
211 TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
213 RegClassInfo.runOnMachineFunction(Fn);
215 // Check for explicit enable/disable of post-ra scheduling.
216 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode =
217 TargetSubtargetInfo::ANTIDEP_NONE;
218 SmallVector<const TargetRegisterClass*, 4> CriticalPathRCs;
219 if (EnablePostRAScheduler.getPosition() > 0) {
220 if (!EnablePostRAScheduler)
223 // Check that post-RA scheduling is enabled for this target.
224 // This may upgrade the AntiDepMode.
225 const TargetSubtargetInfo &ST = Fn.getTarget().getSubtarget<TargetSubtargetInfo>();
226 if (!ST.enablePostRAScheduler(PassConfig->getOptLevel(), AntiDepMode,
231 // Check for antidep breaking override...
232 if (EnableAntiDepBreaking.getPosition() > 0) {
233 AntiDepMode = (EnableAntiDepBreaking == "all")
234 ? TargetSubtargetInfo::ANTIDEP_ALL
235 : ((EnableAntiDepBreaking == "critical")
236 ? TargetSubtargetInfo::ANTIDEP_CRITICAL
237 : TargetSubtargetInfo::ANTIDEP_NONE);
240 DEBUG(dbgs() << "PostRAScheduler\n");
242 SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode,
245 // Loop over all of the basic blocks
246 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
247 MBB != MBBe; ++MBB) {
249 // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
251 static int bbcnt = 0;
252 if (bbcnt++ % DebugDiv != DebugMod)
254 dbgs() << "*** DEBUG scheduling " << Fn.getFunction()->getName()
255 << ":BB#" << MBB->getNumber() << " ***\n";
259 // Initialize register live-range state for scheduling in this block.
260 Scheduler.StartBlock(MBB);
262 // Schedule each sequence of instructions not interrupted by a label
263 // or anything else that effectively needs to shut down scheduling.
264 MachineBasicBlock::iterator Current = MBB->end();
265 unsigned Count = MBB->size(), CurrentCount = Count;
266 for (MachineBasicBlock::iterator I = Current; I != MBB->begin(); ) {
267 MachineInstr *MI = llvm::prior(I);
268 // Calls are not scheduling boundaries before register allocation, but
269 // post-ra we don't gain anything by scheduling across calls since we
270 // don't need to worry about register pressure.
271 if (MI->isCall() || TII->isSchedulingBoundary(MI, MBB, Fn)) {
272 Scheduler.Run(MBB, I, Current, CurrentCount);
273 Scheduler.EmitSchedule();
275 CurrentCount = Count - 1;
276 Scheduler.Observe(MI, CurrentCount);
281 Count -= MI->getBundleSize();
283 assert(Count == 0 && "Instruction count mismatch!");
284 assert((MBB->begin() == Current || CurrentCount != 0) &&
285 "Instruction count mismatch!");
286 Scheduler.Run(MBB, MBB->begin(), Current, CurrentCount);
287 Scheduler.EmitSchedule();
289 // Clean up register live-range state.
290 Scheduler.FinishBlock();
292 // Update register kills
293 Scheduler.FixupKills(MBB);
299 /// StartBlock - Initialize register live-range state for scheduling in
302 void SchedulePostRATDList::StartBlock(MachineBasicBlock *BB) {
303 // Call the superclass.
304 ScheduleDAGInstrs::StartBlock(BB);
306 // Reset the hazard recognizer and anti-dep breaker.
308 if (AntiDepBreak != NULL)
309 AntiDepBreak->StartBlock(BB);
312 /// Schedule - Schedule the instruction range using list scheduling.
314 void SchedulePostRATDList::Schedule() {
315 // Build the scheduling graph.
318 if (AntiDepBreak != NULL) {
320 AntiDepBreak->BreakAntiDependencies(SUnits, Begin, InsertPos,
321 InsertPosIndex, DbgValues);
324 // We made changes. Update the dependency graph.
325 // Theoretically we could update the graph in place:
326 // When a live range is changed to use a different register, remove
327 // the def's anti-dependence *and* output-dependence edges due to
328 // that register, and add new anti-dependence and output-dependence
329 // edges based on the next live range of the register.
336 NumFixedAnti += Broken;
340 DEBUG(dbgs() << "********** List Scheduling **********\n");
341 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
342 SUnits[su].dumpAll(this));
344 AvailableQueue.initNodes(SUnits);
345 ListScheduleTopDown();
346 AvailableQueue.releaseState();
349 /// Observe - Update liveness information to account for the current
350 /// instruction, which will not be scheduled.
352 void SchedulePostRATDList::Observe(MachineInstr *MI, unsigned Count) {
353 if (AntiDepBreak != NULL)
354 AntiDepBreak->Observe(MI, Count, InsertPosIndex);
357 /// FinishBlock - Clean up register live-range state.
359 void SchedulePostRATDList::FinishBlock() {
360 if (AntiDepBreak != NULL)
361 AntiDepBreak->FinishBlock();
363 // Call the superclass.
364 ScheduleDAGInstrs::FinishBlock();
367 /// StartBlockForKills - Initialize register live-range state for updating kills
369 void SchedulePostRATDList::StartBlockForKills(MachineBasicBlock *BB) {
370 // Initialize the indices to indicate that no registers are live.
371 for (unsigned i = 0; i < TRI->getNumRegs(); ++i)
372 KillIndices[i] = ~0u;
374 // Determine the live-out physregs for this block.
375 if (!BB->empty() && BB->back().isReturn()) {
376 // In a return block, examine the function live-out regs.
377 for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
378 E = MRI.liveout_end(); I != E; ++I) {
380 KillIndices[Reg] = BB->size();
381 // Repeat, for all subregs.
382 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
384 KillIndices[*Subreg] = BB->size();
389 // In a non-return block, examine the live-in regs of all successors.
390 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
391 SE = BB->succ_end(); SI != SE; ++SI) {
392 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
393 E = (*SI)->livein_end(); I != E; ++I) {
395 KillIndices[Reg] = BB->size();
396 // Repeat, for all subregs.
397 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
399 KillIndices[*Subreg] = BB->size();
406 bool SchedulePostRATDList::ToggleKillFlag(MachineInstr *MI,
407 MachineOperand &MO) {
408 // Setting kill flag...
414 // If MO itself is live, clear the kill flag...
415 if (KillIndices[MO.getReg()] != ~0u) {
420 // If any subreg of MO is live, then create an imp-def for that
421 // subreg and keep MO marked as killed.
424 const unsigned SuperReg = MO.getReg();
425 for (const unsigned *Subreg = TRI->getSubRegisters(SuperReg);
427 if (KillIndices[*Subreg] != ~0u) {
428 MI->addOperand(MachineOperand::CreateReg(*Subreg,
442 /// FixupKills - Fix the register kill flags, they may have been made
443 /// incorrect by instruction reordering.
445 void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
446 DEBUG(dbgs() << "Fixup kills for BB#" << MBB->getNumber() << '\n');
448 BitVector killedRegs(TRI->getNumRegs());
449 BitVector ReservedRegs = TRI->getReservedRegs(MF);
451 StartBlockForKills(MBB);
453 // Examine block from end to start...
454 unsigned Count = MBB->size();
455 for (MachineBasicBlock::iterator I = MBB->end(), E = MBB->begin();
457 MachineInstr *MI = --I;
458 if (MI->isDebugValue())
461 // Update liveness. Registers that are defed but not used in this
462 // instruction are now dead. Mark register and all subregs as they
463 // are completely defined.
464 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
465 MachineOperand &MO = MI->getOperand(i);
467 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
468 if (MO.clobbersPhysReg(i))
469 KillIndices[i] = ~0u;
470 if (!MO.isReg()) continue;
471 unsigned Reg = MO.getReg();
472 if (Reg == 0) continue;
473 if (!MO.isDef()) continue;
474 // Ignore two-addr defs.
475 if (MI->isRegTiedToUseOperand(i)) continue;
477 KillIndices[Reg] = ~0u;
479 // Repeat for all subregs.
480 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
482 KillIndices[*Subreg] = ~0u;
486 // Examine all used registers and set/clear kill flag. When a
487 // register is used multiple times we only set the kill flag on
490 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
491 MachineOperand &MO = MI->getOperand(i);
492 if (!MO.isReg() || !MO.isUse()) continue;
493 unsigned Reg = MO.getReg();
494 if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
497 if (!killedRegs.test(Reg)) {
499 // A register is not killed if any subregs are live...
500 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
502 if (KillIndices[*Subreg] != ~0u) {
508 // If subreg is not live, then register is killed if it became
509 // live in this instruction
511 kill = (KillIndices[Reg] == ~0u);
514 if (MO.isKill() != kill) {
515 DEBUG(dbgs() << "Fixing " << MO << " in ");
516 // Warning: ToggleKillFlag may invalidate MO.
517 ToggleKillFlag(MI, MO);
524 // Mark any used register (that is not using undef) and subregs as
526 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
527 MachineOperand &MO = MI->getOperand(i);
528 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
529 unsigned Reg = MO.getReg();
530 if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
532 KillIndices[Reg] = Count;
534 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
536 KillIndices[*Subreg] = Count;
542 //===----------------------------------------------------------------------===//
543 // Top-Down Scheduling
544 //===----------------------------------------------------------------------===//
546 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
547 /// the PendingQueue if the count reaches zero. Also update its cycle bound.
548 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
549 SUnit *SuccSU = SuccEdge->getSUnit();
552 if (SuccSU->NumPredsLeft == 0) {
553 dbgs() << "*** Scheduling failed! ***\n";
555 dbgs() << " has been released too many times!\n";
559 --SuccSU->NumPredsLeft;
561 // Standard scheduler algorithms will recompute the depth of the successor
563 // SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency());
565 // However, we lazily compute node depth instead. Note that
566 // ScheduleNodeTopDown has already updated the depth of this node which causes
567 // all descendents to be marked dirty. Setting the successor depth explicitly
568 // here would cause depth to be recomputed for all its ancestors. If the
569 // successor is not yet ready (because of a transitively redundant edge) then
570 // this causes depth computation to be quadratic in the size of the DAG.
572 // If all the node's predecessors are scheduled, this node is ready
573 // to be scheduled. Ignore the special ExitSU node.
574 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
575 PendingQueue.push_back(SuccSU);
578 /// ReleaseSuccessors - Call ReleaseSucc on each of SU's successors.
579 void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) {
580 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
582 ReleaseSucc(SU, &*I);
586 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
587 /// count of its successors. If a successor pending count is zero, add it to
588 /// the Available queue.
589 void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
590 DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
591 DEBUG(SU->dump(this));
593 Sequence.push_back(SU);
594 assert(CurCycle >= SU->getDepth() &&
595 "Node scheduled above its depth!");
596 SU->setDepthToAtLeast(CurCycle);
598 ReleaseSuccessors(SU);
599 SU->isScheduled = true;
600 AvailableQueue.ScheduledNode(SU);
603 /// ListScheduleTopDown - The main loop of list scheduling for top-down
605 void SchedulePostRATDList::ListScheduleTopDown() {
606 unsigned CurCycle = 0;
608 // We're scheduling top-down but we're visiting the regions in
609 // bottom-up order, so we don't know the hazards at the start of a
610 // region. So assume no hazards (this should usually be ok as most
611 // blocks are a single region).
614 // Release any successors of the special Entry node.
615 ReleaseSuccessors(&EntrySU);
617 // Add all leaves to Available queue.
618 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
619 // It is available if it has no predecessors.
620 bool available = SUnits[i].Preds.empty();
622 AvailableQueue.push(&SUnits[i]);
623 SUnits[i].isAvailable = true;
627 // In any cycle where we can't schedule any instructions, we must
628 // stall or emit a noop, depending on the target.
629 bool CycleHasInsts = false;
631 // While Available queue is not empty, grab the node with the highest
632 // priority. If it is not ready put it back. Schedule the node.
633 std::vector<SUnit*> NotReady;
634 Sequence.reserve(SUnits.size());
635 while (!AvailableQueue.empty() || !PendingQueue.empty()) {
636 // Check to see if any of the pending instructions are ready to issue. If
637 // so, add them to the available queue.
638 unsigned MinDepth = ~0u;
639 for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
640 if (PendingQueue[i]->getDepth() <= CurCycle) {
641 AvailableQueue.push(PendingQueue[i]);
642 PendingQueue[i]->isAvailable = true;
643 PendingQueue[i] = PendingQueue.back();
644 PendingQueue.pop_back();
646 } else if (PendingQueue[i]->getDepth() < MinDepth)
647 MinDepth = PendingQueue[i]->getDepth();
650 DEBUG(dbgs() << "\n*** Examining Available\n"; AvailableQueue.dump(this));
652 SUnit *FoundSUnit = 0;
653 bool HasNoopHazards = false;
654 while (!AvailableQueue.empty()) {
655 SUnit *CurSUnit = AvailableQueue.pop();
657 ScheduleHazardRecognizer::HazardType HT =
658 HazardRec->getHazardType(CurSUnit, 0/*no stalls*/);
659 if (HT == ScheduleHazardRecognizer::NoHazard) {
660 FoundSUnit = CurSUnit;
664 // Remember if this is a noop hazard.
665 HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
667 NotReady.push_back(CurSUnit);
670 // Add the nodes that aren't ready back onto the available list.
671 if (!NotReady.empty()) {
672 AvailableQueue.push_all(NotReady);
676 // If we found a node to schedule...
678 // ... schedule the node...
679 ScheduleNodeTopDown(FoundSUnit, CurCycle);
680 HazardRec->EmitInstruction(FoundSUnit);
681 CycleHasInsts = true;
682 if (HazardRec->atIssueLimit()) {
683 DEBUG(dbgs() << "*** Max instructions per cycle " << CurCycle << '\n');
684 HazardRec->AdvanceCycle();
686 CycleHasInsts = false;
690 DEBUG(dbgs() << "*** Finished cycle " << CurCycle << '\n');
691 HazardRec->AdvanceCycle();
692 } else if (!HasNoopHazards) {
693 // Otherwise, we have a pipeline stall, but no other problem,
694 // just advance the current cycle and try again.
695 DEBUG(dbgs() << "*** Stall in cycle " << CurCycle << '\n');
696 HazardRec->AdvanceCycle();
699 // Otherwise, we have no instructions to issue and we have instructions
700 // that will fault if we don't do this right. This is the case for
701 // processors without pipeline interlocks and other cases.
702 DEBUG(dbgs() << "*** Emitting noop in cycle " << CurCycle << '\n');
703 HazardRec->EmitNoop();
704 Sequence.push_back(0); // NULL here means noop
709 CycleHasInsts = false;
714 VerifySchedule(/*isBottomUp=*/false);