1 //===----- SchedulePostRAList.cpp - list scheduler ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a top-down list scheduler, using standard algorithms.
11 // The basic approach uses a priority queue of available nodes to schedule.
12 // One at a time, nodes are taken from the priority queue (thus in priority
13 // order), checked for legality to schedule, and emitted if legal.
15 // Nodes may not be legal to schedule either due to structural hazards (e.g.
16 // pipeline or resource constraints) or because an input to the instruction has
17 // not completed execution.
19 //===----------------------------------------------------------------------===//
21 #define DEBUG_TYPE "post-RA-sched"
22 #include "ExactHazardRecognizer.h"
23 #include "SimpleHazardRecognizer.h"
24 #include "ScheduleDAGInstrs.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/LatencyPriorityQueue.h"
27 #include "llvm/CodeGen/SchedulerRegistry.h"
28 #include "llvm/CodeGen/MachineDominators.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineLoopInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/Target/TargetLowering.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetRegisterInfo.h"
38 #include "llvm/Target/TargetSubtarget.h"
39 #include "llvm/Support/Compiler.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include "llvm/ADT/Statistic.h"
48 STATISTIC(NumNoops, "Number of noops inserted");
49 STATISTIC(NumStalls, "Number of pipeline stalls");
51 // Post-RA scheduling is enabled with
52 // TargetSubtarget.enablePostRAScheduler(). This flag can be used to
53 // override the target.
55 EnablePostRAScheduler("post-RA-scheduler",
56 cl::desc("Enable scheduling after register allocation"),
57 cl::init(false), cl::Hidden);
59 EnableAntiDepBreaking("break-anti-dependencies",
60 cl::desc("Break post-RA scheduling anti-dependencies"),
61 cl::init(true), cl::Hidden);
63 EnablePostRAHazardAvoidance("avoid-hazards",
64 cl::desc("Enable exact hazard avoidance"),
65 cl::init(true), cl::Hidden);
67 // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
69 DebugDiv("postra-sched-debugdiv",
70 cl::desc("Debug control MBBs that are scheduled"),
71 cl::init(0), cl::Hidden);
73 DebugMod("postra-sched-debugmod",
74 cl::desc("Debug control MBBs that are scheduled"),
75 cl::init(0), cl::Hidden);
78 class VISIBILITY_HIDDEN PostRAScheduler : public MachineFunctionPass {
81 PostRAScheduler() : MachineFunctionPass(&ID) {}
83 void getAnalysisUsage(AnalysisUsage &AU) const {
85 AU.addRequired<MachineDominatorTree>();
86 AU.addPreserved<MachineDominatorTree>();
87 AU.addRequired<MachineLoopInfo>();
88 AU.addPreserved<MachineLoopInfo>();
89 MachineFunctionPass::getAnalysisUsage(AU);
92 const char *getPassName() const {
93 return "Post RA top-down list latency scheduler";
96 bool runOnMachineFunction(MachineFunction &Fn);
98 char PostRAScheduler::ID = 0;
100 class VISIBILITY_HIDDEN SchedulePostRATDList : public ScheduleDAGInstrs {
101 /// AvailableQueue - The priority queue to use for the available SUnits.
103 LatencyPriorityQueue AvailableQueue;
105 /// PendingQueue - This contains all of the instructions whose operands have
106 /// been issued, but their results are not ready yet (due to the latency of
107 /// the operation). Once the operands becomes available, the instruction is
108 /// added to the AvailableQueue.
109 std::vector<SUnit*> PendingQueue;
111 /// Topo - A topological ordering for SUnits.
112 ScheduleDAGTopologicalSort Topo;
114 /// AllocatableSet - The set of allocatable registers.
115 /// We'll be ignoring anti-dependencies on non-allocatable registers,
116 /// because they may not be safe to break.
117 const BitVector AllocatableSet;
119 /// HazardRec - The hazard recognizer to use.
120 ScheduleHazardRecognizer *HazardRec;
122 /// Classes - For live regs that are only used in one register class in a
123 /// live range, the register class. If the register is not live, the
124 /// corresponding value is null. If the register is live but used in
125 /// multiple register classes, the corresponding value is -1 casted to a
127 const TargetRegisterClass *
128 Classes[TargetRegisterInfo::FirstVirtualRegister];
130 /// RegRegs - Map registers to all their references within a live range.
131 std::multimap<unsigned, MachineOperand *> RegRefs;
133 /// KillIndices - The index of the most recent kill (proceding bottom-up),
134 /// or ~0u if the register is not live.
135 unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
137 /// DefIndices - The index of the most recent complete def (proceding bottom
138 /// up), or ~0u if the register is live.
139 unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister];
141 /// KeepRegs - A set of registers which are live and cannot be changed to
142 /// break anti-dependencies.
143 SmallSet<unsigned, 4> KeepRegs;
146 SchedulePostRATDList(MachineFunction &MF,
147 const MachineLoopInfo &MLI,
148 const MachineDominatorTree &MDT,
149 ScheduleHazardRecognizer *HR)
150 : ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits),
151 AllocatableSet(TRI->getAllocatableSet(MF)),
154 ~SchedulePostRATDList() {
158 /// StartBlock - Initialize register live-range state for scheduling in
161 void StartBlock(MachineBasicBlock *BB);
163 /// Schedule - Schedule the instruction range using list scheduling.
167 /// FixupKills - Fix register kill flags that have been made
168 /// invalid due to scheduling
170 void FixupKills(MachineBasicBlock *MBB);
172 /// Observe - Update liveness information to account for the current
173 /// instruction, which will not be scheduled.
175 void Observe(MachineInstr *MI, unsigned Count);
177 /// FinishBlock - Clean up register live-range state.
182 void PrescanInstruction(MachineInstr *MI);
183 void ScanInstruction(MachineInstr *MI, unsigned Count);
184 void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
185 void ReleaseSuccessors(SUnit *SU);
186 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
187 void ListScheduleTopDown();
188 bool BreakAntiDependencies();
189 unsigned findSuitableFreeRegister(unsigned AntiDepReg,
191 const TargetRegisterClass *);
192 void StartBlockForKills(MachineBasicBlock *BB);
194 // ToggleKillFlag - Toggle a register operand kill flag. Other
195 // adjustments may be made to the instruction if necessary. Return
196 // true if the operand has been deleted, false if not.
197 bool ToggleKillFlag(MachineInstr *MI, MachineOperand &MO);
201 /// isSchedulingBoundary - Test if the given instruction should be
202 /// considered a scheduling boundary. This primarily includes labels
205 static bool isSchedulingBoundary(const MachineInstr *MI,
206 const MachineFunction &MF) {
207 // Terminators and labels can't be scheduled around.
208 if (MI->getDesc().isTerminator() || MI->isLabel())
211 // Don't attempt to schedule around any instruction that modifies
212 // a stack-oriented pointer, as it's unlikely to be profitable. This
213 // saves compile time, because it doesn't require every single
214 // stack slot reference to depend on the instruction that does the
216 const TargetLowering &TLI = *MF.getTarget().getTargetLowering();
217 if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore()))
223 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
224 // Check for explicit enable/disable of post-ra scheduling.
225 if (EnablePostRAScheduler.getPosition() > 0) {
226 if (!EnablePostRAScheduler)
229 // Check that post-RA scheduling is enabled for this function
230 const TargetSubtarget &ST = Fn.getTarget().getSubtarget<TargetSubtarget>();
231 if (!ST.enablePostRAScheduler())
235 DEBUG(errs() << "PostRAScheduler\n");
237 const MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
238 const MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
239 const InstrItineraryData &InstrItins = Fn.getTarget().getInstrItineraryData();
240 ScheduleHazardRecognizer *HR = EnablePostRAHazardAvoidance ?
241 (ScheduleHazardRecognizer *)new ExactHazardRecognizer(InstrItins) :
242 (ScheduleHazardRecognizer *)new SimpleHazardRecognizer();
244 SchedulePostRATDList Scheduler(Fn, MLI, MDT, HR);
246 // Loop over all of the basic blocks
247 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
248 MBB != MBBe; ++MBB) {
250 // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
252 static int bbcnt = 0;
253 if (bbcnt++ % DebugDiv != DebugMod)
255 errs() << "*** DEBUG scheduling " << Fn.getFunction()->getNameStr() <<
256 ":MBB ID#" << MBB->getNumber() << " ***\n";
260 // Initialize register live-range state for scheduling in this block.
261 Scheduler.StartBlock(MBB);
263 // Schedule each sequence of instructions not interrupted by a label
264 // or anything else that effectively needs to shut down scheduling.
265 MachineBasicBlock::iterator Current = MBB->end();
266 unsigned Count = MBB->size(), CurrentCount = Count;
267 for (MachineBasicBlock::iterator I = Current; I != MBB->begin(); ) {
268 MachineInstr *MI = prior(I);
269 if (isSchedulingBoundary(MI, Fn)) {
270 Scheduler.Run(MBB, I, Current, CurrentCount);
271 Scheduler.EmitSchedule(0);
273 CurrentCount = Count - 1;
274 Scheduler.Observe(MI, CurrentCount);
279 assert(Count == 0 && "Instruction count mismatch!");
280 assert((MBB->begin() == Current || CurrentCount != 0) &&
281 "Instruction count mismatch!");
282 Scheduler.Run(MBB, MBB->begin(), Current, CurrentCount);
283 Scheduler.EmitSchedule(0);
285 // Clean up register live-range state.
286 Scheduler.FinishBlock();
288 // Update register kills
289 Scheduler.FixupKills(MBB);
295 /// StartBlock - Initialize register live-range state for scheduling in
298 void SchedulePostRATDList::StartBlock(MachineBasicBlock *BB) {
299 // Call the superclass.
300 ScheduleDAGInstrs::StartBlock(BB);
302 // Reset the hazard recognizer.
305 // Clear out the register class data.
306 std::fill(Classes, array_endof(Classes),
307 static_cast<const TargetRegisterClass *>(0));
309 // Initialize the indices to indicate that no registers are live.
310 std::fill(KillIndices, array_endof(KillIndices), ~0u);
311 std::fill(DefIndices, array_endof(DefIndices), BB->size());
313 // Clear "do not change" set.
316 bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn());
318 // Determine the live-out physregs for this block.
320 // In a return block, examine the function live-out regs.
321 for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
322 E = MRI.liveout_end(); I != E; ++I) {
324 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
325 KillIndices[Reg] = BB->size();
326 DefIndices[Reg] = ~0u;
327 // Repeat, for all aliases.
328 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
329 unsigned AliasReg = *Alias;
330 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
331 KillIndices[AliasReg] = BB->size();
332 DefIndices[AliasReg] = ~0u;
336 // In a non-return block, examine the live-in regs of all successors.
337 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
338 SE = BB->succ_end(); SI != SE; ++SI)
339 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
340 E = (*SI)->livein_end(); I != E; ++I) {
342 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
343 KillIndices[Reg] = BB->size();
344 DefIndices[Reg] = ~0u;
345 // Repeat, for all aliases.
346 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
347 unsigned AliasReg = *Alias;
348 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
349 KillIndices[AliasReg] = BB->size();
350 DefIndices[AliasReg] = ~0u;
355 // Mark live-out callee-saved registers. In a return block this is
356 // all callee-saved registers. In non-return this is any
357 // callee-saved register that is not saved in the prolog.
358 const MachineFrameInfo *MFI = MF.getFrameInfo();
359 BitVector Pristine = MFI->getPristineRegs(BB);
360 for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
362 if (!IsReturnBlock && !Pristine.test(Reg)) continue;
363 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
364 KillIndices[Reg] = BB->size();
365 DefIndices[Reg] = ~0u;
366 // Repeat, for all aliases.
367 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
368 unsigned AliasReg = *Alias;
369 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
370 KillIndices[AliasReg] = BB->size();
371 DefIndices[AliasReg] = ~0u;
376 /// Schedule - Schedule the instruction range using list scheduling.
378 void SchedulePostRATDList::Schedule() {
379 DEBUG(errs() << "********** List Scheduling **********\n");
381 // Build the scheduling graph.
384 if (EnableAntiDepBreaking) {
385 if (BreakAntiDependencies()) {
386 // We made changes. Update the dependency graph.
387 // Theoretically we could update the graph in place:
388 // When a live range is changed to use a different register, remove
389 // the def's anti-dependence *and* output-dependence edges due to
390 // that register, and add new anti-dependence and output-dependence
391 // edges based on the next live range of the register.
399 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
400 SUnits[su].dumpAll(this));
402 AvailableQueue.initNodes(SUnits);
404 ListScheduleTopDown();
406 AvailableQueue.releaseState();
409 /// Observe - Update liveness information to account for the current
410 /// instruction, which will not be scheduled.
412 void SchedulePostRATDList::Observe(MachineInstr *MI, unsigned Count) {
413 assert(Count < InsertPosIndex && "Instruction index out of expected range!");
415 // Any register which was defined within the previous scheduling region
416 // may have been rescheduled and its lifetime may overlap with registers
417 // in ways not reflected in our current liveness state. For each such
418 // register, adjust the liveness state to be conservatively correct.
419 for (unsigned Reg = 0; Reg != TargetRegisterInfo::FirstVirtualRegister; ++Reg)
420 if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
421 assert(KillIndices[Reg] == ~0u && "Clobbered register is live!");
422 // Mark this register to be non-renamable.
423 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
424 // Move the def index to the end of the previous region, to reflect
425 // that the def could theoretically have been scheduled at the end.
426 DefIndices[Reg] = InsertPosIndex;
429 PrescanInstruction(MI);
430 ScanInstruction(MI, Count);
433 /// FinishBlock - Clean up register live-range state.
435 void SchedulePostRATDList::FinishBlock() {
438 // Call the superclass.
439 ScheduleDAGInstrs::FinishBlock();
442 /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
444 static SDep *CriticalPathStep(SUnit *SU) {
446 unsigned NextDepth = 0;
447 // Find the predecessor edge with the greatest depth.
448 for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
450 SUnit *PredSU = P->getSUnit();
451 unsigned PredLatency = P->getLatency();
452 unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
453 // In the case of a latency tie, prefer an anti-dependency edge over
454 // other types of edges.
455 if (NextDepth < PredTotalLatency ||
456 (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
457 NextDepth = PredTotalLatency;
464 void SchedulePostRATDList::PrescanInstruction(MachineInstr *MI) {
465 // Scan the register operands for this instruction and update
466 // Classes and RegRefs.
467 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
468 MachineOperand &MO = MI->getOperand(i);
469 if (!MO.isReg()) continue;
470 unsigned Reg = MO.getReg();
471 if (Reg == 0) continue;
472 const TargetRegisterClass *NewRC = 0;
474 if (i < MI->getDesc().getNumOperands())
475 NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI);
477 // For now, only allow the register to be changed if its register
478 // class is consistent across all uses.
479 if (!Classes[Reg] && NewRC)
480 Classes[Reg] = NewRC;
481 else if (!NewRC || Classes[Reg] != NewRC)
482 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
484 // Now check for aliases.
485 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
486 // If an alias of the reg is used during the live range, give up.
487 // Note that this allows us to skip checking if AntiDepReg
488 // overlaps with any of the aliases, among other things.
489 unsigned AliasReg = *Alias;
490 if (Classes[AliasReg]) {
491 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
492 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
496 // If we're still willing to consider this register, note the reference.
497 if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
498 RegRefs.insert(std::make_pair(Reg, &MO));
500 // It's not safe to change register allocation for source operands of
501 // that have special allocation requirements.
502 if (MO.isUse() && MI->getDesc().hasExtraSrcRegAllocReq()) {
503 if (KeepRegs.insert(Reg)) {
504 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
506 KeepRegs.insert(*Subreg);
512 void SchedulePostRATDList::ScanInstruction(MachineInstr *MI,
515 // Proceding upwards, registers that are defed but not used in this
516 // instruction are now dead.
517 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
518 MachineOperand &MO = MI->getOperand(i);
519 if (!MO.isReg()) continue;
520 unsigned Reg = MO.getReg();
521 if (Reg == 0) continue;
522 if (!MO.isDef()) continue;
523 // Ignore two-addr defs.
524 if (MI->isRegTiedToUseOperand(i)) continue;
526 DefIndices[Reg] = Count;
527 KillIndices[Reg] = ~0u;
528 assert(((KillIndices[Reg] == ~0u) !=
529 (DefIndices[Reg] == ~0u)) &&
530 "Kill and Def maps aren't consistent for Reg!");
534 // Repeat, for all subregs.
535 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
537 unsigned SubregReg = *Subreg;
538 DefIndices[SubregReg] = Count;
539 KillIndices[SubregReg] = ~0u;
540 KeepRegs.erase(SubregReg);
541 Classes[SubregReg] = 0;
542 RegRefs.erase(SubregReg);
544 // Conservatively mark super-registers as unusable.
545 for (const unsigned *Super = TRI->getSuperRegisters(Reg);
547 unsigned SuperReg = *Super;
548 Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1);
551 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
552 MachineOperand &MO = MI->getOperand(i);
553 if (!MO.isReg()) continue;
554 unsigned Reg = MO.getReg();
555 if (Reg == 0) continue;
556 if (!MO.isUse()) continue;
558 const TargetRegisterClass *NewRC = 0;
559 if (i < MI->getDesc().getNumOperands())
560 NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI);
562 // For now, only allow the register to be changed if its register
563 // class is consistent across all uses.
564 if (!Classes[Reg] && NewRC)
565 Classes[Reg] = NewRC;
566 else if (!NewRC || Classes[Reg] != NewRC)
567 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
569 RegRefs.insert(std::make_pair(Reg, &MO));
571 // It wasn't previously live but now it is, this is a kill.
572 if (KillIndices[Reg] == ~0u) {
573 KillIndices[Reg] = Count;
574 DefIndices[Reg] = ~0u;
575 assert(((KillIndices[Reg] == ~0u) !=
576 (DefIndices[Reg] == ~0u)) &&
577 "Kill and Def maps aren't consistent for Reg!");
579 // Repeat, for all aliases.
580 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
581 unsigned AliasReg = *Alias;
582 if (KillIndices[AliasReg] == ~0u) {
583 KillIndices[AliasReg] = Count;
584 DefIndices[AliasReg] = ~0u;
591 SchedulePostRATDList::findSuitableFreeRegister(unsigned AntiDepReg,
593 const TargetRegisterClass *RC) {
594 for (TargetRegisterClass::iterator R = RC->allocation_order_begin(MF),
595 RE = RC->allocation_order_end(MF); R != RE; ++R) {
596 unsigned NewReg = *R;
597 // Don't replace a register with itself.
598 if (NewReg == AntiDepReg) continue;
599 // Don't replace a register with one that was recently used to repair
600 // an anti-dependence with this AntiDepReg, because that would
601 // re-introduce that anti-dependence.
602 if (NewReg == LastNewReg) continue;
603 // If NewReg is dead and NewReg's most recent def is not before
604 // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
605 assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u)) &&
606 "Kill and Def maps aren't consistent for AntiDepReg!");
607 assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u)) &&
608 "Kill and Def maps aren't consistent for NewReg!");
609 if (KillIndices[NewReg] != ~0u ||
610 Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
611 KillIndices[AntiDepReg] > DefIndices[NewReg])
616 // No registers are free and available!
620 /// BreakAntiDependencies - Identifiy anti-dependencies along the critical path
621 /// of the ScheduleDAG and break them by renaming registers.
623 bool SchedulePostRATDList::BreakAntiDependencies() {
624 // The code below assumes that there is at least one instruction,
625 // so just duck out immediately if the block is empty.
626 if (SUnits.empty()) return false;
628 // Find the node at the bottom of the critical path.
630 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
631 SUnit *SU = &SUnits[i];
632 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
636 DEBUG(errs() << "Critical path has total latency "
637 << (Max->getDepth() + Max->Latency) << "\n");
639 // Track progress along the critical path through the SUnit graph as we walk
641 SUnit *CriticalPathSU = Max;
642 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
644 // Consider this pattern:
653 // There are three anti-dependencies here, and without special care,
654 // we'd break all of them using the same register:
663 // because at each anti-dependence, B is the first register that
664 // isn't A which is free. This re-introduces anti-dependencies
665 // at all but one of the original anti-dependencies that we were
666 // trying to break. To avoid this, keep track of the most recent
667 // register that each register was replaced with, avoid
668 // using it to repair an anti-dependence on the same register.
669 // This lets us produce this:
678 // This still has an anti-dependence on B, but at least it isn't on the
679 // original critical path.
681 // TODO: If we tracked more than one register here, we could potentially
682 // fix that remaining critical edge too. This is a little more involved,
683 // because unlike the most recent register, less recent registers should
684 // still be considered, though only if no other registers are available.
685 unsigned LastNewReg[TargetRegisterInfo::FirstVirtualRegister] = {};
687 // Attempt to break anti-dependence edges on the critical path. Walk the
688 // instructions from the bottom up, tracking information about liveness
689 // as we go to help determine which registers are available.
690 bool Changed = false;
691 unsigned Count = InsertPosIndex - 1;
692 for (MachineBasicBlock::iterator I = InsertPos, E = Begin;
694 MachineInstr *MI = --I;
696 // Check if this instruction has a dependence on the critical path that
697 // is an anti-dependence that we may be able to break. If it is, set
698 // AntiDepReg to the non-zero register associated with the anti-dependence.
700 // We limit our attention to the critical path as a heuristic to avoid
701 // breaking anti-dependence edges that aren't going to significantly
702 // impact the overall schedule. There are a limited number of registers
703 // and we want to save them for the important edges.
705 // TODO: Instructions with multiple defs could have multiple
706 // anti-dependencies. The current code here only knows how to break one
707 // edge per instruction. Note that we'd have to be able to break all of
708 // the anti-dependencies in an instruction in order to be effective.
709 unsigned AntiDepReg = 0;
710 if (MI == CriticalPathMI) {
711 if (SDep *Edge = CriticalPathStep(CriticalPathSU)) {
712 SUnit *NextSU = Edge->getSUnit();
714 // Only consider anti-dependence edges.
715 if (Edge->getKind() == SDep::Anti) {
716 AntiDepReg = Edge->getReg();
717 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
718 if (!AllocatableSet.test(AntiDepReg))
719 // Don't break anti-dependencies on non-allocatable registers.
721 else if (KeepRegs.count(AntiDepReg))
722 // Don't break anti-dependencies if an use down below requires
723 // this exact register.
726 // If the SUnit has other dependencies on the SUnit that it
727 // anti-depends on, don't bother breaking the anti-dependency
728 // since those edges would prevent such units from being
729 // scheduled past each other regardless.
731 // Also, if there are dependencies on other SUnits with the
732 // same register as the anti-dependency, don't attempt to
734 for (SUnit::pred_iterator P = CriticalPathSU->Preds.begin(),
735 PE = CriticalPathSU->Preds.end(); P != PE; ++P)
736 if (P->getSUnit() == NextSU ?
737 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
738 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
744 CriticalPathSU = NextSU;
745 CriticalPathMI = CriticalPathSU->getInstr();
747 // We've reached the end of the critical path.
753 PrescanInstruction(MI);
755 if (MI->getDesc().hasExtraDefRegAllocReq())
756 // If this instruction's defs have special allocation requirement, don't
757 // break this anti-dependency.
759 else if (AntiDepReg) {
760 // If this instruction has a use of AntiDepReg, breaking it
762 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
763 MachineOperand &MO = MI->getOperand(i);
764 if (!MO.isReg()) continue;
765 unsigned Reg = MO.getReg();
766 if (Reg == 0) continue;
767 if (MO.isUse() && AntiDepReg == Reg) {
774 // Determine AntiDepReg's register class, if it is live and is
775 // consistently used within a single class.
776 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0;
777 assert((AntiDepReg == 0 || RC != NULL) &&
778 "Register should be live if it's causing an anti-dependence!");
779 if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
782 // Look for a suitable register to use to break the anti-depenence.
784 // TODO: Instead of picking the first free register, consider which might
786 if (AntiDepReg != 0) {
787 if (unsigned NewReg = findSuitableFreeRegister(AntiDepReg,
788 LastNewReg[AntiDepReg],
790 DEBUG(errs() << "Breaking anti-dependence edge on "
791 << TRI->getName(AntiDepReg)
792 << " with " << RegRefs.count(AntiDepReg) << " references"
793 << " using " << TRI->getName(NewReg) << "!\n");
795 // Update the references to the old register to refer to the new
797 std::pair<std::multimap<unsigned, MachineOperand *>::iterator,
798 std::multimap<unsigned, MachineOperand *>::iterator>
799 Range = RegRefs.equal_range(AntiDepReg);
800 for (std::multimap<unsigned, MachineOperand *>::iterator
801 Q = Range.first, QE = Range.second; Q != QE; ++Q)
802 Q->second->setReg(NewReg);
804 // We just went back in time and modified history; the
805 // liveness information for the anti-depenence reg is now
806 // inconsistent. Set the state as if it were dead.
807 Classes[NewReg] = Classes[AntiDepReg];
808 DefIndices[NewReg] = DefIndices[AntiDepReg];
809 KillIndices[NewReg] = KillIndices[AntiDepReg];
810 assert(((KillIndices[NewReg] == ~0u) !=
811 (DefIndices[NewReg] == ~0u)) &&
812 "Kill and Def maps aren't consistent for NewReg!");
814 Classes[AntiDepReg] = 0;
815 DefIndices[AntiDepReg] = KillIndices[AntiDepReg];
816 KillIndices[AntiDepReg] = ~0u;
817 assert(((KillIndices[AntiDepReg] == ~0u) !=
818 (DefIndices[AntiDepReg] == ~0u)) &&
819 "Kill and Def maps aren't consistent for AntiDepReg!");
821 RegRefs.erase(AntiDepReg);
823 LastNewReg[AntiDepReg] = NewReg;
827 ScanInstruction(MI, Count);
833 /// StartBlockForKills - Initialize register live-range state for updating kills
835 void SchedulePostRATDList::StartBlockForKills(MachineBasicBlock *BB) {
836 // Initialize the indices to indicate that no registers are live.
837 std::fill(KillIndices, array_endof(KillIndices), ~0u);
839 // Determine the live-out physregs for this block.
840 if (!BB->empty() && BB->back().getDesc().isReturn()) {
841 // In a return block, examine the function live-out regs.
842 for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
843 E = MRI.liveout_end(); I != E; ++I) {
845 KillIndices[Reg] = BB->size();
846 // Repeat, for all subregs.
847 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
849 KillIndices[*Subreg] = BB->size();
854 // In a non-return block, examine the live-in regs of all successors.
855 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
856 SE = BB->succ_end(); SI != SE; ++SI) {
857 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
858 E = (*SI)->livein_end(); I != E; ++I) {
860 KillIndices[Reg] = BB->size();
861 // Repeat, for all subregs.
862 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
864 KillIndices[*Subreg] = BB->size();
871 bool SchedulePostRATDList::ToggleKillFlag(MachineInstr *MI,
872 MachineOperand &MO) {
873 // Setting kill flag...
879 // If MO itself is live, clear the kill flag...
880 if (KillIndices[MO.getReg()] != ~0u) {
885 // If any subreg of MO is live, then create an imp-def for that
886 // subreg and keep MO marked as killed.
888 const unsigned SuperReg = MO.getReg();
889 for (const unsigned *Subreg = TRI->getSubRegisters(SuperReg);
891 if (KillIndices[*Subreg] != ~0u) {
892 MI->addOperand(MachineOperand::CreateReg(*Subreg,
901 MO.setIsKill(AllDead);
905 /// FixupKills - Fix the register kill flags, they may have been made
906 /// incorrect by instruction reordering.
908 void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
909 DEBUG(errs() << "Fixup kills for BB ID#" << MBB->getNumber() << '\n');
911 std::set<unsigned> killedRegs;
912 BitVector ReservedRegs = TRI->getReservedRegs(MF);
914 StartBlockForKills(MBB);
916 // Examine block from end to start...
917 unsigned Count = MBB->size();
918 for (MachineBasicBlock::iterator I = MBB->end(), E = MBB->begin();
920 MachineInstr *MI = --I;
922 // Update liveness. Registers that are defed but not used in this
923 // instruction are now dead. Mark register and all subregs as they
924 // are completely defined.
925 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
926 MachineOperand &MO = MI->getOperand(i);
927 if (!MO.isReg()) continue;
928 unsigned Reg = MO.getReg();
929 if (Reg == 0) continue;
930 if (!MO.isDef()) continue;
931 // Ignore two-addr defs.
932 if (MI->isRegTiedToUseOperand(i)) continue;
934 KillIndices[Reg] = ~0u;
936 // Repeat for all subregs.
937 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
939 KillIndices[*Subreg] = ~0u;
943 // Examine all used registers and set/clear kill flag. When a
944 // register is used multiple times we only set the kill flag on
947 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
948 MachineOperand &MO = MI->getOperand(i);
949 if (!MO.isReg() || !MO.isUse()) continue;
950 unsigned Reg = MO.getReg();
951 if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
954 if (killedRegs.find(Reg) == killedRegs.end()) {
956 // A register is not killed if any subregs are live...
957 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
959 if (KillIndices[*Subreg] != ~0u) {
965 // If subreg is not live, then register is killed if it became
966 // live in this instruction
968 kill = (KillIndices[Reg] == ~0u);
971 if (MO.isKill() != kill) {
972 bool removed = ToggleKillFlag(MI, MO);
974 DEBUG(errs() << "Fixed <removed> in ");
976 DEBUG(errs() << "Fixed " << MO << " in ");
981 killedRegs.insert(Reg);
984 // Mark any used register (that is not using undef) and subregs as
986 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
987 MachineOperand &MO = MI->getOperand(i);
988 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
989 unsigned Reg = MO.getReg();
990 if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
992 KillIndices[Reg] = Count;
994 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
996 KillIndices[*Subreg] = Count;
1002 //===----------------------------------------------------------------------===//
1003 // Top-Down Scheduling
1004 //===----------------------------------------------------------------------===//
1006 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
1007 /// the PendingQueue if the count reaches zero. Also update its cycle bound.
1008 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
1009 SUnit *SuccSU = SuccEdge->getSUnit();
1012 if (SuccSU->NumPredsLeft == 0) {
1013 errs() << "*** Scheduling failed! ***\n";
1015 errs() << " has been released too many times!\n";
1016 llvm_unreachable(0);
1019 --SuccSU->NumPredsLeft;
1021 // Compute how many cycles it will be before this actually becomes
1022 // available. This is the max of the start time of all predecessors plus
1024 SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency());
1026 // If all the node's predecessors are scheduled, this node is ready
1027 // to be scheduled. Ignore the special ExitSU node.
1028 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
1029 PendingQueue.push_back(SuccSU);
1032 /// ReleaseSuccessors - Call ReleaseSucc on each of SU's successors.
1033 void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) {
1034 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1036 ReleaseSucc(SU, &*I);
1039 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
1040 /// count of its successors. If a successor pending count is zero, add it to
1041 /// the Available queue.
1042 void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
1043 DEBUG(errs() << "*** Scheduling [" << CurCycle << "]: ");
1044 DEBUG(SU->dump(this));
1046 Sequence.push_back(SU);
1047 assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!");
1048 SU->setDepthToAtLeast(CurCycle);
1050 ReleaseSuccessors(SU);
1051 SU->isScheduled = true;
1052 AvailableQueue.ScheduledNode(SU);
1055 /// ListScheduleTopDown - The main loop of list scheduling for top-down
1057 void SchedulePostRATDList::ListScheduleTopDown() {
1058 unsigned CurCycle = 0;
1060 // Release any successors of the special Entry node.
1061 ReleaseSuccessors(&EntrySU);
1063 // All leaves to Available queue.
1064 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
1065 // It is available if it has no predecessors.
1066 if (SUnits[i].Preds.empty()) {
1067 AvailableQueue.push(&SUnits[i]);
1068 SUnits[i].isAvailable = true;
1072 // In any cycle where we can't schedule any instructions, we must
1073 // stall or emit a noop, depending on the target.
1074 bool CycleHasInsts = false;
1076 // While Available queue is not empty, grab the node with the highest
1077 // priority. If it is not ready put it back. Schedule the node.
1078 std::vector<SUnit*> NotReady;
1079 Sequence.reserve(SUnits.size());
1080 while (!AvailableQueue.empty() || !PendingQueue.empty()) {
1081 // Check to see if any of the pending instructions are ready to issue. If
1082 // so, add them to the available queue.
1083 unsigned MinDepth = ~0u;
1084 for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
1085 if (PendingQueue[i]->getDepth() <= CurCycle) {
1086 AvailableQueue.push(PendingQueue[i]);
1087 PendingQueue[i]->isAvailable = true;
1088 PendingQueue[i] = PendingQueue.back();
1089 PendingQueue.pop_back();
1091 } else if (PendingQueue[i]->getDepth() < MinDepth)
1092 MinDepth = PendingQueue[i]->getDepth();
1095 DEBUG(errs() << "\n*** Examining Available\n";
1096 LatencyPriorityQueue q = AvailableQueue;
1097 while (!q.empty()) {
1098 SUnit *su = q.pop();
1099 errs() << "Height " << su->getHeight() << ": ";
1103 SUnit *FoundSUnit = 0;
1105 bool HasNoopHazards = false;
1106 while (!AvailableQueue.empty()) {
1107 SUnit *CurSUnit = AvailableQueue.pop();
1109 ScheduleHazardRecognizer::HazardType HT =
1110 HazardRec->getHazardType(CurSUnit);
1111 if (HT == ScheduleHazardRecognizer::NoHazard) {
1112 FoundSUnit = CurSUnit;
1116 // Remember if this is a noop hazard.
1117 HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
1119 NotReady.push_back(CurSUnit);
1122 // Add the nodes that aren't ready back onto the available list.
1123 if (!NotReady.empty()) {
1124 AvailableQueue.push_all(NotReady);
1128 // If we found a node to schedule, do it now.
1130 ScheduleNodeTopDown(FoundSUnit, CurCycle);
1131 HazardRec->EmitInstruction(FoundSUnit);
1132 CycleHasInsts = true;
1134 // If we are using the target-specific hazards, then don't
1135 // advance the cycle time just because we schedule a node. If
1136 // the target allows it we can schedule multiple nodes in the
1138 if (!EnablePostRAHazardAvoidance) {
1139 if (FoundSUnit->Latency) // Don't increment CurCycle for pseudo-ops!
1143 if (CycleHasInsts) {
1144 DEBUG(errs() << "*** Finished cycle " << CurCycle << '\n');
1145 HazardRec->AdvanceCycle();
1146 } else if (!HasNoopHazards) {
1147 // Otherwise, we have a pipeline stall, but no other problem,
1148 // just advance the current cycle and try again.
1149 DEBUG(errs() << "*** Stall in cycle " << CurCycle << '\n');
1150 HazardRec->AdvanceCycle();
1153 // Otherwise, we have no instructions to issue and we have instructions
1154 // that will fault if we don't do this right. This is the case for
1155 // processors without pipeline interlocks and other cases.
1156 DEBUG(errs() << "*** Emitting noop in cycle " << CurCycle << '\n');
1157 HazardRec->EmitNoop();
1158 Sequence.push_back(0); // NULL here means noop
1163 CycleHasInsts = false;
1168 VerifySchedule(/*isBottomUp=*/false);
1172 //===----------------------------------------------------------------------===//
1173 // Public Constructor Functions
1174 //===----------------------------------------------------------------------===//
1176 FunctionPass *llvm::createPostRAScheduler() {
1177 return new PostRAScheduler();