1 //===----- SchedulePostRAList.cpp - list scheduler ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a top-down list scheduler, using standard algorithms.
11 // The basic approach uses a priority queue of available nodes to schedule.
12 // One at a time, nodes are taken from the priority queue (thus in priority
13 // order), checked for legality to schedule, and emitted if legal.
15 // Nodes may not be legal to schedule either due to structural hazards (e.g.
16 // pipeline or resource constraints) or because an input to the instruction has
17 // not completed execution.
19 //===----------------------------------------------------------------------===//
21 #define DEBUG_TYPE "post-RA-sched"
22 #include "AntiDepBreaker.h"
23 #include "AggressiveAntiDepBreaker.h"
24 #include "CriticalAntiDepBreaker.h"
25 #include "RegisterClassInfo.h"
26 #include "ScheduleDAGInstrs.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/CodeGen/LatencyPriorityQueue.h"
29 #include "llvm/CodeGen/SchedulerRegistry.h"
30 #include "llvm/CodeGen/MachineDominators.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineLoopInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
36 #include "llvm/Analysis/AliasAnalysis.h"
37 #include "llvm/Target/TargetLowering.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetSubtargetInfo.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/raw_ostream.h"
46 #include "llvm/ADT/BitVector.h"
47 #include "llvm/ADT/Statistic.h"
50 STATISTIC(NumNoops, "Number of noops inserted");
51 STATISTIC(NumStalls, "Number of pipeline stalls");
52 STATISTIC(NumFixedAnti, "Number of fixed anti-dependencies");
54 // Post-RA scheduling is enabled with
55 // TargetSubtargetInfo.enablePostRAScheduler(). This flag can be used to
56 // override the target.
58 EnablePostRAScheduler("post-RA-scheduler",
59 cl::desc("Enable scheduling after register allocation"),
60 cl::init(false), cl::Hidden);
61 static cl::opt<std::string>
62 EnableAntiDepBreaking("break-anti-dependencies",
63 cl::desc("Break post-RA scheduling anti-dependencies: "
64 "\"critical\", \"all\", or \"none\""),
65 cl::init("none"), cl::Hidden);
67 // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
69 DebugDiv("postra-sched-debugdiv",
70 cl::desc("Debug control MBBs that are scheduled"),
71 cl::init(0), cl::Hidden);
73 DebugMod("postra-sched-debugmod",
74 cl::desc("Debug control MBBs that are scheduled"),
75 cl::init(0), cl::Hidden);
77 AntiDepBreaker::~AntiDepBreaker() { }
80 class PostRAScheduler : public MachineFunctionPass {
82 const TargetInstrInfo *TII;
83 RegisterClassInfo RegClassInfo;
87 PostRAScheduler() : MachineFunctionPass(ID) {}
89 void getAnalysisUsage(AnalysisUsage &AU) const {
91 AU.addRequired<AliasAnalysis>();
92 AU.addRequired<TargetPassConfig>();
93 AU.addRequired<MachineDominatorTree>();
94 AU.addPreserved<MachineDominatorTree>();
95 AU.addRequired<MachineLoopInfo>();
96 AU.addPreserved<MachineLoopInfo>();
97 MachineFunctionPass::getAnalysisUsage(AU);
100 bool runOnMachineFunction(MachineFunction &Fn);
102 char PostRAScheduler::ID = 0;
104 class SchedulePostRATDList : public ScheduleDAGInstrs {
105 /// AvailableQueue - The priority queue to use for the available SUnits.
107 LatencyPriorityQueue AvailableQueue;
109 /// PendingQueue - This contains all of the instructions whose operands have
110 /// been issued, but their results are not ready yet (due to the latency of
111 /// the operation). Once the operands becomes available, the instruction is
112 /// added to the AvailableQueue.
113 std::vector<SUnit*> PendingQueue;
115 /// Topo - A topological ordering for SUnits.
116 ScheduleDAGTopologicalSort Topo;
118 /// HazardRec - The hazard recognizer to use.
119 ScheduleHazardRecognizer *HazardRec;
121 /// AntiDepBreak - Anti-dependence breaking object, or NULL if none
122 AntiDepBreaker *AntiDepBreak;
124 /// AA - AliasAnalysis for making memory reference queries.
127 /// LiveRegs - true if the register is live.
131 SchedulePostRATDList(
132 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
133 AliasAnalysis *AA, const RegisterClassInfo&,
134 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
135 SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs);
137 ~SchedulePostRATDList();
139 /// StartBlock - Initialize register live-range state for scheduling in
142 void StartBlock(MachineBasicBlock *BB);
144 /// Schedule - Schedule the instruction range using list scheduling.
148 /// Observe - Update liveness information to account for the current
149 /// instruction, which will not be scheduled.
151 void Observe(MachineInstr *MI, unsigned Count);
153 /// FinishBlock - Clean up register live-range state.
157 /// FixupKills - Fix register kill flags that have been made
158 /// invalid due to scheduling
160 void FixupKills(MachineBasicBlock *MBB);
163 void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
164 void ReleaseSuccessors(SUnit *SU);
165 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
166 void ListScheduleTopDown();
167 void StartBlockForKills(MachineBasicBlock *BB);
169 // ToggleKillFlag - Toggle a register operand kill flag. Other
170 // adjustments may be made to the instruction if necessary. Return
171 // true if the operand has been deleted, false if not.
172 bool ToggleKillFlag(MachineInstr *MI, MachineOperand &MO);
176 char &llvm::PostRASchedulerID = PostRAScheduler::ID;
178 INITIALIZE_PASS(PostRAScheduler, "post-RA-sched",
179 "Post RA top-down list latency scheduler", false, false)
181 SchedulePostRATDList::SchedulePostRATDList(
182 MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
183 AliasAnalysis *AA, const RegisterClassInfo &RCI,
184 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
185 SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs)
186 : ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), Topo(SUnits), AA(AA),
187 LiveRegs(TRI->getNumRegs())
189 const TargetMachine &TM = MF.getTarget();
190 const InstrItineraryData *InstrItins = TM.getInstrItineraryData();
192 TM.getInstrInfo()->CreateTargetPostRAHazardRecognizer(InstrItins, this);
194 ((AntiDepMode == TargetSubtargetInfo::ANTIDEP_ALL) ?
195 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) :
196 ((AntiDepMode == TargetSubtargetInfo::ANTIDEP_CRITICAL) ?
197 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : NULL));
200 SchedulePostRATDList::~SchedulePostRATDList() {
205 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
206 TII = Fn.getTarget().getInstrInfo();
207 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
208 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
209 AliasAnalysis *AA = &getAnalysis<AliasAnalysis>();
210 TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
212 RegClassInfo.runOnMachineFunction(Fn);
214 // Check for explicit enable/disable of post-ra scheduling.
215 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode =
216 TargetSubtargetInfo::ANTIDEP_NONE;
217 SmallVector<const TargetRegisterClass*, 4> CriticalPathRCs;
218 if (EnablePostRAScheduler.getPosition() > 0) {
219 if (!EnablePostRAScheduler)
222 // Check that post-RA scheduling is enabled for this target.
223 // This may upgrade the AntiDepMode.
224 const TargetSubtargetInfo &ST = Fn.getTarget().getSubtarget<TargetSubtargetInfo>();
225 if (!ST.enablePostRAScheduler(PassConfig->getOptLevel(), AntiDepMode,
230 // Check for antidep breaking override...
231 if (EnableAntiDepBreaking.getPosition() > 0) {
232 AntiDepMode = (EnableAntiDepBreaking == "all")
233 ? TargetSubtargetInfo::ANTIDEP_ALL
234 : ((EnableAntiDepBreaking == "critical")
235 ? TargetSubtargetInfo::ANTIDEP_CRITICAL
236 : TargetSubtargetInfo::ANTIDEP_NONE);
239 DEBUG(dbgs() << "PostRAScheduler\n");
241 SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode,
244 // Loop over all of the basic blocks
245 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
246 MBB != MBBe; ++MBB) {
248 // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
250 static int bbcnt = 0;
251 if (bbcnt++ % DebugDiv != DebugMod)
253 dbgs() << "*** DEBUG scheduling " << Fn.getFunction()->getName()
254 << ":BB#" << MBB->getNumber() << " ***\n";
258 // Initialize register live-range state for scheduling in this block.
259 Scheduler.StartBlock(MBB);
261 // Schedule each sequence of instructions not interrupted by a label
262 // or anything else that effectively needs to shut down scheduling.
263 MachineBasicBlock::iterator Current = MBB->end();
264 unsigned Count = MBB->size(), CurrentCount = Count;
265 for (MachineBasicBlock::iterator I = Current; I != MBB->begin(); ) {
266 MachineInstr *MI = llvm::prior(I);
267 // Calls are not scheduling boundaries before register allocation, but
268 // post-ra we don't gain anything by scheduling across calls since we
269 // don't need to worry about register pressure.
270 if (MI->isCall() || TII->isSchedulingBoundary(MI, MBB, Fn)) {
271 Scheduler.Run(MBB, I, Current, CurrentCount);
272 Scheduler.EmitSchedule();
274 CurrentCount = Count - 1;
275 Scheduler.Observe(MI, CurrentCount);
280 Count -= MI->getBundleSize();
282 assert(Count == 0 && "Instruction count mismatch!");
283 assert((MBB->begin() == Current || CurrentCount != 0) &&
284 "Instruction count mismatch!");
285 Scheduler.Run(MBB, MBB->begin(), Current, CurrentCount);
286 Scheduler.EmitSchedule();
288 // Clean up register live-range state.
289 Scheduler.FinishBlock();
291 // Update register kills
292 Scheduler.FixupKills(MBB);
298 /// StartBlock - Initialize register live-range state for scheduling in
301 void SchedulePostRATDList::StartBlock(MachineBasicBlock *BB) {
302 // Call the superclass.
303 ScheduleDAGInstrs::StartBlock(BB);
305 // Reset the hazard recognizer and anti-dep breaker.
307 if (AntiDepBreak != NULL)
308 AntiDepBreak->StartBlock(BB);
311 /// Schedule - Schedule the instruction range using list scheduling.
313 void SchedulePostRATDList::Schedule() {
314 // Build the scheduling graph.
317 if (AntiDepBreak != NULL) {
319 AntiDepBreak->BreakAntiDependencies(SUnits, Begin, InsertPos,
320 InsertPosIndex, DbgValues);
323 // We made changes. Update the dependency graph.
324 // Theoretically we could update the graph in place:
325 // When a live range is changed to use a different register, remove
326 // the def's anti-dependence *and* output-dependence edges due to
327 // that register, and add new anti-dependence and output-dependence
328 // edges based on the next live range of the register.
335 NumFixedAnti += Broken;
339 DEBUG(dbgs() << "********** List Scheduling **********\n");
340 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
341 SUnits[su].dumpAll(this));
343 AvailableQueue.initNodes(SUnits);
344 ListScheduleTopDown();
345 AvailableQueue.releaseState();
348 /// Observe - Update liveness information to account for the current
349 /// instruction, which will not be scheduled.
351 void SchedulePostRATDList::Observe(MachineInstr *MI, unsigned Count) {
352 if (AntiDepBreak != NULL)
353 AntiDepBreak->Observe(MI, Count, InsertPosIndex);
356 /// FinishBlock - Clean up register live-range state.
358 void SchedulePostRATDList::FinishBlock() {
359 if (AntiDepBreak != NULL)
360 AntiDepBreak->FinishBlock();
362 // Call the superclass.
363 ScheduleDAGInstrs::FinishBlock();
366 /// StartBlockForKills - Initialize register live-range state for updating kills
368 void SchedulePostRATDList::StartBlockForKills(MachineBasicBlock *BB) {
369 // Start with no live registers.
372 // Determine the live-out physregs for this block.
373 if (!BB->empty() && BB->back().isReturn()) {
374 // In a return block, examine the function live-out regs.
375 for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
376 E = MRI.liveout_end(); I != E; ++I) {
379 // Repeat, for all subregs.
380 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
382 LiveRegs.set(*Subreg);
386 // In a non-return block, examine the live-in regs of all successors.
387 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
388 SE = BB->succ_end(); SI != SE; ++SI) {
389 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
390 E = (*SI)->livein_end(); I != E; ++I) {
393 // Repeat, for all subregs.
394 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
396 LiveRegs.set(*Subreg);
402 bool SchedulePostRATDList::ToggleKillFlag(MachineInstr *MI,
403 MachineOperand &MO) {
404 // Setting kill flag...
410 // If MO itself is live, clear the kill flag...
411 if (LiveRegs.test(MO.getReg())) {
416 // If any subreg of MO is live, then create an imp-def for that
417 // subreg and keep MO marked as killed.
420 const unsigned SuperReg = MO.getReg();
421 for (const unsigned *Subreg = TRI->getSubRegisters(SuperReg);
423 if (LiveRegs.test(*Subreg)) {
424 MI->addOperand(MachineOperand::CreateReg(*Subreg,
438 /// FixupKills - Fix the register kill flags, they may have been made
439 /// incorrect by instruction reordering.
441 void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
442 DEBUG(dbgs() << "Fixup kills for BB#" << MBB->getNumber() << '\n');
444 BitVector killedRegs(TRI->getNumRegs());
445 BitVector ReservedRegs = TRI->getReservedRegs(MF);
447 StartBlockForKills(MBB);
449 // Examine block from end to start...
450 unsigned Count = MBB->size();
451 for (MachineBasicBlock::iterator I = MBB->end(), E = MBB->begin();
453 MachineInstr *MI = --I;
454 if (MI->isDebugValue())
457 // Update liveness. Registers that are defed but not used in this
458 // instruction are now dead. Mark register and all subregs as they
459 // are completely defined.
460 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
461 MachineOperand &MO = MI->getOperand(i);
463 LiveRegs.clearBitsNotInMask(MO.getRegMask());
464 if (!MO.isReg()) continue;
465 unsigned Reg = MO.getReg();
466 if (Reg == 0) continue;
467 if (!MO.isDef()) continue;
468 // Ignore two-addr defs.
469 if (MI->isRegTiedToUseOperand(i)) continue;
473 // Repeat for all subregs.
474 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
476 LiveRegs.reset(*Subreg);
479 // Examine all used registers and set/clear kill flag. When a
480 // register is used multiple times we only set the kill flag on
483 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
484 MachineOperand &MO = MI->getOperand(i);
485 if (!MO.isReg() || !MO.isUse()) continue;
486 unsigned Reg = MO.getReg();
487 if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
490 if (!killedRegs.test(Reg)) {
492 // A register is not killed if any subregs are live...
493 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
495 if (LiveRegs.test(*Subreg)) {
501 // If subreg is not live, then register is killed if it became
502 // live in this instruction
504 kill = !LiveRegs.test(Reg);
507 if (MO.isKill() != kill) {
508 DEBUG(dbgs() << "Fixing " << MO << " in ");
509 // Warning: ToggleKillFlag may invalidate MO.
510 ToggleKillFlag(MI, MO);
517 // Mark any used register (that is not using undef) and subregs as
519 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
520 MachineOperand &MO = MI->getOperand(i);
521 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
522 unsigned Reg = MO.getReg();
523 if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
527 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
529 LiveRegs.set(*Subreg);
534 //===----------------------------------------------------------------------===//
535 // Top-Down Scheduling
536 //===----------------------------------------------------------------------===//
538 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
539 /// the PendingQueue if the count reaches zero. Also update its cycle bound.
540 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
541 SUnit *SuccSU = SuccEdge->getSUnit();
544 if (SuccSU->NumPredsLeft == 0) {
545 dbgs() << "*** Scheduling failed! ***\n";
547 dbgs() << " has been released too many times!\n";
551 --SuccSU->NumPredsLeft;
553 // Standard scheduler algorithms will recompute the depth of the successor
555 // SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency());
557 // However, we lazily compute node depth instead. Note that
558 // ScheduleNodeTopDown has already updated the depth of this node which causes
559 // all descendents to be marked dirty. Setting the successor depth explicitly
560 // here would cause depth to be recomputed for all its ancestors. If the
561 // successor is not yet ready (because of a transitively redundant edge) then
562 // this causes depth computation to be quadratic in the size of the DAG.
564 // If all the node's predecessors are scheduled, this node is ready
565 // to be scheduled. Ignore the special ExitSU node.
566 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
567 PendingQueue.push_back(SuccSU);
570 /// ReleaseSuccessors - Call ReleaseSucc on each of SU's successors.
571 void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) {
572 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
574 ReleaseSucc(SU, &*I);
578 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
579 /// count of its successors. If a successor pending count is zero, add it to
580 /// the Available queue.
581 void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
582 DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
583 DEBUG(SU->dump(this));
585 Sequence.push_back(SU);
586 assert(CurCycle >= SU->getDepth() &&
587 "Node scheduled above its depth!");
588 SU->setDepthToAtLeast(CurCycle);
590 ReleaseSuccessors(SU);
591 SU->isScheduled = true;
592 AvailableQueue.ScheduledNode(SU);
595 /// ListScheduleTopDown - The main loop of list scheduling for top-down
597 void SchedulePostRATDList::ListScheduleTopDown() {
598 unsigned CurCycle = 0;
600 // We're scheduling top-down but we're visiting the regions in
601 // bottom-up order, so we don't know the hazards at the start of a
602 // region. So assume no hazards (this should usually be ok as most
603 // blocks are a single region).
606 // Release any successors of the special Entry node.
607 ReleaseSuccessors(&EntrySU);
609 // Add all leaves to Available queue.
610 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
611 // It is available if it has no predecessors.
612 bool available = SUnits[i].Preds.empty();
614 AvailableQueue.push(&SUnits[i]);
615 SUnits[i].isAvailable = true;
619 // In any cycle where we can't schedule any instructions, we must
620 // stall or emit a noop, depending on the target.
621 bool CycleHasInsts = false;
623 // While Available queue is not empty, grab the node with the highest
624 // priority. If it is not ready put it back. Schedule the node.
625 std::vector<SUnit*> NotReady;
626 Sequence.reserve(SUnits.size());
627 while (!AvailableQueue.empty() || !PendingQueue.empty()) {
628 // Check to see if any of the pending instructions are ready to issue. If
629 // so, add them to the available queue.
630 unsigned MinDepth = ~0u;
631 for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
632 if (PendingQueue[i]->getDepth() <= CurCycle) {
633 AvailableQueue.push(PendingQueue[i]);
634 PendingQueue[i]->isAvailable = true;
635 PendingQueue[i] = PendingQueue.back();
636 PendingQueue.pop_back();
638 } else if (PendingQueue[i]->getDepth() < MinDepth)
639 MinDepth = PendingQueue[i]->getDepth();
642 DEBUG(dbgs() << "\n*** Examining Available\n"; AvailableQueue.dump(this));
644 SUnit *FoundSUnit = 0;
645 bool HasNoopHazards = false;
646 while (!AvailableQueue.empty()) {
647 SUnit *CurSUnit = AvailableQueue.pop();
649 ScheduleHazardRecognizer::HazardType HT =
650 HazardRec->getHazardType(CurSUnit, 0/*no stalls*/);
651 if (HT == ScheduleHazardRecognizer::NoHazard) {
652 FoundSUnit = CurSUnit;
656 // Remember if this is a noop hazard.
657 HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
659 NotReady.push_back(CurSUnit);
662 // Add the nodes that aren't ready back onto the available list.
663 if (!NotReady.empty()) {
664 AvailableQueue.push_all(NotReady);
668 // If we found a node to schedule...
670 // ... schedule the node...
671 ScheduleNodeTopDown(FoundSUnit, CurCycle);
672 HazardRec->EmitInstruction(FoundSUnit);
673 CycleHasInsts = true;
674 if (HazardRec->atIssueLimit()) {
675 DEBUG(dbgs() << "*** Max instructions per cycle " << CurCycle << '\n');
676 HazardRec->AdvanceCycle();
678 CycleHasInsts = false;
682 DEBUG(dbgs() << "*** Finished cycle " << CurCycle << '\n');
683 HazardRec->AdvanceCycle();
684 } else if (!HasNoopHazards) {
685 // Otherwise, we have a pipeline stall, but no other problem,
686 // just advance the current cycle and try again.
687 DEBUG(dbgs() << "*** Stall in cycle " << CurCycle << '\n');
688 HazardRec->AdvanceCycle();
691 // Otherwise, we have no instructions to issue and we have instructions
692 // that will fault if we don't do this right. This is the case for
693 // processors without pipeline interlocks and other cases.
694 DEBUG(dbgs() << "*** Emitting noop in cycle " << CurCycle << '\n');
695 HazardRec->EmitNoop();
696 Sequence.push_back(0); // NULL here means noop
701 CycleHasInsts = false;
706 VerifySchedule(/*isBottomUp=*/false);