1 //===-- PeepholeOptimizer.cpp - Peephole Optimizations --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Perform peephole optimizations on the machine code:
12 // - Optimize Extensions
14 // Optimization of sign / zero extension instructions. It may be extended to
15 // handle other instructions with similar properties.
17 // On some targets, some instructions, e.g. X86 sign / zero extension, may
18 // leave the source value in the lower part of the result. This optimization
19 // will replace some uses of the pre-extension value with uses of the
20 // sub-register of the results.
22 // - Optimize Comparisons
24 // Optimization of comparison instructions. For instance, in this code:
30 // If the "sub" instruction all ready sets (or could be modified to set) the
31 // same flag that the "cmp" instruction sets and that "bz" uses, then we can
32 // eliminate the "cmp" instruction.
34 // Another instance, in this code:
36 // sub r1, r3 | sub r1, imm
37 // cmp r3, r1 or cmp r1, r3 | cmp r1, imm
40 // If the branch instruction can use flag from "sub", then we can replace
41 // "sub" with "subs" and eliminate the "cmp" instruction.
45 // Loads that can be folded into a later instruction. A load is foldable
46 // if it loads to virtual registers and the virtual register defined has
49 // - Optimize Copies and Bitcast (more generally, target specific copies):
51 // Rewrite copies and bitcasts to avoid cross register bank copies
53 // E.g., Consider the following example, where capital and lower
54 // letters denote different register file:
55 // b = copy A <-- cross-bank copy
56 // C = copy b <-- cross-bank copy
58 // b = copy A <-- cross-bank copy
59 // C = copy A <-- same-bank copy
62 // b = bitcast A <-- cross-bank copy
63 // C = bitcast b <-- cross-bank copy
65 // b = bitcast A <-- cross-bank copy
66 // C = copy A <-- same-bank copy
67 //===----------------------------------------------------------------------===//
69 #include "llvm/CodeGen/Passes.h"
70 #include "llvm/ADT/DenseMap.h"
71 #include "llvm/ADT/SmallPtrSet.h"
72 #include "llvm/ADT/SmallSet.h"
73 #include "llvm/ADT/Statistic.h"
74 #include "llvm/CodeGen/MachineDominators.h"
75 #include "llvm/CodeGen/MachineInstrBuilder.h"
76 #include "llvm/CodeGen/MachineRegisterInfo.h"
77 #include "llvm/Support/CommandLine.h"
78 #include "llvm/Support/Debug.h"
79 #include "llvm/Support/raw_ostream.h"
80 #include "llvm/Target/TargetInstrInfo.h"
81 #include "llvm/Target/TargetRegisterInfo.h"
82 #include "llvm/Target/TargetSubtargetInfo.h"
86 #define DEBUG_TYPE "peephole-opt"
88 // Optimize Extensions
90 Aggressive("aggressive-ext-opt", cl::Hidden,
91 cl::desc("Aggressive extension optimization"));
94 DisablePeephole("disable-peephole", cl::Hidden, cl::init(false),
95 cl::desc("Disable the peephole optimizer"));
98 DisableAdvCopyOpt("disable-adv-copy-opt", cl::Hidden, cl::init(false),
99 cl::desc("Disable advanced copy optimization"));
101 // Limit the number of PHI instructions to process
102 // in PeepholeOptimizer::getNextSource.
103 static cl::opt<unsigned> RewritePHILimit(
104 "rewrite-phi-limit", cl::Hidden, cl::init(10),
105 cl::desc("Limit the length of PHI chains to lookup"));
107 STATISTIC(NumReuse, "Number of extension results reused");
108 STATISTIC(NumCmps, "Number of compares eliminated");
109 STATISTIC(NumImmFold, "Number of move immediate folded");
110 STATISTIC(NumLoadFold, "Number of loads folded");
111 STATISTIC(NumSelects, "Number of selects optimized");
112 STATISTIC(NumUncoalescableCopies, "Number of uncoalescable copies optimized");
113 STATISTIC(NumRewrittenCopies, "Number of copies rewritten");
116 class ValueTrackerResult;
118 class PeepholeOptimizer : public MachineFunctionPass {
119 const TargetInstrInfo *TII;
120 const TargetRegisterInfo *TRI;
121 MachineRegisterInfo *MRI;
122 MachineDominatorTree *DT; // Machine dominator tree
125 static char ID; // Pass identification
126 PeepholeOptimizer() : MachineFunctionPass(ID) {
127 initializePeepholeOptimizerPass(*PassRegistry::getPassRegistry());
130 bool runOnMachineFunction(MachineFunction &MF) override;
132 void getAnalysisUsage(AnalysisUsage &AU) const override {
133 AU.setPreservesCFG();
134 MachineFunctionPass::getAnalysisUsage(AU);
136 AU.addRequired<MachineDominatorTree>();
137 AU.addPreserved<MachineDominatorTree>();
141 /// \brief Track Def -> Use info used for rewriting copies.
142 typedef SmallDenseMap<TargetInstrInfo::RegSubRegPair, ValueTrackerResult>
146 bool optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
147 bool optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
148 SmallPtrSetImpl<MachineInstr*> &LocalMIs);
149 bool optimizeSelect(MachineInstr *MI,
150 SmallPtrSetImpl<MachineInstr *> &LocalMIs);
151 bool optimizeCondBranch(MachineInstr *MI);
152 bool optimizeCopyOrBitcast(MachineInstr *MI);
153 bool optimizeCoalescableCopy(MachineInstr *MI);
154 bool optimizeUncoalescableCopy(MachineInstr *MI,
155 SmallPtrSetImpl<MachineInstr *> &LocalMIs);
156 bool findNextSource(unsigned Reg, unsigned SubReg,
157 RewriteMapTy &RewriteMap);
158 bool isMoveImmediate(MachineInstr *MI,
159 SmallSet<unsigned, 4> &ImmDefRegs,
160 DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
161 bool foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
162 SmallSet<unsigned, 4> &ImmDefRegs,
163 DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
164 bool isLoadFoldable(MachineInstr *MI,
165 SmallSet<unsigned, 16> &FoldAsLoadDefCandidates);
167 /// \brief Check whether \p MI is understood by the register coalescer
168 /// but may require some rewriting.
169 bool isCoalescableCopy(const MachineInstr &MI) {
170 // SubregToRegs are not interesting, because they are already register
171 // coalescer friendly.
172 return MI.isCopy() || (!DisableAdvCopyOpt &&
173 (MI.isRegSequence() || MI.isInsertSubreg() ||
174 MI.isExtractSubreg()));
177 /// \brief Check whether \p MI is a copy like instruction that is
178 /// not recognized by the register coalescer.
179 bool isUncoalescableCopy(const MachineInstr &MI) {
180 return MI.isBitcast() ||
181 (!DisableAdvCopyOpt &&
182 (MI.isRegSequenceLike() || MI.isInsertSubregLike() ||
183 MI.isExtractSubregLike()));
187 /// \brief Helper class to hold a reply for ValueTracker queries. Contains the
188 /// returned sources for a given search and the instructions where the sources
189 /// were tracked from.
190 class ValueTrackerResult {
192 /// Track all sources found by one ValueTracker query.
193 SmallVector<TargetInstrInfo::RegSubRegPair, 2> RegSrcs;
195 /// Instruction using the sources in 'RegSrcs'.
196 const MachineInstr *Inst;
199 ValueTrackerResult() : Inst(nullptr) {}
200 ValueTrackerResult(unsigned Reg, unsigned SubReg) : Inst(nullptr) {
201 addSource(Reg, SubReg);
204 bool isValid() const { return getNumSources() > 0; }
206 void setInst(const MachineInstr *I) { Inst = I; }
207 const MachineInstr *getInst() const { return Inst; }
214 void addSource(unsigned SrcReg, unsigned SrcSubReg) {
215 RegSrcs.push_back(TargetInstrInfo::RegSubRegPair(SrcReg, SrcSubReg));
218 void setSource(int Idx, unsigned SrcReg, unsigned SrcSubReg) {
219 assert(Idx < getNumSources() && "Reg pair source out of index");
220 RegSrcs[Idx] = TargetInstrInfo::RegSubRegPair(SrcReg, SrcSubReg);
223 int getNumSources() const { return RegSrcs.size(); }
225 unsigned getSrcReg(int Idx) const {
226 assert(Idx < getNumSources() && "Reg source out of index");
227 return RegSrcs[Idx].Reg;
230 unsigned getSrcSubReg(int Idx) const {
231 assert(Idx < getNumSources() && "SubReg source out of index");
232 return RegSrcs[Idx].SubReg;
235 bool operator==(const ValueTrackerResult &Other) {
236 if (Other.getInst() != getInst())
239 if (Other.getNumSources() != getNumSources())
242 for (int i = 0, e = Other.getNumSources(); i != e; ++i)
243 if (Other.getSrcReg(i) != getSrcReg(i) ||
244 Other.getSrcSubReg(i) != getSrcSubReg(i))
250 /// \brief Helper class to track the possible sources of a value defined by
251 /// a (chain of) copy related instructions.
252 /// Given a definition (instruction and definition index), this class
253 /// follows the use-def chain to find successive suitable sources.
254 /// The given source can be used to rewrite the definition into
257 /// For instance, let us consider the following snippet:
259 /// v2 = INSERT_SUBREG v1, v0, sub0
260 /// def = COPY v2.sub0
262 /// Using a ValueTracker for def = COPY v2.sub0 will give the following
263 /// suitable sources:
265 /// Then, def can be rewritten into def = COPY v0.
268 /// The current point into the use-def chain.
269 const MachineInstr *Def;
270 /// The index of the definition in Def.
272 /// The sub register index of the definition.
274 /// The register where the value can be found.
276 /// Specifiy whether or not the value tracking looks through
277 /// complex instructions. When this is false, the value tracker
278 /// bails on everything that is not a copy or a bitcast.
280 /// Note: This could have been implemented as a specialized version of
281 /// the ValueTracker class but that would have complicated the code of
282 /// the users of this class.
283 bool UseAdvancedTracking;
284 /// MachineRegisterInfo used to perform tracking.
285 const MachineRegisterInfo &MRI;
286 /// Optional TargetInstrInfo used to perform some complex
288 const TargetInstrInfo *TII;
290 /// \brief Dispatcher to the right underlying implementation of
292 ValueTrackerResult getNextSourceImpl();
293 /// \brief Specialized version of getNextSource for Copy instructions.
294 ValueTrackerResult getNextSourceFromCopy();
295 /// \brief Specialized version of getNextSource for Bitcast instructions.
296 ValueTrackerResult getNextSourceFromBitcast();
297 /// \brief Specialized version of getNextSource for RegSequence
299 ValueTrackerResult getNextSourceFromRegSequence();
300 /// \brief Specialized version of getNextSource for InsertSubreg
302 ValueTrackerResult getNextSourceFromInsertSubreg();
303 /// \brief Specialized version of getNextSource for ExtractSubreg
305 ValueTrackerResult getNextSourceFromExtractSubreg();
306 /// \brief Specialized version of getNextSource for SubregToReg
308 ValueTrackerResult getNextSourceFromSubregToReg();
309 /// \brief Specialized version of getNextSource for PHI instructions.
310 ValueTrackerResult getNextSourceFromPHI();
313 /// \brief Create a ValueTracker instance for the value defined by \p Reg.
314 /// \p DefSubReg represents the sub register index the value tracker will
315 /// track. It does not need to match the sub register index used in the
316 /// definition of \p Reg.
317 /// \p UseAdvancedTracking specifies whether or not the value tracker looks
318 /// through complex instructions. By default (false), it handles only copy
319 /// and bitcast instructions.
320 /// If \p Reg is a physical register, a value tracker constructed with
321 /// this constructor will not find any alternative source.
322 /// Indeed, when \p Reg is a physical register that constructor does not
323 /// know which definition of \p Reg it should track.
324 /// Use the next constructor to track a physical register.
325 ValueTracker(unsigned Reg, unsigned DefSubReg,
326 const MachineRegisterInfo &MRI,
327 bool UseAdvancedTracking = false,
328 const TargetInstrInfo *TII = nullptr)
329 : Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg),
330 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) {
331 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) {
332 Def = MRI.getVRegDef(Reg);
333 DefIdx = MRI.def_begin(Reg).getOperandNo();
337 /// \brief Create a ValueTracker instance for the value defined by
338 /// the pair \p MI, \p DefIdx.
339 /// Unlike the other constructor, the value tracker produced by this one
340 /// may be able to find a new source when the definition is a physical
342 /// This could be useful to rewrite target specific instructions into
343 /// generic copy instructions.
344 ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg,
345 const MachineRegisterInfo &MRI,
346 bool UseAdvancedTracking = false,
347 const TargetInstrInfo *TII = nullptr)
348 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg),
349 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) {
350 assert(DefIdx < Def->getDesc().getNumDefs() &&
351 Def->getOperand(DefIdx).isReg() && "Invalid definition");
352 Reg = Def->getOperand(DefIdx).getReg();
355 /// \brief Following the use-def chain, get the next available source
356 /// for the tracked value.
357 /// \return A ValueTrackerResult containing the a set of registers
358 /// and sub registers with tracked values. A ValueTrackerResult with
359 /// an empty set of registers means no source was found.
360 ValueTrackerResult getNextSource();
362 /// \brief Get the last register where the initial value can be found.
363 /// Initially this is the register of the definition.
364 /// Then, after each successful call to getNextSource, this is the
365 /// register of the last source.
366 unsigned getReg() const { return Reg; }
370 char PeepholeOptimizer::ID = 0;
371 char &llvm::PeepholeOptimizerID = PeepholeOptimizer::ID;
372 INITIALIZE_PASS_BEGIN(PeepholeOptimizer, "peephole-opts",
373 "Peephole Optimizations", false, false)
374 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
375 INITIALIZE_PASS_END(PeepholeOptimizer, "peephole-opts",
376 "Peephole Optimizations", false, false)
378 /// optimizeExtInstr - If instruction is a copy-like instruction, i.e. it reads
379 /// a single register and writes a single register and it does not modify the
380 /// source, and if the source value is preserved as a sub-register of the
381 /// result, then replace all reachable uses of the source with the subreg of the
384 /// Do not generate an EXTRACT that is used only in a debug use, as this changes
385 /// the code. Since this code does not currently share EXTRACTs, just ignore all
387 bool PeepholeOptimizer::
388 optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
389 SmallPtrSetImpl<MachineInstr*> &LocalMIs) {
390 unsigned SrcReg, DstReg, SubIdx;
391 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
394 if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
395 TargetRegisterInfo::isPhysicalRegister(SrcReg))
398 if (MRI->hasOneNonDBGUse(SrcReg))
402 // Ensure DstReg can get a register class that actually supports
403 // sub-registers. Don't change the class until we commit.
404 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
405 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx);
409 // The ext instr may be operating on a sub-register of SrcReg as well.
410 // PPC::EXTSW is a 32 -> 64-bit sign extension, but it reads a 64-bit
412 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of
413 // SrcReg:SubIdx should be replaced.
415 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr;
417 // The source has other uses. See if we can replace the other uses with use of
418 // the result of the extension.
419 SmallPtrSet<MachineBasicBlock*, 4> ReachedBBs;
420 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
421 ReachedBBs.insert(UI.getParent());
423 // Uses that are in the same BB of uses of the result of the instruction.
424 SmallVector<MachineOperand*, 8> Uses;
426 // Uses that the result of the instruction can reach.
427 SmallVector<MachineOperand*, 8> ExtendedUses;
429 bool ExtendLife = true;
430 for (MachineOperand &UseMO : MRI->use_nodbg_operands(SrcReg)) {
431 MachineInstr *UseMI = UseMO.getParent();
435 if (UseMI->isPHI()) {
440 // Only accept uses of SrcReg:SubIdx.
441 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
444 // It's an error to translate this:
446 // %reg1025 = <sext> %reg1024
448 // %reg1026 = SUBREG_TO_REG 0, %reg1024, 4
452 // %reg1025 = <sext> %reg1024
454 // %reg1027 = COPY %reg1025:4
455 // %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
457 // The problem here is that SUBREG_TO_REG is there to assert that an
458 // implicit zext occurs. It doesn't insert a zext instruction. If we allow
459 // the COPY here, it will give us the value after the <sext>, not the
460 // original value of %reg1024 before <sext>.
461 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
464 MachineBasicBlock *UseMBB = UseMI->getParent();
466 // Local uses that come after the extension.
467 if (!LocalMIs.count(UseMI))
468 Uses.push_back(&UseMO);
469 } else if (ReachedBBs.count(UseMBB)) {
470 // Non-local uses where the result of the extension is used. Always
471 // replace these unless it's a PHI.
472 Uses.push_back(&UseMO);
473 } else if (Aggressive && DT->dominates(MBB, UseMBB)) {
474 // We may want to extend the live range of the extension result in order
475 // to replace these uses.
476 ExtendedUses.push_back(&UseMO);
478 // Both will be live out of the def MBB anyway. Don't extend live range of
479 // the extension result.
485 if (ExtendLife && !ExtendedUses.empty())
486 // Extend the liveness of the extension result.
487 Uses.append(ExtendedUses.begin(), ExtendedUses.end());
489 // Now replace all uses.
490 bool Changed = false;
492 SmallPtrSet<MachineBasicBlock*, 4> PHIBBs;
494 // Look for PHI uses of the extended result, we don't want to extend the
495 // liveness of a PHI input. It breaks all kinds of assumptions down
496 // stream. A PHI use is expected to be the kill of its source values.
497 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
499 PHIBBs.insert(UI.getParent());
501 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
502 for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
503 MachineOperand *UseMO = Uses[i];
504 MachineInstr *UseMI = UseMO->getParent();
505 MachineBasicBlock *UseMBB = UseMI->getParent();
506 if (PHIBBs.count(UseMBB))
509 // About to add uses of DstReg, clear DstReg's kill flags.
511 MRI->clearKillFlags(DstReg);
512 MRI->constrainRegClass(DstReg, DstRC);
515 unsigned NewVR = MRI->createVirtualRegister(RC);
516 MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
517 TII->get(TargetOpcode::COPY), NewVR)
518 .addReg(DstReg, 0, SubIdx);
519 // SubIdx applies to both SrcReg and DstReg when UseSrcSubIdx is set.
521 Copy->getOperand(0).setSubReg(SubIdx);
522 Copy->getOperand(0).setIsUndef();
524 UseMO->setReg(NewVR);
533 /// optimizeCmpInstr - If the instruction is a compare and the previous
534 /// instruction it's comparing against all ready sets (or could be modified to
535 /// set) the same flag as the compare, then we can remove the comparison and use
536 /// the flag from the previous instruction.
537 bool PeepholeOptimizer::optimizeCmpInstr(MachineInstr *MI,
538 MachineBasicBlock *MBB) {
539 // If this instruction is a comparison against zero and isn't comparing a
540 // physical register, we can try to optimize it.
541 unsigned SrcReg, SrcReg2;
542 int CmpMask, CmpValue;
543 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
544 TargetRegisterInfo::isPhysicalRegister(SrcReg) ||
545 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2)))
548 // Attempt to optimize the comparison instruction.
549 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
557 /// Optimize a select instruction.
558 bool PeepholeOptimizer::optimizeSelect(MachineInstr *MI,
559 SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
561 unsigned FalseOp = 0;
562 bool Optimizable = false;
563 SmallVector<MachineOperand, 4> Cond;
564 if (TII->analyzeSelect(MI, Cond, TrueOp, FalseOp, Optimizable))
568 if (!TII->optimizeSelect(MI, LocalMIs))
570 MI->eraseFromParent();
575 /// \brief Check if a simpler conditional branch can be
577 bool PeepholeOptimizer::optimizeCondBranch(MachineInstr *MI) {
578 return TII->optimizeCondBranch(MI);
581 /// \brief Check if the registers defined by the pair (RegisterClass, SubReg)
582 /// share the same register file.
583 static bool shareSameRegisterFile(const TargetRegisterInfo &TRI,
584 const TargetRegisterClass *DefRC,
586 const TargetRegisterClass *SrcRC,
587 unsigned SrcSubReg) {
588 // Same register class.
592 // Both operands are sub registers. Check if they share a register class.
593 unsigned SrcIdx, DefIdx;
594 if (SrcSubReg && DefSubReg)
595 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
596 SrcIdx, DefIdx) != nullptr;
597 // At most one of the register is a sub register, make it Src to avoid
598 // duplicating the test.
600 std::swap(DefSubReg, SrcSubReg);
601 std::swap(DefRC, SrcRC);
604 // One of the register is a sub register, check if we can get a superclass.
606 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
608 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
611 /// \brief Try to find the next source that share the same register file
612 /// for the value defined by \p Reg and \p SubReg.
613 /// When true is returned, the \p RewriteMap can be used by the client to
614 /// retrieve all Def -> Use along the way up to the next source. Any found
615 /// Use that is not itself a key for another entry, is the next source to
616 /// use. During the search for the next source, multiple sources can be found
617 /// given multiple incoming sources of a PHI instruction. In this case, we
618 /// look in each PHI source for the next source; all found next sources must
619 /// share the same register file as \p Reg and \p SubReg. The client should
620 /// then be capable to rewrite all intermediate PHIs to get the next source.
621 /// \return False if no alternative sources are available. True otherwise.
622 bool PeepholeOptimizer::findNextSource(unsigned Reg, unsigned SubReg,
623 RewriteMapTy &RewriteMap) {
624 // Do not try to find a new source for a physical register.
625 // So far we do not have any motivating example for doing that.
626 // Thus, instead of maintaining untested code, we will revisit that if
627 // that changes at some point.
628 if (TargetRegisterInfo::isPhysicalRegister(Reg))
630 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
632 SmallVector<TargetInstrInfo::RegSubRegPair, 4> SrcToLook;
633 TargetInstrInfo::RegSubRegPair CurSrcPair(Reg, SubReg);
634 SrcToLook.push_back(CurSrcPair);
635 bool ShouldRewrite = false;
637 unsigned PHILimit = RewritePHILimit;
638 while (!SrcToLook.empty() && PHILimit) {
639 TargetInstrInfo::RegSubRegPair Pair = SrcToLook.pop_back_val();
641 ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI,
642 !DisableAdvCopyOpt, TII);
643 ValueTrackerResult Res;
646 // Follow the chain of copies until we reach the top of the use-def chain
647 // or find a more suitable source.
648 Res = ValTracker.getNextSource();
652 // Insert the Def -> Use entry for the recently found source.
653 ValueTrackerResult CurSrcRes = RewriteMap.lookup(CurSrcPair);
654 if (CurSrcRes.isValid()) {
655 assert(CurSrcRes == Res && "ValueTrackerResult found must match");
658 RewriteMap.insert(std::make_pair(CurSrcPair, Res));
660 // ValueTrackerResult usually have one source unless it's the result from
661 // a PHI instruction. Add the found PHI edges to be looked up further.
662 unsigned NumSrcs = Res.getNumSources();
665 for (unsigned i = 0; i < NumSrcs; ++i)
666 SrcToLook.push_back(TargetInstrInfo::RegSubRegPair(
667 Res.getSrcReg(i), Res.getSrcSubReg(i)));
671 CurSrcPair.Reg = Res.getSrcReg(0);
672 CurSrcPair.SubReg = Res.getSrcSubReg(0);
673 // Do not extend the live-ranges of physical registers as they add
674 // constraints to the register allocator. Moreover, if we want to extend
675 // the live-range of a physical register, unlike SSA virtual register,
676 // we will have to check that they aren't redefine before the related use.
677 if (TargetRegisterInfo::isPhysicalRegister(CurSrcPair.Reg))
680 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg);
682 // If this source does not incur a cross register bank copy, use it.
683 ShouldRewrite = shareSameRegisterFile(*TRI, DefRC, SubReg, SrcRC,
685 } while (!ShouldRewrite);
687 // Continue looking for new sources...
692 DEBUG(dbgs() << "findNextSource: PHI limit reached\n");
696 // Do not continue searching for a new source if the there's at least
697 // one use-def which cannot be rewritten.
702 // If we did not find a more suitable source, there is nothing to optimize.
703 if (CurSrcPair.Reg == Reg)
709 /// \brief Insert a PHI instruction with incoming edges \p SrcRegs that are
710 /// guaranteed to have the same register class. This is necessary whenever we
711 /// successfully traverse a PHI instruction and find suitable sources coming
712 /// from its edges. By inserting a new PHI, we provide a rewritten PHI def
713 /// suitable to be used in a new COPY instruction.
715 insertPHI(MachineRegisterInfo *MRI, const TargetInstrInfo *TII,
716 const SmallVectorImpl<TargetInstrInfo::RegSubRegPair> &SrcRegs,
717 MachineInstr *OrigPHI) {
718 assert(!SrcRegs.empty() && "No sources to create a PHI instruction?");
720 const TargetRegisterClass *NewRC = MRI->getRegClass(SrcRegs[0].Reg);
721 unsigned NewVR = MRI->createVirtualRegister(NewRC);
722 MachineBasicBlock *MBB = OrigPHI->getParent();
723 MachineInstrBuilder MIB = BuildMI(*MBB, OrigPHI, OrigPHI->getDebugLoc(),
724 TII->get(TargetOpcode::PHI), NewVR);
726 unsigned MBBOpIdx = 2;
727 for (auto RegPair : SrcRegs) {
728 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg);
729 MIB.addMBB(OrigPHI->getOperand(MBBOpIdx).getMBB());
730 // Since we're extended the lifetime of RegPair.Reg, clear the
731 // kill flags to account for that and make RegPair.Reg reaches
733 MRI->clearKillFlags(RegPair.Reg);
741 /// \brief Helper class to rewrite the arguments of a copy-like instruction.
744 /// The copy-like instruction.
745 MachineInstr &CopyLike;
746 /// The index of the source being rewritten.
747 unsigned CurrentSrcIdx;
750 CopyRewriter(MachineInstr &MI) : CopyLike(MI), CurrentSrcIdx(0) {}
752 virtual ~CopyRewriter() {}
754 /// \brief Get the next rewritable source (SrcReg, SrcSubReg) and
755 /// the related value that it affects (TrackReg, TrackSubReg).
756 /// A source is considered rewritable if its register class and the
757 /// register class of the related TrackReg may not be register
758 /// coalescer friendly. In other words, given a copy-like instruction
759 /// not all the arguments may be returned at rewritable source, since
760 /// some arguments are none to be register coalescer friendly.
762 /// Each call of this method moves the current source to the next
763 /// rewritable source.
764 /// For instance, let CopyLike be the instruction to rewrite.
765 /// CopyLike has one definition and one source:
766 /// dst.dstSubIdx = CopyLike src.srcSubIdx.
768 /// The first call will give the first rewritable source, i.e.,
769 /// the only source this instruction has:
770 /// (SrcReg, SrcSubReg) = (src, srcSubIdx).
771 /// This source defines the whole definition, i.e.,
772 /// (TrackReg, TrackSubReg) = (dst, dstSubIdx).
774 /// The second and subsequent calls will return false, has there is only one
775 /// rewritable source.
777 /// \return True if a rewritable source has been found, false otherwise.
778 /// The output arguments are valid if and only if true is returned.
779 virtual bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
781 unsigned &TrackSubReg) {
782 // If CurrentSrcIdx == 1, this means this function has already been
783 // called once. CopyLike has one defintiion and one argument, thus,
784 // there is nothing else to rewrite.
785 if (!CopyLike.isCopy() || CurrentSrcIdx == 1)
787 // This is the first call to getNextRewritableSource.
788 // Move the CurrentSrcIdx to remember that we made that call.
790 // The rewritable source is the argument.
791 const MachineOperand &MOSrc = CopyLike.getOperand(1);
792 SrcReg = MOSrc.getReg();
793 SrcSubReg = MOSrc.getSubReg();
794 // What we track are the alternative sources of the definition.
795 const MachineOperand &MODef = CopyLike.getOperand(0);
796 TrackReg = MODef.getReg();
797 TrackSubReg = MODef.getSubReg();
801 /// \brief Rewrite the current source with \p NewReg and \p NewSubReg
803 /// \return True if the rewriting was possible, false otherwise.
804 virtual bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) {
805 if (!CopyLike.isCopy() || CurrentSrcIdx != 1)
807 MachineOperand &MOSrc = CopyLike.getOperand(CurrentSrcIdx);
808 MOSrc.setReg(NewReg);
809 MOSrc.setSubReg(NewSubReg);
813 /// \brief Given a \p Def.Reg and Def.SubReg pair, use \p RewriteMap to find
814 /// the new source to use for rewrite. If \p HandleMultipleSources is true and
815 /// multiple sources for a given \p Def are found along the way, we found a
816 /// PHI instructions that needs to be rewritten.
817 /// TODO: HandleMultipleSources should be removed once we test PHI handling
818 /// with coalescable copies.
819 TargetInstrInfo::RegSubRegPair
820 getNewSource(MachineRegisterInfo *MRI, const TargetInstrInfo *TII,
821 TargetInstrInfo::RegSubRegPair Def,
822 PeepholeOptimizer::RewriteMapTy &RewriteMap,
823 bool HandleMultipleSources = true) {
825 TargetInstrInfo::RegSubRegPair LookupSrc(Def.Reg, Def.SubReg);
827 ValueTrackerResult Res = RewriteMap.lookup(LookupSrc);
828 // If there are no entries on the map, LookupSrc is the new source.
832 // There's only one source for this definition, keep searching...
833 unsigned NumSrcs = Res.getNumSources();
835 LookupSrc.Reg = Res.getSrcReg(0);
836 LookupSrc.SubReg = Res.getSrcSubReg(0);
840 if (!HandleMultipleSources)
843 // Multiple sources, recurse into each source to find a new source
844 // for it. Then, rewrite the PHI accordingly to its new edges.
845 SmallVector<TargetInstrInfo::RegSubRegPair, 4> NewPHISrcs;
846 for (unsigned i = 0; i < NumSrcs; ++i) {
847 TargetInstrInfo::RegSubRegPair PHISrc(Res.getSrcReg(i),
848 Res.getSrcSubReg(i));
849 NewPHISrcs.push_back(
850 getNewSource(MRI, TII, PHISrc, RewriteMap, HandleMultipleSources));
853 // Build the new PHI node and return its def register as the new source.
854 MachineInstr *OrigPHI = const_cast<MachineInstr *>(Res.getInst());
855 MachineInstr *NewPHI = insertPHI(MRI, TII, NewPHISrcs, OrigPHI);
856 const MachineOperand &MODef = NewPHI->getOperand(0);
857 return TargetInstrInfo::RegSubRegPair(MODef.getReg(), MODef.getSubReg());
861 return TargetInstrInfo::RegSubRegPair(0, 0);
864 /// \brief Rewrite the source found through \p Def, by using the \p RewriteMap
865 /// and create a new COPY instruction. More info about RewriteMap in
866 /// PeepholeOptimizer::findNextSource. Right now this is only used to handle
867 /// Uncoalescable copies, since they are copy like instructions that aren't
868 /// recognized by the register allocator.
869 virtual MachineInstr *
870 RewriteSource(TargetInstrInfo::RegSubRegPair Def,
871 PeepholeOptimizer::RewriteMapTy &RewriteMap) {
876 /// \brief Helper class to rewrite uncoalescable copy like instructions
877 /// into new COPY (coalescable friendly) instructions.
878 class UncoalescableRewriter : public CopyRewriter {
880 const TargetInstrInfo &TII;
881 MachineRegisterInfo &MRI;
882 /// The number of defs in the bitcast
886 UncoalescableRewriter(MachineInstr &MI, const TargetInstrInfo &TII,
887 MachineRegisterInfo &MRI)
888 : CopyRewriter(MI), TII(TII), MRI(MRI) {
889 NumDefs = MI.getDesc().getNumDefs();
892 /// \brief Get the next rewritable def source (TrackReg, TrackSubReg)
893 /// All such sources need to be considered rewritable in order to
894 /// rewrite a uncoalescable copy-like instruction. This method return
895 /// each definition that must be checked if rewritable.
897 bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
899 unsigned &TrackSubReg) override {
900 // Find the next non-dead definition and continue from there.
901 if (CurrentSrcIdx == NumDefs)
904 while (CopyLike.getOperand(CurrentSrcIdx).isDead()) {
906 if (CurrentSrcIdx == NumDefs)
910 // What we track are the alternative sources of the definition.
911 const MachineOperand &MODef = CopyLike.getOperand(CurrentSrcIdx);
912 TrackReg = MODef.getReg();
913 TrackSubReg = MODef.getSubReg();
919 /// \brief Rewrite the source found through \p Def, by using the \p RewriteMap
920 /// and create a new COPY instruction. More info about RewriteMap in
921 /// PeepholeOptimizer::findNextSource. Right now this is only used to handle
922 /// Uncoalescable copies, since they are copy like instructions that aren't
923 /// recognized by the register allocator.
925 RewriteSource(TargetInstrInfo::RegSubRegPair Def,
926 PeepholeOptimizer::RewriteMapTy &RewriteMap) override {
927 assert(!TargetRegisterInfo::isPhysicalRegister(Def.Reg) &&
928 "We do not rewrite physical registers");
930 // Find the new source to use in the COPY rewrite.
931 TargetInstrInfo::RegSubRegPair NewSrc =
932 getNewSource(&MRI, &TII, Def, RewriteMap);
935 const TargetRegisterClass *DefRC = MRI.getRegClass(Def.Reg);
936 unsigned NewVR = MRI.createVirtualRegister(DefRC);
938 MachineInstr *NewCopy =
939 BuildMI(*CopyLike.getParent(), &CopyLike, CopyLike.getDebugLoc(),
940 TII.get(TargetOpcode::COPY), NewVR)
941 .addReg(NewSrc.Reg, 0, NewSrc.SubReg);
943 NewCopy->getOperand(0).setSubReg(Def.SubReg);
945 NewCopy->getOperand(0).setIsUndef();
947 MRI.replaceRegWith(Def.Reg, NewVR);
948 MRI.clearKillFlags(NewVR);
950 // We extended the lifetime of NewSrc.Reg, clear the kill flags to
952 MRI.clearKillFlags(NewSrc.Reg);
958 /// \brief Specialized rewriter for INSERT_SUBREG instruction.
959 class InsertSubregRewriter : public CopyRewriter {
961 InsertSubregRewriter(MachineInstr &MI) : CopyRewriter(MI) {
962 assert(MI.isInsertSubreg() && "Invalid instruction");
965 /// \brief See CopyRewriter::getNextRewritableSource.
966 /// Here CopyLike has the following form:
967 /// dst = INSERT_SUBREG Src1, Src2.src2SubIdx, subIdx.
968 /// Src1 has the same register class has dst, hence, there is
969 /// nothing to rewrite.
970 /// Src2.src2SubIdx, may not be register coalescer friendly.
971 /// Therefore, the first call to this method returns:
972 /// (SrcReg, SrcSubReg) = (Src2, src2SubIdx).
973 /// (TrackReg, TrackSubReg) = (dst, subIdx).
975 /// Subsequence calls will return false.
976 bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
978 unsigned &TrackSubReg) override {
979 // If we already get the only source we can rewrite, return false.
980 if (CurrentSrcIdx == 2)
982 // We are looking at v2 = INSERT_SUBREG v0, v1, sub0.
984 const MachineOperand &MOInsertedReg = CopyLike.getOperand(2);
985 SrcReg = MOInsertedReg.getReg();
986 SrcSubReg = MOInsertedReg.getSubReg();
987 const MachineOperand &MODef = CopyLike.getOperand(0);
989 // We want to track something that is compatible with the
990 // partial definition.
991 TrackReg = MODef.getReg();
992 if (MODef.getSubReg())
993 // Bails if we have to compose sub-register indices.
995 TrackSubReg = (unsigned)CopyLike.getOperand(3).getImm();
998 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
999 if (CurrentSrcIdx != 2)
1001 // We are rewriting the inserted reg.
1002 MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
1004 MO.setSubReg(NewSubReg);
1009 /// \brief Specialized rewriter for EXTRACT_SUBREG instruction.
1010 class ExtractSubregRewriter : public CopyRewriter {
1011 const TargetInstrInfo &TII;
1014 ExtractSubregRewriter(MachineInstr &MI, const TargetInstrInfo &TII)
1015 : CopyRewriter(MI), TII(TII) {
1016 assert(MI.isExtractSubreg() && "Invalid instruction");
1019 /// \brief See CopyRewriter::getNextRewritableSource.
1020 /// Here CopyLike has the following form:
1021 /// dst.dstSubIdx = EXTRACT_SUBREG Src, subIdx.
1022 /// There is only one rewritable source: Src.subIdx,
1023 /// which defines dst.dstSubIdx.
1024 bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
1026 unsigned &TrackSubReg) override {
1027 // If we already get the only source we can rewrite, return false.
1028 if (CurrentSrcIdx == 1)
1030 // We are looking at v1 = EXTRACT_SUBREG v0, sub0.
1032 const MachineOperand &MOExtractedReg = CopyLike.getOperand(1);
1033 SrcReg = MOExtractedReg.getReg();
1034 // If we have to compose sub-register indices, bails out.
1035 if (MOExtractedReg.getSubReg())
1038 SrcSubReg = CopyLike.getOperand(2).getImm();
1040 // We want to track something that is compatible with the definition.
1041 const MachineOperand &MODef = CopyLike.getOperand(0);
1042 TrackReg = MODef.getReg();
1043 TrackSubReg = MODef.getSubReg();
1047 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
1048 // The only source we can rewrite is the input register.
1049 if (CurrentSrcIdx != 1)
1052 CopyLike.getOperand(CurrentSrcIdx).setReg(NewReg);
1054 // If we find a source that does not require to extract something,
1055 // rewrite the operation with a copy.
1057 // Move the current index to an invalid position.
1058 // We do not want another call to this method to be able
1059 // to do any change.
1061 // Rewrite the operation as a COPY.
1062 // Get rid of the sub-register index.
1063 CopyLike.RemoveOperand(2);
1064 // Morph the operation into a COPY.
1065 CopyLike.setDesc(TII.get(TargetOpcode::COPY));
1068 CopyLike.getOperand(CurrentSrcIdx + 1).setImm(NewSubReg);
1073 /// \brief Specialized rewriter for REG_SEQUENCE instruction.
1074 class RegSequenceRewriter : public CopyRewriter {
1076 RegSequenceRewriter(MachineInstr &MI) : CopyRewriter(MI) {
1077 assert(MI.isRegSequence() && "Invalid instruction");
1080 /// \brief See CopyRewriter::getNextRewritableSource.
1081 /// Here CopyLike has the following form:
1082 /// dst = REG_SEQUENCE Src1.src1SubIdx, subIdx1, Src2.src2SubIdx, subIdx2.
1083 /// Each call will return a different source, walking all the available
1086 /// The first call returns:
1087 /// (SrcReg, SrcSubReg) = (Src1, src1SubIdx).
1088 /// (TrackReg, TrackSubReg) = (dst, subIdx1).
1090 /// The second call returns:
1091 /// (SrcReg, SrcSubReg) = (Src2, src2SubIdx).
1092 /// (TrackReg, TrackSubReg) = (dst, subIdx2).
1094 /// And so on, until all the sources have been traversed, then
1095 /// it returns false.
1096 bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
1098 unsigned &TrackSubReg) override {
1099 // We are looking at v0 = REG_SEQUENCE v1, sub1, v2, sub2, etc.
1101 // If this is the first call, move to the first argument.
1102 if (CurrentSrcIdx == 0) {
1105 // Otherwise, move to the next argument and check that it is valid.
1107 if (CurrentSrcIdx >= CopyLike.getNumOperands())
1110 const MachineOperand &MOInsertedReg = CopyLike.getOperand(CurrentSrcIdx);
1111 SrcReg = MOInsertedReg.getReg();
1112 // If we have to compose sub-register indices, bails out.
1113 if ((SrcSubReg = MOInsertedReg.getSubReg()))
1116 // We want to track something that is compatible with the related
1117 // partial definition.
1118 TrackSubReg = CopyLike.getOperand(CurrentSrcIdx + 1).getImm();
1120 const MachineOperand &MODef = CopyLike.getOperand(0);
1121 TrackReg = MODef.getReg();
1122 // If we have to compose sub-registers, bails.
1123 return MODef.getSubReg() == 0;
1126 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
1127 // We cannot rewrite out of bound operands.
1128 // Moreover, rewritable sources are at odd positions.
1129 if ((CurrentSrcIdx & 1) != 1 || CurrentSrcIdx > CopyLike.getNumOperands())
1132 MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
1134 MO.setSubReg(NewSubReg);
1140 /// \brief Get the appropriated CopyRewriter for \p MI.
1141 /// \return A pointer to a dynamically allocated CopyRewriter or nullptr
1142 /// if no rewriter works for \p MI.
1143 static CopyRewriter *getCopyRewriter(MachineInstr &MI,
1144 const TargetInstrInfo &TII,
1145 MachineRegisterInfo &MRI) {
1146 // Handle uncoalescable copy-like instructions.
1147 if (MI.isBitcast() || (MI.isRegSequenceLike() || MI.isInsertSubregLike() ||
1148 MI.isExtractSubregLike()))
1149 return new UncoalescableRewriter(MI, TII, MRI);
1151 switch (MI.getOpcode()) {
1154 case TargetOpcode::COPY:
1155 return new CopyRewriter(MI);
1156 case TargetOpcode::INSERT_SUBREG:
1157 return new InsertSubregRewriter(MI);
1158 case TargetOpcode::EXTRACT_SUBREG:
1159 return new ExtractSubregRewriter(MI, TII);
1160 case TargetOpcode::REG_SEQUENCE:
1161 return new RegSequenceRewriter(MI);
1163 llvm_unreachable(nullptr);
1166 /// \brief Optimize generic copy instructions to avoid cross
1167 /// register bank copy. The optimization looks through a chain of
1168 /// copies and tries to find a source that has a compatible register
1170 /// Two register classes are considered to be compatible if they share
1171 /// the same register bank.
1172 /// New copies issued by this optimization are register allocator
1173 /// friendly. This optimization does not remove any copy as it may
1174 /// overconstraint the register allocator, but replaces some operands
1176 /// \pre isCoalescableCopy(*MI) is true.
1177 /// \return True, when \p MI has been rewritten. False otherwise.
1178 bool PeepholeOptimizer::optimizeCoalescableCopy(MachineInstr *MI) {
1179 assert(MI && isCoalescableCopy(*MI) && "Invalid argument");
1180 assert(MI->getDesc().getNumDefs() == 1 &&
1181 "Coalescer can understand multiple defs?!");
1182 const MachineOperand &MODef = MI->getOperand(0);
1183 // Do not rewrite physical definitions.
1184 if (TargetRegisterInfo::isPhysicalRegister(MODef.getReg()))
1187 bool Changed = false;
1188 // Get the right rewriter for the current copy.
1189 std::unique_ptr<CopyRewriter> CpyRewriter(getCopyRewriter(*MI, *TII, *MRI));
1190 // If none exists, bails out.
1193 // Rewrite each rewritable source.
1194 unsigned SrcReg, SrcSubReg, TrackReg, TrackSubReg;
1195 while (CpyRewriter->getNextRewritableSource(SrcReg, SrcSubReg, TrackReg,
1197 // Keep track of PHI nodes and its incoming edges when looking for sources.
1198 RewriteMapTy RewriteMap;
1199 // Try to find a more suitable source. If we failed to do so, or get the
1200 // actual source, move to the next source.
1201 if (!findNextSource(TrackReg, TrackSubReg, RewriteMap))
1204 // Get the new source to rewrite. TODO: Only enable handling of multiple
1205 // sources (PHIs) once we have a motivating example and testcases for it.
1206 TargetInstrInfo::RegSubRegPair TrackPair(TrackReg, TrackSubReg);
1207 TargetInstrInfo::RegSubRegPair NewSrc = CpyRewriter->getNewSource(
1208 MRI, TII, TrackPair, RewriteMap, false /* multiple sources */);
1209 if (SrcReg == NewSrc.Reg)
1213 if (CpyRewriter->RewriteCurrentSource(NewSrc.Reg, NewSrc.SubReg)) {
1214 // We may have extended the live-range of NewSrc, account for that.
1215 MRI->clearKillFlags(NewSrc.Reg);
1219 // TODO: We could have a clean-up method to tidy the instruction.
1220 // E.g., v0 = INSERT_SUBREG v1, v1.sub0, sub0
1222 // Currently we haven't seen motivating example for that and we
1223 // want to avoid untested code.
1224 NumRewrittenCopies += Changed;
1228 /// \brief Optimize copy-like instructions to create
1229 /// register coalescer friendly instruction.
1230 /// The optimization tries to kill-off the \p MI by looking
1231 /// through a chain of copies to find a source that has a compatible
1233 /// If such a source is found, it replace \p MI by a generic COPY
1235 /// \pre isUncoalescableCopy(*MI) is true.
1236 /// \return True, when \p MI has been optimized. In that case, \p MI has
1237 /// been removed from its parent.
1238 /// All COPY instructions created, are inserted in \p LocalMIs.
1239 bool PeepholeOptimizer::optimizeUncoalescableCopy(
1240 MachineInstr *MI, SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
1241 assert(MI && isUncoalescableCopy(*MI) && "Invalid argument");
1243 // Check if we can rewrite all the values defined by this instruction.
1244 SmallVector<TargetInstrInfo::RegSubRegPair, 4> RewritePairs;
1245 // Get the right rewriter for the current copy.
1246 std::unique_ptr<CopyRewriter> CpyRewriter(getCopyRewriter(*MI, *TII, *MRI));
1247 // If none exists, bails out.
1251 // Rewrite each rewritable source by generating new COPYs. This works
1252 // differently from optimizeCoalescableCopy since it first makes sure that all
1253 // definitions can be rewritten.
1254 RewriteMapTy RewriteMap;
1255 unsigned Reg, SubReg, CopyDefReg, CopyDefSubReg;
1256 while (CpyRewriter->getNextRewritableSource(Reg, SubReg, CopyDefReg,
1258 // If a physical register is here, this is probably for a good reason.
1259 // Do not rewrite that.
1260 if (TargetRegisterInfo::isPhysicalRegister(CopyDefReg))
1263 // If we do not know how to rewrite this definition, there is no point
1264 // in trying to kill this instruction.
1265 TargetInstrInfo::RegSubRegPair Def(CopyDefReg, CopyDefSubReg);
1266 if (!findNextSource(Def.Reg, Def.SubReg, RewriteMap))
1269 RewritePairs.push_back(Def);
1272 // The change is possible for all defs, do it.
1273 for (const auto &Def : RewritePairs) {
1274 // Rewrite the "copy" in a way the register coalescer understands.
1275 MachineInstr *NewCopy = CpyRewriter->RewriteSource(Def, RewriteMap);
1276 assert(NewCopy && "Should be able to always generate a new copy");
1277 LocalMIs.insert(NewCopy);
1281 MI->eraseFromParent();
1282 ++NumUncoalescableCopies;
1286 /// isLoadFoldable - Check whether MI is a candidate for folding into a later
1287 /// instruction. We only fold loads to virtual registers and the virtual
1288 /// register defined has a single use.
1289 bool PeepholeOptimizer::isLoadFoldable(
1291 SmallSet<unsigned, 16> &FoldAsLoadDefCandidates) {
1292 if (!MI->canFoldAsLoad() || !MI->mayLoad())
1294 const MCInstrDesc &MCID = MI->getDesc();
1295 if (MCID.getNumDefs() != 1)
1298 unsigned Reg = MI->getOperand(0).getReg();
1299 // To reduce compilation time, we check MRI->hasOneNonDBGUse when inserting
1300 // loads. It should be checked when processing uses of the load, since
1301 // uses can be removed during peephole.
1302 if (!MI->getOperand(0).getSubReg() &&
1303 TargetRegisterInfo::isVirtualRegister(Reg) &&
1304 MRI->hasOneNonDBGUse(Reg)) {
1305 FoldAsLoadDefCandidates.insert(Reg);
1311 bool PeepholeOptimizer::isMoveImmediate(MachineInstr *MI,
1312 SmallSet<unsigned, 4> &ImmDefRegs,
1313 DenseMap<unsigned, MachineInstr*> &ImmDefMIs) {
1314 const MCInstrDesc &MCID = MI->getDesc();
1315 if (!MI->isMoveImmediate())
1317 if (MCID.getNumDefs() != 1)
1319 unsigned Reg = MI->getOperand(0).getReg();
1320 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1321 ImmDefMIs.insert(std::make_pair(Reg, MI));
1322 ImmDefRegs.insert(Reg);
1329 /// foldImmediate - Try folding register operands that are defined by move
1330 /// immediate instructions, i.e. a trivial constant folding optimization, if
1331 /// and only if the def and use are in the same BB.
1332 bool PeepholeOptimizer::foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
1333 SmallSet<unsigned, 4> &ImmDefRegs,
1334 DenseMap<unsigned, MachineInstr*> &ImmDefMIs) {
1335 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
1336 MachineOperand &MO = MI->getOperand(i);
1337 if (!MO.isReg() || MO.isDef())
1339 unsigned Reg = MO.getReg();
1340 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1342 if (ImmDefRegs.count(Reg) == 0)
1344 DenseMap<unsigned, MachineInstr*>::iterator II = ImmDefMIs.find(Reg);
1345 assert(II != ImmDefMIs.end());
1346 if (TII->FoldImmediate(MI, II->second, Reg, MRI)) {
1354 bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
1355 if (skipOptnoneFunction(*MF.getFunction()))
1358 DEBUG(dbgs() << "********** PEEPHOLE OPTIMIZER **********\n");
1359 DEBUG(dbgs() << "********** Function: " << MF.getName() << '\n');
1361 if (DisablePeephole)
1364 TII = MF.getSubtarget().getInstrInfo();
1365 TRI = MF.getSubtarget().getRegisterInfo();
1366 MRI = &MF.getRegInfo();
1367 DT = Aggressive ? &getAnalysis<MachineDominatorTree>() : nullptr;
1369 bool Changed = false;
1371 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
1372 MachineBasicBlock *MBB = &*I;
1374 bool SeenMoveImm = false;
1376 // During this forward scan, at some point it needs to answer the question
1377 // "given a pointer to an MI in the current BB, is it located before or
1378 // after the current instruction".
1379 // To perform this, the following set keeps track of the MIs already seen
1380 // during the scan, if a MI is not in the set, it is assumed to be located
1381 // after. Newly created MIs have to be inserted in the set as well.
1382 SmallPtrSet<MachineInstr*, 16> LocalMIs;
1383 SmallSet<unsigned, 4> ImmDefRegs;
1384 DenseMap<unsigned, MachineInstr*> ImmDefMIs;
1385 SmallSet<unsigned, 16> FoldAsLoadDefCandidates;
1387 for (MachineBasicBlock::iterator
1388 MII = I->begin(), MIE = I->end(); MII != MIE; ) {
1389 MachineInstr *MI = &*MII;
1390 // We may be erasing MI below, increment MII now.
1392 LocalMIs.insert(MI);
1394 // Skip debug values. They should not affect this peephole optimization.
1395 if (MI->isDebugValue())
1398 // If there exists an instruction which belongs to the following
1399 // categories, we will discard the load candidates.
1400 if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() ||
1401 MI->isKill() || MI->isInlineAsm() ||
1402 MI->hasUnmodeledSideEffects()) {
1403 FoldAsLoadDefCandidates.clear();
1406 if (MI->mayStore() || MI->isCall())
1407 FoldAsLoadDefCandidates.clear();
1409 if ((isUncoalescableCopy(*MI) &&
1410 optimizeUncoalescableCopy(MI, LocalMIs)) ||
1411 (MI->isCompare() && optimizeCmpInstr(MI, MBB)) ||
1412 (MI->isSelect() && optimizeSelect(MI, LocalMIs))) {
1419 if (MI->isConditionalBranch() && optimizeCondBranch(MI)) {
1424 if (isCoalescableCopy(*MI) && optimizeCoalescableCopy(MI)) {
1425 // MI is just rewritten.
1430 if (isMoveImmediate(MI, ImmDefRegs, ImmDefMIs)) {
1433 Changed |= optimizeExtInstr(MI, MBB, LocalMIs);
1434 // optimizeExtInstr might have created new instructions after MI
1435 // and before the already incremented MII. Adjust MII so that the
1436 // next iteration sees the new instructions.
1440 Changed |= foldImmediate(MI, MBB, ImmDefRegs, ImmDefMIs);
1443 // Check whether MI is a load candidate for folding into a later
1444 // instruction. If MI is not a candidate, check whether we can fold an
1445 // earlier load into MI.
1446 if (!isLoadFoldable(MI, FoldAsLoadDefCandidates) &&
1447 !FoldAsLoadDefCandidates.empty()) {
1448 const MCInstrDesc &MIDesc = MI->getDesc();
1449 for (unsigned i = MIDesc.getNumDefs(); i != MIDesc.getNumOperands();
1451 const MachineOperand &MOp = MI->getOperand(i);
1454 unsigned FoldAsLoadDefReg = MOp.getReg();
1455 if (FoldAsLoadDefCandidates.count(FoldAsLoadDefReg)) {
1456 // We need to fold load after optimizeCmpInstr, since
1457 // optimizeCmpInstr can enable folding by converting SUB to CMP.
1458 // Save FoldAsLoadDefReg because optimizeLoadInstr() resets it and
1459 // we need it for markUsesInDebugValueAsUndef().
1460 unsigned FoldedReg = FoldAsLoadDefReg;
1461 MachineInstr *DefMI = nullptr;
1462 MachineInstr *FoldMI = TII->optimizeLoadInstr(MI, MRI,
1466 // Update LocalMIs since we replaced MI with FoldMI and deleted
1468 DEBUG(dbgs() << "Replacing: " << *MI);
1469 DEBUG(dbgs() << " With: " << *FoldMI);
1471 LocalMIs.erase(DefMI);
1472 LocalMIs.insert(FoldMI);
1473 MI->eraseFromParent();
1474 DefMI->eraseFromParent();
1475 MRI->markUsesInDebugValueAsUndef(FoldedReg);
1476 FoldAsLoadDefCandidates.erase(FoldedReg);
1478 // MI is replaced with FoldMI.
1491 ValueTrackerResult ValueTracker::getNextSourceFromCopy() {
1492 assert(Def->isCopy() && "Invalid definition");
1493 // Copy instruction are supposed to be: Def = Src.
1494 // If someone breaks this assumption, bad things will happen everywhere.
1495 assert(Def->getNumOperands() == 2 && "Invalid number of operands");
1497 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
1498 // If we look for a different subreg, it means we want a subreg of src.
1499 // Bails as we do not support composing subreg yet.
1500 return ValueTrackerResult();
1501 // Otherwise, we want the whole source.
1502 const MachineOperand &Src = Def->getOperand(1);
1503 return ValueTrackerResult(Src.getReg(), Src.getSubReg());
1506 ValueTrackerResult ValueTracker::getNextSourceFromBitcast() {
1507 assert(Def->isBitcast() && "Invalid definition");
1509 // Bail if there are effects that a plain copy will not expose.
1510 if (Def->hasUnmodeledSideEffects())
1511 return ValueTrackerResult();
1513 // Bitcasts with more than one def are not supported.
1514 if (Def->getDesc().getNumDefs() != 1)
1515 return ValueTrackerResult();
1516 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
1517 // If we look for a different subreg, it means we want a subreg of the src.
1518 // Bails as we do not support composing subreg yet.
1519 return ValueTrackerResult();
1521 unsigned SrcIdx = Def->getNumOperands();
1522 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx;
1524 const MachineOperand &MO = Def->getOperand(OpIdx);
1525 if (!MO.isReg() || !MO.getReg())
1527 assert(!MO.isDef() && "We should have skipped all the definitions by now");
1528 if (SrcIdx != EndOpIdx)
1529 // Multiple sources?
1530 return ValueTrackerResult();
1533 const MachineOperand &Src = Def->getOperand(SrcIdx);
1534 return ValueTrackerResult(Src.getReg(), Src.getSubReg());
1537 ValueTrackerResult ValueTracker::getNextSourceFromRegSequence() {
1538 assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&
1539 "Invalid definition");
1541 if (Def->getOperand(DefIdx).getSubReg())
1542 // If we are composing subreg, bails out.
1543 // The case we are checking is Def.<subreg> = REG_SEQUENCE.
1544 // This should almost never happen as the SSA property is tracked at
1545 // the register level (as opposed to the subreg level).
1549 // is a valid SSA representation for Def.sub0 and Def.sub1, but not for
1550 // Def. Thus, it must not be generated.
1551 // However, some code could theoretically generates a single
1552 // Def.sub0 (i.e, not defining the other subregs) and we would
1554 // If we can ascertain (or force) that this never happens, we could
1555 // turn that into an assertion.
1556 return ValueTrackerResult();
1559 // We could handle the REG_SEQUENCE here, but we do not want to
1560 // duplicate the code from the generic TII.
1561 return ValueTrackerResult();
1563 SmallVector<TargetInstrInfo::RegSubRegPairAndIdx, 8> RegSeqInputRegs;
1564 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))
1565 return ValueTrackerResult();
1567 // We are looking at:
1568 // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
1569 // Check if one of the operand defines the subreg we are interested in.
1570 for (auto &RegSeqInput : RegSeqInputRegs) {
1571 if (RegSeqInput.SubIdx == DefSubReg) {
1572 if (RegSeqInput.SubReg)
1573 // Bails if we have to compose sub registers.
1574 return ValueTrackerResult();
1576 return ValueTrackerResult(RegSeqInput.Reg, RegSeqInput.SubReg);
1580 // If the subreg we are tracking is super-defined by another subreg,
1581 // we could follow this value. However, this would require to compose
1582 // the subreg and we do not do that for now.
1583 return ValueTrackerResult();
1586 ValueTrackerResult ValueTracker::getNextSourceFromInsertSubreg() {
1587 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) &&
1588 "Invalid definition");
1590 if (Def->getOperand(DefIdx).getSubReg())
1591 // If we are composing subreg, bails out.
1592 // Same remark as getNextSourceFromRegSequence.
1593 // I.e., this may be turned into an assert.
1594 return ValueTrackerResult();
1597 // We could handle the REG_SEQUENCE here, but we do not want to
1598 // duplicate the code from the generic TII.
1599 return ValueTrackerResult();
1601 TargetInstrInfo::RegSubRegPair BaseReg;
1602 TargetInstrInfo::RegSubRegPairAndIdx InsertedReg;
1603 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg))
1604 return ValueTrackerResult();
1606 // We are looking at:
1607 // Def = INSERT_SUBREG v0, v1, sub1
1608 // There are two cases:
1609 // 1. DefSubReg == sub1, get v1.
1610 // 2. DefSubReg != sub1, the value may be available through v0.
1612 // #1 Check if the inserted register matches the required sub index.
1613 if (InsertedReg.SubIdx == DefSubReg) {
1614 return ValueTrackerResult(InsertedReg.Reg, InsertedReg.SubReg);
1616 // #2 Otherwise, if the sub register we are looking for is not partial
1617 // defined by the inserted element, we can look through the main
1619 const MachineOperand &MODef = Def->getOperand(DefIdx);
1620 // If the result register (Def) and the base register (v0) do not
1621 // have the same register class or if we have to compose
1622 // subregisters, bails out.
1623 if (MRI.getRegClass(MODef.getReg()) != MRI.getRegClass(BaseReg.Reg) ||
1625 return ValueTrackerResult();
1627 // Get the TRI and check if the inserted sub-register overlaps with the
1628 // sub-register we are tracking.
1629 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
1631 (TRI->getSubRegIndexLaneMask(DefSubReg) &
1632 TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)) != 0)
1633 return ValueTrackerResult();
1634 // At this point, the value is available in v0 via the same subreg
1636 return ValueTrackerResult(BaseReg.Reg, DefSubReg);
1639 ValueTrackerResult ValueTracker::getNextSourceFromExtractSubreg() {
1640 assert((Def->isExtractSubreg() ||
1641 Def->isExtractSubregLike()) && "Invalid definition");
1642 // We are looking at:
1643 // Def = EXTRACT_SUBREG v0, sub0
1645 // Bails if we have to compose sub registers.
1646 // Indeed, if DefSubReg != 0, we would have to compose it with sub0.
1648 return ValueTrackerResult();
1651 // We could handle the EXTRACT_SUBREG here, but we do not want to
1652 // duplicate the code from the generic TII.
1653 return ValueTrackerResult();
1655 TargetInstrInfo::RegSubRegPairAndIdx ExtractSubregInputReg;
1656 if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg))
1657 return ValueTrackerResult();
1659 // Bails if we have to compose sub registers.
1660 // Likewise, if v0.subreg != 0, we would have to compose v0.subreg with sub0.
1661 if (ExtractSubregInputReg.SubReg)
1662 return ValueTrackerResult();
1663 // Otherwise, the value is available in the v0.sub0.
1664 return ValueTrackerResult(ExtractSubregInputReg.Reg, ExtractSubregInputReg.SubIdx);
1667 ValueTrackerResult ValueTracker::getNextSourceFromSubregToReg() {
1668 assert(Def->isSubregToReg() && "Invalid definition");
1669 // We are looking at:
1670 // Def = SUBREG_TO_REG Imm, v0, sub0
1672 // Bails if we have to compose sub registers.
1673 // If DefSubReg != sub0, we would have to check that all the bits
1674 // we track are included in sub0 and if yes, we would have to
1675 // determine the right subreg in v0.
1676 if (DefSubReg != Def->getOperand(3).getImm())
1677 return ValueTrackerResult();
1678 // Bails if we have to compose sub registers.
1679 // Likewise, if v0.subreg != 0, we would have to compose it with sub0.
1680 if (Def->getOperand(2).getSubReg())
1681 return ValueTrackerResult();
1683 return ValueTrackerResult(Def->getOperand(2).getReg(),
1684 Def->getOperand(3).getImm());
1687 /// \brief Explore each PHI incoming operand and return its sources
1688 ValueTrackerResult ValueTracker::getNextSourceFromPHI() {
1689 assert(Def->isPHI() && "Invalid definition");
1690 ValueTrackerResult Res;
1692 // If we look for a different subreg, bails as we do not
1693 // support composing subreg yet.
1694 if (Def->getOperand(0).getSubReg() != DefSubReg)
1695 return ValueTrackerResult();
1697 // Return all register sources for PHI instructions.
1698 for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) {
1699 auto &MO = Def->getOperand(i);
1700 assert(MO.isReg() && "Invalid PHI instruction");
1701 Res.addSource(MO.getReg(), MO.getSubReg());
1707 ValueTrackerResult ValueTracker::getNextSourceImpl() {
1708 assert(Def && "This method needs a valid definition");
1711 (DefIdx < Def->getDesc().getNumDefs() || Def->getDesc().isVariadic()) &&
1712 Def->getOperand(DefIdx).isDef() && "Invalid DefIdx");
1714 return getNextSourceFromCopy();
1715 if (Def->isBitcast())
1716 return getNextSourceFromBitcast();
1717 // All the remaining cases involve "complex" instructions.
1718 // Bails if we did not ask for the advanced tracking.
1719 if (!UseAdvancedTracking)
1720 return ValueTrackerResult();
1721 if (Def->isRegSequence() || Def->isRegSequenceLike())
1722 return getNextSourceFromRegSequence();
1723 if (Def->isInsertSubreg() || Def->isInsertSubregLike())
1724 return getNextSourceFromInsertSubreg();
1725 if (Def->isExtractSubreg() || Def->isExtractSubregLike())
1726 return getNextSourceFromExtractSubreg();
1727 if (Def->isSubregToReg())
1728 return getNextSourceFromSubregToReg();
1730 return getNextSourceFromPHI();
1731 return ValueTrackerResult();
1734 ValueTrackerResult ValueTracker::getNextSource() {
1735 // If we reach a point where we cannot move up in the use-def chain,
1736 // there is nothing we can get.
1738 return ValueTrackerResult();
1740 ValueTrackerResult Res = getNextSourceImpl();
1741 if (Res.isValid()) {
1742 // Update definition, definition index, and subregister for the
1743 // next call of getNextSource.
1744 // Update the current register.
1745 bool OneRegSrc = Res.getNumSources() == 1;
1747 Reg = Res.getSrcReg(0);
1748 // Update the result before moving up in the use-def chain
1749 // with the instruction containing the last found sources.
1752 // If we can still move up in the use-def chain, move to the next
1754 if (!TargetRegisterInfo::isPhysicalRegister(Reg) && OneRegSrc) {
1755 Def = MRI.getVRegDef(Reg);
1756 DefIdx = MRI.def_begin(Reg).getOperandNo();
1757 DefSubReg = Res.getSrcSubReg(0);
1761 // If we end up here, this means we will not be able to find another source
1762 // for the next iteration. Make sure any new call to getNextSource bails out
1763 // early by cutting the use-def chain.