1 //===-- PeepholeOptimizer.cpp - Peephole Optimizations --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Perform peephole optimizations on the machine code:
12 // - Optimize Extensions
14 // Optimization of sign / zero extension instructions. It may be extended to
15 // handle other instructions with similar properties.
17 // On some targets, some instructions, e.g. X86 sign / zero extension, may
18 // leave the source value in the lower part of the result. This optimization
19 // will replace some uses of the pre-extension value with uses of the
20 // sub-register of the results.
22 // - Optimize Comparisons
24 // Optimization of comparison instructions. For instance, in this code:
30 // If the "sub" instruction all ready sets (or could be modified to set) the
31 // same flag that the "cmp" instruction sets and that "bz" uses, then we can
32 // eliminate the "cmp" instruction.
34 // Another instance, in this code:
36 // sub r1, r3 | sub r1, imm
37 // cmp r3, r1 or cmp r1, r3 | cmp r1, imm
40 // If the branch instruction can use flag from "sub", then we can replace
41 // "sub" with "subs" and eliminate the "cmp" instruction.
43 // - Optimize Bitcast pairs:
52 //===----------------------------------------------------------------------===//
54 #define DEBUG_TYPE "peephole-opt"
55 #include "llvm/CodeGen/Passes.h"
56 #include "llvm/CodeGen/MachineDominators.h"
57 #include "llvm/CodeGen/MachineInstrBuilder.h"
58 #include "llvm/CodeGen/MachineRegisterInfo.h"
59 #include "llvm/Target/TargetInstrInfo.h"
60 #include "llvm/Target/TargetRegisterInfo.h"
61 #include "llvm/Support/CommandLine.h"
62 #include "llvm/ADT/DenseMap.h"
63 #include "llvm/ADT/SmallPtrSet.h"
64 #include "llvm/ADT/SmallSet.h"
65 #include "llvm/ADT/Statistic.h"
68 // Optimize Extensions
70 Aggressive("aggressive-ext-opt", cl::Hidden,
71 cl::desc("Aggressive extension optimization"));
74 DisablePeephole("disable-peephole", cl::Hidden, cl::init(false),
75 cl::desc("Disable the peephole optimizer"));
77 STATISTIC(NumReuse, "Number of extension results reused");
78 STATISTIC(NumBitcasts, "Number of bitcasts eliminated");
79 STATISTIC(NumCmps, "Number of compares eliminated");
80 STATISTIC(NumImmFold, "Number of move immediate folded");
81 STATISTIC(NumLoadFold, "Number of loads folded");
84 class PeepholeOptimizer : public MachineFunctionPass {
85 const TargetMachine *TM;
86 const TargetInstrInfo *TII;
87 MachineRegisterInfo *MRI;
88 MachineDominatorTree *DT; // Machine dominator tree
91 static char ID; // Pass identification
92 PeepholeOptimizer() : MachineFunctionPass(ID) {
93 initializePeepholeOptimizerPass(*PassRegistry::getPassRegistry());
96 virtual bool runOnMachineFunction(MachineFunction &MF);
98 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
100 MachineFunctionPass::getAnalysisUsage(AU);
102 AU.addRequired<MachineDominatorTree>();
103 AU.addPreserved<MachineDominatorTree>();
108 bool optimizeBitcastInstr(MachineInstr *MI, MachineBasicBlock *MBB);
109 bool optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
110 bool optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
111 SmallPtrSet<MachineInstr*, 8> &LocalMIs);
112 bool isMoveImmediate(MachineInstr *MI,
113 SmallSet<unsigned, 4> &ImmDefRegs,
114 DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
115 bool foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
116 SmallSet<unsigned, 4> &ImmDefRegs,
117 DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
121 char PeepholeOptimizer::ID = 0;
122 char &llvm::PeepholeOptimizerID = PeepholeOptimizer::ID;
123 INITIALIZE_PASS_BEGIN(PeepholeOptimizer, "peephole-opts",
124 "Peephole Optimizations", false, false)
125 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
126 INITIALIZE_PASS_END(PeepholeOptimizer, "peephole-opts",
127 "Peephole Optimizations", false, false)
129 /// optimizeExtInstr - If instruction is a copy-like instruction, i.e. it reads
130 /// a single register and writes a single register and it does not modify the
131 /// source, and if the source value is preserved as a sub-register of the
132 /// result, then replace all reachable uses of the source with the subreg of the
135 /// Do not generate an EXTRACT that is used only in a debug use, as this changes
136 /// the code. Since this code does not currently share EXTRACTs, just ignore all
138 bool PeepholeOptimizer::
139 optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
140 SmallPtrSet<MachineInstr*, 8> &LocalMIs) {
141 unsigned SrcReg, DstReg, SubIdx;
142 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
145 if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
146 TargetRegisterInfo::isPhysicalRegister(SrcReg))
149 if (MRI->hasOneNonDBGUse(SrcReg))
153 // Ensure DstReg can get a register class that actually supports
154 // sub-registers. Don't change the class until we commit.
155 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
156 DstRC = TM->getRegisterInfo()->getSubClassWithSubReg(DstRC, SubIdx);
160 // The ext instr may be operating on a sub-register of SrcReg as well.
161 // PPC::EXTSW is a 32 -> 64-bit sign extension, but it reads a 64-bit
163 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of
164 // SrcReg:SubIdx should be replaced.
165 bool UseSrcSubIdx = TM->getRegisterInfo()->
166 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0;
168 // The source has other uses. See if we can replace the other uses with use of
169 // the result of the extension.
170 SmallPtrSet<MachineBasicBlock*, 4> ReachedBBs;
171 for (MachineRegisterInfo::use_nodbg_iterator
172 UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end();
174 ReachedBBs.insert(UI->getParent());
176 // Uses that are in the same BB of uses of the result of the instruction.
177 SmallVector<MachineOperand*, 8> Uses;
179 // Uses that the result of the instruction can reach.
180 SmallVector<MachineOperand*, 8> ExtendedUses;
182 bool ExtendLife = true;
183 for (MachineRegisterInfo::use_nodbg_iterator
184 UI = MRI->use_nodbg_begin(SrcReg), UE = MRI->use_nodbg_end();
186 MachineOperand &UseMO = UI.getOperand();
187 MachineInstr *UseMI = &*UI;
191 if (UseMI->isPHI()) {
196 // Only accept uses of SrcReg:SubIdx.
197 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
200 // It's an error to translate this:
202 // %reg1025 = <sext> %reg1024
204 // %reg1026 = SUBREG_TO_REG 0, %reg1024, 4
208 // %reg1025 = <sext> %reg1024
210 // %reg1027 = COPY %reg1025:4
211 // %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
213 // The problem here is that SUBREG_TO_REG is there to assert that an
214 // implicit zext occurs. It doesn't insert a zext instruction. If we allow
215 // the COPY here, it will give us the value after the <sext>, not the
216 // original value of %reg1024 before <sext>.
217 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
220 MachineBasicBlock *UseMBB = UseMI->getParent();
222 // Local uses that come after the extension.
223 if (!LocalMIs.count(UseMI))
224 Uses.push_back(&UseMO);
225 } else if (ReachedBBs.count(UseMBB)) {
226 // Non-local uses where the result of the extension is used. Always
227 // replace these unless it's a PHI.
228 Uses.push_back(&UseMO);
229 } else if (Aggressive && DT->dominates(MBB, UseMBB)) {
230 // We may want to extend the live range of the extension result in order
231 // to replace these uses.
232 ExtendedUses.push_back(&UseMO);
234 // Both will be live out of the def MBB anyway. Don't extend live range of
235 // the extension result.
241 if (ExtendLife && !ExtendedUses.empty())
242 // Extend the liveness of the extension result.
243 std::copy(ExtendedUses.begin(), ExtendedUses.end(),
244 std::back_inserter(Uses));
246 // Now replace all uses.
247 bool Changed = false;
249 SmallPtrSet<MachineBasicBlock*, 4> PHIBBs;
251 // Look for PHI uses of the extended result, we don't want to extend the
252 // liveness of a PHI input. It breaks all kinds of assumptions down
253 // stream. A PHI use is expected to be the kill of its source values.
254 for (MachineRegisterInfo::use_nodbg_iterator
255 UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end();
258 PHIBBs.insert(UI->getParent());
260 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
261 for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
262 MachineOperand *UseMO = Uses[i];
263 MachineInstr *UseMI = UseMO->getParent();
264 MachineBasicBlock *UseMBB = UseMI->getParent();
265 if (PHIBBs.count(UseMBB))
268 // About to add uses of DstReg, clear DstReg's kill flags.
270 MRI->clearKillFlags(DstReg);
271 MRI->constrainRegClass(DstReg, DstRC);
274 unsigned NewVR = MRI->createVirtualRegister(RC);
275 MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
276 TII->get(TargetOpcode::COPY), NewVR)
277 .addReg(DstReg, 0, SubIdx);
278 // SubIdx applies to both SrcReg and DstReg when UseSrcSubIdx is set.
280 Copy->getOperand(0).setSubReg(SubIdx);
281 Copy->getOperand(0).setIsUndef();
283 UseMO->setReg(NewVR);
292 /// optimizeBitcastInstr - If the instruction is a bitcast instruction A that
293 /// cannot be optimized away during isel (e.g. ARM::VMOVSR, which bitcast
294 /// a value cross register classes), and the source is defined by another
295 /// bitcast instruction B. And if the register class of source of B matches
296 /// the register class of instruction A, then it is legal to replace all uses
297 /// of the def of A with source of B. e.g.
298 /// %vreg0<def> = VMOVSR %vreg1
299 /// %vreg3<def> = VMOVRS %vreg0
300 /// Replace all uses of vreg3 with vreg1.
302 bool PeepholeOptimizer::optimizeBitcastInstr(MachineInstr *MI,
303 MachineBasicBlock *MBB) {
304 unsigned NumDefs = MI->getDesc().getNumDefs();
305 unsigned NumSrcs = MI->getDesc().getNumOperands() - NumDefs;
311 for (unsigned i = 0, e = NumDefs + NumSrcs; i != e; ++i) {
312 const MachineOperand &MO = MI->getOperand(i);
315 unsigned Reg = MO.getReg();
327 assert(Def && Src && "Malformed bitcast instruction!");
329 MachineInstr *DefMI = MRI->getVRegDef(Src);
330 if (!DefMI || !DefMI->isBitcast())
334 NumDefs = DefMI->getDesc().getNumDefs();
335 NumSrcs = DefMI->getDesc().getNumOperands() - NumDefs;
338 for (unsigned i = 0, e = NumDefs + NumSrcs; i != e; ++i) {
339 const MachineOperand &MO = DefMI->getOperand(i);
340 if (!MO.isReg() || MO.isDef())
342 unsigned Reg = MO.getReg();
354 if (MRI->getRegClass(SrcSrc) != MRI->getRegClass(Def))
357 MRI->replaceRegWith(Def, SrcSrc);
358 MRI->clearKillFlags(SrcSrc);
359 MI->eraseFromParent();
364 /// optimizeCmpInstr - If the instruction is a compare and the previous
365 /// instruction it's comparing against all ready sets (or could be modified to
366 /// set) the same flag as the compare, then we can remove the comparison and use
367 /// the flag from the previous instruction.
368 bool PeepholeOptimizer::optimizeCmpInstr(MachineInstr *MI,
369 MachineBasicBlock *MBB) {
370 // If this instruction is a comparison against zero and isn't comparing a
371 // physical register, we can try to optimize it.
372 unsigned SrcReg, SrcReg2;
373 int CmpMask, CmpValue;
374 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
375 TargetRegisterInfo::isPhysicalRegister(SrcReg) ||
376 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2)))
379 // Attempt to optimize the comparison instruction.
380 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
388 bool PeepholeOptimizer::isMoveImmediate(MachineInstr *MI,
389 SmallSet<unsigned, 4> &ImmDefRegs,
390 DenseMap<unsigned, MachineInstr*> &ImmDefMIs) {
391 const MCInstrDesc &MCID = MI->getDesc();
392 if (!MI->isMoveImmediate())
394 if (MCID.getNumDefs() != 1)
396 unsigned Reg = MI->getOperand(0).getReg();
397 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
398 ImmDefMIs.insert(std::make_pair(Reg, MI));
399 ImmDefRegs.insert(Reg);
406 /// foldImmediate - Try folding register operands that are defined by move
407 /// immediate instructions, i.e. a trivial constant folding optimization, if
408 /// and only if the def and use are in the same BB.
409 bool PeepholeOptimizer::foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
410 SmallSet<unsigned, 4> &ImmDefRegs,
411 DenseMap<unsigned, MachineInstr*> &ImmDefMIs) {
412 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
413 MachineOperand &MO = MI->getOperand(i);
414 if (!MO.isReg() || MO.isDef())
416 unsigned Reg = MO.getReg();
417 if (!TargetRegisterInfo::isVirtualRegister(Reg))
419 if (ImmDefRegs.count(Reg) == 0)
421 DenseMap<unsigned, MachineInstr*>::iterator II = ImmDefMIs.find(Reg);
422 assert(II != ImmDefMIs.end());
423 if (TII->FoldImmediate(MI, II->second, Reg, MRI)) {
431 bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
435 TM = &MF.getTarget();
436 TII = TM->getInstrInfo();
437 MRI = &MF.getRegInfo();
438 DT = Aggressive ? &getAnalysis<MachineDominatorTree>() : 0;
440 bool Changed = false;
442 SmallPtrSet<MachineInstr*, 8> LocalMIs;
443 SmallSet<unsigned, 4> ImmDefRegs;
444 DenseMap<unsigned, MachineInstr*> ImmDefMIs;
445 SmallSet<unsigned, 4> FoldAsLoadDefRegs;
446 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
447 MachineBasicBlock *MBB = &*I;
449 bool SeenMoveImm = false;
453 FoldAsLoadDefRegs.clear();
456 MachineBasicBlock::iterator PMII;
457 for (MachineBasicBlock::iterator
458 MII = I->begin(), MIE = I->end(); MII != MIE; ) {
459 MachineInstr *MI = &*MII;
462 if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
463 MI->isKill() || MI->isInlineAsm() || MI->isDebugValue() ||
464 MI->hasUnmodeledSideEffects()) {
469 if (MI->isBitcast()) {
470 if (optimizeBitcastInstr(MI, MBB)) {
474 MII = First ? I->begin() : llvm::next(PMII);
477 } else if (MI->isCompare()) {
478 if (optimizeCmpInstr(MI, MBB)) {
482 MII = First ? I->begin() : llvm::next(PMII);
487 if (isMoveImmediate(MI, ImmDefRegs, ImmDefMIs)) {
490 Changed |= optimizeExtInstr(MI, MBB, LocalMIs);
492 Changed |= foldImmediate(MI, MBB, ImmDefRegs, ImmDefMIs);
495 MachineInstr *DefMI = 0;
496 MachineInstr *FoldMI = TII->optimizeLoadInstr(MI, MRI, FoldAsLoadDefRegs,
499 // Update LocalMIs since we replaced MI with FoldMI and deleted DefMI.
501 LocalMIs.erase(DefMI);
502 LocalMIs.insert(FoldMI);
503 MI->eraseFromParent();
504 DefMI->eraseFromParent();
507 // MI is replaced with FoldMI.
510 MII = llvm::next(PMII);