1 //===-- Passes.cpp - Target independent code generation passes ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code
11 // generation passes provided by the LLVM backend.
13 //===---------------------------------------------------------------------===//
15 #include "llvm/Analysis/Passes.h"
16 #include "llvm/Analysis/Verifier.h"
17 #include "llvm/Transforms/Scalar.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/CodeGen/GCStrategy.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/MC/MCAsmInfo.h"
26 #include "llvm/Assembly/PrintModulePass.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
33 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
34 cl::desc("Disable Post Regalloc"));
35 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
36 cl::desc("Disable branch folding"));
37 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
38 cl::desc("Disable tail duplication"));
39 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
40 cl::desc("Disable pre-register allocation tail duplication"));
41 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
42 cl::Hidden, cl::desc("Disable the probability-driven block placement, and "
43 "re-enable the old code placement pass"));
44 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
45 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
46 static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
47 cl::desc("Disable code placement"));
48 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
49 cl::desc("Disable Stack Slot Coloring"));
50 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
51 cl::desc("Disable Machine Dead Code Elimination"));
52 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
53 cl::desc("Disable Machine LICM"));
54 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
55 cl::desc("Disable Machine Common Subexpression Elimination"));
56 static cl::opt<cl::boolOrDefault>
57 OptimizeRegAlloc("optimize-regalloc", cl::Hidden,
58 cl::desc("Enable optimized register allocation compilation path."));
59 static cl::opt<cl::boolOrDefault>
60 EnableMachineSched("enable-misched", cl::Hidden,
61 cl::desc("Enable the machine instruction scheduling pass."));
62 static cl::opt<bool> EnableStrongPHIElim("strong-phi-elim", cl::Hidden,
63 cl::desc("Use strong PHI elimination."));
64 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
66 cl::desc("Disable Machine LICM"));
67 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
68 cl::desc("Disable Machine Sinking"));
69 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
70 cl::desc("Disable Loop Strength Reduction Pass"));
71 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
72 cl::desc("Disable Codegen Prepare"));
73 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
74 cl::desc("Disable Copy Propagation pass"));
75 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
76 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
77 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
78 cl::desc("Print LLVM IR input to isel pass"));
79 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
80 cl::desc("Dump garbage collector data"));
81 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
82 cl::desc("Verify generated machine code"),
83 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
84 static cl::opt<std::string>
85 PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
86 cl::desc("Print machine instrs"),
87 cl::value_desc("pass-name"), cl::init("option-unspecified"));
89 /// Allow standard passes to be disabled by command line options. This supports
90 /// simple binary flags that either suppress the pass or do nothing.
91 /// i.e. -disable-mypass=false has no effect.
92 /// These should be converted to boolOrDefault in order to use applyOverride.
93 static AnalysisID applyDisable(AnalysisID ID, bool Override) {
99 /// Allow Pass selection to be overriden by command line options. This supports
100 /// flags with ternary conditions. TargetID is passed through by default. The
101 /// pass is suppressed when the option is false. When the option is true, the
102 /// StandardID is selected if the target provides no default.
103 static AnalysisID applyOverride(AnalysisID TargetID, cl::boolOrDefault Override,
104 AnalysisID StandardID) {
109 if (TargetID != &NoPassID)
111 if (StandardID == &NoPassID)
112 report_fatal_error("Target cannot enable pass");
117 llvm_unreachable("Invalid command line option state");
120 /// Allow standard passes to be disabled by the command line, regardless of who
121 /// is adding the pass.
123 /// StandardID is the pass identified in the standard pass pipeline and provided
124 /// to addPass(). It may be a target-specific ID in the case that the target
125 /// directly adds its own pass, but in that case we harmlessly fall through.
127 /// TargetID is the pass that the target has configured to override StandardID.
129 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
130 /// pass to run. This allows multiple options to control a single pass depending
131 /// on where in the pipeline that pass is added.
132 static AnalysisID overridePass(AnalysisID StandardID, AnalysisID TargetID) {
133 if (StandardID == &PostRASchedulerID)
134 return applyDisable(TargetID, DisablePostRA);
136 if (StandardID == &BranchFolderPassID)
137 return applyDisable(TargetID, DisableBranchFold);
139 if (StandardID == &TailDuplicateID)
140 return applyDisable(TargetID, DisableTailDuplicate);
142 if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
143 return applyDisable(TargetID, DisableEarlyTailDup);
145 if (StandardID == &MachineBlockPlacementID)
146 return applyDisable(TargetID, DisableCodePlace);
148 if (StandardID == &CodePlacementOptID)
149 return applyDisable(TargetID, DisableCodePlace);
151 if (StandardID == &StackSlotColoringID)
152 return applyDisable(TargetID, DisableSSC);
154 if (StandardID == &DeadMachineInstructionElimID)
155 return applyDisable(TargetID, DisableMachineDCE);
157 if (StandardID == &MachineLICMID)
158 return applyDisable(TargetID, DisableMachineLICM);
160 if (StandardID == &MachineCSEID)
161 return applyDisable(TargetID, DisableMachineCSE);
163 if (StandardID == &MachineSchedulerID)
164 return applyOverride(TargetID, EnableMachineSched, StandardID);
166 if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
167 return applyDisable(TargetID, DisablePostRAMachineLICM);
169 if (StandardID == &MachineSinkingID)
170 return applyDisable(TargetID, DisableMachineSink);
172 if (StandardID == &MachineCopyPropagationID)
173 return applyDisable(TargetID, DisableCopyProp);
178 //===---------------------------------------------------------------------===//
180 //===---------------------------------------------------------------------===//
182 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
183 "Target Pass Configuration", false, false)
184 char TargetPassConfig::ID = 0;
186 static char NoPassIDAnchor = 0;
187 char &llvm::NoPassID = NoPassIDAnchor;
190 char TargetPassConfig::EarlyTailDuplicateID = 0;
191 char TargetPassConfig::PostRAMachineLICMID = 0;
194 class PassConfigImpl {
196 // List of passes explicitly substituted by this target. Normally this is
197 // empty, but it is a convenient way to suppress or replace specific passes
198 // that are part of a standard pass pipeline without overridding the entire
199 // pipeline. This mechanism allows target options to inherit a standard pass's
200 // user interface. For example, a target may disable a standard pass by
201 // default by substituting NoPass, and the user may still enable that standard
202 // pass with an explicit command line option.
203 DenseMap<AnalysisID,AnalysisID> TargetPasses;
205 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
206 /// is inserted after each instance of the first one.
207 SmallVector<std::pair<AnalysisID, AnalysisID>, 4> InsertedPasses;
211 // Out of line virtual method.
212 TargetPassConfig::~TargetPassConfig() {
216 // Out of line constructor provides default values for pass options and
217 // registers all common codegen passes.
218 TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
219 : ImmutablePass(ID), PM(&pm), TM(tm), Impl(0), Initialized(false),
220 DisableVerify(false),
221 EnableTailMerge(true) {
223 Impl = new PassConfigImpl();
225 // Register all target independent codegen passes to activate their PassIDs,
226 // including this pass itself.
227 initializeCodeGen(*PassRegistry::getPassRegistry());
229 // Substitute Pseudo Pass IDs for real ones.
230 substitutePass(EarlyTailDuplicateID, TailDuplicateID);
231 substitutePass(PostRAMachineLICMID, MachineLICMID);
233 // Temporarily disable experimental passes.
234 substitutePass(MachineSchedulerID, NoPassID);
237 /// Insert InsertedPassID pass after TargetPassID.
238 void TargetPassConfig::insertPass(const char &TargetPassID,
239 const char &InsertedPassID) {
240 assert(&TargetPassID != &InsertedPassID && "Insert a pass after itself!");
241 std::pair<AnalysisID, AnalysisID> P(&TargetPassID, &InsertedPassID);
242 Impl->InsertedPasses.push_back(P);
245 /// createPassConfig - Create a pass configuration object to be used by
246 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
248 /// Targets may override this to extend TargetPassConfig.
249 TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
250 return new TargetPassConfig(this, PM);
253 TargetPassConfig::TargetPassConfig()
254 : ImmutablePass(ID), PM(0) {
255 llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
258 // Helper to verify the analysis is really immutable.
259 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
260 assert(!Initialized && "PassConfig is immutable");
264 void TargetPassConfig::substitutePass(char &StandardID, char &TargetID) {
265 Impl->TargetPasses[&StandardID] = &TargetID;
268 AnalysisID TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
269 DenseMap<AnalysisID, AnalysisID>::const_iterator
270 I = Impl->TargetPasses.find(ID);
271 if (I == Impl->TargetPasses.end())
276 /// Add a pass to the PassManager.
277 void TargetPassConfig::addPass(Pass *P) {
281 /// Add a CodeGen pass at this point in the pipeline after checking for target
282 /// and command line overrides.
283 AnalysisID TargetPassConfig::addPass(char &ID) {
284 assert(!Initialized && "PassConfig is immutable");
286 AnalysisID TargetID = getPassSubstitution(&ID);
287 AnalysisID FinalID = overridePass(&ID, TargetID);
288 if (FinalID == &NoPassID)
291 Pass *P = Pass::createPass(FinalID);
293 llvm_unreachable("Pass ID not registered");
295 // Add the passes after the pass P if there is any.
296 for (SmallVector<std::pair<AnalysisID, AnalysisID>, 4>::iterator
297 I = Impl->InsertedPasses.begin(), E = Impl->InsertedPasses.end();
299 if ((*I).first == &ID) {
300 assert((*I).second && "Illegal Pass ID!");
301 Pass *NP = Pass::createPass((*I).second);
302 assert(NP && "Pass ID not registered");
309 void TargetPassConfig::printAndVerify(const char *Banner) {
310 if (TM->shouldPrintMachineCode())
311 addPass(createMachineFunctionPrinterPass(dbgs(), Banner));
313 if (VerifyMachineCode)
314 addPass(createMachineVerifierPass(Banner));
317 /// Add common target configurable passes that perform LLVM IR to IR transforms
318 /// following machine independent optimization.
319 void TargetPassConfig::addIRPasses() {
320 // Basic AliasAnalysis support.
321 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
322 // BasicAliasAnalysis wins if they disagree. This is intended to help
323 // support "obvious" type-punning idioms.
324 addPass(createTypeBasedAliasAnalysisPass());
325 addPass(createBasicAliasAnalysisPass());
327 // Before running any passes, run the verifier to determine if the input
328 // coming from the front-end and/or optimizer is valid.
330 addPass(createVerifierPass());
332 // Run loop strength reduction before anything else.
333 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
334 addPass(createLoopStrengthReducePass(getTargetLowering()));
336 addPass(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
339 addPass(createGCLoweringPass());
341 // Make sure that no unreachable blocks are instruction selected.
342 addPass(createUnreachableBlockEliminationPass());
345 /// Turn exception handling constructs into something the code generators can
347 void TargetPassConfig::addPassesToHandleExceptions() {
348 switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
349 case ExceptionHandling::SjLj:
350 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
351 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
352 // catch info can get misplaced when a selector ends up more than one block
353 // removed from the parent invoke(s). This could happen when a landing
354 // pad is shared by multiple invokes and is also a target of a normal
355 // edge from elsewhere.
356 addPass(createSjLjEHPreparePass(TM->getTargetLowering()));
358 case ExceptionHandling::DwarfCFI:
359 case ExceptionHandling::ARM:
360 case ExceptionHandling::Win64:
361 addPass(createDwarfEHPass(TM));
363 case ExceptionHandling::None:
364 addPass(createLowerInvokePass(TM->getTargetLowering()));
366 // The lower invoke pass may create unreachable code. Remove it.
367 addPass(createUnreachableBlockEliminationPass());
372 /// Add common passes that perform LLVM IR to IR transforms in preparation for
373 /// instruction selection.
374 void TargetPassConfig::addISelPrepare() {
375 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
376 addPass(createCodeGenPreparePass(getTargetLowering()));
378 addPass(createStackProtectorPass(getTargetLowering()));
383 addPass(createPrintFunctionPass("\n\n"
384 "*** Final LLVM Code input to ISel ***\n",
387 // All passes which modify the LLVM IR are now complete; run the verifier
388 // to ensure that the IR is valid.
390 addPass(createVerifierPass());
393 /// Add the complete set of target-independent postISel code generator passes.
395 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
396 /// with nontrivial configuration or multiple passes are broken out below in
397 /// add%Stage routines.
399 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
400 /// addPre/Post methods with empty header implementations allow injecting
401 /// target-specific fixups just before or after major stages. Additionally,
402 /// targets have the flexibility to change pass order within a stage by
403 /// overriding default implementation of add%Stage routines below. Each
404 /// technique has maintainability tradeoffs because alternate pass orders are
405 /// not well supported. addPre/Post works better if the target pass is easily
406 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
407 /// the target should override the stage instead.
409 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
410 /// before/after any target-independent pass. But it's currently overkill.
411 void TargetPassConfig::addMachinePasses() {
412 // Print the instruction selected machine code...
413 printAndVerify("After Instruction Selection");
415 // Insert a machine instr printer pass after the specified pass.
416 // If -print-machineinstrs specified, print machineinstrs after all passes.
417 if (StringRef(PrintMachineInstrs.getValue()).equals(""))
418 TM->Options.PrintMachineCode = true;
419 else if (!StringRef(PrintMachineInstrs.getValue())
420 .equals("option-unspecified")) {
421 const PassRegistry *PR = PassRegistry::getPassRegistry();
422 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
423 const PassInfo *IPI = PR->getPassInfo(StringRef("print-machineinstrs"));
424 assert (TPI && IPI && "Pass ID not registered!");
425 const char *TID = (char *)(TPI->getTypeInfo());
426 const char *IID = (char *)(IPI->getTypeInfo());
427 insertPass(*TID, *IID);
430 // Expand pseudo-instructions emitted by ISel.
431 addPass(ExpandISelPseudosID);
433 // Add passes that optimize machine instructions in SSA form.
434 if (getOptLevel() != CodeGenOpt::None) {
435 addMachineSSAOptimization();
438 // If the target requests it, assign local variables to stack slots relative
439 // to one another and simplify frame index references where possible.
440 addPass(LocalStackSlotAllocationID);
443 // Run pre-ra passes.
444 if (addPreRegAlloc())
445 printAndVerify("After PreRegAlloc passes");
447 // Run register allocation and passes that are tightly coupled with it,
448 // including phi elimination and scheduling.
449 if (getOptimizeRegAlloc())
450 addOptimizedRegAlloc(createRegAllocPass(true));
452 addFastRegAlloc(createRegAllocPass(false));
454 // Run post-ra passes.
455 if (addPostRegAlloc())
456 printAndVerify("After PostRegAlloc passes");
458 // Insert prolog/epilog code. Eliminate abstract frame index references...
459 addPass(PrologEpilogCodeInserterID);
460 printAndVerify("After PrologEpilogCodeInserter");
462 /// Add passes that optimize machine instructions after register allocation.
463 if (getOptLevel() != CodeGenOpt::None)
464 addMachineLateOptimization();
466 // Expand pseudo instructions before second scheduling pass.
467 addPass(ExpandPostRAPseudosID);
468 printAndVerify("After ExpandPostRAPseudos");
470 // Run pre-sched2 passes.
472 printAndVerify("After PreSched2 passes");
474 // Second pass scheduler.
475 if (getOptLevel() != CodeGenOpt::None) {
476 addPass(PostRASchedulerID);
477 printAndVerify("After PostRAScheduler");
481 addPass(GCMachineCodeAnalysisID);
483 addPass(createGCInfoPrinter(dbgs()));
485 // Basic block placement.
486 if (getOptLevel() != CodeGenOpt::None)
489 if (addPreEmitPass())
490 printAndVerify("After PreEmit passes");
493 /// Add passes that optimize machine instructions in SSA form.
494 void TargetPassConfig::addMachineSSAOptimization() {
495 // Pre-ra tail duplication.
496 if (addPass(EarlyTailDuplicateID) != &NoPassID)
497 printAndVerify("After Pre-RegAlloc TailDuplicate");
499 // Optimize PHIs before DCE: removing dead PHI cycles may make more
500 // instructions dead.
501 addPass(OptimizePHIsID);
503 // If the target requests it, assign local variables to stack slots relative
504 // to one another and simplify frame index references where possible.
505 addPass(LocalStackSlotAllocationID);
507 // With optimization, dead code should already be eliminated. However
508 // there is one known exception: lowered code for arguments that are only
509 // used by tail calls, where the tail calls reuse the incoming stack
510 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
511 addPass(DeadMachineInstructionElimID);
512 printAndVerify("After codegen DCE pass");
514 addPass(MachineLICMID);
515 addPass(MachineCSEID);
516 addPass(MachineSinkingID);
517 printAndVerify("After Machine LICM, CSE and Sinking passes");
519 addPass(PeepholeOptimizerID);
520 printAndVerify("After codegen peephole optimization pass");
523 //===---------------------------------------------------------------------===//
524 /// Register Allocation Pass Configuration
525 //===---------------------------------------------------------------------===//
527 bool TargetPassConfig::getOptimizeRegAlloc() const {
528 switch (OptimizeRegAlloc) {
529 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
530 case cl::BOU_TRUE: return true;
531 case cl::BOU_FALSE: return false;
533 llvm_unreachable("Invalid optimize-regalloc state");
536 /// RegisterRegAlloc's global Registry tracks allocator registration.
537 MachinePassRegistry RegisterRegAlloc::Registry;
539 /// A dummy default pass factory indicates whether the register allocator is
540 /// overridden on the command line.
541 static FunctionPass *useDefaultRegisterAllocator() { return 0; }
542 static RegisterRegAlloc
543 defaultRegAlloc("default",
544 "pick register allocator based on -O option",
545 useDefaultRegisterAllocator);
547 /// -regalloc=... command line option.
548 static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
549 RegisterPassParser<RegisterRegAlloc> >
551 cl::init(&useDefaultRegisterAllocator),
552 cl::desc("Register allocator to use"));
555 /// Instantiate the default register allocator pass for this target for either
556 /// the optimized or unoptimized allocation path. This will be added to the pass
557 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
558 /// in the optimized case.
560 /// A target that uses the standard regalloc pass order for fast or optimized
561 /// allocation may still override this for per-target regalloc
562 /// selection. But -regalloc=... always takes precedence.
563 FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
565 return createGreedyRegisterAllocator();
567 return createFastRegisterAllocator();
570 /// Find and instantiate the register allocation pass requested by this target
571 /// at the current optimization level. Different register allocators are
572 /// defined as separate passes because they may require different analysis.
574 /// This helper ensures that the regalloc= option is always available,
575 /// even for targets that override the default allocator.
577 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
578 /// this can be folded into addPass.
579 FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
580 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
582 // Initialize the global default.
585 RegisterRegAlloc::setDefault(RegAlloc);
587 if (Ctor != useDefaultRegisterAllocator)
590 // With no -regalloc= override, ask the target for a regalloc pass.
591 return createTargetRegisterAllocator(Optimized);
594 /// Add the minimum set of target-independent passes that are required for
595 /// register allocation. No coalescing or scheduling.
596 void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
597 addPass(PHIEliminationID);
598 addPass(TwoAddressInstructionPassID);
600 addPass(RegAllocPass);
601 printAndVerify("After Register Allocation");
604 /// Add standard target-independent passes that are tightly coupled with
605 /// optimized register allocation, including coalescing, machine instruction
606 /// scheduling, and register allocation itself.
607 void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
608 addPass(ProcessImplicitDefsID);
610 // LiveVariables currently requires pure SSA form.
612 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
613 // LiveVariables can be removed completely, and LiveIntervals can be directly
614 // computed. (We still either need to regenerate kill flags after regalloc, or
615 // preferably fix the scavenger to not depend on them).
616 addPass(LiveVariablesID);
618 // Add passes that move from transformed SSA into conventional SSA. This is a
619 // "copy coalescing" problem.
621 if (!EnableStrongPHIElim) {
622 // Edge splitting is smarter with machine loop info.
623 addPass(MachineLoopInfoID);
624 addPass(PHIEliminationID);
626 addPass(TwoAddressInstructionPassID);
628 if (EnableStrongPHIElim)
629 addPass(StrongPHIEliminationID);
631 addPass(RegisterCoalescerID);
633 // PreRA instruction scheduling.
634 if (addPass(MachineSchedulerID) != &NoPassID)
635 printAndVerify("After Machine Scheduling");
637 // Add the selected register allocation pass.
638 addPass(RegAllocPass);
639 printAndVerify("After Register Allocation, before rewriter");
641 // Allow targets to change the register assignments before rewriting.
643 printAndVerify("After pre-rewrite passes");
645 // Finally rewrite virtual registers.
646 addPass(VirtRegRewriterID);
647 printAndVerify("After Virtual Register Rewriter");
649 // FinalizeRegAlloc is convenient until MachineInstrBundles is more mature,
650 // but eventually, all users of it should probably be moved to addPostRA and
651 // it can go away. Currently, it's the intended place for targets to run
652 // FinalizeMachineBundles, because passes other than MachineScheduling an
653 // RegAlloc itself may not be aware of bundles.
654 if (addFinalizeRegAlloc())
655 printAndVerify("After RegAlloc finalization");
657 // Perform stack slot coloring and post-ra machine LICM.
659 // FIXME: Re-enable coloring with register when it's capable of adding
661 addPass(StackSlotColoringID);
663 // Run post-ra machine LICM to hoist reloads / remats.
665 // FIXME: can this move into MachineLateOptimization?
666 addPass(PostRAMachineLICMID);
668 printAndVerify("After StackSlotColoring and postra Machine LICM");
671 //===---------------------------------------------------------------------===//
672 /// Post RegAlloc Pass Configuration
673 //===---------------------------------------------------------------------===//
675 /// Add passes that optimize machine instructions after register allocation.
676 void TargetPassConfig::addMachineLateOptimization() {
677 // Branch folding must be run after regalloc and prolog/epilog insertion.
678 if (addPass(BranchFolderPassID) != &NoPassID)
679 printAndVerify("After BranchFolding");
682 if (addPass(TailDuplicateID) != &NoPassID)
683 printAndVerify("After TailDuplicate");
686 if (addPass(MachineCopyPropagationID) != &NoPassID)
687 printAndVerify("After copy propagation pass");
690 /// Add standard basic block placement passes.
691 void TargetPassConfig::addBlockPlacement() {
692 AnalysisID ID = &NoPassID;
693 if (!DisableBlockPlacement) {
694 // MachineBlockPlacement is a new pass which subsumes the functionality of
695 // CodPlacementOpt. The old code placement pass can be restored by
696 // disabling block placement, but eventually it will be removed.
697 ID = addPass(MachineBlockPlacementID);
699 ID = addPass(CodePlacementOptID);
701 if (ID != &NoPassID) {
702 // Run a separate pass to collect block placement statistics.
703 if (EnableBlockPlacementStats)
704 addPass(MachineBlockPlacementStatsID);
706 printAndVerify("After machine block placement.");