1 //===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass eliminates machine instruction PHI nodes by inserting copy
11 // instructions. This destroys SSA information, but is the desired input for
12 // some register allocators.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "phielim"
17 #include "PHIElimination.h"
18 #include "llvm/CodeGen/LiveVariables.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/MachineDominators.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Function.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/ADT/SmallPtrSet.h"
29 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
37 STATISTIC(NumAtomic, "Number of atomic phis lowered");
38 STATISTIC(NumReused, "Number of reused lowered phis");
40 char PHIElimination::ID = 0;
41 static RegisterPass<PHIElimination>
42 X("phi-node-elimination", "Eliminate PHI nodes for register allocation");
44 char &llvm::PHIEliminationID = PHIElimination::ID;
46 void llvm::PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
47 AU.addPreserved<LiveVariables>();
48 AU.addRequired<MachineLoopInfo>();
49 AU.addPreserved<MachineDominatorTree>();
50 AU.addPreservedID(MachineLoopInfoID);
51 MachineFunctionPass::getAnalysisUsage(AU);
54 bool llvm::PHIElimination::runOnMachineFunction(MachineFunction &MF) {
55 MRI = &MF.getRegInfo();
59 // Split critical edges to help the coalescer
60 if (LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>())
61 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
62 Changed |= SplitPHIEdges(MF, *I, *LV);
64 // Populate VRegPHIUseCount
67 // Eliminate PHI instructions by inserting copies into predecessor blocks.
68 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
69 Changed |= EliminatePHINodes(MF, *I);
71 // Remove dead IMPLICIT_DEF instructions.
72 for (SmallPtrSet<MachineInstr*, 4>::iterator I = ImpDefs.begin(),
73 E = ImpDefs.end(); I != E; ++I) {
74 MachineInstr *DefMI = *I;
75 unsigned DefReg = DefMI->getOperand(0).getReg();
76 if (MRI->use_nodbg_empty(DefReg))
77 DefMI->eraseFromParent();
80 // Clean up the lowered PHI instructions.
81 for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end();
83 MF.DeleteMachineInstr(I->first);
87 VRegPHIUseCount.clear();
92 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
93 /// predecessor basic blocks.
95 bool llvm::PHIElimination::EliminatePHINodes(MachineFunction &MF,
96 MachineBasicBlock &MBB) {
97 if (MBB.empty() || !MBB.front().isPHI())
98 return false; // Quick exit for basic blocks without PHIs.
100 // Get an iterator to the first instruction after the last PHI node (this may
101 // also be the end of the basic block).
102 MachineBasicBlock::iterator AfterPHIsIt = SkipPHIsAndLabels(MBB, MBB.begin());
104 while (MBB.front().isPHI())
105 LowerAtomicPHINode(MBB, AfterPHIsIt);
110 /// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
111 /// are implicit_def's.
112 static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
113 const MachineRegisterInfo *MRI) {
114 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
115 unsigned SrcReg = MPhi->getOperand(i).getReg();
116 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
117 if (!DefMI || !DefMI->isImplicitDef())
123 // FindCopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg
124 // when following the CFG edge to SuccMBB. This needs to be after any def of
125 // SrcReg, but before any subsequent point where control flow might jump out of
127 MachineBasicBlock::iterator
128 llvm::PHIElimination::FindCopyInsertPoint(MachineBasicBlock &MBB,
129 MachineBasicBlock &SuccMBB,
131 // Handle the trivial case trivially.
135 // Usually, we just want to insert the copy before the first terminator
136 // instruction. However, for the edge going to a landing pad, we must insert
137 // the copy before the call/invoke instruction.
138 if (!SuccMBB.isLandingPad())
139 return MBB.getFirstTerminator();
141 // Discover any defs/uses in this basic block.
142 SmallPtrSet<MachineInstr*, 8> DefUsesInMBB;
143 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
144 RE = MRI->reg_end(); RI != RE; ++RI) {
145 MachineInstr *DefUseMI = &*RI;
146 if (DefUseMI->getParent() == &MBB)
147 DefUsesInMBB.insert(DefUseMI);
150 MachineBasicBlock::iterator InsertPoint;
151 if (DefUsesInMBB.empty()) {
152 // No defs. Insert the copy at the start of the basic block.
153 InsertPoint = MBB.begin();
154 } else if (DefUsesInMBB.size() == 1) {
155 // Insert the copy immediately after the def/use.
156 InsertPoint = *DefUsesInMBB.begin();
159 // Insert the copy immediately after the last def/use.
160 InsertPoint = MBB.end();
161 while (!DefUsesInMBB.count(&*--InsertPoint)) {}
165 // Make sure the copy goes after any phi nodes however.
166 return SkipPHIsAndLabels(MBB, InsertPoint);
169 /// LowerAtomicPHINode - Lower the PHI node at the top of the specified block,
170 /// under the assuption that it needs to be lowered in a way that supports
171 /// atomic execution of PHIs. This lowering method is always correct all of the
174 void llvm::PHIElimination::LowerAtomicPHINode(
175 MachineBasicBlock &MBB,
176 MachineBasicBlock::iterator AfterPHIsIt) {
178 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
179 MachineInstr *MPhi = MBB.remove(MBB.begin());
181 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
182 unsigned DestReg = MPhi->getOperand(0).getReg();
183 bool isDead = MPhi->getOperand(0).isDead();
185 // Create a new register for the incoming PHI arguments.
186 MachineFunction &MF = *MBB.getParent();
187 unsigned IncomingReg = 0;
188 bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
190 // Insert a register to register copy at the top of the current block (but
191 // after any remaining phi nodes) which copies the new incoming register
192 // into the phi node destination.
193 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
194 if (isSourceDefinedByImplicitDef(MPhi, MRI))
195 // If all sources of a PHI node are implicit_def, just emit an
196 // implicit_def instead of a copy.
197 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
198 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
200 // Can we reuse an earlier PHI node? This only happens for critical edges,
201 // typically those created by tail duplication.
202 unsigned &entry = LoweredPHIs[MPhi];
204 // An identical PHI node was already lowered. Reuse the incoming register.
206 reusedIncoming = true;
208 DEBUG(dbgs() << "Reusing %reg" << IncomingReg << " for " << *MPhi);
210 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
211 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
213 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
214 TII->get(TargetOpcode::COPY), DestReg)
215 .addReg(IncomingReg);
218 // Update live variable information if there is any.
219 LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>();
221 MachineInstr *PHICopy = prior(AfterPHIsIt);
224 LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
226 // Increment use count of the newly created virtual register.
228 LV->setPHIJoin(IncomingReg);
230 // When we are reusing the incoming register, it may already have been
231 // killed in this block. The old kill will also have been inserted at
232 // AfterPHIsIt, so it appears before the current PHICopy.
234 if (MachineInstr *OldKill = VI.findKill(&MBB)) {
235 DEBUG(dbgs() << "Remove old kill from " << *OldKill);
236 LV->removeVirtualRegisterKilled(IncomingReg, OldKill);
240 // Add information to LiveVariables to know that the incoming value is
241 // killed. Note that because the value is defined in several places (once
242 // each for each incoming block), the "def" block and instruction fields
243 // for the VarInfo is not filled in.
244 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
247 // Since we are going to be deleting the PHI node, if it is the last use of
248 // any registers, or if the value itself is dead, we need to move this
249 // information over to the new copy we just inserted.
250 LV->removeVirtualRegistersKilled(MPhi);
252 // If the result is dead, update LV.
254 LV->addVirtualRegisterDead(DestReg, PHICopy);
255 LV->removeVirtualRegisterDead(DestReg, MPhi);
259 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
260 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
261 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
262 MPhi->getOperand(i).getReg())];
264 // Now loop over all of the incoming arguments, changing them to copy into the
265 // IncomingReg register in the corresponding predecessor basic block.
266 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
267 for (int i = NumSrcs - 1; i >= 0; --i) {
268 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
269 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
270 "Machine PHI Operands must all be virtual registers!");
272 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
274 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
276 // If source is defined by an implicit def, there is no need to insert a
278 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
279 if (DefMI->isImplicitDef()) {
280 ImpDefs.insert(DefMI);
284 // Check to make sure we haven't already emitted the copy for this block.
285 // This can happen because PHI nodes may have multiple entries for the same
287 if (!MBBsInsertedInto.insert(&opBlock))
288 continue; // If the copy has already been emitted, we're done.
290 // Find a safe location to insert the copy, this may be the first terminator
291 // in the block (or end()).
292 MachineBasicBlock::iterator InsertPos =
293 FindCopyInsertPoint(opBlock, MBB, SrcReg);
296 if (!reusedIncoming && IncomingReg)
297 BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
298 TII->get(TargetOpcode::COPY), IncomingReg).addReg(SrcReg);
300 // Now update live variable information if we have it. Otherwise we're done
303 // We want to be able to insert a kill of the register if this PHI (aka, the
304 // copy we just inserted) is the last use of the source value. Live
305 // variable analysis conservatively handles this by saying that the value is
306 // live until the end of the block the PHI entry lives in. If the value
307 // really is dead at the PHI copy, there will be no successor blocks which
308 // have the value live-in.
310 // Also check to see if this register is in use by another PHI node which
311 // has not yet been eliminated. If so, it will be killed at an appropriate
314 // Is it used by any PHI instructions in this block?
315 bool ValueIsUsed = VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)];
317 // Okay, if we now know that the value is not live out of the block, we can
318 // add a kill marker in this block saying that it kills the incoming value!
319 if (!ValueIsUsed && !LV->isLiveOut(SrcReg, opBlock)) {
320 // In our final twist, we have to decide which instruction kills the
321 // register. In most cases this is the copy, however, the first
322 // terminator instruction at the end of the block may also use the value.
323 // In this case, we should mark *it* as being the killing block, not the
325 MachineBasicBlock::iterator KillInst;
326 MachineBasicBlock::iterator Term = opBlock.getFirstTerminator();
327 if (Term != opBlock.end() && Term->readsRegister(SrcReg)) {
330 // Check that no other terminators use values.
332 for (MachineBasicBlock::iterator TI = llvm::next(Term);
333 TI != opBlock.end(); ++TI) {
334 assert(!TI->readsRegister(SrcReg) &&
335 "Terminator instructions cannot use virtual registers unless"
336 "they are the first terminator in a block!");
339 } else if (reusedIncoming || !IncomingReg) {
340 // We may have to rewind a bit if we didn't insert a copy this time.
342 while (KillInst != opBlock.begin())
343 if ((--KillInst)->readsRegister(SrcReg))
346 // We just inserted this copy.
347 KillInst = prior(InsertPos);
349 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
351 // Finally, mark it killed.
352 LV->addVirtualRegisterKilled(SrcReg, KillInst);
354 // This vreg no longer lives all of the way through opBlock.
355 unsigned opBlockNum = opBlock.getNumber();
356 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
360 // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
361 if (reusedIncoming || !IncomingReg)
362 MF.DeleteMachineInstr(MPhi);
365 /// analyzePHINodes - Gather information about the PHI nodes in here. In
366 /// particular, we want to map the number of uses of a virtual register which is
367 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
368 /// used later to determine when the vreg is killed in the BB.
370 void llvm::PHIElimination::analyzePHINodes(const MachineFunction& MF) {
371 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
373 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
374 BBI != BBE && BBI->isPHI(); ++BBI)
375 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
376 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i+1).getMBB()->getNumber(),
377 BBI->getOperand(i).getReg())];
380 bool llvm::PHIElimination::SplitPHIEdges(MachineFunction &MF,
381 MachineBasicBlock &MBB,
383 if (MBB.empty() || !MBB.front().isPHI() || MBB.isLandingPad())
384 return false; // Quick exit for basic blocks without PHIs.
386 bool Changed = false;
387 for (MachineBasicBlock::const_iterator BBI = MBB.begin(), BBE = MBB.end();
388 BBI != BBE && BBI->isPHI(); ++BBI) {
389 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
390 unsigned Reg = BBI->getOperand(i).getReg();
391 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
392 // We break edges when registers are live out from the predecessor block
393 // (not considering PHI nodes). If the register is live in to this block
394 // anyway, we would gain nothing from splitting.
395 if (!LV.isLiveIn(Reg, MBB) && LV.isLiveOut(Reg, *PreMBB))
396 Changed |= PreMBB->SplitCriticalEdge(&MBB, this) != 0;