1 //===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass eliminates machine instruction PHI nodes by inserting copy
11 // instructions. This destroys SSA information, but is the desired input for
12 // some register allocators.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "phielim"
17 #include "llvm/CodeGen/Passes.h"
18 #include "PHIEliminationUtils.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetMachine.h"
39 DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false),
40 cl::Hidden, cl::desc("Disable critical edge splitting "
41 "during PHI elimination"));
44 SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(false),
45 cl::Hidden, cl::desc("Split all critical edges during "
49 class PHIElimination : public MachineFunctionPass {
50 MachineRegisterInfo *MRI; // Machine register information
55 static char ID; // Pass identification, replacement for typeid
56 PHIElimination() : MachineFunctionPass(ID) {
57 initializePHIEliminationPass(*PassRegistry::getPassRegistry());
60 virtual bool runOnMachineFunction(MachineFunction &Fn);
61 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
64 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
65 /// in predecessor basic blocks.
67 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
68 void LowerPHINode(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator AfterPHIsIt);
71 /// analyzePHINodes - Gather information about the PHI nodes in
72 /// here. In particular, we want to map the number of uses of a virtual
73 /// register which is used in a PHI node. We map that to the BB the
74 /// vreg is coming from. This is used later to determine when the vreg
75 /// is killed in the BB.
77 void analyzePHINodes(const MachineFunction& Fn);
79 /// Split critical edges where necessary for good coalescer performance.
80 bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
81 MachineLoopInfo *MLI);
83 // These functions are temporary abstractions around LiveVariables and
84 // LiveIntervals, so they can go away when LiveVariables does.
85 bool isLiveIn(unsigned Reg, MachineBasicBlock *MBB);
86 bool isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB);
88 typedef std::pair<unsigned, unsigned> BBVRegPair;
89 typedef DenseMap<BBVRegPair, unsigned> VRegPHIUse;
91 VRegPHIUse VRegPHIUseCount;
93 // Defs of PHI sources which are implicit_def.
94 SmallPtrSet<MachineInstr*, 4> ImpDefs;
96 // Map reusable lowered PHI node -> incoming join register.
97 typedef DenseMap<MachineInstr*, unsigned,
98 MachineInstrExpressionTrait> LoweredPHIMap;
99 LoweredPHIMap LoweredPHIs;
103 STATISTIC(NumLowered, "Number of phis lowered");
104 STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
105 STATISTIC(NumReused, "Number of reused lowered phis");
107 char PHIElimination::ID = 0;
108 char& llvm::PHIEliminationID = PHIElimination::ID;
110 INITIALIZE_PASS_BEGIN(PHIElimination, "phi-node-elimination",
111 "Eliminate PHI nodes for register allocation",
113 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
114 INITIALIZE_PASS_END(PHIElimination, "phi-node-elimination",
115 "Eliminate PHI nodes for register allocation", false, false)
117 void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
118 AU.addPreserved<LiveVariables>();
119 AU.addPreserved<SlotIndexes>();
120 AU.addPreserved<LiveIntervals>();
121 AU.addPreserved<MachineDominatorTree>();
122 AU.addPreserved<MachineLoopInfo>();
123 MachineFunctionPass::getAnalysisUsage(AU);
126 bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
127 MRI = &MF.getRegInfo();
128 LV = getAnalysisIfAvailable<LiveVariables>();
129 LIS = getAnalysisIfAvailable<LiveIntervals>();
131 bool Changed = false;
133 // This pass takes the function out of SSA form.
136 // Split critical edges to help the coalescer. This does not yet support
137 // updating LiveIntervals, so we disable it.
138 if (!DisableEdgeSplitting && (LV || LIS)) {
139 MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>();
140 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
141 Changed |= SplitPHIEdges(MF, *I, MLI);
144 // Populate VRegPHIUseCount
147 // Eliminate PHI instructions by inserting copies into predecessor blocks.
148 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
149 Changed |= EliminatePHINodes(MF, *I);
151 // Remove dead IMPLICIT_DEF instructions.
152 for (SmallPtrSet<MachineInstr*, 4>::iterator I = ImpDefs.begin(),
153 E = ImpDefs.end(); I != E; ++I) {
154 MachineInstr *DefMI = *I;
155 unsigned DefReg = DefMI->getOperand(0).getReg();
156 if (MRI->use_nodbg_empty(DefReg)) {
158 LIS->RemoveMachineInstrFromMaps(DefMI);
159 DefMI->eraseFromParent();
163 // Clean up the lowered PHI instructions.
164 for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end();
167 LIS->RemoveMachineInstrFromMaps(I->first);
168 MF.DeleteMachineInstr(I->first);
173 VRegPHIUseCount.clear();
176 MF.verify(this, "After PHI elimination");
181 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
182 /// predecessor basic blocks.
184 bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
185 MachineBasicBlock &MBB) {
186 if (MBB.empty() || !MBB.front().isPHI())
187 return false; // Quick exit for basic blocks without PHIs.
189 // Get an iterator to the first instruction after the last PHI node (this may
190 // also be the end of the basic block).
191 MachineBasicBlock::iterator AfterPHIsIt = MBB.SkipPHIsAndLabels(MBB.begin());
193 while (MBB.front().isPHI())
194 LowerPHINode(MBB, AfterPHIsIt);
199 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
200 /// This includes registers with no defs.
201 static bool isImplicitlyDefined(unsigned VirtReg,
202 const MachineRegisterInfo *MRI) {
203 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(VirtReg),
204 DE = MRI->def_end(); DI != DE; ++DI)
205 if (!DI->isImplicitDef())
210 /// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
211 /// are implicit_def's.
212 static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
213 const MachineRegisterInfo *MRI) {
214 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
215 if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI))
221 /// LowerPHINode - Lower the PHI node at the top of the specified block,
223 void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
224 MachineBasicBlock::iterator AfterPHIsIt) {
226 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
227 MachineInstr *MPhi = MBB.remove(MBB.begin());
229 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
230 unsigned DestReg = MPhi->getOperand(0).getReg();
231 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
232 bool isDead = MPhi->getOperand(0).isDead();
234 // Create a new register for the incoming PHI arguments.
235 MachineFunction &MF = *MBB.getParent();
236 unsigned IncomingReg = 0;
237 bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
239 // Insert a register to register copy at the top of the current block (but
240 // after any remaining phi nodes) which copies the new incoming register
241 // into the phi node destination.
242 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
243 if (isSourceDefinedByImplicitDef(MPhi, MRI))
244 // If all sources of a PHI node are implicit_def, just emit an
245 // implicit_def instead of a copy.
246 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
247 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
249 // Can we reuse an earlier PHI node? This only happens for critical edges,
250 // typically those created by tail duplication.
251 unsigned &entry = LoweredPHIs[MPhi];
253 // An identical PHI node was already lowered. Reuse the incoming register.
255 reusedIncoming = true;
257 DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
259 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
260 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
262 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
263 TII->get(TargetOpcode::COPY), DestReg)
264 .addReg(IncomingReg);
267 // Update live variable information if there is any.
269 MachineInstr *PHICopy = prior(AfterPHIsIt);
272 LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
274 // Increment use count of the newly created virtual register.
275 LV->setPHIJoin(IncomingReg);
277 // When we are reusing the incoming register, it may already have been
278 // killed in this block. The old kill will also have been inserted at
279 // AfterPHIsIt, so it appears before the current PHICopy.
281 if (MachineInstr *OldKill = VI.findKill(&MBB)) {
282 DEBUG(dbgs() << "Remove old kill from " << *OldKill);
283 LV->removeVirtualRegisterKilled(IncomingReg, OldKill);
287 // Add information to LiveVariables to know that the incoming value is
288 // killed. Note that because the value is defined in several places (once
289 // each for each incoming block), the "def" block and instruction fields
290 // for the VarInfo is not filled in.
291 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
294 // Since we are going to be deleting the PHI node, if it is the last use of
295 // any registers, or if the value itself is dead, we need to move this
296 // information over to the new copy we just inserted.
297 LV->removeVirtualRegistersKilled(MPhi);
299 // If the result is dead, update LV.
301 LV->addVirtualRegisterDead(DestReg, PHICopy);
302 LV->removeVirtualRegisterDead(DestReg, MPhi);
306 // Update LiveIntervals for the new copy or implicit def.
308 MachineInstr *NewInstr = prior(AfterPHIsIt);
309 SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(NewInstr);
311 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
313 // Add the region from the beginning of MBB to the copy instruction to
314 // IncomingReg's live interval.
315 LiveInterval &IncomingLI = LIS->getOrCreateInterval(IncomingReg);
316 VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex);
318 IncomingVNI = IncomingLI.getNextValue(MBBStartIndex,
319 LIS->getVNInfoAllocator());
320 IncomingLI.addRange(LiveRange(MBBStartIndex,
321 DestCopyIndex.getRegSlot(),
325 LiveInterval &DestLI = LIS->getOrCreateInterval(DestReg);
326 if (NewInstr->getOperand(0).isDead()) {
327 // A dead PHI's live range begins and ends at the start of the MBB, but
328 // the lowered copy, which will still be dead, needs to begin and end at
329 // the copy instruction.
330 VNInfo *OrigDestVNI = DestLI.getVNInfoAt(MBBStartIndex);
331 assert(OrigDestVNI && "PHI destination should be live at block entry.");
332 DestLI.removeRange(MBBStartIndex, MBBStartIndex.getDeadSlot());
333 DestLI.createDeadDef(DestCopyIndex.getRegSlot(),
334 LIS->getVNInfoAllocator());
335 DestLI.removeValNo(OrigDestVNI);
337 // Otherwise, remove the region from the beginning of MBB to the copy
338 // instruction from DestReg's live interval.
339 DestLI.removeRange(MBBStartIndex, DestCopyIndex.getRegSlot());
340 VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
341 assert(DestVNI && "PHI destination should be live at its definition.");
342 DestVNI->def = DestCopyIndex.getRegSlot();
346 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
347 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
348 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
349 MPhi->getOperand(i).getReg())];
351 // Now loop over all of the incoming arguments, changing them to copy into the
352 // IncomingReg register in the corresponding predecessor basic block.
353 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
354 for (int i = NumSrcs - 1; i >= 0; --i) {
355 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
356 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
357 bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
358 isImplicitlyDefined(SrcReg, MRI);
359 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
360 "Machine PHI Operands must all be virtual registers!");
362 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
364 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
366 // Check to make sure we haven't already emitted the copy for this block.
367 // This can happen because PHI nodes may have multiple entries for the same
369 if (!MBBsInsertedInto.insert(&opBlock))
370 continue; // If the copy has already been emitted, we're done.
372 // Find a safe location to insert the copy, this may be the first terminator
373 // in the block (or end()).
374 MachineBasicBlock::iterator InsertPos =
375 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
378 MachineInstr *NewSrcInstr = 0;
379 if (!reusedIncoming && IncomingReg) {
381 // The source register is undefined, so there is no need for a real
382 // COPY, but we still need to ensure joint dominance by defs.
383 // Insert an IMPLICIT_DEF instruction.
384 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
385 TII->get(TargetOpcode::IMPLICIT_DEF),
388 // Clean up the old implicit-def, if there even was one.
389 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
390 if (DefMI->isImplicitDef())
391 ImpDefs.insert(DefMI);
393 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
394 TII->get(TargetOpcode::COPY), IncomingReg)
395 .addReg(SrcReg, 0, SrcSubReg);
399 // We only need to update the LiveVariables kill of SrcReg if this was the
400 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
401 // out of the predecessor. We can also ignore undef sources.
402 if (LV && !SrcUndef &&
403 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
404 !LV->isLiveOut(SrcReg, opBlock)) {
405 // We want to be able to insert a kill of the register if this PHI (aka,
406 // the copy we just inserted) is the last use of the source value. Live
407 // variable analysis conservatively handles this by saying that the value
408 // is live until the end of the block the PHI entry lives in. If the value
409 // really is dead at the PHI copy, there will be no successor blocks which
410 // have the value live-in.
412 // Okay, if we now know that the value is not live out of the block, we
413 // can add a kill marker in this block saying that it kills the incoming
416 // In our final twist, we have to decide which instruction kills the
417 // register. In most cases this is the copy, however, terminator
418 // instructions at the end of the block may also use the value. In this
419 // case, we should mark the last such terminator as being the killing
420 // block, not the copy.
421 MachineBasicBlock::iterator KillInst = opBlock.end();
422 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
423 for (MachineBasicBlock::iterator Term = FirstTerm;
424 Term != opBlock.end(); ++Term) {
425 if (Term->readsRegister(SrcReg))
429 if (KillInst == opBlock.end()) {
430 // No terminator uses the register.
432 if (reusedIncoming || !IncomingReg) {
433 // We may have to rewind a bit if we didn't insert a copy this time.
434 KillInst = FirstTerm;
435 while (KillInst != opBlock.begin()) {
437 if (KillInst->isDebugValue())
439 if (KillInst->readsRegister(SrcReg))
443 // We just inserted this copy.
444 KillInst = prior(InsertPos);
447 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
449 // Finally, mark it killed.
450 LV->addVirtualRegisterKilled(SrcReg, KillInst);
452 // This vreg no longer lives all of the way through opBlock.
453 unsigned opBlockNum = opBlock.getNumber();
454 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
459 LIS->InsertMachineInstrInMaps(NewSrcInstr);
460 LIS->addLiveRangeToEndOfBlock(IncomingReg, NewSrcInstr);
464 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) {
465 LiveInterval &SrcLI = LIS->getInterval(SrcReg);
467 bool isLiveOut = false;
468 for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
469 SE = opBlock.succ_end(); SI != SE; ++SI) {
470 SlotIndex startIdx = LIS->getMBBStartIdx(*SI);
471 VNInfo *VNI = SrcLI.getVNInfoAt(startIdx);
473 // Definitions by other PHIs are not truly live-in for our purposes.
474 if (VNI && VNI->def != startIdx) {
481 MachineBasicBlock::iterator KillInst = opBlock.end();
482 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
483 for (MachineBasicBlock::iterator Term = FirstTerm;
484 Term != opBlock.end(); ++Term) {
485 if (Term->readsRegister(SrcReg))
489 if (KillInst == opBlock.end()) {
490 // No terminator uses the register.
492 if (reusedIncoming || !IncomingReg) {
493 // We may have to rewind a bit if we didn't just insert a copy.
494 KillInst = FirstTerm;
495 while (KillInst != opBlock.begin()) {
497 if (KillInst->isDebugValue())
499 if (KillInst->readsRegister(SrcReg))
503 // We just inserted this copy.
504 KillInst = prior(InsertPos);
507 assert(KillInst->readsRegister(SrcReg) &&
508 "Cannot find kill instruction");
510 SlotIndex LastUseIndex = LIS->getInstructionIndex(KillInst);
511 SrcLI.removeRange(LastUseIndex.getRegSlot(),
512 LIS->getMBBEndIdx(&opBlock));
518 // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
519 if (reusedIncoming || !IncomingReg) {
521 LIS->RemoveMachineInstrFromMaps(MPhi);
522 MF.DeleteMachineInstr(MPhi);
526 /// analyzePHINodes - Gather information about the PHI nodes in here. In
527 /// particular, we want to map the number of uses of a virtual register which is
528 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
529 /// used later to determine when the vreg is killed in the BB.
531 void PHIElimination::analyzePHINodes(const MachineFunction& MF) {
532 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
534 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
535 BBI != BBE && BBI->isPHI(); ++BBI)
536 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
537 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i+1).getMBB()->getNumber(),
538 BBI->getOperand(i).getReg())];
541 bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
542 MachineBasicBlock &MBB,
543 MachineLoopInfo *MLI) {
544 if (MBB.empty() || !MBB.front().isPHI() || MBB.isLandingPad())
545 return false; // Quick exit for basic blocks without PHIs.
547 const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : 0;
548 bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader();
550 bool Changed = false;
551 for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
552 BBI != BBE && BBI->isPHI(); ++BBI) {
553 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
554 unsigned Reg = BBI->getOperand(i).getReg();
555 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
556 // Is there a critical edge from PreMBB to MBB?
557 if (PreMBB->succ_size() == 1)
560 // Avoid splitting backedges of loops. It would introduce small
561 // out-of-line blocks into the loop which is very bad for code placement.
562 if (PreMBB == &MBB && !SplitAllCriticalEdges)
564 const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : 0;
565 if (IsLoopHeader && PreLoop == CurLoop && !SplitAllCriticalEdges)
568 // LV doesn't consider a phi use live-out, so isLiveOut only returns true
569 // when the source register is live-out for some other reason than a phi
570 // use. That means the copy we will insert in PreMBB won't be a kill, and
571 // there is a risk it may not be coalesced away.
573 // If the copy would be a kill, there is no need to split the edge.
574 if (!isLiveOutPastPHIs(Reg, PreMBB) && !SplitAllCriticalEdges)
577 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
578 << PreMBB->getNumber() << " -> BB#" << MBB.getNumber()
581 // If Reg is not live-in to MBB, it means it must be live-in to some
582 // other PreMBB successor, and we can avoid the interference by splitting
585 // If Reg *is* live-in to MBB, the interference is inevitable and a copy
586 // is likely to be left after coalescing. If we are looking at a loop
587 // exiting edge, split it so we won't insert code in the loop, otherwise
589 bool ShouldSplit = !isLiveIn(Reg, &MBB) || SplitAllCriticalEdges;
591 // Check for a loop exiting edge.
592 if (!ShouldSplit && CurLoop != PreLoop) {
594 dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
595 if (PreLoop) dbgs() << "PreLoop: " << *PreLoop;
596 if (CurLoop) dbgs() << "CurLoop: " << *CurLoop;
598 // This edge could be entering a loop, exiting a loop, or it could be
599 // both: Jumping directly form one loop to the header of a sibling
601 // Split unless this edge is entering CurLoop from an outer loop.
602 ShouldSplit = PreLoop && !PreLoop->contains(CurLoop);
606 if (!PreMBB->SplitCriticalEdge(&MBB, this)) {
607 DEBUG(dbgs() << "Failed to split ciritcal edge.\n");
611 ++NumCriticalEdgesSplit;
617 bool PHIElimination::isLiveIn(unsigned Reg, MachineBasicBlock *MBB) {
618 assert((LV || LIS) &&
619 "isLiveIn() requires either LiveVariables or LiveIntervals");
621 return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB);
623 return LV->isLiveIn(Reg, *MBB);
626 bool PHIElimination::isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB) {
627 assert((LV || LIS) &&
628 "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
629 // LiveVariables considers uses in PHIs to be in the predecessor basic block,
630 // so that a register used only in a PHI is not live out of the block. In
631 // contrast, LiveIntervals considers uses in PHIs to be on the edge rather than
632 // in the predecessor basic block, so that a register used only in a PHI is live
635 const LiveInterval &LI = LIS->getInterval(Reg);
636 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
637 SE = MBB->succ_end(); SI != SE; ++SI) {
638 if (LI.liveAt(LIS->getMBBStartIdx(*SI)))
643 return LV->isLiveOut(Reg, *MBB);