1 //===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MachineScheduler schedules machine instructions after phi elimination. It
11 // preserves LiveIntervals so it can be invoked before register allocation.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "misched"
17 #include "ScheduleDAGInstrs.h"
18 #include "LiveDebugVariables.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/MachinePassRegistry.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/ADT/OwningPtr.h"
32 //===----------------------------------------------------------------------===//
33 // Machine Instruction Scheduling Pass and Registry
34 //===----------------------------------------------------------------------===//
37 /// MachineSchedulerPass runs after coalescing and before register allocation.
38 class MachineSchedulerPass : public MachineFunctionPass {
41 const TargetInstrInfo *TII;
42 const MachineLoopInfo *MLI;
43 const MachineDominatorTree *MDT;
45 MachineSchedulerPass();
47 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
49 virtual void releaseMemory() {}
51 virtual bool runOnMachineFunction(MachineFunction&);
53 virtual void print(raw_ostream &O, const Module* = 0) const;
55 static char ID; // Class identification, replacement for typeinfo
59 char MachineSchedulerPass::ID = 0;
61 char &llvm::MachineSchedulerPassID = MachineSchedulerPass::ID;
63 INITIALIZE_PASS_BEGIN(MachineSchedulerPass, "misched",
64 "Machine Instruction Scheduler", false, false)
65 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
66 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
67 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
68 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
69 INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
70 INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
71 INITIALIZE_PASS_END(MachineSchedulerPass, "misched",
72 "Machine Instruction Scheduler", false, false)
74 MachineSchedulerPass::MachineSchedulerPass()
75 : MachineFunctionPass(ID), MF(0), MLI(0), MDT(0) {
76 initializeMachineSchedulerPassPass(*PassRegistry::getPassRegistry());
79 void MachineSchedulerPass::getAnalysisUsage(AnalysisUsage &AU) const {
81 AU.addRequiredID(MachineDominatorsID);
82 AU.addRequired<MachineLoopInfo>();
83 AU.addRequired<AliasAnalysis>();
84 AU.addPreserved<AliasAnalysis>();
85 AU.addRequired<SlotIndexes>();
86 AU.addPreserved<SlotIndexes>();
87 AU.addRequired<LiveIntervals>();
88 AU.addPreserved<LiveIntervals>();
89 AU.addRequired<LiveDebugVariables>();
90 AU.addPreserved<LiveDebugVariables>();
92 AU.addRequiredID(StrongPHIEliminationID);
93 AU.addPreservedID(StrongPHIEliminationID);
95 AU.addRequiredID(RegisterCoalescerPassID);
96 AU.addPreservedID(RegisterCoalescerPassID);
97 MachineFunctionPass::getAnalysisUsage(AU);
101 /// MachineSchedRegistry provides a selection of available machine instruction
103 class MachineSchedRegistry : public MachinePassRegistryNode {
105 typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedulerPass *);
107 // RegisterPassParser requires a (misnamed) FunctionPassCtor type.
108 typedef ScheduleDAGCtor FunctionPassCtor;
110 static MachinePassRegistry Registry;
112 MachineSchedRegistry(const char *N, const char *D, ScheduleDAGCtor C)
113 : MachinePassRegistryNode(N, D, (MachinePassCtor)C) {
116 ~MachineSchedRegistry() { Registry.Remove(this); }
120 MachineSchedRegistry *getNext() const {
121 return (MachineSchedRegistry *)MachinePassRegistryNode::getNext();
123 static MachineSchedRegistry *getList() {
124 return (MachineSchedRegistry *)Registry.getList();
126 static ScheduleDAGCtor getDefault() {
127 return (ScheduleDAGCtor)Registry.getDefault();
129 static void setDefault(ScheduleDAGCtor C) {
130 Registry.setDefault((MachinePassCtor)C);
132 static void setListener(MachinePassRegistryListener *L) {
133 Registry.setListener(L);
138 MachinePassRegistry MachineSchedRegistry::Registry;
140 static ScheduleDAGInstrs *createDefaultMachineSched(MachineSchedulerPass *P);
142 /// MachineSchedOpt allows command line selection of the scheduler.
143 static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
144 RegisterPassParser<MachineSchedRegistry> >
145 MachineSchedOpt("misched",
146 cl::init(&createDefaultMachineSched), cl::Hidden,
147 cl::desc("Machine instruction scheduler to use"));
149 //===----------------------------------------------------------------------===//
150 // Machine Instruction Scheduling Implementation
151 //===----------------------------------------------------------------------===//
154 /// MachineScheduler is an implementation of ScheduleDAGInstrs that schedules
155 /// machine instructions while updating LiveIntervals.
156 class MachineScheduler : public ScheduleDAGInstrs {
157 MachineSchedulerPass *Pass;
159 MachineScheduler(MachineSchedulerPass *P):
160 ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false), Pass(P) {}
162 /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
163 /// time to do some work.
164 virtual void Schedule();
168 static ScheduleDAGInstrs *createDefaultMachineSched(MachineSchedulerPass *P) {
169 return new MachineScheduler(P);
171 static MachineSchedRegistry
172 SchedDefaultRegistry("default", "Activate the scheduler pass, "
173 "but don't reorder instructions",
174 createDefaultMachineSched);
176 /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
177 /// time to do some work.
178 void MachineScheduler::Schedule() {
179 BuildSchedGraph(&Pass->getAnalysis<AliasAnalysis>());
181 DEBUG(dbgs() << "********** MI Scheduling **********\n");
182 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
183 SUnits[su].dumpAll(this));
185 // TODO: Put interesting things here.
188 bool MachineSchedulerPass::runOnMachineFunction(MachineFunction &mf) {
189 // Initialize the context of the pass.
191 MLI = &getAnalysis<MachineLoopInfo>();
192 MDT = &getAnalysis<MachineDominatorTree>();
193 TII = MF->getTarget().getInstrInfo();
195 // Select the scheduler, or set the default.
196 MachineSchedRegistry::ScheduleDAGCtor Ctor =
197 MachineSchedRegistry::getDefault();
199 Ctor = MachineSchedOpt;
200 MachineSchedRegistry::setDefault(Ctor);
202 // Instantiate the selected scheduler.
203 OwningPtr<ScheduleDAGInstrs> Scheduler(Ctor(this));
205 // Visit all machine basic blocks.
206 for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
207 MBB != MBBEnd; ++MBB) {
209 // Break the block into scheduling regions [I, RegionEnd), and schedule each
210 // region as soon as it is discovered.
211 unsigned RemainingCount = MBB->size();
212 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
213 RegionEnd != MBB->begin();) {
214 // The next region starts above the previous region. Look backward in the
215 // instruction stream until we find the nearest boundary.
216 MachineBasicBlock::iterator I = RegionEnd;
217 for(;I != MBB->begin(); --I, --RemainingCount) {
218 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, *MF))
221 if (I == RegionEnd) {
222 // Skip empty scheduling regions.
223 RegionEnd = llvm::prior(RegionEnd);
227 // Schedule regions with more than one instruction.
228 if (I != llvm::prior(RegionEnd)) {
229 DEBUG(dbgs() << "MachineScheduling " << MF->getFunction()->getName()
230 << ":BB#" << MBB->getNumber() << "\n From: " << *I << " To: "
231 << *RegionEnd << " Remaining: " << RemainingCount << "\n");
233 // Inform ScheduleDAGInstrs of the region being scheduled. It calls back
234 // to our Schedule() method.
235 Scheduler->Run(MBB, I, RegionEnd, MBB->size());
239 assert(RemainingCount == 0 && "Instruction count mismatch!");
244 void MachineSchedulerPass::print(raw_ostream &O, const Module* m) const {
248 //===----------------------------------------------------------------------===//
249 // Machine Instruction Shuffler for Correctness Testing
250 //===----------------------------------------------------------------------===//
254 /// Reorder instructions as much as possible.
255 class InstructionShuffler : public ScheduleDAGInstrs {
256 MachineSchedulerPass *Pass;
258 InstructionShuffler(MachineSchedulerPass *P):
259 ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false), Pass(P) {}
261 /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
262 /// time to do some work.
263 virtual void Schedule() {
264 llvm_unreachable("unimplemented");
269 static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedulerPass *P) {
270 return new InstructionShuffler(P);
272 static MachineSchedRegistry ShufflerRegistry("shuffle",
273 "Shuffle machine instructions",
274 createInstructionShuffler);