1 //===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MachineScheduler schedules machine instructions after phi elimination. It
11 // preserves LiveIntervals so it can be invoked before register allocation.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/MachineScheduler.h"
16 #include "llvm/ADT/PriorityQueue.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/MachineDominators.h"
20 #include "llvm/CodeGen/MachineLoopInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/CodeGen/RegisterClassInfo.h"
24 #include "llvm/CodeGen/ScheduleDFS.h"
25 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/GraphWriter.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/Target/TargetInstrInfo.h"
36 #define DEBUG_TYPE "misched"
39 cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
40 cl::desc("Force top-down list scheduling"));
41 cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
42 cl::desc("Force bottom-up list scheduling"));
44 DumpCriticalPathLength("misched-dcpl", cl::Hidden,
45 cl::desc("Print critical path length to stdout"));
49 static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden,
50 cl::desc("Pop up a window to show MISched dags after they are processed"));
52 /// In some situations a few uninteresting nodes depend on nearly all other
53 /// nodes in the graph, provide a cutoff to hide them.
54 static cl::opt<unsigned> ViewMISchedCutoff("view-misched-cutoff", cl::Hidden,
55 cl::desc("Hide nodes with more predecessor/successor than cutoff"));
57 static cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden,
58 cl::desc("Stop scheduling after N instructions"), cl::init(~0U));
60 static cl::opt<std::string> SchedOnlyFunc("misched-only-func", cl::Hidden,
61 cl::desc("Only schedule this function"));
62 static cl::opt<unsigned> SchedOnlyBlock("misched-only-block", cl::Hidden,
63 cl::desc("Only schedule this MBB#"));
65 static bool ViewMISchedDAGs = false;
68 static cl::opt<bool> EnableRegPressure("misched-regpressure", cl::Hidden,
69 cl::desc("Enable register pressure scheduling."), cl::init(true));
71 static cl::opt<bool> EnableCyclicPath("misched-cyclicpath", cl::Hidden,
72 cl::desc("Enable cyclic critical path analysis."), cl::init(true));
74 static cl::opt<bool> EnableLoadCluster("misched-cluster", cl::Hidden,
75 cl::desc("Enable load clustering."), cl::init(true));
77 // Experimental heuristics
78 static cl::opt<bool> EnableMacroFusion("misched-fusion", cl::Hidden,
79 cl::desc("Enable scheduling for macro fusion."), cl::init(true));
81 static cl::opt<bool> VerifyScheduling("verify-misched", cl::Hidden,
82 cl::desc("Verify machine instrs before and after machine scheduling"));
84 // DAG subtrees must have at least this many nodes.
85 static const unsigned MinSubtreeSize = 8;
87 // Pin the vtables to this file.
88 void MachineSchedStrategy::anchor() {}
89 void ScheduleDAGMutation::anchor() {}
91 //===----------------------------------------------------------------------===//
92 // Machine Instruction Scheduling Pass and Registry
93 //===----------------------------------------------------------------------===//
95 MachineSchedContext::MachineSchedContext():
96 MF(nullptr), MLI(nullptr), MDT(nullptr), PassConfig(nullptr), AA(nullptr), LIS(nullptr) {
97 RegClassInfo = new RegisterClassInfo();
100 MachineSchedContext::~MachineSchedContext() {
105 /// Base class for a machine scheduler class that can run at any point.
106 class MachineSchedulerBase : public MachineSchedContext,
107 public MachineFunctionPass {
109 MachineSchedulerBase(char &ID): MachineFunctionPass(ID) {}
111 void print(raw_ostream &O, const Module* = nullptr) const override;
114 void scheduleRegions(ScheduleDAGInstrs &Scheduler);
117 /// MachineScheduler runs after coalescing and before register allocation.
118 class MachineScheduler : public MachineSchedulerBase {
122 void getAnalysisUsage(AnalysisUsage &AU) const override;
124 bool runOnMachineFunction(MachineFunction&) override;
126 static char ID; // Class identification, replacement for typeinfo
129 ScheduleDAGInstrs *createMachineScheduler();
132 /// PostMachineScheduler runs after shortly before code emission.
133 class PostMachineScheduler : public MachineSchedulerBase {
135 PostMachineScheduler();
137 void getAnalysisUsage(AnalysisUsage &AU) const override;
139 bool runOnMachineFunction(MachineFunction&) override;
141 static char ID; // Class identification, replacement for typeinfo
144 ScheduleDAGInstrs *createPostMachineScheduler();
148 char MachineScheduler::ID = 0;
150 char &llvm::MachineSchedulerID = MachineScheduler::ID;
152 INITIALIZE_PASS_BEGIN(MachineScheduler, "machine-scheduler",
153 "Machine Instruction Scheduler", false, false)
154 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
155 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
156 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
157 INITIALIZE_PASS_END(MachineScheduler, "machine-scheduler",
158 "Machine Instruction Scheduler", false, false)
160 MachineScheduler::MachineScheduler()
161 : MachineSchedulerBase(ID) {
162 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
165 void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
166 AU.setPreservesCFG();
167 AU.addRequiredID(MachineDominatorsID);
168 AU.addRequired<MachineLoopInfo>();
169 AU.addRequired<AAResultsWrapperPass>();
170 AU.addRequired<TargetPassConfig>();
171 AU.addRequired<SlotIndexes>();
172 AU.addPreserved<SlotIndexes>();
173 AU.addRequired<LiveIntervals>();
174 AU.addPreserved<LiveIntervals>();
175 MachineFunctionPass::getAnalysisUsage(AU);
178 char PostMachineScheduler::ID = 0;
180 char &llvm::PostMachineSchedulerID = PostMachineScheduler::ID;
182 INITIALIZE_PASS(PostMachineScheduler, "postmisched",
183 "PostRA Machine Instruction Scheduler", false, false)
185 PostMachineScheduler::PostMachineScheduler()
186 : MachineSchedulerBase(ID) {
187 initializePostMachineSchedulerPass(*PassRegistry::getPassRegistry());
190 void PostMachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
191 AU.setPreservesCFG();
192 AU.addRequiredID(MachineDominatorsID);
193 AU.addRequired<MachineLoopInfo>();
194 AU.addRequired<TargetPassConfig>();
195 MachineFunctionPass::getAnalysisUsage(AU);
198 MachinePassRegistry MachineSchedRegistry::Registry;
200 /// A dummy default scheduler factory indicates whether the scheduler
201 /// is overridden on the command line.
202 static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) {
206 /// MachineSchedOpt allows command line selection of the scheduler.
207 static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
208 RegisterPassParser<MachineSchedRegistry> >
209 MachineSchedOpt("misched",
210 cl::init(&useDefaultMachineSched), cl::Hidden,
211 cl::desc("Machine instruction scheduler to use"));
213 static MachineSchedRegistry
214 DefaultSchedRegistry("default", "Use the target's default scheduler choice.",
215 useDefaultMachineSched);
217 static cl::opt<bool> EnableMachineSched(
219 cl::desc("Enable the machine instruction scheduling pass."), cl::init(true),
222 /// Forward declare the standard machine scheduler. This will be used as the
223 /// default scheduler if the target does not set a default.
224 static ScheduleDAGInstrs *createGenericSchedLive(MachineSchedContext *C);
225 static ScheduleDAGInstrs *createGenericSchedPostRA(MachineSchedContext *C);
227 /// Decrement this iterator until reaching the top or a non-debug instr.
228 static MachineBasicBlock::const_iterator
229 priorNonDebug(MachineBasicBlock::const_iterator I,
230 MachineBasicBlock::const_iterator Beg) {
231 assert(I != Beg && "reached the top of the region, cannot decrement");
233 if (!I->isDebugValue())
239 /// Non-const version.
240 static MachineBasicBlock::iterator
241 priorNonDebug(MachineBasicBlock::iterator I,
242 MachineBasicBlock::const_iterator Beg) {
243 return const_cast<MachineInstr*>(
244 &*priorNonDebug(MachineBasicBlock::const_iterator(I), Beg));
247 /// If this iterator is a debug value, increment until reaching the End or a
248 /// non-debug instruction.
249 static MachineBasicBlock::const_iterator
250 nextIfDebug(MachineBasicBlock::const_iterator I,
251 MachineBasicBlock::const_iterator End) {
252 for(; I != End; ++I) {
253 if (!I->isDebugValue())
259 /// Non-const version.
260 static MachineBasicBlock::iterator
261 nextIfDebug(MachineBasicBlock::iterator I,
262 MachineBasicBlock::const_iterator End) {
263 // Cast the return value to nonconst MachineInstr, then cast to an
264 // instr_iterator, which does not check for null, finally return a
266 return MachineBasicBlock::instr_iterator(
267 const_cast<MachineInstr*>(
268 &*nextIfDebug(MachineBasicBlock::const_iterator(I), End)));
271 /// Instantiate a ScheduleDAGInstrs that will be owned by the caller.
272 ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() {
273 // Select the scheduler, or set the default.
274 MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
275 if (Ctor != useDefaultMachineSched)
278 // Get the default scheduler set by the target for this function.
279 ScheduleDAGInstrs *Scheduler = PassConfig->createMachineScheduler(this);
283 // Default to GenericScheduler.
284 return createGenericSchedLive(this);
287 /// Instantiate a ScheduleDAGInstrs for PostRA scheduling that will be owned by
288 /// the caller. We don't have a command line option to override the postRA
289 /// scheduler. The Target must configure it.
290 ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
291 // Get the postRA scheduler set by the target for this function.
292 ScheduleDAGInstrs *Scheduler = PassConfig->createPostMachineScheduler(this);
296 // Default to GenericScheduler.
297 return createGenericSchedPostRA(this);
300 /// Top-level MachineScheduler pass driver.
302 /// Visit blocks in function order. Divide each block into scheduling regions
303 /// and visit them bottom-up. Visiting regions bottom-up is not required, but is
304 /// consistent with the DAG builder, which traverses the interior of the
305 /// scheduling regions bottom-up.
307 /// This design avoids exposing scheduling boundaries to the DAG builder,
308 /// simplifying the DAG builder's support for "special" target instructions.
309 /// At the same time the design allows target schedulers to operate across
310 /// scheduling boundaries, for example to bundle the boudary instructions
311 /// without reordering them. This creates complexity, because the target
312 /// scheduler must update the RegionBegin and RegionEnd positions cached by
313 /// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
314 /// design would be to split blocks at scheduling boundaries, but LLVM has a
315 /// general bias against block splitting purely for implementation simplicity.
316 bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
317 if (EnableMachineSched.getNumOccurrences()) {
318 if (!EnableMachineSched)
320 } else if (!mf.getSubtarget().enableMachineScheduler())
323 DEBUG(dbgs() << "Before MISsched:\n"; mf.print(dbgs()));
325 // Initialize the context of the pass.
327 MLI = &getAnalysis<MachineLoopInfo>();
328 MDT = &getAnalysis<MachineDominatorTree>();
329 PassConfig = &getAnalysis<TargetPassConfig>();
330 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
332 LIS = &getAnalysis<LiveIntervals>();
334 if (VerifyScheduling) {
336 MF->verify(this, "Before machine scheduling.");
338 RegClassInfo->runOnMachineFunction(*MF);
340 // Instantiate the selected scheduler for this target, function, and
341 // optimization level.
342 std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler());
343 scheduleRegions(*Scheduler);
346 if (VerifyScheduling)
347 MF->verify(this, "After machine scheduling.");
351 bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
352 if (skipOptnoneFunction(*mf.getFunction()))
355 if (!mf.getSubtarget().enablePostRAScheduler()) {
356 DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n");
359 DEBUG(dbgs() << "Before post-MI-sched:\n"; mf.print(dbgs()));
361 // Initialize the context of the pass.
363 PassConfig = &getAnalysis<TargetPassConfig>();
365 if (VerifyScheduling)
366 MF->verify(this, "Before post machine scheduling.");
368 // Instantiate the selected scheduler for this target, function, and
369 // optimization level.
370 std::unique_ptr<ScheduleDAGInstrs> Scheduler(createPostMachineScheduler());
371 scheduleRegions(*Scheduler);
373 if (VerifyScheduling)
374 MF->verify(this, "After post machine scheduling.");
378 /// Return true of the given instruction should not be included in a scheduling
381 /// MachineScheduler does not currently support scheduling across calls. To
382 /// handle calls, the DAG builder needs to be modified to create register
383 /// anti/output dependencies on the registers clobbered by the call's regmask
384 /// operand. In PreRA scheduling, the stack pointer adjustment already prevents
385 /// scheduling across calls. In PostRA scheduling, we need the isCall to enforce
386 /// the boundary, but there would be no benefit to postRA scheduling across
387 /// calls this late anyway.
388 static bool isSchedBoundary(MachineBasicBlock::iterator MI,
389 MachineBasicBlock *MBB,
391 const TargetInstrInfo *TII,
393 return MI->isCall() || TII->isSchedulingBoundary(MI, MBB, *MF);
396 /// Main driver for both MachineScheduler and PostMachineScheduler.
397 void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler) {
398 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
399 bool IsPostRA = Scheduler.isPostRA();
401 // Visit all machine basic blocks.
403 // TODO: Visit blocks in global postorder or postorder within the bottom-up
404 // loop tree. Then we can optionally compute global RegPressure.
405 for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
406 MBB != MBBEnd; ++MBB) {
408 Scheduler.startBlock(MBB);
411 if (SchedOnlyFunc.getNumOccurrences() && SchedOnlyFunc != MF->getName())
413 if (SchedOnlyBlock.getNumOccurrences()
414 && (int)SchedOnlyBlock != MBB->getNumber())
418 // Break the block into scheduling regions [I, RegionEnd), and schedule each
419 // region as soon as it is discovered. RegionEnd points the scheduling
420 // boundary at the bottom of the region. The DAG does not include RegionEnd,
421 // but the region does (i.e. the next RegionEnd is above the previous
422 // RegionBegin). If the current block has no terminator then RegionEnd ==
423 // MBB->end() for the bottom region.
425 // The Scheduler may insert instructions during either schedule() or
426 // exitRegion(), even for empty regions. So the local iterators 'I' and
427 // 'RegionEnd' are invalid across these calls.
429 // MBB::size() uses instr_iterator to count. Here we need a bundle to count
430 // as a single instruction.
431 unsigned RemainingInstrs = std::distance(MBB->begin(), MBB->end());
432 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
433 RegionEnd != MBB->begin(); RegionEnd = Scheduler.begin()) {
435 // Avoid decrementing RegionEnd for blocks with no terminator.
436 if (RegionEnd != MBB->end() ||
437 isSchedBoundary(std::prev(RegionEnd), MBB, MF, TII, IsPostRA)) {
439 // Count the boundary instruction.
443 // The next region starts above the previous region. Look backward in the
444 // instruction stream until we find the nearest boundary.
445 unsigned NumRegionInstrs = 0;
446 MachineBasicBlock::iterator I = RegionEnd;
447 for(;I != MBB->begin(); --I, --RemainingInstrs) {
448 if (isSchedBoundary(std::prev(I), MBB, MF, TII, IsPostRA))
450 if (!I->isDebugValue())
453 // Notify the scheduler of the region, even if we may skip scheduling
454 // it. Perhaps it still needs to be bundled.
455 Scheduler.enterRegion(MBB, I, RegionEnd, NumRegionInstrs);
457 // Skip empty scheduling regions (0 or 1 schedulable instructions).
458 if (I == RegionEnd || I == std::prev(RegionEnd)) {
459 // Close the current region. Bundle the terminator if needed.
460 // This invalidates 'RegionEnd' and 'I'.
461 Scheduler.exitRegion();
464 DEBUG(dbgs() << "********** " << ((Scheduler.isPostRA()) ? "PostRA " : "")
465 << "MI Scheduling **********\n");
466 DEBUG(dbgs() << MF->getName()
467 << ":BB#" << MBB->getNumber() << " " << MBB->getName()
468 << "\n From: " << *I << " To: ";
469 if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
470 else dbgs() << "End";
471 dbgs() << " RegionInstrs: " << NumRegionInstrs
472 << " Remaining: " << RemainingInstrs << "\n");
473 if (DumpCriticalPathLength) {
474 errs() << MF->getName();
475 errs() << ":BB# " << MBB->getNumber();
476 errs() << " " << MBB->getName() << " \n";
479 // Schedule a region: possibly reorder instructions.
480 // This invalidates 'RegionEnd' and 'I'.
481 Scheduler.schedule();
483 // Close the current region.
484 Scheduler.exitRegion();
486 // Scheduling has invalidated the current iterator 'I'. Ask the
487 // scheduler for the top of it's scheduled region.
488 RegionEnd = Scheduler.begin();
490 assert(RemainingInstrs == 0 && "Instruction count mismatch!");
491 Scheduler.finishBlock();
492 if (Scheduler.isPostRA()) {
493 // FIXME: Ideally, no further passes should rely on kill flags. However,
494 // thumb2 size reduction is currently an exception.
495 Scheduler.fixupKills(MBB);
498 Scheduler.finalizeSchedule();
501 void MachineSchedulerBase::print(raw_ostream &O, const Module* m) const {
506 void ReadyQueue::dump() {
507 dbgs() << Name << ": ";
508 for (unsigned i = 0, e = Queue.size(); i < e; ++i)
509 dbgs() << Queue[i]->NodeNum << " ";
513 //===----------------------------------------------------------------------===//
514 // ScheduleDAGMI - Basic machine instruction scheduling. This is
515 // independent of PreRA/PostRA scheduling and involves no extra book-keeping for
516 // virtual registers.
517 // ===----------------------------------------------------------------------===/
519 // Provide a vtable anchor.
520 ScheduleDAGMI::~ScheduleDAGMI() {
523 bool ScheduleDAGMI::canAddEdge(SUnit *SuccSU, SUnit *PredSU) {
524 return SuccSU == &ExitSU || !Topo.IsReachable(PredSU, SuccSU);
527 bool ScheduleDAGMI::addEdge(SUnit *SuccSU, const SDep &PredDep) {
528 if (SuccSU != &ExitSU) {
529 // Do not use WillCreateCycle, it assumes SD scheduling.
530 // If Pred is reachable from Succ, then the edge creates a cycle.
531 if (Topo.IsReachable(PredDep.getSUnit(), SuccSU))
533 Topo.AddPred(SuccSU, PredDep.getSUnit());
535 SuccSU->addPred(PredDep, /*Required=*/!PredDep.isArtificial());
536 // Return true regardless of whether a new edge needed to be inserted.
540 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
541 /// NumPredsLeft reaches zero, release the successor node.
543 /// FIXME: Adjust SuccSU height based on MinLatency.
544 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
545 SUnit *SuccSU = SuccEdge->getSUnit();
547 if (SuccEdge->isWeak()) {
548 --SuccSU->WeakPredsLeft;
549 if (SuccEdge->isCluster())
550 NextClusterSucc = SuccSU;
554 if (SuccSU->NumPredsLeft == 0) {
555 dbgs() << "*** Scheduling failed! ***\n";
557 dbgs() << " has been released too many times!\n";
558 llvm_unreachable(nullptr);
561 // SU->TopReadyCycle was set to CurrCycle when it was scheduled. However,
562 // CurrCycle may have advanced since then.
563 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency())
564 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency();
566 --SuccSU->NumPredsLeft;
567 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
568 SchedImpl->releaseTopNode(SuccSU);
571 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
572 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
573 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
575 releaseSucc(SU, &*I);
579 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. When
580 /// NumSuccsLeft reaches zero, release the predecessor node.
582 /// FIXME: Adjust PredSU height based on MinLatency.
583 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
584 SUnit *PredSU = PredEdge->getSUnit();
586 if (PredEdge->isWeak()) {
587 --PredSU->WeakSuccsLeft;
588 if (PredEdge->isCluster())
589 NextClusterPred = PredSU;
593 if (PredSU->NumSuccsLeft == 0) {
594 dbgs() << "*** Scheduling failed! ***\n";
596 dbgs() << " has been released too many times!\n";
597 llvm_unreachable(nullptr);
600 // SU->BotReadyCycle was set to CurrCycle when it was scheduled. However,
601 // CurrCycle may have advanced since then.
602 if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency())
603 PredSU->BotReadyCycle = SU->BotReadyCycle + PredEdge->getLatency();
605 --PredSU->NumSuccsLeft;
606 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU)
607 SchedImpl->releaseBottomNode(PredSU);
610 /// releasePredecessors - Call releasePred on each of SU's predecessors.
611 void ScheduleDAGMI::releasePredecessors(SUnit *SU) {
612 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
614 releasePred(SU, &*I);
618 /// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
619 /// crossing a scheduling boundary. [begin, end) includes all instructions in
620 /// the region, including the boundary itself and single-instruction regions
621 /// that don't get scheduled.
622 void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb,
623 MachineBasicBlock::iterator begin,
624 MachineBasicBlock::iterator end,
625 unsigned regioninstrs)
627 ScheduleDAGInstrs::enterRegion(bb, begin, end, regioninstrs);
629 SchedImpl->initPolicy(begin, end, regioninstrs);
632 /// This is normally called from the main scheduler loop but may also be invoked
633 /// by the scheduling strategy to perform additional code motion.
634 void ScheduleDAGMI::moveInstruction(
635 MachineInstr *MI, MachineBasicBlock::iterator InsertPos) {
636 // Advance RegionBegin if the first instruction moves down.
637 if (&*RegionBegin == MI)
640 // Update the instruction stream.
641 BB->splice(InsertPos, BB, MI);
643 // Update LiveIntervals
645 LIS->handleMove(MI, /*UpdateFlags=*/true);
647 // Recede RegionBegin if an instruction moves above the first.
648 if (RegionBegin == InsertPos)
652 bool ScheduleDAGMI::checkSchedLimit() {
654 if (NumInstrsScheduled == MISchedCutoff && MISchedCutoff != ~0U) {
655 CurrentTop = CurrentBottom;
658 ++NumInstrsScheduled;
663 /// Per-region scheduling driver, called back from
664 /// MachineScheduler::runOnMachineFunction. This is a simplified driver that
665 /// does not consider liveness or register pressure. It is useful for PostRA
666 /// scheduling and potentially other custom schedulers.
667 void ScheduleDAGMI::schedule() {
671 Topo.InitDAGTopologicalSorting();
675 SmallVector<SUnit*, 8> TopRoots, BotRoots;
676 findRootsAndBiasEdges(TopRoots, BotRoots);
678 // Initialize the strategy before modifying the DAG.
679 // This may initialize a DFSResult to be used for queue priority.
680 SchedImpl->initialize(this);
682 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
683 SUnits[su].dumpAll(this));
684 if (ViewMISchedDAGs) viewGraph();
686 // Initialize ready queues now that the DAG and priority data are finalized.
687 initQueues(TopRoots, BotRoots);
689 bool IsTopNode = false;
690 while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) {
691 assert(!SU->isScheduled && "Node already scheduled");
692 if (!checkSchedLimit())
695 MachineInstr *MI = SU->getInstr();
697 assert(SU->isTopReady() && "node still has unscheduled dependencies");
698 if (&*CurrentTop == MI)
699 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
701 moveInstruction(MI, CurrentTop);
704 assert(SU->isBottomReady() && "node still has unscheduled dependencies");
705 MachineBasicBlock::iterator priorII =
706 priorNonDebug(CurrentBottom, CurrentTop);
708 CurrentBottom = priorII;
710 if (&*CurrentTop == MI)
711 CurrentTop = nextIfDebug(++CurrentTop, priorII);
712 moveInstruction(MI, CurrentBottom);
716 // Notify the scheduling strategy before updating the DAG.
717 // This sets the scheduled node's ReadyCycle to CurrCycle. When updateQueues
718 // runs, it can then use the accurate ReadyCycle time to determine whether
719 // newly released nodes can move to the readyQ.
720 SchedImpl->schedNode(SU, IsTopNode);
722 updateQueues(SU, IsTopNode);
724 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
729 unsigned BBNum = begin()->getParent()->getNumber();
730 dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
736 /// Apply each ScheduleDAGMutation step in order.
737 void ScheduleDAGMI::postprocessDAG() {
738 for (unsigned i = 0, e = Mutations.size(); i < e; ++i) {
739 Mutations[i]->apply(this);
744 findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,
745 SmallVectorImpl<SUnit*> &BotRoots) {
746 for (std::vector<SUnit>::iterator
747 I = SUnits.begin(), E = SUnits.end(); I != E; ++I) {
749 assert(!SU->isBoundaryNode() && "Boundary node should not be in SUnits");
751 // Order predecessors so DFSResult follows the critical path.
752 SU->biasCriticalPath();
754 // A SUnit is ready to top schedule if it has no predecessors.
755 if (!I->NumPredsLeft)
756 TopRoots.push_back(SU);
757 // A SUnit is ready to bottom schedule if it has no successors.
758 if (!I->NumSuccsLeft)
759 BotRoots.push_back(SU);
761 ExitSU.biasCriticalPath();
764 /// Identify DAG roots and setup scheduler queues.
765 void ScheduleDAGMI::initQueues(ArrayRef<SUnit*> TopRoots,
766 ArrayRef<SUnit*> BotRoots) {
767 NextClusterSucc = nullptr;
768 NextClusterPred = nullptr;
770 // Release all DAG roots for scheduling, not including EntrySU/ExitSU.
772 // Nodes with unreleased weak edges can still be roots.
773 // Release top roots in forward order.
774 for (SmallVectorImpl<SUnit*>::const_iterator
775 I = TopRoots.begin(), E = TopRoots.end(); I != E; ++I) {
776 SchedImpl->releaseTopNode(*I);
778 // Release bottom roots in reverse order so the higher priority nodes appear
779 // first. This is more natural and slightly more efficient.
780 for (SmallVectorImpl<SUnit*>::const_reverse_iterator
781 I = BotRoots.rbegin(), E = BotRoots.rend(); I != E; ++I) {
782 SchedImpl->releaseBottomNode(*I);
785 releaseSuccessors(&EntrySU);
786 releasePredecessors(&ExitSU);
788 SchedImpl->registerRoots();
790 // Advance past initial DebugValues.
791 CurrentTop = nextIfDebug(RegionBegin, RegionEnd);
792 CurrentBottom = RegionEnd;
795 /// Update scheduler queues after scheduling an instruction.
796 void ScheduleDAGMI::updateQueues(SUnit *SU, bool IsTopNode) {
797 // Release dependent instructions for scheduling.
799 releaseSuccessors(SU);
801 releasePredecessors(SU);
803 SU->isScheduled = true;
806 /// Reinsert any remaining debug_values, just like the PostRA scheduler.
807 void ScheduleDAGMI::placeDebugValues() {
808 // If first instruction was a DBG_VALUE then put it back.
810 BB->splice(RegionBegin, BB, FirstDbgValue);
811 RegionBegin = FirstDbgValue;
814 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
815 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
816 std::pair<MachineInstr *, MachineInstr *> P = *std::prev(DI);
817 MachineInstr *DbgValue = P.first;
818 MachineBasicBlock::iterator OrigPrevMI = P.second;
819 if (&*RegionBegin == DbgValue)
821 BB->splice(++OrigPrevMI, BB, DbgValue);
822 if (OrigPrevMI == std::prev(RegionEnd))
823 RegionEnd = DbgValue;
826 FirstDbgValue = nullptr;
829 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
830 void ScheduleDAGMI::dumpSchedule() const {
831 for (MachineBasicBlock::iterator MI = begin(), ME = end(); MI != ME; ++MI) {
832 if (SUnit *SU = getSUnit(&(*MI)))
835 dbgs() << "Missing SUnit\n";
840 //===----------------------------------------------------------------------===//
841 // ScheduleDAGMILive - Base class for MachineInstr scheduling with LiveIntervals
843 //===----------------------------------------------------------------------===//
845 ScheduleDAGMILive::~ScheduleDAGMILive() {
849 /// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
850 /// crossing a scheduling boundary. [begin, end) includes all instructions in
851 /// the region, including the boundary itself and single-instruction regions
852 /// that don't get scheduled.
853 void ScheduleDAGMILive::enterRegion(MachineBasicBlock *bb,
854 MachineBasicBlock::iterator begin,
855 MachineBasicBlock::iterator end,
856 unsigned regioninstrs)
858 // ScheduleDAGMI initializes SchedImpl's per-region policy.
859 ScheduleDAGMI::enterRegion(bb, begin, end, regioninstrs);
861 // For convenience remember the end of the liveness region.
862 LiveRegionEnd = (RegionEnd == bb->end()) ? RegionEnd : std::next(RegionEnd);
864 SUPressureDiffs.clear();
866 ShouldTrackPressure = SchedImpl->shouldTrackPressure();
869 // Setup the register pressure trackers for the top scheduled top and bottom
870 // scheduled regions.
871 void ScheduleDAGMILive::initRegPressure() {
872 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin);
873 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
875 // Close the RPTracker to finalize live ins.
876 RPTracker.closeRegion();
878 DEBUG(RPTracker.dump());
880 // Initialize the live ins and live outs.
881 TopRPTracker.addLiveRegs(RPTracker.getLiveIn());
882 BotRPTracker.addLiveRegs(RPTracker.getLiveOut());
884 // Close one end of the tracker so we can call
885 // getMaxUpward/DownwardPressureDelta before advancing across any
886 // instructions. This converts currently live regs into live ins/outs.
887 TopRPTracker.closeTop();
888 BotRPTracker.closeBottom();
890 BotRPTracker.initLiveThru(RPTracker);
891 if (!BotRPTracker.getLiveThru().empty()) {
892 TopRPTracker.initLiveThru(BotRPTracker.getLiveThru());
893 DEBUG(dbgs() << "Live Thru: ";
894 dumpRegSetPressure(BotRPTracker.getLiveThru(), TRI));
897 // For each live out vreg reduce the pressure change associated with other
898 // uses of the same vreg below the live-out reaching def.
899 updatePressureDiffs(RPTracker.getLiveOut());
901 // Account for liveness generated by the region boundary.
902 if (LiveRegionEnd != RegionEnd) {
903 SmallVector<unsigned, 8> LiveUses;
904 BotRPTracker.recede(&LiveUses);
905 updatePressureDiffs(LiveUses);
908 assert(BotRPTracker.getPos() == RegionEnd && "Can't find the region bottom");
910 // Cache the list of excess pressure sets in this region. This will also track
911 // the max pressure in the scheduled code for these sets.
912 RegionCriticalPSets.clear();
913 const std::vector<unsigned> &RegionPressure =
914 RPTracker.getPressure().MaxSetPressure;
915 for (unsigned i = 0, e = RegionPressure.size(); i < e; ++i) {
916 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
917 if (RegionPressure[i] > Limit) {
918 DEBUG(dbgs() << TRI->getRegPressureSetName(i)
919 << " Limit " << Limit
920 << " Actual " << RegionPressure[i] << "\n");
921 RegionCriticalPSets.push_back(PressureChange(i));
924 DEBUG(dbgs() << "Excess PSets: ";
925 for (unsigned i = 0, e = RegionCriticalPSets.size(); i != e; ++i)
926 dbgs() << TRI->getRegPressureSetName(
927 RegionCriticalPSets[i].getPSet()) << " ";
931 void ScheduleDAGMILive::
932 updateScheduledPressure(const SUnit *SU,
933 const std::vector<unsigned> &NewMaxPressure) {
934 const PressureDiff &PDiff = getPressureDiff(SU);
935 unsigned CritIdx = 0, CritEnd = RegionCriticalPSets.size();
936 for (PressureDiff::const_iterator I = PDiff.begin(), E = PDiff.end();
940 unsigned ID = I->getPSet();
941 while (CritIdx != CritEnd && RegionCriticalPSets[CritIdx].getPSet() < ID)
943 if (CritIdx != CritEnd && RegionCriticalPSets[CritIdx].getPSet() == ID) {
944 if ((int)NewMaxPressure[ID] > RegionCriticalPSets[CritIdx].getUnitInc()
945 && NewMaxPressure[ID] <= INT16_MAX)
946 RegionCriticalPSets[CritIdx].setUnitInc(NewMaxPressure[ID]);
948 unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID);
949 if (NewMaxPressure[ID] >= Limit - 2) {
950 DEBUG(dbgs() << " " << TRI->getRegPressureSetName(ID) << ": "
951 << NewMaxPressure[ID]
952 << ((NewMaxPressure[ID] > Limit) ? " > " : " <= ") << Limit
953 << "(+ " << BotRPTracker.getLiveThru()[ID] << " livethru)\n");
958 /// Update the PressureDiff array for liveness after scheduling this
960 void ScheduleDAGMILive::updatePressureDiffs(ArrayRef<unsigned> LiveUses) {
961 for (unsigned LUIdx = 0, LUEnd = LiveUses.size(); LUIdx != LUEnd; ++LUIdx) {
962 /// FIXME: Currently assuming single-use physregs.
963 unsigned Reg = LiveUses[LUIdx];
964 DEBUG(dbgs() << " LiveReg: " << PrintVRegOrUnit(Reg, TRI) << "\n");
965 if (!TRI->isVirtualRegister(Reg))
968 // This may be called before CurrentBottom has been initialized. However,
969 // BotRPTracker must have a valid position. We want the value live into the
970 // instruction or live out of the block, so ask for the previous
971 // instruction's live-out.
972 const LiveInterval &LI = LIS->getInterval(Reg);
974 MachineBasicBlock::const_iterator I =
975 nextIfDebug(BotRPTracker.getPos(), BB->end());
977 VNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
979 LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(I));
982 // RegisterPressureTracker guarantees that readsReg is true for LiveUses.
983 assert(VNI && "No live value at use.");
984 for (VReg2UseMap::iterator
985 UI = VRegUses.find(Reg); UI != VRegUses.end(); ++UI) {
987 DEBUG(dbgs() << " UpdateRegP: SU(" << SU->NodeNum << ") "
989 // If this use comes before the reaching def, it cannot be a last use, so
990 // descrease its pressure change.
991 if (!SU->isScheduled && SU != &ExitSU) {
993 = LI.Query(LIS->getInstructionIndex(SU->getInstr()));
994 if (LRQ.valueIn() == VNI)
995 getPressureDiff(SU).addPressureChange(Reg, true, &MRI);
1001 /// schedule - Called back from MachineScheduler::runOnMachineFunction
1002 /// after setting up the current scheduling region. [RegionBegin, RegionEnd)
1003 /// only includes instructions that have DAG nodes, not scheduling boundaries.
1005 /// This is a skeletal driver, with all the functionality pushed into helpers,
1006 /// so that it can be easily extended by experimental schedulers. Generally,
1007 /// implementing MachineSchedStrategy should be sufficient to implement a new
1008 /// scheduling algorithm. However, if a scheduler further subclasses
1009 /// ScheduleDAGMILive then it will want to override this virtual method in order
1010 /// to update any specialized state.
1011 void ScheduleDAGMILive::schedule() {
1012 buildDAGWithRegPressure();
1014 Topo.InitDAGTopologicalSorting();
1018 SmallVector<SUnit*, 8> TopRoots, BotRoots;
1019 findRootsAndBiasEdges(TopRoots, BotRoots);
1021 // Initialize the strategy before modifying the DAG.
1022 // This may initialize a DFSResult to be used for queue priority.
1023 SchedImpl->initialize(this);
1025 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
1026 SUnits[su].dumpAll(this));
1027 if (ViewMISchedDAGs) viewGraph();
1029 // Initialize ready queues now that the DAG and priority data are finalized.
1030 initQueues(TopRoots, BotRoots);
1032 if (ShouldTrackPressure) {
1033 assert(TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker");
1034 TopRPTracker.setPos(CurrentTop);
1037 bool IsTopNode = false;
1038 while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) {
1039 assert(!SU->isScheduled && "Node already scheduled");
1040 if (!checkSchedLimit())
1043 scheduleMI(SU, IsTopNode);
1046 unsigned SubtreeID = DFSResult->getSubtreeID(SU);
1047 if (!ScheduledTrees.test(SubtreeID)) {
1048 ScheduledTrees.set(SubtreeID);
1049 DFSResult->scheduleTree(SubtreeID);
1050 SchedImpl->scheduleTree(SubtreeID);
1054 // Notify the scheduling strategy after updating the DAG.
1055 SchedImpl->schedNode(SU, IsTopNode);
1057 updateQueues(SU, IsTopNode);
1059 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
1064 unsigned BBNum = begin()->getParent()->getNumber();
1065 dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
1071 /// Build the DAG and setup three register pressure trackers.
1072 void ScheduleDAGMILive::buildDAGWithRegPressure() {
1073 if (!ShouldTrackPressure) {
1075 RegionCriticalPSets.clear();
1076 buildSchedGraph(AA);
1080 // Initialize the register pressure tracker used by buildSchedGraph.
1081 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd,
1082 /*TrackUntiedDefs=*/true);
1084 // Account for liveness generate by the region boundary.
1085 if (LiveRegionEnd != RegionEnd)
1088 // Build the DAG, and compute current register pressure.
1089 buildSchedGraph(AA, &RPTracker, &SUPressureDiffs);
1091 // Initialize top/bottom trackers after computing region pressure.
1095 void ScheduleDAGMILive::computeDFSResult() {
1097 DFSResult = new SchedDFSResult(/*BottomU*/true, MinSubtreeSize);
1099 ScheduledTrees.clear();
1100 DFSResult->resize(SUnits.size());
1101 DFSResult->compute(SUnits);
1102 ScheduledTrees.resize(DFSResult->getNumSubtrees());
1105 /// Compute the max cyclic critical path through the DAG. The scheduling DAG
1106 /// only provides the critical path for single block loops. To handle loops that
1107 /// span blocks, we could use the vreg path latencies provided by
1108 /// MachineTraceMetrics instead. However, MachineTraceMetrics is not currently
1109 /// available for use in the scheduler.
1111 /// The cyclic path estimation identifies a def-use pair that crosses the back
1112 /// edge and considers the depth and height of the nodes. For example, consider
1113 /// the following instruction sequence where each instruction has unit latency
1114 /// and defines an epomymous virtual register:
1116 /// a->b(a,c)->c(b)->d(c)->exit
1118 /// The cyclic critical path is a two cycles: b->c->b
1119 /// The acyclic critical path is four cycles: a->b->c->d->exit
1120 /// LiveOutHeight = height(c) = len(c->d->exit) = 2
1121 /// LiveOutDepth = depth(c) + 1 = len(a->b->c) + 1 = 3
1122 /// LiveInHeight = height(b) + 1 = len(b->c->d->exit) + 1 = 4
1123 /// LiveInDepth = depth(b) = len(a->b) = 1
1125 /// LiveOutDepth - LiveInDepth = 3 - 1 = 2
1126 /// LiveInHeight - LiveOutHeight = 4 - 2 = 2
1127 /// CyclicCriticalPath = min(2, 2) = 2
1129 /// This could be relevant to PostRA scheduling, but is currently implemented
1130 /// assuming LiveIntervals.
1131 unsigned ScheduleDAGMILive::computeCyclicCriticalPath() {
1132 // This only applies to single block loop.
1133 if (!BB->isSuccessor(BB))
1136 unsigned MaxCyclicLatency = 0;
1137 // Visit each live out vreg def to find def/use pairs that cross iterations.
1138 ArrayRef<unsigned> LiveOuts = RPTracker.getLiveOut();
1139 for (ArrayRef<unsigned>::iterator RI = LiveOuts.begin(), RE = LiveOuts.end();
1142 if (!TRI->isVirtualRegister(Reg))
1144 const LiveInterval &LI = LIS->getInterval(Reg);
1145 const VNInfo *DefVNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
1149 MachineInstr *DefMI = LIS->getInstructionFromIndex(DefVNI->def);
1150 const SUnit *DefSU = getSUnit(DefMI);
1154 unsigned LiveOutHeight = DefSU->getHeight();
1155 unsigned LiveOutDepth = DefSU->getDepth() + DefSU->Latency;
1156 // Visit all local users of the vreg def.
1157 for (VReg2UseMap::iterator
1158 UI = VRegUses.find(Reg); UI != VRegUses.end(); ++UI) {
1159 if (UI->SU == &ExitSU)
1162 // Only consider uses of the phi.
1163 LiveQueryResult LRQ =
1164 LI.Query(LIS->getInstructionIndex(UI->SU->getInstr()));
1165 if (!LRQ.valueIn()->isPHIDef())
1168 // Assume that a path spanning two iterations is a cycle, which could
1169 // overestimate in strange cases. This allows cyclic latency to be
1170 // estimated as the minimum slack of the vreg's depth or height.
1171 unsigned CyclicLatency = 0;
1172 if (LiveOutDepth > UI->SU->getDepth())
1173 CyclicLatency = LiveOutDepth - UI->SU->getDepth();
1175 unsigned LiveInHeight = UI->SU->getHeight() + DefSU->Latency;
1176 if (LiveInHeight > LiveOutHeight) {
1177 if (LiveInHeight - LiveOutHeight < CyclicLatency)
1178 CyclicLatency = LiveInHeight - LiveOutHeight;
1183 DEBUG(dbgs() << "Cyclic Path: SU(" << DefSU->NodeNum << ") -> SU("
1184 << UI->SU->NodeNum << ") = " << CyclicLatency << "c\n");
1185 if (CyclicLatency > MaxCyclicLatency)
1186 MaxCyclicLatency = CyclicLatency;
1189 DEBUG(dbgs() << "Cyclic Critical Path: " << MaxCyclicLatency << "c\n");
1190 return MaxCyclicLatency;
1193 /// Move an instruction and update register pressure.
1194 void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) {
1195 // Move the instruction to its new location in the instruction stream.
1196 MachineInstr *MI = SU->getInstr();
1199 assert(SU->isTopReady() && "node still has unscheduled dependencies");
1200 if (&*CurrentTop == MI)
1201 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
1203 moveInstruction(MI, CurrentTop);
1204 TopRPTracker.setPos(MI);
1207 if (ShouldTrackPressure) {
1208 // Update top scheduled pressure.
1209 TopRPTracker.advance();
1210 assert(TopRPTracker.getPos() == CurrentTop && "out of sync");
1211 updateScheduledPressure(SU, TopRPTracker.getPressure().MaxSetPressure);
1215 assert(SU->isBottomReady() && "node still has unscheduled dependencies");
1216 MachineBasicBlock::iterator priorII =
1217 priorNonDebug(CurrentBottom, CurrentTop);
1218 if (&*priorII == MI)
1219 CurrentBottom = priorII;
1221 if (&*CurrentTop == MI) {
1222 CurrentTop = nextIfDebug(++CurrentTop, priorII);
1223 TopRPTracker.setPos(CurrentTop);
1225 moveInstruction(MI, CurrentBottom);
1228 if (ShouldTrackPressure) {
1229 // Update bottom scheduled pressure.
1230 SmallVector<unsigned, 8> LiveUses;
1231 BotRPTracker.recede(&LiveUses);
1232 assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
1233 updateScheduledPressure(SU, BotRPTracker.getPressure().MaxSetPressure);
1234 updatePressureDiffs(LiveUses);
1239 //===----------------------------------------------------------------------===//
1240 // LoadClusterMutation - DAG post-processing to cluster loads.
1241 //===----------------------------------------------------------------------===//
1244 /// \brief Post-process the DAG to create cluster edges between neighboring
1246 class LoadClusterMutation : public ScheduleDAGMutation {
1251 LoadInfo(SUnit *su, unsigned reg, unsigned ofs)
1252 : SU(su), BaseReg(reg), Offset(ofs) {}
1254 bool operator<(const LoadInfo &RHS) const {
1255 return std::tie(BaseReg, Offset) < std::tie(RHS.BaseReg, RHS.Offset);
1259 const TargetInstrInfo *TII;
1260 const TargetRegisterInfo *TRI;
1262 LoadClusterMutation(const TargetInstrInfo *tii,
1263 const TargetRegisterInfo *tri)
1264 : TII(tii), TRI(tri) {}
1266 void apply(ScheduleDAGMI *DAG) override;
1268 void clusterNeighboringLoads(ArrayRef<SUnit*> Loads, ScheduleDAGMI *DAG);
1272 void LoadClusterMutation::clusterNeighboringLoads(ArrayRef<SUnit*> Loads,
1273 ScheduleDAGMI *DAG) {
1274 SmallVector<LoadClusterMutation::LoadInfo,32> LoadRecords;
1275 for (unsigned Idx = 0, End = Loads.size(); Idx != End; ++Idx) {
1276 SUnit *SU = Loads[Idx];
1279 if (TII->getMemOpBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
1280 LoadRecords.push_back(LoadInfo(SU, BaseReg, Offset));
1282 if (LoadRecords.size() < 2)
1284 std::sort(LoadRecords.begin(), LoadRecords.end());
1285 unsigned ClusterLength = 1;
1286 for (unsigned Idx = 0, End = LoadRecords.size(); Idx < (End - 1); ++Idx) {
1287 if (LoadRecords[Idx].BaseReg != LoadRecords[Idx+1].BaseReg) {
1292 SUnit *SUa = LoadRecords[Idx].SU;
1293 SUnit *SUb = LoadRecords[Idx+1].SU;
1294 if (TII->shouldClusterLoads(SUa->getInstr(), SUb->getInstr(), ClusterLength)
1295 && DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
1297 DEBUG(dbgs() << "Cluster loads SU(" << SUa->NodeNum << ") - SU("
1298 << SUb->NodeNum << ")\n");
1299 // Copy successor edges from SUa to SUb. Interleaving computation
1300 // dependent on SUa can prevent load combining due to register reuse.
1301 // Predecessor edges do not need to be copied from SUb to SUa since nearby
1302 // loads should have effectively the same inputs.
1303 for (SUnit::const_succ_iterator
1304 SI = SUa->Succs.begin(), SE = SUa->Succs.end(); SI != SE; ++SI) {
1305 if (SI->getSUnit() == SUb)
1307 DEBUG(dbgs() << " Copy Succ SU(" << SI->getSUnit()->NodeNum << ")\n");
1308 DAG->addEdge(SI->getSUnit(), SDep(SUb, SDep::Artificial));
1317 /// \brief Callback from DAG postProcessing to create cluster edges for loads.
1318 void LoadClusterMutation::apply(ScheduleDAGMI *DAG) {
1319 // Map DAG NodeNum to store chain ID.
1320 DenseMap<unsigned, unsigned> StoreChainIDs;
1321 // Map each store chain to a set of dependent loads.
1322 SmallVector<SmallVector<SUnit*,4>, 32> StoreChainDependents;
1323 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
1324 SUnit *SU = &DAG->SUnits[Idx];
1325 if (!SU->getInstr()->mayLoad())
1327 unsigned ChainPredID = DAG->SUnits.size();
1328 for (SUnit::const_pred_iterator
1329 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
1331 ChainPredID = PI->getSUnit()->NodeNum;
1335 // Check if this chain-like pred has been seen
1336 // before. ChainPredID==MaxNodeID for loads at the top of the schedule.
1337 unsigned NumChains = StoreChainDependents.size();
1338 std::pair<DenseMap<unsigned, unsigned>::iterator, bool> Result =
1339 StoreChainIDs.insert(std::make_pair(ChainPredID, NumChains));
1341 StoreChainDependents.resize(NumChains + 1);
1342 StoreChainDependents[Result.first->second].push_back(SU);
1344 // Iterate over the store chains.
1345 for (unsigned Idx = 0, End = StoreChainDependents.size(); Idx != End; ++Idx)
1346 clusterNeighboringLoads(StoreChainDependents[Idx], DAG);
1349 //===----------------------------------------------------------------------===//
1350 // MacroFusion - DAG post-processing to encourage fusion of macro ops.
1351 //===----------------------------------------------------------------------===//
1354 /// \brief Post-process the DAG to create cluster edges between instructions
1355 /// that may be fused by the processor into a single operation.
1356 class MacroFusion : public ScheduleDAGMutation {
1357 const TargetInstrInfo &TII;
1358 const TargetRegisterInfo &TRI;
1360 MacroFusion(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI)
1361 : TII(TII), TRI(TRI) {}
1363 void apply(ScheduleDAGMI *DAG) override;
1367 /// Returns true if \p MI reads a register written by \p Other.
1368 static bool HasDataDep(const TargetRegisterInfo &TRI, const MachineInstr &MI,
1369 const MachineInstr &Other) {
1370 for (const MachineOperand &MO : MI.uses()) {
1371 if (!MO.isReg() || !MO.readsReg())
1374 unsigned Reg = MO.getReg();
1375 if (Other.modifiesRegister(Reg, &TRI))
1381 /// \brief Callback from DAG postProcessing to create cluster edges to encourage
1382 /// fused operations.
1383 void MacroFusion::apply(ScheduleDAGMI *DAG) {
1384 // For now, assume targets can only fuse with the branch.
1385 SUnit &ExitSU = DAG->ExitSU;
1386 MachineInstr *Branch = ExitSU.getInstr();
1390 for (SUnit &SU : DAG->SUnits) {
1391 // SUnits with successors can't be schedule in front of the ExitSU.
1392 if (!SU.Succs.empty())
1394 // We only care if the node writes to a register that the branch reads.
1395 MachineInstr *Pred = SU.getInstr();
1396 if (!HasDataDep(TRI, *Branch, *Pred))
1399 if (!TII.shouldScheduleAdjacent(Pred, Branch))
1402 // Create a single weak edge from SU to ExitSU. The only effect is to cause
1403 // bottom-up scheduling to heavily prioritize the clustered SU. There is no
1404 // need to copy predecessor edges from ExitSU to SU, since top-down
1405 // scheduling cannot prioritize ExitSU anyway. To defer top-down scheduling
1406 // of SU, we could create an artificial edge from the deepest root, but it
1407 // hasn't been needed yet.
1408 bool Success = DAG->addEdge(&ExitSU, SDep(&SU, SDep::Cluster));
1410 assert(Success && "No DAG nodes should be reachable from ExitSU");
1412 DEBUG(dbgs() << "Macro Fuse SU(" << SU.NodeNum << ")\n");
1417 //===----------------------------------------------------------------------===//
1418 // CopyConstrain - DAG post-processing to encourage copy elimination.
1419 //===----------------------------------------------------------------------===//
1422 /// \brief Post-process the DAG to create weak edges from all uses of a copy to
1423 /// the one use that defines the copy's source vreg, most likely an induction
1424 /// variable increment.
1425 class CopyConstrain : public ScheduleDAGMutation {
1427 SlotIndex RegionBeginIdx;
1428 // RegionEndIdx is the slot index of the last non-debug instruction in the
1429 // scheduling region. So we may have RegionBeginIdx == RegionEndIdx.
1430 SlotIndex RegionEndIdx;
1432 CopyConstrain(const TargetInstrInfo *, const TargetRegisterInfo *) {}
1434 void apply(ScheduleDAGMI *DAG) override;
1437 void constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG);
1441 /// constrainLocalCopy handles two possibilities:
1446 /// I3: dst = src (copy)
1447 /// (create pred->succ edges I0->I1, I2->I1)
1450 /// I0: dst = src (copy)
1454 /// (create pred->succ edges I1->I2, I3->I2)
1456 /// Although the MachineScheduler is currently constrained to single blocks,
1457 /// this algorithm should handle extended blocks. An EBB is a set of
1458 /// contiguously numbered blocks such that the previous block in the EBB is
1459 /// always the single predecessor.
1460 void CopyConstrain::constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG) {
1461 LiveIntervals *LIS = DAG->getLIS();
1462 MachineInstr *Copy = CopySU->getInstr();
1464 // Check for pure vreg copies.
1465 unsigned SrcReg = Copy->getOperand(1).getReg();
1466 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
1469 unsigned DstReg = Copy->getOperand(0).getReg();
1470 if (!TargetRegisterInfo::isVirtualRegister(DstReg))
1473 // Check if either the dest or source is local. If it's live across a back
1474 // edge, it's not local. Note that if both vregs are live across the back
1475 // edge, we cannot successfully contrain the copy without cyclic scheduling.
1476 // If both the copy's source and dest are local live intervals, then we
1477 // should treat the dest as the global for the purpose of adding
1478 // constraints. This adds edges from source's other uses to the copy.
1479 unsigned LocalReg = SrcReg;
1480 unsigned GlobalReg = DstReg;
1481 LiveInterval *LocalLI = &LIS->getInterval(LocalReg);
1482 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx)) {
1485 LocalLI = &LIS->getInterval(LocalReg);
1486 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx))
1489 LiveInterval *GlobalLI = &LIS->getInterval(GlobalReg);
1491 // Find the global segment after the start of the local LI.
1492 LiveInterval::iterator GlobalSegment = GlobalLI->find(LocalLI->beginIndex());
1493 // If GlobalLI does not overlap LocalLI->start, then a copy directly feeds a
1494 // local live range. We could create edges from other global uses to the local
1495 // start, but the coalescer should have already eliminated these cases, so
1496 // don't bother dealing with it.
1497 if (GlobalSegment == GlobalLI->end())
1500 // If GlobalSegment is killed at the LocalLI->start, the call to find()
1501 // returned the next global segment. But if GlobalSegment overlaps with
1502 // LocalLI->start, then advance to the next segement. If a hole in GlobalLI
1503 // exists in LocalLI's vicinity, GlobalSegment will be the end of the hole.
1504 if (GlobalSegment->contains(LocalLI->beginIndex()))
1507 if (GlobalSegment == GlobalLI->end())
1510 // Check if GlobalLI contains a hole in the vicinity of LocalLI.
1511 if (GlobalSegment != GlobalLI->begin()) {
1512 // Two address defs have no hole.
1513 if (SlotIndex::isSameInstr(std::prev(GlobalSegment)->end,
1514 GlobalSegment->start)) {
1517 // If the prior global segment may be defined by the same two-address
1518 // instruction that also defines LocalLI, then can't make a hole here.
1519 if (SlotIndex::isSameInstr(std::prev(GlobalSegment)->start,
1520 LocalLI->beginIndex())) {
1523 // If GlobalLI has a prior segment, it must be live into the EBB. Otherwise
1524 // it would be a disconnected component in the live range.
1525 assert(std::prev(GlobalSegment)->start < LocalLI->beginIndex() &&
1526 "Disconnected LRG within the scheduling region.");
1528 MachineInstr *GlobalDef = LIS->getInstructionFromIndex(GlobalSegment->start);
1532 SUnit *GlobalSU = DAG->getSUnit(GlobalDef);
1536 // GlobalDef is the bottom of the GlobalLI hole. Open the hole by
1537 // constraining the uses of the last local def to precede GlobalDef.
1538 SmallVector<SUnit*,8> LocalUses;
1539 const VNInfo *LastLocalVN = LocalLI->getVNInfoBefore(LocalLI->endIndex());
1540 MachineInstr *LastLocalDef = LIS->getInstructionFromIndex(LastLocalVN->def);
1541 SUnit *LastLocalSU = DAG->getSUnit(LastLocalDef);
1542 for (SUnit::const_succ_iterator
1543 I = LastLocalSU->Succs.begin(), E = LastLocalSU->Succs.end();
1545 if (I->getKind() != SDep::Data || I->getReg() != LocalReg)
1547 if (I->getSUnit() == GlobalSU)
1549 if (!DAG->canAddEdge(GlobalSU, I->getSUnit()))
1551 LocalUses.push_back(I->getSUnit());
1553 // Open the top of the GlobalLI hole by constraining any earlier global uses
1554 // to precede the start of LocalLI.
1555 SmallVector<SUnit*,8> GlobalUses;
1556 MachineInstr *FirstLocalDef =
1557 LIS->getInstructionFromIndex(LocalLI->beginIndex());
1558 SUnit *FirstLocalSU = DAG->getSUnit(FirstLocalDef);
1559 for (SUnit::const_pred_iterator
1560 I = GlobalSU->Preds.begin(), E = GlobalSU->Preds.end(); I != E; ++I) {
1561 if (I->getKind() != SDep::Anti || I->getReg() != GlobalReg)
1563 if (I->getSUnit() == FirstLocalSU)
1565 if (!DAG->canAddEdge(FirstLocalSU, I->getSUnit()))
1567 GlobalUses.push_back(I->getSUnit());
1569 DEBUG(dbgs() << "Constraining copy SU(" << CopySU->NodeNum << ")\n");
1570 // Add the weak edges.
1571 for (SmallVectorImpl<SUnit*>::const_iterator
1572 I = LocalUses.begin(), E = LocalUses.end(); I != E; ++I) {
1573 DEBUG(dbgs() << " Local use SU(" << (*I)->NodeNum << ") -> SU("
1574 << GlobalSU->NodeNum << ")\n");
1575 DAG->addEdge(GlobalSU, SDep(*I, SDep::Weak));
1577 for (SmallVectorImpl<SUnit*>::const_iterator
1578 I = GlobalUses.begin(), E = GlobalUses.end(); I != E; ++I) {
1579 DEBUG(dbgs() << " Global use SU(" << (*I)->NodeNum << ") -> SU("
1580 << FirstLocalSU->NodeNum << ")\n");
1581 DAG->addEdge(FirstLocalSU, SDep(*I, SDep::Weak));
1585 /// \brief Callback from DAG postProcessing to create weak edges to encourage
1586 /// copy elimination.
1587 void CopyConstrain::apply(ScheduleDAGMI *DAG) {
1588 assert(DAG->hasVRegLiveness() && "Expect VRegs with LiveIntervals");
1590 MachineBasicBlock::iterator FirstPos = nextIfDebug(DAG->begin(), DAG->end());
1591 if (FirstPos == DAG->end())
1593 RegionBeginIdx = DAG->getLIS()->getInstructionIndex(&*FirstPos);
1594 RegionEndIdx = DAG->getLIS()->getInstructionIndex(
1595 &*priorNonDebug(DAG->end(), DAG->begin()));
1597 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
1598 SUnit *SU = &DAG->SUnits[Idx];
1599 if (!SU->getInstr()->isCopy())
1602 constrainLocalCopy(SU, static_cast<ScheduleDAGMILive*>(DAG));
1606 //===----------------------------------------------------------------------===//
1607 // MachineSchedStrategy helpers used by GenericScheduler, GenericPostScheduler
1608 // and possibly other custom schedulers.
1609 //===----------------------------------------------------------------------===//
1611 static const unsigned InvalidCycle = ~0U;
1613 SchedBoundary::~SchedBoundary() { delete HazardRec; }
1615 void SchedBoundary::reset() {
1616 // A new HazardRec is created for each DAG and owned by SchedBoundary.
1617 // Destroying and reconstructing it is very expensive though. So keep
1618 // invalid, placeholder HazardRecs.
1619 if (HazardRec && HazardRec->isEnabled()) {
1621 HazardRec = nullptr;
1625 CheckPending = false;
1629 MinReadyCycle = UINT_MAX;
1630 ExpectedLatency = 0;
1631 DependentLatency = 0;
1633 MaxExecutedResCount = 0;
1635 IsResourceLimited = false;
1636 ReservedCycles.clear();
1638 // Track the maximum number of stall cycles that could arise either from the
1639 // latency of a DAG edge or the number of cycles that a processor resource is
1640 // reserved (SchedBoundary::ReservedCycles).
1641 MaxObservedStall = 0;
1643 // Reserve a zero-count for invalid CritResIdx.
1644 ExecutedResCounts.resize(1);
1645 assert(!ExecutedResCounts[0] && "nonzero count for bad resource");
1648 void SchedRemainder::
1649 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) {
1651 if (!SchedModel->hasInstrSchedModel())
1653 RemainingCounts.resize(SchedModel->getNumProcResourceKinds());
1654 for (std::vector<SUnit>::iterator
1655 I = DAG->SUnits.begin(), E = DAG->SUnits.end(); I != E; ++I) {
1656 const MCSchedClassDesc *SC = DAG->getSchedClass(&*I);
1657 RemIssueCount += SchedModel->getNumMicroOps(I->getInstr(), SC)
1658 * SchedModel->getMicroOpFactor();
1659 for (TargetSchedModel::ProcResIter
1660 PI = SchedModel->getWriteProcResBegin(SC),
1661 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1662 unsigned PIdx = PI->ProcResourceIdx;
1663 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1664 RemainingCounts[PIdx] += (Factor * PI->Cycles);
1669 void SchedBoundary::
1670 init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) {
1673 SchedModel = smodel;
1675 if (SchedModel->hasInstrSchedModel()) {
1676 ExecutedResCounts.resize(SchedModel->getNumProcResourceKinds());
1677 ReservedCycles.resize(SchedModel->getNumProcResourceKinds(), InvalidCycle);
1681 /// Compute the stall cycles based on this SUnit's ready time. Heuristics treat
1682 /// these "soft stalls" differently than the hard stall cycles based on CPU
1683 /// resources and computed by checkHazard(). A fully in-order model
1684 /// (MicroOpBufferSize==0) will not make use of this since instructions are not
1685 /// available for scheduling until they are ready. However, a weaker in-order
1686 /// model may use this for heuristics. For example, if a processor has in-order
1687 /// behavior when reading certain resources, this may come into play.
1688 unsigned SchedBoundary::getLatencyStallCycles(SUnit *SU) {
1689 if (!SU->isUnbuffered)
1692 unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle);
1693 if (ReadyCycle > CurrCycle)
1694 return ReadyCycle - CurrCycle;
1698 /// Compute the next cycle at which the given processor resource can be
1700 unsigned SchedBoundary::
1701 getNextResourceCycle(unsigned PIdx, unsigned Cycles) {
1702 unsigned NextUnreserved = ReservedCycles[PIdx];
1703 // If this resource has never been used, always return cycle zero.
1704 if (NextUnreserved == InvalidCycle)
1706 // For bottom-up scheduling add the cycles needed for the current operation.
1708 NextUnreserved += Cycles;
1709 return NextUnreserved;
1712 /// Does this SU have a hazard within the current instruction group.
1714 /// The scheduler supports two modes of hazard recognition. The first is the
1715 /// ScheduleHazardRecognizer API. It is a fully general hazard recognizer that
1716 /// supports highly complicated in-order reservation tables
1717 /// (ScoreboardHazardRecognizer) and arbitraty target-specific logic.
1719 /// The second is a streamlined mechanism that checks for hazards based on
1720 /// simple counters that the scheduler itself maintains. It explicitly checks
1721 /// for instruction dispatch limitations, including the number of micro-ops that
1722 /// can dispatch per cycle.
1724 /// TODO: Also check whether the SU must start a new group.
1725 bool SchedBoundary::checkHazard(SUnit *SU) {
1726 if (HazardRec->isEnabled()
1727 && HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard) {
1730 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
1731 if ((CurrMOps > 0) && (CurrMOps + uops > SchedModel->getIssueWidth())) {
1732 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") uops="
1733 << SchedModel->getNumMicroOps(SU->getInstr()) << '\n');
1736 if (SchedModel->hasInstrSchedModel() && SU->hasReservedResource) {
1737 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
1738 for (TargetSchedModel::ProcResIter
1739 PI = SchedModel->getWriteProcResBegin(SC),
1740 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1741 unsigned NRCycle = getNextResourceCycle(PI->ProcResourceIdx, PI->Cycles);
1742 if (NRCycle > CurrCycle) {
1744 MaxObservedStall = std::max(PI->Cycles, MaxObservedStall);
1746 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") "
1747 << SchedModel->getResourceName(PI->ProcResourceIdx)
1748 << "=" << NRCycle << "c\n");
1756 // Find the unscheduled node in ReadySUs with the highest latency.
1757 unsigned SchedBoundary::
1758 findMaxLatency(ArrayRef<SUnit*> ReadySUs) {
1759 SUnit *LateSU = nullptr;
1760 unsigned RemLatency = 0;
1761 for (ArrayRef<SUnit*>::iterator I = ReadySUs.begin(), E = ReadySUs.end();
1763 unsigned L = getUnscheduledLatency(*I);
1764 if (L > RemLatency) {
1770 DEBUG(dbgs() << Available.getName() << " RemLatency SU("
1771 << LateSU->NodeNum << ") " << RemLatency << "c\n");
1776 // Count resources in this zone and the remaining unscheduled
1777 // instruction. Return the max count, scaled. Set OtherCritIdx to the critical
1778 // resource index, or zero if the zone is issue limited.
1779 unsigned SchedBoundary::
1780 getOtherResourceCount(unsigned &OtherCritIdx) {
1782 if (!SchedModel->hasInstrSchedModel())
1785 unsigned OtherCritCount = Rem->RemIssueCount
1786 + (RetiredMOps * SchedModel->getMicroOpFactor());
1787 DEBUG(dbgs() << " " << Available.getName() << " + Remain MOps: "
1788 << OtherCritCount / SchedModel->getMicroOpFactor() << '\n');
1789 for (unsigned PIdx = 1, PEnd = SchedModel->getNumProcResourceKinds();
1790 PIdx != PEnd; ++PIdx) {
1791 unsigned OtherCount = getResourceCount(PIdx) + Rem->RemainingCounts[PIdx];
1792 if (OtherCount > OtherCritCount) {
1793 OtherCritCount = OtherCount;
1794 OtherCritIdx = PIdx;
1798 DEBUG(dbgs() << " " << Available.getName() << " + Remain CritRes: "
1799 << OtherCritCount / SchedModel->getResourceFactor(OtherCritIdx)
1800 << " " << SchedModel->getResourceName(OtherCritIdx) << "\n");
1802 return OtherCritCount;
1805 void SchedBoundary::releaseNode(SUnit *SU, unsigned ReadyCycle) {
1806 assert(SU->getInstr() && "Scheduled SUnit must have instr");
1809 // ReadyCycle was been bumped up to the CurrCycle when this node was
1810 // scheduled, but CurrCycle may have been eagerly advanced immediately after
1811 // scheduling, so may now be greater than ReadyCycle.
1812 if (ReadyCycle > CurrCycle)
1813 MaxObservedStall = std::max(ReadyCycle - CurrCycle, MaxObservedStall);
1816 if (ReadyCycle < MinReadyCycle)
1817 MinReadyCycle = ReadyCycle;
1819 // Check for interlocks first. For the purpose of other heuristics, an
1820 // instruction that cannot issue appears as if it's not in the ReadyQueue.
1821 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
1822 if ((!IsBuffered && ReadyCycle > CurrCycle) || checkHazard(SU))
1827 // Record this node as an immediate dependent of the scheduled node.
1831 void SchedBoundary::releaseTopNode(SUnit *SU) {
1832 if (SU->isScheduled)
1835 releaseNode(SU, SU->TopReadyCycle);
1838 void SchedBoundary::releaseBottomNode(SUnit *SU) {
1839 if (SU->isScheduled)
1842 releaseNode(SU, SU->BotReadyCycle);
1845 /// Move the boundary of scheduled code by one cycle.
1846 void SchedBoundary::bumpCycle(unsigned NextCycle) {
1847 if (SchedModel->getMicroOpBufferSize() == 0) {
1848 assert(MinReadyCycle < UINT_MAX && "MinReadyCycle uninitialized");
1849 if (MinReadyCycle > NextCycle)
1850 NextCycle = MinReadyCycle;
1852 // Update the current micro-ops, which will issue in the next cycle.
1853 unsigned DecMOps = SchedModel->getIssueWidth() * (NextCycle - CurrCycle);
1854 CurrMOps = (CurrMOps <= DecMOps) ? 0 : CurrMOps - DecMOps;
1856 // Decrement DependentLatency based on the next cycle.
1857 if ((NextCycle - CurrCycle) > DependentLatency)
1858 DependentLatency = 0;
1860 DependentLatency -= (NextCycle - CurrCycle);
1862 if (!HazardRec->isEnabled()) {
1863 // Bypass HazardRec virtual calls.
1864 CurrCycle = NextCycle;
1867 // Bypass getHazardType calls in case of long latency.
1868 for (; CurrCycle != NextCycle; ++CurrCycle) {
1870 HazardRec->AdvanceCycle();
1872 HazardRec->RecedeCycle();
1875 CheckPending = true;
1876 unsigned LFactor = SchedModel->getLatencyFactor();
1878 (int)(getCriticalCount() - (getScheduledLatency() * LFactor))
1881 DEBUG(dbgs() << "Cycle: " << CurrCycle << ' ' << Available.getName() << '\n');
1884 void SchedBoundary::incExecutedResources(unsigned PIdx, unsigned Count) {
1885 ExecutedResCounts[PIdx] += Count;
1886 if (ExecutedResCounts[PIdx] > MaxExecutedResCount)
1887 MaxExecutedResCount = ExecutedResCounts[PIdx];
1890 /// Add the given processor resource to this scheduled zone.
1892 /// \param Cycles indicates the number of consecutive (non-pipelined) cycles
1893 /// during which this resource is consumed.
1895 /// \return the next cycle at which the instruction may execute without
1896 /// oversubscribing resources.
1897 unsigned SchedBoundary::
1898 countResource(unsigned PIdx, unsigned Cycles, unsigned NextCycle) {
1899 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1900 unsigned Count = Factor * Cycles;
1901 DEBUG(dbgs() << " " << SchedModel->getResourceName(PIdx)
1902 << " +" << Cycles << "x" << Factor << "u\n");
1904 // Update Executed resources counts.
1905 incExecutedResources(PIdx, Count);
1906 assert(Rem->RemainingCounts[PIdx] >= Count && "resource double counted");
1907 Rem->RemainingCounts[PIdx] -= Count;
1909 // Check if this resource exceeds the current critical resource. If so, it
1910 // becomes the critical resource.
1911 if (ZoneCritResIdx != PIdx && (getResourceCount(PIdx) > getCriticalCount())) {
1912 ZoneCritResIdx = PIdx;
1913 DEBUG(dbgs() << " *** Critical resource "
1914 << SchedModel->getResourceName(PIdx) << ": "
1915 << getResourceCount(PIdx) / SchedModel->getLatencyFactor() << "c\n");
1917 // For reserved resources, record the highest cycle using the resource.
1918 unsigned NextAvailable = getNextResourceCycle(PIdx, Cycles);
1919 if (NextAvailable > CurrCycle) {
1920 DEBUG(dbgs() << " Resource conflict: "
1921 << SchedModel->getProcResource(PIdx)->Name << " reserved until @"
1922 << NextAvailable << "\n");
1924 return NextAvailable;
1927 /// Move the boundary of scheduled code by one SUnit.
1928 void SchedBoundary::bumpNode(SUnit *SU) {
1929 // Update the reservation table.
1930 if (HazardRec->isEnabled()) {
1931 if (!isTop() && SU->isCall) {
1932 // Calls are scheduled with their preceding instructions. For bottom-up
1933 // scheduling, clear the pipeline state before emitting.
1936 HazardRec->EmitInstruction(SU);
1938 // checkHazard should prevent scheduling multiple instructions per cycle that
1939 // exceed the issue width.
1940 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
1941 unsigned IncMOps = SchedModel->getNumMicroOps(SU->getInstr());
1943 (CurrMOps == 0 || (CurrMOps + IncMOps) <= SchedModel->getIssueWidth()) &&
1944 "Cannot schedule this instruction's MicroOps in the current cycle.");
1946 unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle);
1947 DEBUG(dbgs() << " Ready @" << ReadyCycle << "c\n");
1949 unsigned NextCycle = CurrCycle;
1950 switch (SchedModel->getMicroOpBufferSize()) {
1952 assert(ReadyCycle <= CurrCycle && "Broken PendingQueue");
1955 if (ReadyCycle > NextCycle) {
1956 NextCycle = ReadyCycle;
1957 DEBUG(dbgs() << " *** Stall until: " << ReadyCycle << "\n");
1961 // We don't currently model the OOO reorder buffer, so consider all
1962 // scheduled MOps to be "retired". We do loosely model in-order resource
1963 // latency. If this instruction uses an in-order resource, account for any
1964 // likely stall cycles.
1965 if (SU->isUnbuffered && ReadyCycle > NextCycle)
1966 NextCycle = ReadyCycle;
1969 RetiredMOps += IncMOps;
1971 // Update resource counts and critical resource.
1972 if (SchedModel->hasInstrSchedModel()) {
1973 unsigned DecRemIssue = IncMOps * SchedModel->getMicroOpFactor();
1974 assert(Rem->RemIssueCount >= DecRemIssue && "MOps double counted");
1975 Rem->RemIssueCount -= DecRemIssue;
1976 if (ZoneCritResIdx) {
1977 // Scale scheduled micro-ops for comparing with the critical resource.
1978 unsigned ScaledMOps =
1979 RetiredMOps * SchedModel->getMicroOpFactor();
1981 // If scaled micro-ops are now more than the previous critical resource by
1982 // a full cycle, then micro-ops issue becomes critical.
1983 if ((int)(ScaledMOps - getResourceCount(ZoneCritResIdx))
1984 >= (int)SchedModel->getLatencyFactor()) {
1986 DEBUG(dbgs() << " *** Critical resource NumMicroOps: "
1987 << ScaledMOps / SchedModel->getLatencyFactor() << "c\n");
1990 for (TargetSchedModel::ProcResIter
1991 PI = SchedModel->getWriteProcResBegin(SC),
1992 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1994 countResource(PI->ProcResourceIdx, PI->Cycles, NextCycle);
1995 if (RCycle > NextCycle)
1998 if (SU->hasReservedResource) {
1999 // For reserved resources, record the highest cycle using the resource.
2000 // For top-down scheduling, this is the cycle in which we schedule this
2001 // instruction plus the number of cycles the operations reserves the
2002 // resource. For bottom-up is it simply the instruction's cycle.
2003 for (TargetSchedModel::ProcResIter
2004 PI = SchedModel->getWriteProcResBegin(SC),
2005 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
2006 unsigned PIdx = PI->ProcResourceIdx;
2007 if (SchedModel->getProcResource(PIdx)->BufferSize == 0) {
2009 ReservedCycles[PIdx] =
2010 std::max(getNextResourceCycle(PIdx, 0), NextCycle + PI->Cycles);
2013 ReservedCycles[PIdx] = NextCycle;
2018 // Update ExpectedLatency and DependentLatency.
2019 unsigned &TopLatency = isTop() ? ExpectedLatency : DependentLatency;
2020 unsigned &BotLatency = isTop() ? DependentLatency : ExpectedLatency;
2021 if (SU->getDepth() > TopLatency) {
2022 TopLatency = SU->getDepth();
2023 DEBUG(dbgs() << " " << Available.getName()
2024 << " TopLatency SU(" << SU->NodeNum << ") " << TopLatency << "c\n");
2026 if (SU->getHeight() > BotLatency) {
2027 BotLatency = SU->getHeight();
2028 DEBUG(dbgs() << " " << Available.getName()
2029 << " BotLatency SU(" << SU->NodeNum << ") " << BotLatency << "c\n");
2031 // If we stall for any reason, bump the cycle.
2032 if (NextCycle > CurrCycle) {
2033 bumpCycle(NextCycle);
2036 // After updating ZoneCritResIdx and ExpectedLatency, check if we're
2037 // resource limited. If a stall occurred, bumpCycle does this.
2038 unsigned LFactor = SchedModel->getLatencyFactor();
2040 (int)(getCriticalCount() - (getScheduledLatency() * LFactor))
2043 // Update CurrMOps after calling bumpCycle to handle stalls, since bumpCycle
2044 // resets CurrMOps. Loop to handle instructions with more MOps than issue in
2045 // one cycle. Since we commonly reach the max MOps here, opportunistically
2046 // bump the cycle to avoid uselessly checking everything in the readyQ.
2047 CurrMOps += IncMOps;
2048 while (CurrMOps >= SchedModel->getIssueWidth()) {
2049 DEBUG(dbgs() << " *** Max MOps " << CurrMOps
2050 << " at cycle " << CurrCycle << '\n');
2051 bumpCycle(++NextCycle);
2053 DEBUG(dumpScheduledState());
2056 /// Release pending ready nodes in to the available queue. This makes them
2057 /// visible to heuristics.
2058 void SchedBoundary::releasePending() {
2059 // If the available queue is empty, it is safe to reset MinReadyCycle.
2060 if (Available.empty())
2061 MinReadyCycle = UINT_MAX;
2063 // Check to see if any of the pending instructions are ready to issue. If
2064 // so, add them to the available queue.
2065 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
2066 for (unsigned i = 0, e = Pending.size(); i != e; ++i) {
2067 SUnit *SU = *(Pending.begin()+i);
2068 unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle;
2070 if (ReadyCycle < MinReadyCycle)
2071 MinReadyCycle = ReadyCycle;
2073 if (!IsBuffered && ReadyCycle > CurrCycle)
2076 if (checkHazard(SU))
2080 Pending.remove(Pending.begin()+i);
2083 DEBUG(if (!Pending.empty()) Pending.dump());
2084 CheckPending = false;
2087 /// Remove SU from the ready set for this boundary.
2088 void SchedBoundary::removeReady(SUnit *SU) {
2089 if (Available.isInQueue(SU))
2090 Available.remove(Available.find(SU));
2092 assert(Pending.isInQueue(SU) && "bad ready count");
2093 Pending.remove(Pending.find(SU));
2097 /// If this queue only has one ready candidate, return it. As a side effect,
2098 /// defer any nodes that now hit a hazard, and advance the cycle until at least
2099 /// one node is ready. If multiple instructions are ready, return NULL.
2100 SUnit *SchedBoundary::pickOnlyChoice() {
2105 // Defer any ready instrs that now have a hazard.
2106 for (ReadyQueue::iterator I = Available.begin(); I != Available.end();) {
2107 if (checkHazard(*I)) {
2109 I = Available.remove(I);
2115 for (unsigned i = 0; Available.empty(); ++i) {
2116 // FIXME: Re-enable assert once PR20057 is resolved.
2117 // assert(i <= (HazardRec->getMaxLookAhead() + MaxObservedStall) &&
2118 // "permanent hazard");
2120 bumpCycle(CurrCycle + 1);
2123 if (Available.size() == 1)
2124 return *Available.begin();
2129 // This is useful information to dump after bumpNode.
2130 // Note that the Queue contents are more useful before pickNodeFromQueue.
2131 void SchedBoundary::dumpScheduledState() {
2134 if (ZoneCritResIdx) {
2135 ResFactor = SchedModel->getResourceFactor(ZoneCritResIdx);
2136 ResCount = getResourceCount(ZoneCritResIdx);
2139 ResFactor = SchedModel->getMicroOpFactor();
2140 ResCount = RetiredMOps * SchedModel->getMicroOpFactor();
2142 unsigned LFactor = SchedModel->getLatencyFactor();
2143 dbgs() << Available.getName() << " @" << CurrCycle << "c\n"
2144 << " Retired: " << RetiredMOps;
2145 dbgs() << "\n Executed: " << getExecutedCount() / LFactor << "c";
2146 dbgs() << "\n Critical: " << ResCount / LFactor << "c, "
2147 << ResCount / ResFactor << " "
2148 << SchedModel->getResourceName(ZoneCritResIdx)
2149 << "\n ExpectedLatency: " << ExpectedLatency << "c\n"
2150 << (IsResourceLimited ? " - Resource" : " - Latency")
2155 //===----------------------------------------------------------------------===//
2156 // GenericScheduler - Generic implementation of MachineSchedStrategy.
2157 //===----------------------------------------------------------------------===//
2159 void GenericSchedulerBase::SchedCandidate::
2160 initResourceDelta(const ScheduleDAGMI *DAG,
2161 const TargetSchedModel *SchedModel) {
2162 if (!Policy.ReduceResIdx && !Policy.DemandResIdx)
2165 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
2166 for (TargetSchedModel::ProcResIter
2167 PI = SchedModel->getWriteProcResBegin(SC),
2168 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
2169 if (PI->ProcResourceIdx == Policy.ReduceResIdx)
2170 ResDelta.CritResources += PI->Cycles;
2171 if (PI->ProcResourceIdx == Policy.DemandResIdx)
2172 ResDelta.DemandedResources += PI->Cycles;
2176 /// Set the CandPolicy given a scheduling zone given the current resources and
2177 /// latencies inside and outside the zone.
2178 void GenericSchedulerBase::setPolicy(CandPolicy &Policy,
2180 SchedBoundary &CurrZone,
2181 SchedBoundary *OtherZone) {
2182 // Apply preemptive heuristics based on the total latency and resources
2183 // inside and outside this zone. Potential stalls should be considered before
2184 // following this policy.
2186 // Compute remaining latency. We need this both to determine whether the
2187 // overall schedule has become latency-limited and whether the instructions
2188 // outside this zone are resource or latency limited.
2190 // The "dependent" latency is updated incrementally during scheduling as the
2191 // max height/depth of scheduled nodes minus the cycles since it was
2193 // DLat = max (N.depth - (CurrCycle - N.ReadyCycle) for N in Zone
2195 // The "independent" latency is the max ready queue depth:
2196 // ILat = max N.depth for N in Available|Pending
2198 // RemainingLatency is the greater of independent and dependent latency.
2199 unsigned RemLatency = CurrZone.getDependentLatency();
2200 RemLatency = std::max(RemLatency,
2201 CurrZone.findMaxLatency(CurrZone.Available.elements()));
2202 RemLatency = std::max(RemLatency,
2203 CurrZone.findMaxLatency(CurrZone.Pending.elements()));
2205 // Compute the critical resource outside the zone.
2206 unsigned OtherCritIdx = 0;
2207 unsigned OtherCount =
2208 OtherZone ? OtherZone->getOtherResourceCount(OtherCritIdx) : 0;
2210 bool OtherResLimited = false;
2211 if (SchedModel->hasInstrSchedModel()) {
2212 unsigned LFactor = SchedModel->getLatencyFactor();
2213 OtherResLimited = (int)(OtherCount - (RemLatency * LFactor)) > (int)LFactor;
2215 // Schedule aggressively for latency in PostRA mode. We don't check for
2216 // acyclic latency during PostRA, and highly out-of-order processors will
2217 // skip PostRA scheduling.
2218 if (!OtherResLimited) {
2219 if (IsPostRA || (RemLatency + CurrZone.getCurrCycle() > Rem.CriticalPath)) {
2220 Policy.ReduceLatency |= true;
2221 DEBUG(dbgs() << " " << CurrZone.Available.getName()
2222 << " RemainingLatency " << RemLatency << " + "
2223 << CurrZone.getCurrCycle() << "c > CritPath "
2224 << Rem.CriticalPath << "\n");
2227 // If the same resource is limiting inside and outside the zone, do nothing.
2228 if (CurrZone.getZoneCritResIdx() == OtherCritIdx)
2232 if (CurrZone.isResourceLimited()) {
2233 dbgs() << " " << CurrZone.Available.getName() << " ResourceLimited: "
2234 << SchedModel->getResourceName(CurrZone.getZoneCritResIdx())
2237 if (OtherResLimited)
2238 dbgs() << " RemainingLimit: "
2239 << SchedModel->getResourceName(OtherCritIdx) << "\n";
2240 if (!CurrZone.isResourceLimited() && !OtherResLimited)
2241 dbgs() << " Latency limited both directions.\n");
2243 if (CurrZone.isResourceLimited() && !Policy.ReduceResIdx)
2244 Policy.ReduceResIdx = CurrZone.getZoneCritResIdx();
2246 if (OtherResLimited)
2247 Policy.DemandResIdx = OtherCritIdx;
2251 const char *GenericSchedulerBase::getReasonStr(
2252 GenericSchedulerBase::CandReason Reason) {
2254 case NoCand: return "NOCAND ";
2255 case PhysRegCopy: return "PREG-COPY";
2256 case RegExcess: return "REG-EXCESS";
2257 case RegCritical: return "REG-CRIT ";
2258 case Stall: return "STALL ";
2259 case Cluster: return "CLUSTER ";
2260 case Weak: return "WEAK ";
2261 case RegMax: return "REG-MAX ";
2262 case ResourceReduce: return "RES-REDUCE";
2263 case ResourceDemand: return "RES-DEMAND";
2264 case TopDepthReduce: return "TOP-DEPTH ";
2265 case TopPathReduce: return "TOP-PATH ";
2266 case BotHeightReduce:return "BOT-HEIGHT";
2267 case BotPathReduce: return "BOT-PATH ";
2268 case NextDefUse: return "DEF-USE ";
2269 case NodeOrder: return "ORDER ";
2271 llvm_unreachable("Unknown reason!");
2274 void GenericSchedulerBase::traceCandidate(const SchedCandidate &Cand) {
2276 unsigned ResIdx = 0;
2277 unsigned Latency = 0;
2278 switch (Cand.Reason) {
2282 P = Cand.RPDelta.Excess;
2285 P = Cand.RPDelta.CriticalMax;
2288 P = Cand.RPDelta.CurrentMax;
2290 case ResourceReduce:
2291 ResIdx = Cand.Policy.ReduceResIdx;
2293 case ResourceDemand:
2294 ResIdx = Cand.Policy.DemandResIdx;
2296 case TopDepthReduce:
2297 Latency = Cand.SU->getDepth();
2300 Latency = Cand.SU->getHeight();
2302 case BotHeightReduce:
2303 Latency = Cand.SU->getHeight();
2306 Latency = Cand.SU->getDepth();
2309 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason);
2311 dbgs() << " " << TRI->getRegPressureSetName(P.getPSet())
2312 << ":" << P.getUnitInc() << " ";
2316 dbgs() << " " << SchedModel->getProcResource(ResIdx)->Name << " ";
2320 dbgs() << " " << Latency << " cycles ";
2327 /// Return true if this heuristic determines order.
2328 static bool tryLess(int TryVal, int CandVal,
2329 GenericSchedulerBase::SchedCandidate &TryCand,
2330 GenericSchedulerBase::SchedCandidate &Cand,
2331 GenericSchedulerBase::CandReason Reason) {
2332 if (TryVal < CandVal) {
2333 TryCand.Reason = Reason;
2336 if (TryVal > CandVal) {
2337 if (Cand.Reason > Reason)
2338 Cand.Reason = Reason;
2341 Cand.setRepeat(Reason);
2345 static bool tryGreater(int TryVal, int CandVal,
2346 GenericSchedulerBase::SchedCandidate &TryCand,
2347 GenericSchedulerBase::SchedCandidate &Cand,
2348 GenericSchedulerBase::CandReason Reason) {
2349 if (TryVal > CandVal) {
2350 TryCand.Reason = Reason;
2353 if (TryVal < CandVal) {
2354 if (Cand.Reason > Reason)
2355 Cand.Reason = Reason;
2358 Cand.setRepeat(Reason);
2362 static bool tryLatency(GenericSchedulerBase::SchedCandidate &TryCand,
2363 GenericSchedulerBase::SchedCandidate &Cand,
2364 SchedBoundary &Zone) {
2366 if (Cand.SU->getDepth() > Zone.getScheduledLatency()) {
2367 if (tryLess(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2368 TryCand, Cand, GenericSchedulerBase::TopDepthReduce))
2371 if (tryGreater(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2372 TryCand, Cand, GenericSchedulerBase::TopPathReduce))
2376 if (Cand.SU->getHeight() > Zone.getScheduledLatency()) {
2377 if (tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2378 TryCand, Cand, GenericSchedulerBase::BotHeightReduce))
2381 if (tryGreater(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2382 TryCand, Cand, GenericSchedulerBase::BotPathReduce))
2388 static void tracePick(const GenericSchedulerBase::SchedCandidate &Cand,
2390 DEBUG(dbgs() << "Pick " << (IsTop ? "Top " : "Bot ")
2391 << GenericSchedulerBase::getReasonStr(Cand.Reason) << '\n');
2394 void GenericScheduler::initialize(ScheduleDAGMI *dag) {
2395 assert(dag->hasVRegLiveness() &&
2396 "(PreRA)GenericScheduler needs vreg liveness");
2397 DAG = static_cast<ScheduleDAGMILive*>(dag);
2398 SchedModel = DAG->getSchedModel();
2401 Rem.init(DAG, SchedModel);
2402 Top.init(DAG, SchedModel, &Rem);
2403 Bot.init(DAG, SchedModel, &Rem);
2405 // Initialize resource counts.
2407 // Initialize the HazardRecognizers. If itineraries don't exist, are empty, or
2408 // are disabled, then these HazardRecs will be disabled.
2409 const InstrItineraryData *Itin = SchedModel->getInstrItineraries();
2410 if (!Top.HazardRec) {
2412 DAG->MF.getSubtarget().getInstrInfo()->CreateTargetMIHazardRecognizer(
2415 if (!Bot.HazardRec) {
2417 DAG->MF.getSubtarget().getInstrInfo()->CreateTargetMIHazardRecognizer(
2422 /// Initialize the per-region scheduling policy.
2423 void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
2424 MachineBasicBlock::iterator End,
2425 unsigned NumRegionInstrs) {
2426 const MachineFunction &MF = *Begin->getParent()->getParent();
2427 const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
2429 // Avoid setting up the register pressure tracker for small regions to save
2430 // compile time. As a rough heuristic, only track pressure when the number of
2431 // schedulable instructions exceeds half the integer register file.
2432 RegionPolicy.ShouldTrackPressure = true;
2433 for (unsigned VT = MVT::i32; VT > (unsigned)MVT::i1; --VT) {
2434 MVT::SimpleValueType LegalIntVT = (MVT::SimpleValueType)VT;
2435 if (TLI->isTypeLegal(LegalIntVT)) {
2436 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs(
2437 TLI->getRegClassFor(LegalIntVT));
2438 RegionPolicy.ShouldTrackPressure = NumRegionInstrs > (NIntRegs / 2);
2442 // For generic targets, we default to bottom-up, because it's simpler and more
2443 // compile-time optimizations have been implemented in that direction.
2444 RegionPolicy.OnlyBottomUp = true;
2446 // Allow the subtarget to override default policy.
2447 MF.getSubtarget().overrideSchedPolicy(RegionPolicy, Begin, End,
2450 // After subtarget overrides, apply command line options.
2451 if (!EnableRegPressure)
2452 RegionPolicy.ShouldTrackPressure = false;
2454 // Check -misched-topdown/bottomup can force or unforce scheduling direction.
2455 // e.g. -misched-bottomup=false allows scheduling in both directions.
2456 assert((!ForceTopDown || !ForceBottomUp) &&
2457 "-misched-topdown incompatible with -misched-bottomup");
2458 if (ForceBottomUp.getNumOccurrences() > 0) {
2459 RegionPolicy.OnlyBottomUp = ForceBottomUp;
2460 if (RegionPolicy.OnlyBottomUp)
2461 RegionPolicy.OnlyTopDown = false;
2463 if (ForceTopDown.getNumOccurrences() > 0) {
2464 RegionPolicy.OnlyTopDown = ForceTopDown;
2465 if (RegionPolicy.OnlyTopDown)
2466 RegionPolicy.OnlyBottomUp = false;
2470 /// Set IsAcyclicLatencyLimited if the acyclic path is longer than the cyclic
2471 /// critical path by more cycles than it takes to drain the instruction buffer.
2472 /// We estimate an upper bounds on in-flight instructions as:
2474 /// CyclesPerIteration = max( CyclicPath, Loop-Resource-Height )
2475 /// InFlightIterations = AcyclicPath / CyclesPerIteration
2476 /// InFlightResources = InFlightIterations * LoopResources
2478 /// TODO: Check execution resources in addition to IssueCount.
2479 void GenericScheduler::checkAcyclicLatency() {
2480 if (Rem.CyclicCritPath == 0 || Rem.CyclicCritPath >= Rem.CriticalPath)
2483 // Scaled number of cycles per loop iteration.
2484 unsigned IterCount =
2485 std::max(Rem.CyclicCritPath * SchedModel->getLatencyFactor(),
2487 // Scaled acyclic critical path.
2488 unsigned AcyclicCount = Rem.CriticalPath * SchedModel->getLatencyFactor();
2489 // InFlightCount = (AcyclicPath / IterCycles) * InstrPerLoop
2490 unsigned InFlightCount =
2491 (AcyclicCount * Rem.RemIssueCount + IterCount-1) / IterCount;
2492 unsigned BufferLimit =
2493 SchedModel->getMicroOpBufferSize() * SchedModel->getMicroOpFactor();
2495 Rem.IsAcyclicLatencyLimited = InFlightCount > BufferLimit;
2497 DEBUG(dbgs() << "IssueCycles="
2498 << Rem.RemIssueCount / SchedModel->getLatencyFactor() << "c "
2499 << "IterCycles=" << IterCount / SchedModel->getLatencyFactor()
2500 << "c NumIters=" << (AcyclicCount + IterCount-1) / IterCount
2501 << " InFlight=" << InFlightCount / SchedModel->getMicroOpFactor()
2502 << "m BufferLim=" << SchedModel->getMicroOpBufferSize() << "m\n";
2503 if (Rem.IsAcyclicLatencyLimited)
2504 dbgs() << " ACYCLIC LATENCY LIMIT\n");
2507 void GenericScheduler::registerRoots() {
2508 Rem.CriticalPath = DAG->ExitSU.getDepth();
2510 // Some roots may not feed into ExitSU. Check all of them in case.
2511 for (std::vector<SUnit*>::const_iterator
2512 I = Bot.Available.begin(), E = Bot.Available.end(); I != E; ++I) {
2513 if ((*I)->getDepth() > Rem.CriticalPath)
2514 Rem.CriticalPath = (*I)->getDepth();
2516 DEBUG(dbgs() << "Critical Path(GS-RR ): " << Rem.CriticalPath << '\n');
2517 if (DumpCriticalPathLength) {
2518 errs() << "Critical Path(GS-RR ): " << Rem.CriticalPath << " \n";
2521 if (EnableCyclicPath) {
2522 Rem.CyclicCritPath = DAG->computeCyclicCriticalPath();
2523 checkAcyclicLatency();
2527 static bool tryPressure(const PressureChange &TryP,
2528 const PressureChange &CandP,
2529 GenericSchedulerBase::SchedCandidate &TryCand,
2530 GenericSchedulerBase::SchedCandidate &Cand,
2531 GenericSchedulerBase::CandReason Reason) {
2532 int TryRank = TryP.getPSetOrMax();
2533 int CandRank = CandP.getPSetOrMax();
2534 // If both candidates affect the same set, go with the smallest increase.
2535 if (TryRank == CandRank) {
2536 return tryLess(TryP.getUnitInc(), CandP.getUnitInc(), TryCand, Cand,
2539 // If one candidate decreases and the other increases, go with it.
2540 // Invalid candidates have UnitInc==0.
2541 if (tryGreater(TryP.getUnitInc() < 0, CandP.getUnitInc() < 0, TryCand, Cand,
2545 // If the candidates are decreasing pressure, reverse priority.
2546 if (TryP.getUnitInc() < 0)
2547 std::swap(TryRank, CandRank);
2548 return tryGreater(TryRank, CandRank, TryCand, Cand, Reason);
2551 static unsigned getWeakLeft(const SUnit *SU, bool isTop) {
2552 return (isTop) ? SU->WeakPredsLeft : SU->WeakSuccsLeft;
2555 /// Minimize physical register live ranges. Regalloc wants them adjacent to
2556 /// their physreg def/use.
2558 /// FIXME: This is an unnecessary check on the critical path. Most are root/leaf
2559 /// copies which can be prescheduled. The rest (e.g. x86 MUL) could be bundled
2560 /// with the operation that produces or consumes the physreg. We'll do this when
2561 /// regalloc has support for parallel copies.
2562 static int biasPhysRegCopy(const SUnit *SU, bool isTop) {
2563 const MachineInstr *MI = SU->getInstr();
2567 unsigned ScheduledOper = isTop ? 1 : 0;
2568 unsigned UnscheduledOper = isTop ? 0 : 1;
2569 // If we have already scheduled the physreg produce/consumer, immediately
2570 // schedule the copy.
2571 if (TargetRegisterInfo::isPhysicalRegister(
2572 MI->getOperand(ScheduledOper).getReg()))
2574 // If the physreg is at the boundary, defer it. Otherwise schedule it
2575 // immediately to free the dependent. We can hoist the copy later.
2576 bool AtBoundary = isTop ? !SU->NumSuccsLeft : !SU->NumPredsLeft;
2577 if (TargetRegisterInfo::isPhysicalRegister(
2578 MI->getOperand(UnscheduledOper).getReg()))
2579 return AtBoundary ? -1 : 1;
2583 /// Apply a set of heursitics to a new candidate. Heuristics are currently
2584 /// hierarchical. This may be more efficient than a graduated cost model because
2585 /// we don't need to evaluate all aspects of the model for each node in the
2586 /// queue. But it's really done to make the heuristics easier to debug and
2587 /// statistically analyze.
2589 /// \param Cand provides the policy and current best candidate.
2590 /// \param TryCand refers to the next SUnit candidate, otherwise uninitialized.
2591 /// \param Zone describes the scheduled zone that we are extending.
2592 /// \param RPTracker describes reg pressure within the scheduled zone.
2593 /// \param TempTracker is a scratch pressure tracker to reuse in queries.
2594 void GenericScheduler::tryCandidate(SchedCandidate &Cand,
2595 SchedCandidate &TryCand,
2596 SchedBoundary &Zone,
2597 const RegPressureTracker &RPTracker,
2598 RegPressureTracker &TempTracker) {
2600 if (DAG->isTrackingPressure()) {
2601 // Always initialize TryCand's RPDelta.
2603 TempTracker.getMaxDownwardPressureDelta(
2604 TryCand.SU->getInstr(),
2606 DAG->getRegionCriticalPSets(),
2607 DAG->getRegPressure().MaxSetPressure);
2610 if (VerifyScheduling) {
2611 TempTracker.getMaxUpwardPressureDelta(
2612 TryCand.SU->getInstr(),
2613 &DAG->getPressureDiff(TryCand.SU),
2615 DAG->getRegionCriticalPSets(),
2616 DAG->getRegPressure().MaxSetPressure);
2619 RPTracker.getUpwardPressureDelta(
2620 TryCand.SU->getInstr(),
2621 DAG->getPressureDiff(TryCand.SU),
2623 DAG->getRegionCriticalPSets(),
2624 DAG->getRegPressure().MaxSetPressure);
2628 DEBUG(if (TryCand.RPDelta.Excess.isValid())
2629 dbgs() << " SU(" << TryCand.SU->NodeNum << ") "
2630 << TRI->getRegPressureSetName(TryCand.RPDelta.Excess.getPSet())
2631 << ":" << TryCand.RPDelta.Excess.getUnitInc() << "\n");
2633 // Initialize the candidate if needed.
2634 if (!Cand.isValid()) {
2635 TryCand.Reason = NodeOrder;
2639 if (tryGreater(biasPhysRegCopy(TryCand.SU, Zone.isTop()),
2640 biasPhysRegCopy(Cand.SU, Zone.isTop()),
2641 TryCand, Cand, PhysRegCopy))
2644 // Avoid exceeding the target's limit.
2645 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.Excess,
2646 Cand.RPDelta.Excess,
2647 TryCand, Cand, RegExcess))
2650 // Avoid increasing the max critical pressure in the scheduled region.
2651 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.CriticalMax,
2652 Cand.RPDelta.CriticalMax,
2653 TryCand, Cand, RegCritical))
2656 // For loops that are acyclic path limited, aggressively schedule for latency.
2657 // This can result in very long dependence chains scheduled in sequence, so
2658 // once every cycle (when CurrMOps == 0), switch to normal heuristics.
2659 if (Rem.IsAcyclicLatencyLimited && !Zone.getCurrMOps()
2660 && tryLatency(TryCand, Cand, Zone))
2663 // Prioritize instructions that read unbuffered resources by stall cycles.
2664 if (tryLess(Zone.getLatencyStallCycles(TryCand.SU),
2665 Zone.getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall))
2668 // Keep clustered nodes together to encourage downstream peephole
2669 // optimizations which may reduce resource requirements.
2671 // This is a best effort to set things up for a post-RA pass. Optimizations
2672 // like generating loads of multiple registers should ideally be done within
2673 // the scheduler pass by combining the loads during DAG postprocessing.
2674 const SUnit *NextClusterSU =
2675 Zone.isTop() ? DAG->getNextClusterSucc() : DAG->getNextClusterPred();
2676 if (tryGreater(TryCand.SU == NextClusterSU, Cand.SU == NextClusterSU,
2677 TryCand, Cand, Cluster))
2680 // Weak edges are for clustering and other constraints.
2681 if (tryLess(getWeakLeft(TryCand.SU, Zone.isTop()),
2682 getWeakLeft(Cand.SU, Zone.isTop()),
2683 TryCand, Cand, Weak)) {
2686 // Avoid increasing the max pressure of the entire region.
2687 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.CurrentMax,
2688 Cand.RPDelta.CurrentMax,
2689 TryCand, Cand, RegMax))
2692 // Avoid critical resource consumption and balance the schedule.
2693 TryCand.initResourceDelta(DAG, SchedModel);
2694 if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
2695 TryCand, Cand, ResourceReduce))
2697 if (tryGreater(TryCand.ResDelta.DemandedResources,
2698 Cand.ResDelta.DemandedResources,
2699 TryCand, Cand, ResourceDemand))
2702 // Avoid serializing long latency dependence chains.
2703 // For acyclic path limited loops, latency was already checked above.
2704 if (Cand.Policy.ReduceLatency && !Rem.IsAcyclicLatencyLimited
2705 && tryLatency(TryCand, Cand, Zone)) {
2709 // Prefer immediate defs/users of the last scheduled instruction. This is a
2710 // local pressure avoidance strategy that also makes the machine code
2712 if (tryGreater(Zone.isNextSU(TryCand.SU), Zone.isNextSU(Cand.SU),
2713 TryCand, Cand, NextDefUse))
2716 // Fall through to original instruction order.
2717 if ((Zone.isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum)
2718 || (!Zone.isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) {
2719 TryCand.Reason = NodeOrder;
2723 /// Pick the best candidate from the queue.
2725 /// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during
2726 /// DAG building. To adjust for the current scheduling location we need to
2727 /// maintain the number of vreg uses remaining to be top-scheduled.
2728 void GenericScheduler::pickNodeFromQueue(SchedBoundary &Zone,
2729 const RegPressureTracker &RPTracker,
2730 SchedCandidate &Cand) {
2731 ReadyQueue &Q = Zone.Available;
2735 // getMaxPressureDelta temporarily modifies the tracker.
2736 RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker);
2738 for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
2740 SchedCandidate TryCand(Cand.Policy);
2742 tryCandidate(Cand, TryCand, Zone, RPTracker, TempTracker);
2743 if (TryCand.Reason != NoCand) {
2744 // Initialize resource delta if needed in case future heuristics query it.
2745 if (TryCand.ResDelta == SchedResourceDelta())
2746 TryCand.initResourceDelta(DAG, SchedModel);
2747 Cand.setBest(TryCand);
2748 DEBUG(traceCandidate(Cand));
2753 /// Pick the best candidate node from either the top or bottom queue.
2754 SUnit *GenericScheduler::pickNodeBidirectional(bool &IsTopNode) {
2755 // Schedule as far as possible in the direction of no choice. This is most
2756 // efficient, but also provides the best heuristics for CriticalPSets.
2757 if (SUnit *SU = Bot.pickOnlyChoice()) {
2759 DEBUG(dbgs() << "Pick Bot NOCAND\n");
2762 if (SUnit *SU = Top.pickOnlyChoice()) {
2764 DEBUG(dbgs() << "Pick Top NOCAND\n");
2767 CandPolicy NoPolicy;
2768 SchedCandidate BotCand(NoPolicy);
2769 SchedCandidate TopCand(NoPolicy);
2770 // Set the bottom-up policy based on the state of the current bottom zone and
2771 // the instructions outside the zone, including the top zone.
2772 setPolicy(BotCand.Policy, /*IsPostRA=*/false, Bot, &Top);
2773 // Set the top-down policy based on the state of the current top zone and
2774 // the instructions outside the zone, including the bottom zone.
2775 setPolicy(TopCand.Policy, /*IsPostRA=*/false, Top, &Bot);
2777 // Prefer bottom scheduling when heuristics are silent.
2778 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2779 assert(BotCand.Reason != NoCand && "failed to find the first candidate");
2781 // If either Q has a single candidate that provides the least increase in
2782 // Excess pressure, we can immediately schedule from that Q.
2784 // RegionCriticalPSets summarizes the pressure within the scheduled region and
2785 // affects picking from either Q. If scheduling in one direction must
2786 // increase pressure for one of the excess PSets, then schedule in that
2787 // direction first to provide more freedom in the other direction.
2788 if ((BotCand.Reason == RegExcess && !BotCand.isRepeat(RegExcess))
2789 || (BotCand.Reason == RegCritical
2790 && !BotCand.isRepeat(RegCritical)))
2793 tracePick(BotCand, IsTopNode);
2796 // Check if the top Q has a better candidate.
2797 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2798 assert(TopCand.Reason != NoCand && "failed to find the first candidate");
2800 // Choose the queue with the most important (lowest enum) reason.
2801 if (TopCand.Reason < BotCand.Reason) {
2803 tracePick(TopCand, IsTopNode);
2806 // Otherwise prefer the bottom candidate, in node order if all else failed.
2808 tracePick(BotCand, IsTopNode);
2812 /// Pick the best node to balance the schedule. Implements MachineSchedStrategy.
2813 SUnit *GenericScheduler::pickNode(bool &IsTopNode) {
2814 if (DAG->top() == DAG->bottom()) {
2815 assert(Top.Available.empty() && Top.Pending.empty() &&
2816 Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage");
2821 if (RegionPolicy.OnlyTopDown) {
2822 SU = Top.pickOnlyChoice();
2824 CandPolicy NoPolicy;
2825 SchedCandidate TopCand(NoPolicy);
2826 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2827 assert(TopCand.Reason != NoCand && "failed to find a candidate");
2828 tracePick(TopCand, true);
2833 else if (RegionPolicy.OnlyBottomUp) {
2834 SU = Bot.pickOnlyChoice();
2836 CandPolicy NoPolicy;
2837 SchedCandidate BotCand(NoPolicy);
2838 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2839 assert(BotCand.Reason != NoCand && "failed to find a candidate");
2840 tracePick(BotCand, false);
2846 SU = pickNodeBidirectional(IsTopNode);
2848 } while (SU->isScheduled);
2850 if (SU->isTopReady())
2851 Top.removeReady(SU);
2852 if (SU->isBottomReady())
2853 Bot.removeReady(SU);
2855 DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr());
2859 void GenericScheduler::reschedulePhysRegCopies(SUnit *SU, bool isTop) {
2861 MachineBasicBlock::iterator InsertPos = SU->getInstr();
2864 SmallVectorImpl<SDep> &Deps = isTop ? SU->Preds : SU->Succs;
2866 // Find already scheduled copies with a single physreg dependence and move
2867 // them just above the scheduled instruction.
2868 for (SmallVectorImpl<SDep>::iterator I = Deps.begin(), E = Deps.end();
2870 if (I->getKind() != SDep::Data || !TRI->isPhysicalRegister(I->getReg()))
2872 SUnit *DepSU = I->getSUnit();
2873 if (isTop ? DepSU->Succs.size() > 1 : DepSU->Preds.size() > 1)
2875 MachineInstr *Copy = DepSU->getInstr();
2876 if (!Copy->isCopy())
2878 DEBUG(dbgs() << " Rescheduling physreg copy ";
2879 I->getSUnit()->dump(DAG));
2880 DAG->moveInstruction(Copy, InsertPos);
2884 /// Update the scheduler's state after scheduling a node. This is the same node
2885 /// that was just returned by pickNode(). However, ScheduleDAGMILive needs to
2886 /// update it's state based on the current cycle before MachineSchedStrategy
2889 /// FIXME: Eventually, we may bundle physreg copies rather than rescheduling
2890 /// them here. See comments in biasPhysRegCopy.
2891 void GenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
2893 SU->TopReadyCycle = std::max(SU->TopReadyCycle, Top.getCurrCycle());
2895 if (SU->hasPhysRegUses)
2896 reschedulePhysRegCopies(SU, true);
2899 SU->BotReadyCycle = std::max(SU->BotReadyCycle, Bot.getCurrCycle());
2901 if (SU->hasPhysRegDefs)
2902 reschedulePhysRegCopies(SU, false);
2906 /// Create the standard converging machine scheduler. This will be used as the
2907 /// default scheduler if the target does not set a default.
2908 static ScheduleDAGInstrs *createGenericSchedLive(MachineSchedContext *C) {
2909 ScheduleDAGMILive *DAG = new ScheduleDAGMILive(C, make_unique<GenericScheduler>(C));
2910 // Register DAG post-processors.
2912 // FIXME: extend the mutation API to allow earlier mutations to instantiate
2913 // data and pass it to later mutations. Have a single mutation that gathers
2914 // the interesting nodes in one pass.
2915 DAG->addMutation(make_unique<CopyConstrain>(DAG->TII, DAG->TRI));
2916 if (EnableLoadCluster && DAG->TII->enableClusterLoads())
2917 DAG->addMutation(make_unique<LoadClusterMutation>(DAG->TII, DAG->TRI));
2918 if (EnableMacroFusion)
2919 DAG->addMutation(make_unique<MacroFusion>(*DAG->TII, *DAG->TRI));
2923 static MachineSchedRegistry
2924 GenericSchedRegistry("converge", "Standard converging scheduler.",
2925 createGenericSchedLive);
2927 //===----------------------------------------------------------------------===//
2928 // PostGenericScheduler - Generic PostRA implementation of MachineSchedStrategy.
2929 //===----------------------------------------------------------------------===//
2931 void PostGenericScheduler::initialize(ScheduleDAGMI *Dag) {
2933 SchedModel = DAG->getSchedModel();
2936 Rem.init(DAG, SchedModel);
2937 Top.init(DAG, SchedModel, &Rem);
2940 // Initialize the HazardRecognizers. If itineraries don't exist, are empty,
2941 // or are disabled, then these HazardRecs will be disabled.
2942 const InstrItineraryData *Itin = SchedModel->getInstrItineraries();
2943 if (!Top.HazardRec) {
2945 DAG->MF.getSubtarget().getInstrInfo()->CreateTargetMIHazardRecognizer(
2951 void PostGenericScheduler::registerRoots() {
2952 Rem.CriticalPath = DAG->ExitSU.getDepth();
2954 // Some roots may not feed into ExitSU. Check all of them in case.
2955 for (SmallVectorImpl<SUnit*>::const_iterator
2956 I = BotRoots.begin(), E = BotRoots.end(); I != E; ++I) {
2957 if ((*I)->getDepth() > Rem.CriticalPath)
2958 Rem.CriticalPath = (*I)->getDepth();
2960 DEBUG(dbgs() << "Critical Path: (PGS-RR) " << Rem.CriticalPath << '\n');
2961 if (DumpCriticalPathLength) {
2962 errs() << "Critical Path(PGS-RR ): " << Rem.CriticalPath << " \n";
2966 /// Apply a set of heursitics to a new candidate for PostRA scheduling.
2968 /// \param Cand provides the policy and current best candidate.
2969 /// \param TryCand refers to the next SUnit candidate, otherwise uninitialized.
2970 void PostGenericScheduler::tryCandidate(SchedCandidate &Cand,
2971 SchedCandidate &TryCand) {
2973 // Initialize the candidate if needed.
2974 if (!Cand.isValid()) {
2975 TryCand.Reason = NodeOrder;
2979 // Prioritize instructions that read unbuffered resources by stall cycles.
2980 if (tryLess(Top.getLatencyStallCycles(TryCand.SU),
2981 Top.getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall))
2984 // Avoid critical resource consumption and balance the schedule.
2985 if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
2986 TryCand, Cand, ResourceReduce))
2988 if (tryGreater(TryCand.ResDelta.DemandedResources,
2989 Cand.ResDelta.DemandedResources,
2990 TryCand, Cand, ResourceDemand))
2993 // Avoid serializing long latency dependence chains.
2994 if (Cand.Policy.ReduceLatency && tryLatency(TryCand, Cand, Top)) {
2998 // Fall through to original instruction order.
2999 if (TryCand.SU->NodeNum < Cand.SU->NodeNum)
3000 TryCand.Reason = NodeOrder;
3003 void PostGenericScheduler::pickNodeFromQueue(SchedCandidate &Cand) {
3004 ReadyQueue &Q = Top.Available;
3008 for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
3009 SchedCandidate TryCand(Cand.Policy);
3011 TryCand.initResourceDelta(DAG, SchedModel);
3012 tryCandidate(Cand, TryCand);
3013 if (TryCand.Reason != NoCand) {
3014 Cand.setBest(TryCand);
3015 DEBUG(traceCandidate(Cand));
3020 /// Pick the next node to schedule.
3021 SUnit *PostGenericScheduler::pickNode(bool &IsTopNode) {
3022 if (DAG->top() == DAG->bottom()) {
3023 assert(Top.Available.empty() && Top.Pending.empty() && "ReadyQ garbage");
3028 SU = Top.pickOnlyChoice();
3030 CandPolicy NoPolicy;
3031 SchedCandidate TopCand(NoPolicy);
3032 // Set the top-down policy based on the state of the current top zone and
3033 // the instructions outside the zone, including the bottom zone.
3034 setPolicy(TopCand.Policy, /*IsPostRA=*/true, Top, nullptr);
3035 pickNodeFromQueue(TopCand);
3036 assert(TopCand.Reason != NoCand && "failed to find a candidate");
3037 tracePick(TopCand, true);
3040 } while (SU->isScheduled);
3043 Top.removeReady(SU);
3045 DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr());
3049 /// Called after ScheduleDAGMI has scheduled an instruction and updated
3050 /// scheduled/remaining flags in the DAG nodes.
3051 void PostGenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
3052 SU->TopReadyCycle = std::max(SU->TopReadyCycle, Top.getCurrCycle());
3056 /// Create a generic scheduler with no vreg liveness or DAG mutation passes.
3057 static ScheduleDAGInstrs *createGenericSchedPostRA(MachineSchedContext *C) {
3058 return new ScheduleDAGMI(C, make_unique<PostGenericScheduler>(C), /*IsPostRA=*/true);
3061 //===----------------------------------------------------------------------===//
3062 // ILP Scheduler. Currently for experimental analysis of heuristics.
3063 //===----------------------------------------------------------------------===//
3066 /// \brief Order nodes by the ILP metric.
3068 const SchedDFSResult *DFSResult;
3069 const BitVector *ScheduledTrees;
3072 ILPOrder(bool MaxILP)
3073 : DFSResult(nullptr), ScheduledTrees(nullptr), MaximizeILP(MaxILP) {}
3075 /// \brief Apply a less-than relation on node priority.
3077 /// (Return true if A comes after B in the Q.)
3078 bool operator()(const SUnit *A, const SUnit *B) const {
3079 unsigned SchedTreeA = DFSResult->getSubtreeID(A);
3080 unsigned SchedTreeB = DFSResult->getSubtreeID(B);
3081 if (SchedTreeA != SchedTreeB) {
3082 // Unscheduled trees have lower priority.
3083 if (ScheduledTrees->test(SchedTreeA) != ScheduledTrees->test(SchedTreeB))
3084 return ScheduledTrees->test(SchedTreeB);
3086 // Trees with shallower connections have have lower priority.
3087 if (DFSResult->getSubtreeLevel(SchedTreeA)
3088 != DFSResult->getSubtreeLevel(SchedTreeB)) {
3089 return DFSResult->getSubtreeLevel(SchedTreeA)
3090 < DFSResult->getSubtreeLevel(SchedTreeB);
3094 return DFSResult->getILP(A) < DFSResult->getILP(B);
3096 return DFSResult->getILP(A) > DFSResult->getILP(B);
3100 /// \brief Schedule based on the ILP metric.
3101 class ILPScheduler : public MachineSchedStrategy {
3102 ScheduleDAGMILive *DAG;
3105 std::vector<SUnit*> ReadyQ;
3107 ILPScheduler(bool MaximizeILP): DAG(nullptr), Cmp(MaximizeILP) {}
3109 void initialize(ScheduleDAGMI *dag) override {
3110 assert(dag->hasVRegLiveness() && "ILPScheduler needs vreg liveness");
3111 DAG = static_cast<ScheduleDAGMILive*>(dag);
3112 DAG->computeDFSResult();
3113 Cmp.DFSResult = DAG->getDFSResult();
3114 Cmp.ScheduledTrees = &DAG->getScheduledTrees();
3118 void registerRoots() override {
3119 // Restore the heap in ReadyQ with the updated DFS results.
3120 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3123 /// Implement MachineSchedStrategy interface.
3124 /// -----------------------------------------
3126 /// Callback to select the highest priority node from the ready Q.
3127 SUnit *pickNode(bool &IsTopNode) override {
3128 if (ReadyQ.empty()) return nullptr;
3129 std::pop_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3130 SUnit *SU = ReadyQ.back();
3133 DEBUG(dbgs() << "Pick node " << "SU(" << SU->NodeNum << ") "
3134 << " ILP: " << DAG->getDFSResult()->getILP(SU)
3135 << " Tree: " << DAG->getDFSResult()->getSubtreeID(SU) << " @"
3136 << DAG->getDFSResult()->getSubtreeLevel(
3137 DAG->getDFSResult()->getSubtreeID(SU)) << '\n'
3138 << "Scheduling " << *SU->getInstr());
3142 /// \brief Scheduler callback to notify that a new subtree is scheduled.
3143 void scheduleTree(unsigned SubtreeID) override {
3144 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3147 /// Callback after a node is scheduled. Mark a newly scheduled tree, notify
3148 /// DFSResults, and resort the priority Q.
3149 void schedNode(SUnit *SU, bool IsTopNode) override {
3150 assert(!IsTopNode && "SchedDFSResult needs bottom-up");
3153 void releaseTopNode(SUnit *) override { /*only called for top roots*/ }
3155 void releaseBottomNode(SUnit *SU) override {
3156 ReadyQ.push_back(SU);
3157 std::push_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3162 static ScheduleDAGInstrs *createILPMaxScheduler(MachineSchedContext *C) {
3163 return new ScheduleDAGMILive(C, make_unique<ILPScheduler>(true));
3165 static ScheduleDAGInstrs *createILPMinScheduler(MachineSchedContext *C) {
3166 return new ScheduleDAGMILive(C, make_unique<ILPScheduler>(false));
3168 static MachineSchedRegistry ILPMaxRegistry(
3169 "ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler);
3170 static MachineSchedRegistry ILPMinRegistry(
3171 "ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler);
3173 //===----------------------------------------------------------------------===//
3174 // Machine Instruction Shuffler for Correctness Testing
3175 //===----------------------------------------------------------------------===//
3179 /// Apply a less-than relation on the node order, which corresponds to the
3180 /// instruction order prior to scheduling. IsReverse implements greater-than.
3181 template<bool IsReverse>
3183 bool operator()(SUnit *A, SUnit *B) const {
3185 return A->NodeNum > B->NodeNum;
3187 return A->NodeNum < B->NodeNum;
3191 /// Reorder instructions as much as possible.
3192 class InstructionShuffler : public MachineSchedStrategy {
3196 // Using a less-than relation (SUnitOrder<false>) for the TopQ priority
3197 // gives nodes with a higher number higher priority causing the latest
3198 // instructions to be scheduled first.
3199 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false> >
3201 // When scheduling bottom-up, use greater-than as the queue priority.
3202 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true> >
3205 InstructionShuffler(bool alternate, bool topdown)
3206 : IsAlternating(alternate), IsTopDown(topdown) {}
3208 void initialize(ScheduleDAGMI*) override {
3213 /// Implement MachineSchedStrategy interface.
3214 /// -----------------------------------------
3216 SUnit *pickNode(bool &IsTopNode) override {
3220 if (TopQ.empty()) return nullptr;
3223 } while (SU->isScheduled);
3228 if (BottomQ.empty()) return nullptr;
3231 } while (SU->isScheduled);
3235 IsTopDown = !IsTopDown;
3239 void schedNode(SUnit *SU, bool IsTopNode) override {}
3241 void releaseTopNode(SUnit *SU) override {
3244 void releaseBottomNode(SUnit *SU) override {
3250 static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
3251 bool Alternate = !ForceTopDown && !ForceBottomUp;
3252 bool TopDown = !ForceBottomUp;
3253 assert((TopDown || !ForceTopDown) &&
3254 "-misched-topdown incompatible with -misched-bottomup");
3255 return new ScheduleDAGMILive(C, make_unique<InstructionShuffler>(Alternate, TopDown));
3257 static MachineSchedRegistry ShufflerRegistry(
3258 "shuffle", "Shuffle machine instructions alternating directions",
3259 createInstructionShuffler);
3262 //===----------------------------------------------------------------------===//
3263 // GraphWriter support for ScheduleDAGMILive.
3264 //===----------------------------------------------------------------------===//
3269 template<> struct GraphTraits<
3270 ScheduleDAGMI*> : public GraphTraits<ScheduleDAG*> {};
3273 struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits {
3275 DOTGraphTraits (bool isSimple=false) : DefaultDOTGraphTraits(isSimple) {}
3277 static std::string getGraphName(const ScheduleDAG *G) {
3278 return G->MF.getName();
3281 static bool renderGraphFromBottomUp() {
3285 static bool isNodeHidden(const SUnit *Node) {
3286 if (ViewMISchedCutoff == 0)
3288 return (Node->Preds.size() > ViewMISchedCutoff
3289 || Node->Succs.size() > ViewMISchedCutoff);
3292 static bool hasNodeAddressLabel(const SUnit *Node,
3293 const ScheduleDAG *Graph) {
3297 /// If you want to override the dot attributes printed for a particular
3298 /// edge, override this method.
3299 static std::string getEdgeAttributes(const SUnit *Node,
3301 const ScheduleDAG *Graph) {
3302 if (EI.isArtificialDep())
3303 return "color=cyan,style=dashed";
3305 return "color=blue,style=dashed";
3309 static std::string getNodeLabel(const SUnit *SU, const ScheduleDAG *G) {
3311 raw_string_ostream SS(Str);
3312 const ScheduleDAGMI *DAG = static_cast<const ScheduleDAGMI*>(G);
3313 const SchedDFSResult *DFS = DAG->hasVRegLiveness() ?
3314 static_cast<const ScheduleDAGMILive*>(G)->getDFSResult() : nullptr;
3315 SS << "SU:" << SU->NodeNum;
3317 SS << " I:" << DFS->getNumInstrs(SU);
3320 static std::string getNodeDescription(const SUnit *SU, const ScheduleDAG *G) {
3321 return G->getGraphNodeLabel(SU);
3324 static std::string getNodeAttributes(const SUnit *N, const ScheduleDAG *G) {
3325 std::string Str("shape=Mrecord");
3326 const ScheduleDAGMI *DAG = static_cast<const ScheduleDAGMI*>(G);
3327 const SchedDFSResult *DFS = DAG->hasVRegLiveness() ?
3328 static_cast<const ScheduleDAGMILive*>(G)->getDFSResult() : nullptr;
3330 Str += ",style=filled,fillcolor=\"#";
3331 Str += DOT::getColorString(DFS->getSubtreeID(N));
3340 /// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
3341 /// rendered using 'dot'.
3343 void ScheduleDAGMI::viewGraph(const Twine &Name, const Twine &Title) {
3345 ViewGraph(this, Name, false, Title);
3347 errs() << "ScheduleDAGMI::viewGraph is only available in debug builds on "
3348 << "systems with Graphviz or gv!\n";
3352 /// Out-of-line implementation with no arguments is handy for gdb.
3353 void ScheduleDAGMI::viewGraph() {
3354 viewGraph(getDAGName(), "Scheduling-Units Graph for " + getDAGName());