1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/InlineAsm.h"
17 #include "llvm/Value.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetInstrDesc.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Analysis/DebugInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/LeakDetector.h"
28 #include "llvm/Support/MathExtras.h"
29 #include "llvm/Support/Streams.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/ADT/FoldingSet.h"
34 //===----------------------------------------------------------------------===//
35 // MachineOperand Implementation
36 //===----------------------------------------------------------------------===//
38 /// AddRegOperandToRegInfo - Add this register operand to the specified
39 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
40 /// explicitly nulled out.
41 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
42 assert(isReg() && "Can only add reg operand to use lists");
44 // If the reginfo pointer is null, just explicitly null out or next/prev
45 // pointers, to ensure they are not garbage.
47 Contents.Reg.Prev = 0;
48 Contents.Reg.Next = 0;
52 // Otherwise, add this operand to the head of the registers use/def list.
53 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
55 // For SSA values, we prefer to keep the definition at the start of the list.
56 // we do this by skipping over the definition if it is at the head of the
58 if (*Head && (*Head)->isDef())
59 Head = &(*Head)->Contents.Reg.Next;
61 Contents.Reg.Next = *Head;
62 if (Contents.Reg.Next) {
63 assert(getReg() == Contents.Reg.Next->getReg() &&
64 "Different regs on the same list!");
65 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
68 Contents.Reg.Prev = Head;
72 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
73 /// MachineRegisterInfo it is linked with.
74 void MachineOperand::RemoveRegOperandFromRegInfo() {
75 assert(isOnRegUseList() && "Reg operand is not on a use list");
76 // Unlink this from the doubly linked list of operands.
77 MachineOperand *NextOp = Contents.Reg.Next;
78 *Contents.Reg.Prev = NextOp;
80 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
81 NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
83 Contents.Reg.Prev = 0;
84 Contents.Reg.Next = 0;
87 void MachineOperand::setReg(unsigned Reg) {
88 if (getReg() == Reg) return; // No change.
90 // Otherwise, we have to change the register. If this operand is embedded
91 // into a machine function, we need to update the old and new register's
93 if (MachineInstr *MI = getParent())
94 if (MachineBasicBlock *MBB = MI->getParent())
95 if (MachineFunction *MF = MBB->getParent()) {
96 RemoveRegOperandFromRegInfo();
97 Contents.Reg.RegNo = Reg;
98 AddRegOperandToRegInfo(&MF->getRegInfo());
102 // Otherwise, just change the register, no problem. :)
103 Contents.Reg.RegNo = Reg;
106 /// ChangeToImmediate - Replace this operand with a new immediate operand of
107 /// the specified value. If an operand is known to be an immediate already,
108 /// the setImm method should be used.
109 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
110 // If this operand is currently a register operand, and if this is in a
111 // function, deregister the operand from the register's use/def list.
112 if (isReg() && getParent() && getParent()->getParent() &&
113 getParent()->getParent()->getParent())
114 RemoveRegOperandFromRegInfo();
116 OpKind = MO_Immediate;
117 Contents.ImmVal = ImmVal;
120 /// ChangeToRegister - Replace this operand with a new register operand of
121 /// the specified value. If an operand is known to be an register already,
122 /// the setReg method should be used.
123 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
124 bool isKill, bool isDead, bool isUndef) {
125 // If this operand is already a register operand, use setReg to update the
126 // register's use/def lists.
128 assert(!isEarlyClobber());
131 // Otherwise, change this to a register and set the reg#.
132 OpKind = MO_Register;
133 Contents.Reg.RegNo = Reg;
135 // If this operand is embedded in a function, add the operand to the
136 // register's use/def list.
137 if (MachineInstr *MI = getParent())
138 if (MachineBasicBlock *MBB = MI->getParent())
139 if (MachineFunction *MF = MBB->getParent())
140 AddRegOperandToRegInfo(&MF->getRegInfo());
148 IsEarlyClobber = false;
152 /// isIdenticalTo - Return true if this operand is identical to the specified
154 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
155 if (getType() != Other.getType() ||
156 getTargetFlags() != Other.getTargetFlags())
160 default: llvm_unreachable("Unrecognized operand type");
161 case MachineOperand::MO_Register:
162 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
163 getSubReg() == Other.getSubReg();
164 case MachineOperand::MO_Immediate:
165 return getImm() == Other.getImm();
166 case MachineOperand::MO_FPImmediate:
167 return getFPImm() == Other.getFPImm();
168 case MachineOperand::MO_MachineBasicBlock:
169 return getMBB() == Other.getMBB();
170 case MachineOperand::MO_FrameIndex:
171 return getIndex() == Other.getIndex();
172 case MachineOperand::MO_ConstantPoolIndex:
173 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
174 case MachineOperand::MO_JumpTableIndex:
175 return getIndex() == Other.getIndex();
176 case MachineOperand::MO_GlobalAddress:
177 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
178 case MachineOperand::MO_ExternalSymbol:
179 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
180 getOffset() == Other.getOffset();
184 /// print - Print the specified machine operand.
186 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
188 case MachineOperand::MO_Register:
189 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
190 OS << "%reg" << getReg();
192 // If the instruction is embedded into a basic block, we can find the
193 // target info for the instruction.
195 if (const MachineInstr *MI = getParent())
196 if (const MachineBasicBlock *MBB = MI->getParent())
197 if (const MachineFunction *MF = MBB->getParent())
198 TM = &MF->getTarget();
201 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
203 OS << "%mreg" << getReg();
206 if (getSubReg() != 0)
207 OS << ':' << getSubReg();
209 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
212 bool NeedComma = false;
214 if (NeedComma) OS << ',';
215 OS << (isDef() ? "imp-def" : "imp-use");
217 } else if (isDef()) {
218 if (NeedComma) OS << ',';
219 if (isEarlyClobber())
220 OS << "earlyclobber,";
224 if (isKill() || isDead() || isUndef()) {
225 if (NeedComma) OS << ',';
226 if (isKill()) OS << "kill";
227 if (isDead()) OS << "dead";
229 if (isKill() || isDead())
237 case MachineOperand::MO_Immediate:
240 case MachineOperand::MO_FPImmediate:
241 if (getFPImm()->getType() == Type::getFloatTy(getFPImm()->getContext()))
242 OS << getFPImm()->getValueAPF().convertToFloat();
244 OS << getFPImm()->getValueAPF().convertToDouble();
246 case MachineOperand::MO_MachineBasicBlock:
248 << ((Value*)getMBB()->getBasicBlock())->getName()
249 << "," << (void*)getMBB() << '>';
251 case MachineOperand::MO_FrameIndex:
252 OS << "<fi#" << getIndex() << '>';
254 case MachineOperand::MO_ConstantPoolIndex:
255 OS << "<cp#" << getIndex();
256 if (getOffset()) OS << "+" << getOffset();
259 case MachineOperand::MO_JumpTableIndex:
260 OS << "<jt#" << getIndex() << '>';
262 case MachineOperand::MO_GlobalAddress:
263 OS << "<ga:" << ((Value*)getGlobal())->getName();
264 if (getOffset()) OS << "+" << getOffset();
267 case MachineOperand::MO_ExternalSymbol:
268 OS << "<es:" << getSymbolName();
269 if (getOffset()) OS << "+" << getOffset();
273 llvm_unreachable("Unrecognized operand type");
276 if (unsigned TF = getTargetFlags())
277 OS << "[TF=" << TF << ']';
280 //===----------------------------------------------------------------------===//
281 // MachineMemOperand Implementation
282 //===----------------------------------------------------------------------===//
284 MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
285 int64_t o, uint64_t s, unsigned int a)
286 : Offset(o), Size(s), V(v),
287 Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
288 assert(isPowerOf2_32(a) && "Alignment is not a power of 2!");
289 assert((isLoad() || isStore()) && "Not a load/store!");
292 /// Profile - Gather unique data for the object.
294 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
295 ID.AddInteger(Offset);
298 ID.AddInteger(Flags);
301 //===----------------------------------------------------------------------===//
302 // MachineInstr Implementation
303 //===----------------------------------------------------------------------===//
305 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
306 /// TID NULL and no operands.
307 MachineInstr::MachineInstr()
308 : TID(0), NumImplicitOps(0), Parent(0), debugLoc(DebugLoc::getUnknownLoc()) {
309 // Make sure that we get added to a machine basicblock
310 LeakDetector::addGarbageObject(this);
313 void MachineInstr::addImplicitDefUseOperands() {
314 if (TID->ImplicitDefs)
315 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
316 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
317 if (TID->ImplicitUses)
318 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
319 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
322 /// MachineInstr ctor - This constructor create a MachineInstr and add the
323 /// implicit operands. It reserves space for number of operands specified by
324 /// TargetInstrDesc or the numOperands if it is not zero. (for
325 /// instructions with variable number of operands).
326 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
327 : TID(&tid), NumImplicitOps(0), Parent(0),
328 debugLoc(DebugLoc::getUnknownLoc()) {
329 if (!NoImp && TID->getImplicitDefs())
330 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
332 if (!NoImp && TID->getImplicitUses())
333 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
335 Operands.reserve(NumImplicitOps + TID->getNumOperands());
337 addImplicitDefUseOperands();
338 // Make sure that we get added to a machine basicblock
339 LeakDetector::addGarbageObject(this);
342 /// MachineInstr ctor - As above, but with a DebugLoc.
343 MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
345 : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
346 if (!NoImp && TID->getImplicitDefs())
347 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
349 if (!NoImp && TID->getImplicitUses())
350 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
352 Operands.reserve(NumImplicitOps + TID->getNumOperands());
354 addImplicitDefUseOperands();
355 // Make sure that we get added to a machine basicblock
356 LeakDetector::addGarbageObject(this);
359 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
360 /// that the MachineInstr is created and added to the end of the specified
363 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
364 : TID(&tid), NumImplicitOps(0), Parent(0),
365 debugLoc(DebugLoc::getUnknownLoc()) {
366 assert(MBB && "Cannot use inserting ctor with null basic block!");
367 if (TID->ImplicitDefs)
368 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
370 if (TID->ImplicitUses)
371 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
373 Operands.reserve(NumImplicitOps + TID->getNumOperands());
374 addImplicitDefUseOperands();
375 // Make sure that we get added to a machine basicblock
376 LeakDetector::addGarbageObject(this);
377 MBB->push_back(this); // Add instruction to end of basic block!
380 /// MachineInstr ctor - As above, but with a DebugLoc.
382 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
383 const TargetInstrDesc &tid)
384 : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
385 assert(MBB && "Cannot use inserting ctor with null basic block!");
386 if (TID->ImplicitDefs)
387 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
389 if (TID->ImplicitUses)
390 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
392 Operands.reserve(NumImplicitOps + TID->getNumOperands());
393 addImplicitDefUseOperands();
394 // Make sure that we get added to a machine basicblock
395 LeakDetector::addGarbageObject(this);
396 MBB->push_back(this); // Add instruction to end of basic block!
399 /// MachineInstr ctor - Copies MachineInstr arg exactly
401 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
402 : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0),
403 debugLoc(MI.getDebugLoc()) {
404 Operands.reserve(MI.getNumOperands());
407 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
408 addOperand(MI.getOperand(i));
409 NumImplicitOps = MI.NumImplicitOps;
411 // Add memory operands.
412 for (std::list<MachineMemOperand>::const_iterator i = MI.memoperands_begin(),
413 j = MI.memoperands_end(); i != j; ++i)
414 addMemOperand(MF, *i);
416 // Set parent to null.
419 LeakDetector::addGarbageObject(this);
422 MachineInstr::~MachineInstr() {
423 LeakDetector::removeGarbageObject(this);
424 assert(MemOperands.empty() &&
425 "MachineInstr being deleted with live memoperands!");
427 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
428 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
429 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
430 "Reg operand def/use list corrupted");
435 /// getRegInfo - If this instruction is embedded into a MachineFunction,
436 /// return the MachineRegisterInfo object for the current function, otherwise
438 MachineRegisterInfo *MachineInstr::getRegInfo() {
439 if (MachineBasicBlock *MBB = getParent())
440 return &MBB->getParent()->getRegInfo();
444 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
445 /// this instruction from their respective use lists. This requires that the
446 /// operands already be on their use lists.
447 void MachineInstr::RemoveRegOperandsFromUseLists() {
448 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
449 if (Operands[i].isReg())
450 Operands[i].RemoveRegOperandFromRegInfo();
454 /// AddRegOperandsToUseLists - Add all of the register operands in
455 /// this instruction from their respective use lists. This requires that the
456 /// operands not be on their use lists yet.
457 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
458 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
459 if (Operands[i].isReg())
460 Operands[i].AddRegOperandToRegInfo(&RegInfo);
465 /// addOperand - Add the specified operand to the instruction. If it is an
466 /// implicit operand, it is added to the end of the operand list. If it is
467 /// an explicit operand it is added at the end of the explicit operand list
468 /// (before the first implicit operand).
469 void MachineInstr::addOperand(const MachineOperand &Op) {
470 bool isImpReg = Op.isReg() && Op.isImplicit();
471 assert((isImpReg || !OperandsComplete()) &&
472 "Trying to add an operand to a machine instr that is already done!");
474 MachineRegisterInfo *RegInfo = getRegInfo();
476 // If we are adding the operand to the end of the list, our job is simpler.
477 // This is true most of the time, so this is a reasonable optimization.
478 if (isImpReg || NumImplicitOps == 0) {
479 // We can only do this optimization if we know that the operand list won't
481 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
482 Operands.push_back(Op);
484 // Set the parent of the operand.
485 Operands.back().ParentMI = this;
487 // If the operand is a register, update the operand's use list.
489 Operands.back().AddRegOperandToRegInfo(RegInfo);
494 // Otherwise, we have to insert a real operand before any implicit ones.
495 unsigned OpNo = Operands.size()-NumImplicitOps;
497 // If this instruction isn't embedded into a function, then we don't need to
498 // update any operand lists.
500 // Simple insertion, no reginfo update needed for other register operands.
501 Operands.insert(Operands.begin()+OpNo, Op);
502 Operands[OpNo].ParentMI = this;
504 // Do explicitly set the reginfo for this operand though, to ensure the
505 // next/prev fields are properly nulled out.
506 if (Operands[OpNo].isReg())
507 Operands[OpNo].AddRegOperandToRegInfo(0);
509 } else if (Operands.size()+1 <= Operands.capacity()) {
510 // Otherwise, we have to remove register operands from their register use
511 // list, add the operand, then add the register operands back to their use
512 // list. This also must handle the case when the operand list reallocates
513 // to somewhere else.
515 // If insertion of this operand won't cause reallocation of the operand
516 // list, just remove the implicit operands, add the operand, then re-add all
517 // the rest of the operands.
518 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
519 assert(Operands[i].isReg() && "Should only be an implicit reg!");
520 Operands[i].RemoveRegOperandFromRegInfo();
523 // Add the operand. If it is a register, add it to the reg list.
524 Operands.insert(Operands.begin()+OpNo, Op);
525 Operands[OpNo].ParentMI = this;
527 if (Operands[OpNo].isReg())
528 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
530 // Re-add all the implicit ops.
531 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
532 assert(Operands[i].isReg() && "Should only be an implicit reg!");
533 Operands[i].AddRegOperandToRegInfo(RegInfo);
536 // Otherwise, we will be reallocating the operand list. Remove all reg
537 // operands from their list, then readd them after the operand list is
539 RemoveRegOperandsFromUseLists();
541 Operands.insert(Operands.begin()+OpNo, Op);
542 Operands[OpNo].ParentMI = this;
544 // Re-add all the operands.
545 AddRegOperandsToUseLists(*RegInfo);
549 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
550 /// fewer operand than it started with.
552 void MachineInstr::RemoveOperand(unsigned OpNo) {
553 assert(OpNo < Operands.size() && "Invalid operand number");
555 // Special case removing the last one.
556 if (OpNo == Operands.size()-1) {
557 // If needed, remove from the reg def/use list.
558 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
559 Operands.back().RemoveRegOperandFromRegInfo();
565 // Otherwise, we are removing an interior operand. If we have reginfo to
566 // update, remove all operands that will be shifted down from their reg lists,
567 // move everything down, then re-add them.
568 MachineRegisterInfo *RegInfo = getRegInfo();
570 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
571 if (Operands[i].isReg())
572 Operands[i].RemoveRegOperandFromRegInfo();
576 Operands.erase(Operands.begin()+OpNo);
579 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
580 if (Operands[i].isReg())
581 Operands[i].AddRegOperandToRegInfo(RegInfo);
586 /// addMemOperand - Add a MachineMemOperand to the machine instruction,
587 /// referencing arbitrary storage.
588 void MachineInstr::addMemOperand(MachineFunction &MF,
589 const MachineMemOperand &MO) {
590 MemOperands.push_back(MO);
593 /// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
594 void MachineInstr::clearMemOperands(MachineFunction &MF) {
599 /// removeFromParent - This method unlinks 'this' from the containing basic
600 /// block, and returns it, but does not delete it.
601 MachineInstr *MachineInstr::removeFromParent() {
602 assert(getParent() && "Not embedded in a basic block!");
603 getParent()->remove(this);
608 /// eraseFromParent - This method unlinks 'this' from the containing basic
609 /// block, and deletes it.
610 void MachineInstr::eraseFromParent() {
611 assert(getParent() && "Not embedded in a basic block!");
612 getParent()->erase(this);
616 /// OperandComplete - Return true if it's illegal to add a new operand
618 bool MachineInstr::OperandsComplete() const {
619 unsigned short NumOperands = TID->getNumOperands();
620 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
621 return true; // Broken: we have all the operands of this instruction!
625 /// getNumExplicitOperands - Returns the number of non-implicit operands.
627 unsigned MachineInstr::getNumExplicitOperands() const {
628 unsigned NumOperands = TID->getNumOperands();
629 if (!TID->isVariadic())
632 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
633 const MachineOperand &MO = getOperand(i);
634 if (!MO.isReg() || !MO.isImplicit())
641 /// isLabel - Returns true if the MachineInstr represents a label.
643 bool MachineInstr::isLabel() const {
644 return getOpcode() == TargetInstrInfo::DBG_LABEL ||
645 getOpcode() == TargetInstrInfo::EH_LABEL ||
646 getOpcode() == TargetInstrInfo::GC_LABEL;
649 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
651 bool MachineInstr::isDebugLabel() const {
652 return getOpcode() == TargetInstrInfo::DBG_LABEL;
655 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
656 /// the specific register or -1 if it is not found. It further tightening
657 /// the search criteria to a use that kills the register if isKill is true.
658 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
659 const TargetRegisterInfo *TRI) const {
660 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
661 const MachineOperand &MO = getOperand(i);
662 if (!MO.isReg() || !MO.isUse())
664 unsigned MOReg = MO.getReg();
669 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
670 TargetRegisterInfo::isPhysicalRegister(Reg) &&
671 TRI->isSubRegister(MOReg, Reg)))
672 if (!isKill || MO.isKill())
678 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
679 /// the specified register or -1 if it is not found. If isDead is true, defs
680 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
681 /// also checks if there is a def of a super-register.
682 int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
683 const TargetRegisterInfo *TRI) const {
684 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
685 const MachineOperand &MO = getOperand(i);
686 if (!MO.isReg() || !MO.isDef())
688 unsigned MOReg = MO.getReg();
691 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
692 TargetRegisterInfo::isPhysicalRegister(Reg) &&
693 TRI->isSubRegister(MOReg, Reg)))
694 if (!isDead || MO.isDead())
700 /// findFirstPredOperandIdx() - Find the index of the first operand in the
701 /// operand list that is used to represent the predicate. It returns -1 if
703 int MachineInstr::findFirstPredOperandIdx() const {
704 const TargetInstrDesc &TID = getDesc();
705 if (TID.isPredicable()) {
706 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
707 if (TID.OpInfo[i].isPredicate())
714 /// isRegTiedToUseOperand - Given the index of a register def operand,
715 /// check if the register def is tied to a source operand, due to either
716 /// two-address elimination or inline assembly constraints. Returns the
717 /// first tied use operand index by reference is UseOpIdx is not null.
719 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
720 if (getOpcode() == TargetInstrInfo::INLINEASM) {
721 assert(DefOpIdx >= 2);
722 const MachineOperand &MO = getOperand(DefOpIdx);
723 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
725 // Determine the actual operand index that corresponds to this index.
727 unsigned DefPart = 0;
728 for (unsigned i = 1, e = getNumOperands(); i < e; ) {
729 const MachineOperand &FMO = getOperand(i);
730 // After the normal asm operands there may be additional imp-def regs.
733 // Skip over this def.
734 unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
735 unsigned PrevDef = i + 1;
736 i = PrevDef + NumOps;
738 DefPart = DefOpIdx - PrevDef;
743 for (unsigned i = 1, e = getNumOperands(); i != e; ++i) {
744 const MachineOperand &FMO = getOperand(i);
747 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
750 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
753 *UseOpIdx = (unsigned)i + 1 + DefPart;
760 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
761 const TargetInstrDesc &TID = getDesc();
762 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
763 const MachineOperand &MO = getOperand(i);
764 if (MO.isReg() && MO.isUse() &&
765 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
767 *UseOpIdx = (unsigned)i;
774 /// isRegTiedToDefOperand - Return true if the operand of the specified index
775 /// is a register use and it is tied to an def operand. It also returns the def
776 /// operand index by reference.
778 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
779 if (getOpcode() == TargetInstrInfo::INLINEASM) {
780 const MachineOperand &MO = getOperand(UseOpIdx);
781 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
784 // Find the flag operand corresponding to UseOpIdx
785 unsigned FlagIdx, NumOps=0;
786 for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
787 const MachineOperand &UFMO = getOperand(FlagIdx);
788 // After the normal asm operands there may be additional imp-def regs.
791 NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
792 assert(NumOps < getNumOperands() && "Invalid inline asm flag");
793 if (UseOpIdx < FlagIdx+NumOps+1)
796 if (FlagIdx >= UseOpIdx)
798 const MachineOperand &UFMO = getOperand(FlagIdx);
800 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
805 // Remember to adjust the index. First operand is asm string, then there
806 // is a flag for each.
808 const MachineOperand &FMO = getOperand(DefIdx);
810 // Skip over this def.
811 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
814 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
820 const TargetInstrDesc &TID = getDesc();
821 if (UseOpIdx >= TID.getNumOperands())
823 const MachineOperand &MO = getOperand(UseOpIdx);
824 if (!MO.isReg() || !MO.isUse())
826 int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
830 *DefOpIdx = (unsigned)DefIdx;
834 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
836 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
837 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
838 const MachineOperand &MO = MI->getOperand(i);
839 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
841 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
842 MachineOperand &MOp = getOperand(j);
843 if (!MOp.isIdenticalTo(MO))
854 /// copyPredicates - Copies predicate operand(s) from MI.
855 void MachineInstr::copyPredicates(const MachineInstr *MI) {
856 const TargetInstrDesc &TID = MI->getDesc();
857 if (!TID.isPredicable())
859 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
860 if (TID.OpInfo[i].isPredicate()) {
861 // Predicated operands must be last operands.
862 addOperand(MI->getOperand(i));
867 /// isSafeToMove - Return true if it is safe to move this instruction. If
868 /// SawStore is set to true, it means that there is a store (or call) between
869 /// the instruction's location and its intended destination.
870 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
871 bool &SawStore) const {
872 // Ignore stuff that we obviously can't move.
873 if (TID->mayStore() || TID->isCall()) {
877 if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
880 // See if this instruction does a load. If so, we have to guarantee that the
881 // loaded value doesn't change between the load and the its intended
882 // destination. The check for isInvariantLoad gives the targe the chance to
883 // classify the load as always returning a constant, e.g. a constant pool
885 if (TID->mayLoad() && !TII->isInvariantLoad(this))
886 // Otherwise, this is a real load. If there is a store between the load and
887 // end of block, or if the load is volatile, we can't move it.
888 return !SawStore && !hasVolatileMemoryRef();
893 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
894 /// instruction which defined the specified register instead of copying it.
895 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
896 unsigned DstReg) const {
897 bool SawStore = false;
898 if (!getDesc().isRematerializable() ||
899 !TII->isTriviallyReMaterializable(this) ||
900 !isSafeToMove(TII, SawStore))
902 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
903 const MachineOperand &MO = getOperand(i);
906 // FIXME: For now, do not remat any instruction with register operands.
907 // Later on, we can loosen the restriction is the register operands have
908 // not been modified between the def and use. Note, this is different from
909 // MachineSink because the code is no longer in two-address form (at least
913 else if (!MO.isDead() && MO.getReg() != DstReg)
919 /// hasVolatileMemoryRef - Return true if this instruction may have a
920 /// volatile memory reference, or if the information describing the
921 /// memory reference is not available. Return false if it is known to
922 /// have no volatile memory references.
923 bool MachineInstr::hasVolatileMemoryRef() const {
924 // An instruction known never to access memory won't have a volatile access.
925 if (!TID->mayStore() &&
928 !TID->hasUnmodeledSideEffects())
931 // Otherwise, if the instruction has no memory reference information,
932 // conservatively assume it wasn't preserved.
933 if (memoperands_empty())
936 // Check the memory reference information for volatile references.
937 for (std::list<MachineMemOperand>::const_iterator I = memoperands_begin(),
938 E = memoperands_end(); I != E; ++I)
945 void MachineInstr::dump() const {
946 errs() << " " << *this;
949 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
950 // Specialize printing if op#0 is definition
951 unsigned StartOp = 0;
952 if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
953 getOperand(0).print(OS, TM);
955 ++StartOp; // Don't print this operand again!
958 OS << getDesc().getName();
960 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
964 getOperand(i).print(OS, TM);
967 if (!memoperands_empty()) {
969 for (std::list<MachineMemOperand>::const_iterator i = memoperands_begin(),
970 e = memoperands_end(); i != e; ++i) {
971 const MachineMemOperand &MRO = *i;
972 const Value *V = MRO.getValue();
974 assert((MRO.isLoad() || MRO.isStore()) &&
975 "SV has to be a load, store or both.");
977 if (MRO.isVolatile())
985 OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
989 else if (!V->getName().empty())
991 else if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
996 OS << " + " << MRO.getOffset() << "]";
1000 if (!debugLoc.isUnknown()) {
1001 const MachineFunction *MF = getParent()->getParent();
1002 DebugLocTuple DLT = MF->getDebugLocTuple(debugLoc);
1003 DICompileUnit CU(DLT.CompileUnit);
1004 std::string Dir, Fn;
1006 << CU.getDirectory(Dir) << '/' << CU.getFilename(Fn) << ","
1014 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1015 const TargetRegisterInfo *RegInfo,
1016 bool AddIfNotFound) {
1017 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1018 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1020 SmallVector<unsigned,4> DeadOps;
1021 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1022 MachineOperand &MO = getOperand(i);
1023 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1025 unsigned Reg = MO.getReg();
1029 if (Reg == IncomingReg) {
1032 // The register is already marked kill.
1034 if (isPhysReg && isRegTiedToDefOperand(i))
1035 // Two-address uses of physregs must not be marked kill.
1040 } else if (hasAliases && MO.isKill() &&
1041 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1042 // A super-register kill already exists.
1043 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1045 if (RegInfo->isSubRegister(IncomingReg, Reg))
1046 DeadOps.push_back(i);
1050 // Trim unneeded kill operands.
1051 while (!DeadOps.empty()) {
1052 unsigned OpIdx = DeadOps.back();
1053 if (getOperand(OpIdx).isImplicit())
1054 RemoveOperand(OpIdx);
1056 getOperand(OpIdx).setIsKill(false);
1060 // If not found, this means an alias of one of the operands is killed. Add a
1061 // new implicit operand if required.
1062 if (!Found && AddIfNotFound) {
1063 addOperand(MachineOperand::CreateReg(IncomingReg,
1072 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1073 const TargetRegisterInfo *RegInfo,
1074 bool AddIfNotFound) {
1075 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1076 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1078 SmallVector<unsigned,4> DeadOps;
1079 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1080 MachineOperand &MO = getOperand(i);
1081 if (!MO.isReg() || !MO.isDef())
1083 unsigned Reg = MO.getReg();
1087 if (Reg == IncomingReg) {
1090 // The register is already marked dead.
1095 } else if (hasAliases && MO.isDead() &&
1096 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1097 // There exists a super-register that's marked dead.
1098 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1100 if (RegInfo->getSubRegisters(IncomingReg) &&
1101 RegInfo->getSuperRegisters(Reg) &&
1102 RegInfo->isSubRegister(IncomingReg, Reg))
1103 DeadOps.push_back(i);
1107 // Trim unneeded dead operands.
1108 while (!DeadOps.empty()) {
1109 unsigned OpIdx = DeadOps.back();
1110 if (getOperand(OpIdx).isImplicit())
1111 RemoveOperand(OpIdx);
1113 getOperand(OpIdx).setIsDead(false);
1117 // If not found, this means an alias of one of the operands is dead. Add a
1118 // new implicit operand if required.
1119 if (Found || !AddIfNotFound)
1122 addOperand(MachineOperand::CreateReg(IncomingReg,