1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 // FIXME: Now that MachineInstrs have parent pointers, they should always
13 // print themselves using their MachineFunction's TargetMachine.
15 //===----------------------------------------------------------------------===//
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Value.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/MRegisterInfo.h"
23 #include "llvm/Support/LeakDetector.h"
28 // Global variable holding an array of descriptors for machine instructions.
29 // The actual object needs to be created separately for each target machine.
30 // This variable is initialized and reset by class TargetInstrInfo.
32 // FIXME: This should be a property of the target so that more than one target
33 // at a time can be active...
36 extern const TargetInstrDescriptor *TargetInstrDescriptors;
39 // Constructor for instructions with variable #operands
40 MachineInstr::MachineInstr(short opcode, unsigned numOperands)
42 operands(numOperands, MachineOperand()),
44 // Make sure that we get added to a machine basicblock
45 LeakDetector::addGarbageObject(this);
48 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
49 /// not a resize for them. It is expected that if you use this that you call
50 /// add* methods below to fill up the operands, instead of the Set methods.
51 /// Eventually, the "resizing" ctors will be phased out.
53 MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY)
54 : Opcode(opcode), parent(0) {
55 operands.reserve(numOperands);
56 // Make sure that we get added to a machine basicblock
57 LeakDetector::addGarbageObject(this);
60 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
61 /// MachineInstr is created and added to the end of the specified basic block.
63 MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
65 : Opcode(opcode), parent(0) {
66 assert(MBB && "Cannot use inserting ctor with null basic block!");
67 operands.reserve(numOperands);
68 // Make sure that we get added to a machine basicblock
69 LeakDetector::addGarbageObject(this);
70 MBB->push_back(this); // Add instruction to end of basic block!
73 /// MachineInstr ctor - Copies MachineInstr arg exactly
75 MachineInstr::MachineInstr(const MachineInstr &MI) {
76 Opcode = MI.getOpcode();
77 operands.reserve(MI.getNumOperands());
80 for (unsigned i = 0; i < MI.getNumOperands(); ++i)
81 operands.push_back(MachineOperand(MI.getOperand(i)));
83 // Set parent, next, and prev to null
90 MachineInstr::~MachineInstr() {
91 LeakDetector::removeGarbageObject(this);
94 /// clone - Create a copy of 'this' instruction that is identical in all ways
95 /// except the following: the new instruction has no parent and it has no name
97 MachineInstr* MachineInstr::clone() const {
98 return new MachineInstr(*this);
101 /// removeFromParent - This method unlinks 'this' from the containing basic
102 /// block, and returns it, but does not delete it.
103 MachineInstr *MachineInstr::removeFromParent() {
104 assert(getParent() && "Not embedded in a basic block!");
105 getParent()->remove(this);
110 /// OperandComplete - Return true if it's illegal to add a new operand
112 bool MachineInstr::OperandsComplete() const {
113 int NumOperands = TargetInstrDescriptors[Opcode].numOperands;
114 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
115 return true; // Broken: we have all the operands of this instruction!
119 void MachineInstr::SetMachineOperandVal(unsigned i,
120 MachineOperand::MachineOperandType opTy,
122 assert(i < operands.size()); // may be explicit or implicit op
123 operands[i].opType = opTy;
124 operands[i].contents.value = V;
125 operands[i].extra.regNum = -1;
129 MachineInstr::SetMachineOperandConst(unsigned i,
130 MachineOperand::MachineOperandType opTy,
132 assert(i < getNumOperands()); // must be explicit op
133 assert(TargetInstrDescriptors[Opcode].resultPos != (int) i &&
134 "immed. constant cannot be defined");
136 operands[i].opType = opTy;
137 operands[i].contents.value = NULL;
138 operands[i].contents.immedVal = intValue;
139 operands[i].extra.regNum = -1;
140 operands[i].flags = 0;
143 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
144 assert(i < getNumOperands()); // must be explicit op
146 operands[i].opType = MachineOperand::MO_MachineRegister;
147 operands[i].contents.value = NULL;
148 operands[i].extra.regNum = regNum;
151 void MachineInstr::dump() const {
152 std::cerr << " " << *this;
155 static inline std::ostream& OutputValue(std::ostream &os, const Value* val) {
157 os << (void*) val; // print address always
158 if (val && val->hasName())
159 os << " " << val->getName(); // print name also, if available
164 static inline void OutputReg(std::ostream &os, unsigned RegNo,
165 const MRegisterInfo *MRI = 0) {
166 if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
168 os << "%" << MRI->get(RegNo).Name;
170 os << "%mreg(" << RegNo << ")";
172 os << "%reg" << RegNo;
175 static void print(const MachineOperand &MO, std::ostream &OS,
176 const TargetMachine *TM) {
177 const MRegisterInfo *MRI = 0;
179 if (TM) MRI = TM->getRegisterInfo();
181 bool CloseParen = true;
184 else if (MO.isLoBits32())
186 else if (MO.isHiBits64())
188 else if (MO.isLoBits64())
193 switch (MO.getType()) {
194 case MachineOperand::MO_VirtualRegister:
195 if (MO.getVRegValue()) {
197 OutputValue(OS, MO.getVRegValue());
198 if (MO.hasAllocatedReg())
201 if (MO.hasAllocatedReg())
202 OutputReg(OS, MO.getReg(), MRI);
204 case MachineOperand::MO_CCRegister:
206 OutputValue(OS, MO.getVRegValue());
207 if (MO.hasAllocatedReg()) {
209 OutputReg(OS, MO.getReg(), MRI);
212 case MachineOperand::MO_MachineRegister:
213 OutputReg(OS, MO.getMachineRegNum(), MRI);
215 case MachineOperand::MO_SignExtendedImmed:
216 OS << (long)MO.getImmedValue();
218 case MachineOperand::MO_UnextendedImmed:
219 OS << (long)MO.getImmedValue();
221 case MachineOperand::MO_PCRelativeDisp: {
222 const Value* opVal = MO.getVRegValue();
223 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
224 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
225 if (opVal->hasName())
226 OS << opVal->getName();
228 OS << (const void*) opVal;
232 case MachineOperand::MO_MachineBasicBlock:
234 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
235 << "," << (void*)MO.getMachineBasicBlock() << ">";
237 case MachineOperand::MO_FrameIndex:
238 OS << "<fi#" << MO.getFrameIndex() << ">";
240 case MachineOperand::MO_ConstantPoolIndex:
241 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
243 case MachineOperand::MO_GlobalAddress:
244 OS << "<ga:" << ((Value*)MO.getGlobal())->getName();
245 if (MO.getOffset()) OS << "+" << MO.getOffset();
248 case MachineOperand::MO_ExternalSymbol:
249 OS << "<es:" << MO.getSymbolName();
250 if (MO.getOffset()) OS << "+" << MO.getOffset();
254 assert(0 && "Unrecognized operand type");
261 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
262 unsigned StartOp = 0;
264 // Specialize printing if op#0 is definition
265 if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
266 ::print(getOperand(0), OS, TM);
268 ++StartOp; // Don't print this operand again!
271 // Must check if Target machine is not null because machine BB could not
272 // be attached to a Machine function yet
274 OS << TM->getInstrInfo()->getName(getOpcode());
276 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
277 const MachineOperand& mop = getOperand(i);
281 ::print(mop, OS, TM);
294 std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
295 // If the instruction is embedded into a basic block, we can find the target
296 // info for the instruction.
297 if (const MachineBasicBlock *MBB = MI.getParent()) {
298 const MachineFunction *MF = MBB->getParent();
300 MI.print(os, &MF->getTarget());
306 // Otherwise, print it out in the "raw" format without symbolic register names
308 os << TargetInstrDescriptors[MI.getOpcode()].Name;
310 for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) {
311 os << "\t" << MI.getOperand(i);
312 if (MI.getOperand(i).isDef())
313 if (MI.getOperand(i).isUse())
322 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
325 else if (MO.isLoBits32())
327 else if (MO.isHiBits64())
329 else if (MO.isLoBits64())
332 switch (MO.getType()) {
333 case MachineOperand::MO_VirtualRegister:
334 if (MO.hasAllocatedReg())
335 OutputReg(OS, MO.getReg());
337 if (MO.getVRegValue()) {
338 if (MO.hasAllocatedReg()) OS << "==";
340 OutputValue(OS, MO.getVRegValue());
343 case MachineOperand::MO_CCRegister:
345 OutputValue(OS, MO.getVRegValue());
346 if (MO.hasAllocatedReg()) {
348 OutputReg(OS, MO.getReg());
351 case MachineOperand::MO_MachineRegister:
352 OutputReg(OS, MO.getMachineRegNum());
354 case MachineOperand::MO_SignExtendedImmed:
355 OS << (long)MO.getImmedValue();
357 case MachineOperand::MO_UnextendedImmed:
358 OS << (long)MO.getImmedValue();
360 case MachineOperand::MO_PCRelativeDisp: {
361 const Value* opVal = MO.getVRegValue();
362 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
363 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
364 if (opVal->hasName())
365 OS << opVal->getName();
367 OS << (const void*) opVal;
371 case MachineOperand::MO_MachineBasicBlock:
373 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
374 << "@" << (void*)MO.getMachineBasicBlock() << ">";
376 case MachineOperand::MO_FrameIndex:
377 OS << "<fi#" << MO.getFrameIndex() << ">";
379 case MachineOperand::MO_ConstantPoolIndex:
380 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
382 case MachineOperand::MO_GlobalAddress:
383 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
385 case MachineOperand::MO_ExternalSymbol:
386 OS << "<es:" << MO.getSymbolName() << ">";
389 assert(0 && "Unrecognized operand type");
393 if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64())