1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 //===----------------------------------------------------------------------===//
5 #include "llvm/CodeGen/MachineInstr.h"
6 #include "llvm/CodeGen/MachineBasicBlock.h"
7 #include "llvm/Value.h"
8 #include "llvm/Target/TargetMachine.h"
9 #include "llvm/Target/TargetInstrInfo.h"
10 #include "llvm/Target/MRegisterInfo.h"
12 // Global variable holding an array of descriptors for machine instructions.
13 // The actual object needs to be created separately for each target machine.
14 // This variable is initialized and reset by class TargetInstrInfo.
16 // FIXME: This should be a property of the target so that more than one target
17 // at a time can be active...
19 extern const TargetInstrDescriptor *TargetInstrDescriptors;
21 // Constructor for instructions with variable #operands
22 MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
25 operands(numOperands, MachineOperand()),
30 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
31 /// not a resize for them. It is expected that if you use this that you call
32 /// add* methods below to fill up the operands, instead of the Set methods.
33 /// Eventually, the "resizing" ctors will be phased out.
35 MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
41 operands.reserve(numOperands);
44 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
45 /// MachineInstr is created and added to the end of the specified basic block.
47 MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
53 assert(MBB && "Cannot use inserting ctor with null basic block!");
54 operands.reserve(numOperands);
55 MBB->push_back(this); // Add instruction to end of basic block!
59 // OperandComplete - Return true if it's illegal to add a new operand
60 bool MachineInstr::OperandsComplete() const
62 int NumOperands = TargetInstrDescriptors[opCode].numOperands;
63 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
64 return true; // Broken: we have all the operands of this instruction!
70 // Support for replacing opcode and operands of a MachineInstr in place.
71 // This only resets the size of the operand vector and initializes it.
72 // The new operands must be set explicitly later.
74 void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
76 assert(getNumImplicitRefs() == 0 &&
77 "This is probably broken because implicit refs are going to be lost.");
80 operands.resize(numOperands, MachineOperand());
83 void MachineInstr::SetMachineOperandVal(unsigned i,
84 MachineOperand::MachineOperandType opTy,
86 assert(i < operands.size()); // may be explicit or implicit op
87 operands[i].opType = opTy;
88 operands[i].value = V;
89 operands[i].regNum = -1;
93 MachineInstr::SetMachineOperandConst(unsigned i,
94 MachineOperand::MachineOperandType operandType,
97 assert(i < getNumOperands()); // must be explicit op
98 assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
99 "immed. constant cannot be defined");
101 operands[i].opType = operandType;
102 operands[i].value = NULL;
103 operands[i].immedVal = intValue;
104 operands[i].regNum = -1;
105 operands[i].flags = 0;
108 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
109 assert(i < getNumOperands()); // must be explicit op
111 operands[i].opType = MachineOperand::MO_MachineRegister;
112 operands[i].value = NULL;
113 operands[i].regNum = regNum;
114 insertUsedReg(regNum);
118 MachineInstr::SetRegForOperand(unsigned i, int regNum)
120 assert(i < getNumOperands()); // must be explicit op
121 operands[i].setRegForValue(regNum);
122 insertUsedReg(regNum);
126 MachineInstr::SetRegForImplicitRef(unsigned i, int regNum)
128 getImplicitOp(i).setRegForValue(regNum);
129 insertUsedReg(regNum);
133 // Subsitute all occurrences of Value* oldVal with newVal in all operands
134 // and all implicit refs.
135 // If defsOnly == true, substitute defs only.
137 MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
138 bool defsOnly, bool notDefsAndUses,
139 bool& someArgsWereIgnored)
141 assert((defsOnly || !notDefsAndUses) &&
142 "notDefsAndUses is irrelevant if defsOnly == false.");
144 unsigned numSubst = 0;
146 // Subsitute operands
147 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
150 notDefsAndUses && O.isDefOnly() ||
151 !notDefsAndUses && !O.isUseOnly())
153 O.getMachineOperand().value = newVal;
157 someArgsWereIgnored = true;
159 // Subsitute implicit refs
160 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
161 if (getImplicitRef(i) == oldVal)
163 notDefsAndUses && getImplicitOp(i).opIsDefOnly() ||
164 !notDefsAndUses && !getImplicitOp(i).opIsUse())
166 getImplicitOp(i).value = newVal;
170 someArgsWereIgnored = true;
177 MachineInstr::dump() const
179 std::cerr << " " << *this;
182 static inline std::ostream&
183 OutputValue(std::ostream &os, const Value* val)
186 os << (void*) val; // print address always
187 if (val && val->hasName())
188 os << " " << val->getName() << ")"; // print name also, if available
192 static inline void OutputReg(std::ostream &os, unsigned RegNo,
193 const MRegisterInfo *MRI = 0) {
195 if (RegNo < MRegisterInfo::FirstVirtualRegister)
196 os << "%" << MRI->get(RegNo).Name;
198 os << "%reg" << RegNo;
200 os << "%mreg(" << RegNo << ")";
203 static void print(const MachineOperand &MO, std::ostream &OS,
204 const TargetMachine &TM) {
205 const MRegisterInfo *MRI = TM.getRegisterInfo();
206 bool CloseParen = true;
209 else if (MO.opLoBits32())
211 else if (MO.opHiBits64())
213 else if (MO.opLoBits64())
218 switch (MO.getType()) {
219 case MachineOperand::MO_VirtualRegister:
220 if (MO.getVRegValue()) {
222 OutputValue(OS, MO.getVRegValue());
223 if (MO.hasAllocatedReg())
226 if (MO.hasAllocatedReg())
227 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
229 case MachineOperand::MO_CCRegister:
231 OutputValue(OS, MO.getVRegValue());
232 if (MO.hasAllocatedReg()) {
234 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
237 case MachineOperand::MO_MachineRegister:
238 OutputReg(OS, MO.getMachineRegNum(), MRI);
240 case MachineOperand::MO_SignExtendedImmed:
241 OS << (long)MO.getImmedValue();
243 case MachineOperand::MO_UnextendedImmed:
244 OS << (long)MO.getImmedValue();
246 case MachineOperand::MO_PCRelativeDisp: {
247 const Value* opVal = MO.getVRegValue();
248 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
249 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
250 if (opVal->hasName())
251 OS << opVal->getName();
253 OS << (const void*) opVal;
257 case MachineOperand::MO_MachineBasicBlock:
259 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
260 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
262 case MachineOperand::MO_FrameIndex:
263 OS << "<fi#" << MO.getFrameIndex() << ">";
265 case MachineOperand::MO_ConstantPoolIndex:
266 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
268 case MachineOperand::MO_GlobalAddress:
269 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
271 case MachineOperand::MO_ExternalSymbol:
272 OS << "<es:" << MO.getSymbolName() << ">";
275 assert(0 && "Unrecognized operand type");
282 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
283 unsigned StartOp = 0;
285 // Specialize printing if op#0 is definition
286 if (getNumOperands() &&
287 (getOperand(0).opIsDefOnly() || getOperand(0).opIsDefAndUse())) {
288 ::print(getOperand(0), OS, TM);
290 ++StartOp; // Don't print this operand again!
292 OS << TM.getInstrInfo().getName(getOpcode());
294 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
295 const MachineOperand& mop = getOperand(i);
299 ::print(mop, OS, TM);
301 if (mop.opIsDefAndUse())
303 else if (mop.opIsDefOnly())
307 // code for printing implict references
308 if (getNumImplicitRefs()) {
309 OS << "\tImplicitRefs: ";
310 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
312 OutputValue(OS, getImplicitRef(i));
313 if (getImplicitOp(i).opIsDefAndUse())
315 else if (getImplicitOp(i).opIsDefOnly())
324 std::ostream &operator<<(std::ostream& os, const MachineInstr& MI)
326 os << TargetInstrDescriptors[MI.opCode].Name;
328 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
329 os << "\t" << MI.getOperand(i);
330 if (MI.getOperand(i).opIsDefOnly())
332 if (MI.getOperand(i).opIsDefAndUse())
336 // code for printing implict references
337 unsigned NumOfImpRefs = MI.getNumImplicitRefs();
338 if (NumOfImpRefs > 0) {
339 os << "\tImplicit: ";
340 for (unsigned z=0; z < NumOfImpRefs; z++) {
341 OutputValue(os, MI.getImplicitRef(z));
342 if (MI.getImplicitOp(z).opIsDefOnly()) os << "<d>";
343 if (MI.getImplicitOp(z).opIsDefAndUse()) os << "<d&u>";
351 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO)
355 else if (MO.opLoBits32())
357 else if (MO.opHiBits64())
359 else if (MO.opLoBits64())
362 switch (MO.getType())
364 case MachineOperand::MO_VirtualRegister:
365 if (MO.hasAllocatedReg())
366 OutputReg(OS, MO.getAllocatedRegNum());
368 if (MO.getVRegValue()) {
369 if (MO.hasAllocatedReg()) OS << "==";
371 OutputValue(OS, MO.getVRegValue());
374 case MachineOperand::MO_CCRegister:
376 OutputValue(OS, MO.getVRegValue());
377 if (MO.hasAllocatedReg()) {
379 OutputReg(OS, MO.getAllocatedRegNum());
382 case MachineOperand::MO_MachineRegister:
383 OutputReg(OS, MO.getMachineRegNum());
385 case MachineOperand::MO_SignExtendedImmed:
386 OS << (long)MO.getImmedValue();
388 case MachineOperand::MO_UnextendedImmed:
389 OS << (long)MO.getImmedValue();
391 case MachineOperand::MO_PCRelativeDisp:
393 const Value* opVal = MO.getVRegValue();
394 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
395 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
396 if (opVal->hasName())
397 OS << opVal->getName();
399 OS << (const void*) opVal;
403 case MachineOperand::MO_MachineBasicBlock:
405 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
406 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
408 case MachineOperand::MO_FrameIndex:
409 OS << "<fi#" << MO.getFrameIndex() << ">";
411 case MachineOperand::MO_ConstantPoolIndex:
412 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
414 case MachineOperand::MO_GlobalAddress:
415 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
417 case MachineOperand::MO_ExternalSymbol:
418 OS << "<es:" << MO.getSymbolName() << ">";
421 assert(0 && "Unrecognized operand type");
426 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
427 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))