1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Constants.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/Value.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/CodeGen/SelectionDAGNodes.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetInstrDesc.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Support/LeakDetector.h"
26 #include "llvm/Support/MathExtras.h"
27 #include "llvm/Support/Streams.h"
31 //===----------------------------------------------------------------------===//
32 // MachineOperand Implementation
33 //===----------------------------------------------------------------------===//
35 /// AddRegOperandToRegInfo - Add this register operand to the specified
36 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
37 /// explicitly nulled out.
38 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
39 assert(isReg() && "Can only add reg operand to use lists");
41 // If the reginfo pointer is null, just explicitly null out or next/prev
42 // pointers, to ensure they are not garbage.
44 Contents.Reg.Prev = 0;
45 Contents.Reg.Next = 0;
49 // Otherwise, add this operand to the head of the registers use/def list.
50 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
52 // For SSA values, we prefer to keep the definition at the start of the list.
53 // we do this by skipping over the definition if it is at the head of the
55 if (*Head && (*Head)->isDef())
56 Head = &(*Head)->Contents.Reg.Next;
58 Contents.Reg.Next = *Head;
59 if (Contents.Reg.Next) {
60 assert(getReg() == Contents.Reg.Next->getReg() &&
61 "Different regs on the same list!");
62 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
65 Contents.Reg.Prev = Head;
69 void MachineOperand::setReg(unsigned Reg) {
70 if (getReg() == Reg) return; // No change.
72 // Otherwise, we have to change the register. If this operand is embedded
73 // into a machine function, we need to update the old and new register's
75 if (MachineInstr *MI = getParent())
76 if (MachineBasicBlock *MBB = MI->getParent())
77 if (MachineFunction *MF = MBB->getParent()) {
78 RemoveRegOperandFromRegInfo();
79 Contents.Reg.RegNo = Reg;
80 AddRegOperandToRegInfo(&MF->getRegInfo());
84 // Otherwise, just change the register, no problem. :)
85 Contents.Reg.RegNo = Reg;
88 /// ChangeToImmediate - Replace this operand with a new immediate operand of
89 /// the specified value. If an operand is known to be an immediate already,
90 /// the setImm method should be used.
91 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
92 // If this operand is currently a register operand, and if this is in a
93 // function, deregister the operand from the register's use/def list.
94 if (isReg() && getParent() && getParent()->getParent() &&
95 getParent()->getParent()->getParent())
96 RemoveRegOperandFromRegInfo();
98 OpKind = MO_Immediate;
99 Contents.ImmVal = ImmVal;
102 /// ChangeToRegister - Replace this operand with a new register operand of
103 /// the specified value. If an operand is known to be an register already,
104 /// the setReg method should be used.
105 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
106 bool isKill, bool isDead) {
107 // If this operand is already a register operand, use setReg to update the
108 // register's use/def lists.
112 // Otherwise, change this to a register and set the reg#.
113 OpKind = MO_Register;
114 Contents.Reg.RegNo = Reg;
116 // If this operand is embedded in a function, add the operand to the
117 // register's use/def list.
118 if (MachineInstr *MI = getParent())
119 if (MachineBasicBlock *MBB = MI->getParent())
120 if (MachineFunction *MF = MBB->getParent())
121 AddRegOperandToRegInfo(&MF->getRegInfo());
131 /// isIdenticalTo - Return true if this operand is identical to the specified
133 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
134 if (getType() != Other.getType()) return false;
137 default: assert(0 && "Unrecognized operand type");
138 case MachineOperand::MO_Register:
139 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
140 getSubReg() == Other.getSubReg();
141 case MachineOperand::MO_Immediate:
142 return getImm() == Other.getImm();
143 case MachineOperand::MO_FPImmediate:
144 return getFPImm() == Other.getFPImm();
145 case MachineOperand::MO_MachineBasicBlock:
146 return getMBB() == Other.getMBB();
147 case MachineOperand::MO_FrameIndex:
148 return getIndex() == Other.getIndex();
149 case MachineOperand::MO_ConstantPoolIndex:
150 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
151 case MachineOperand::MO_JumpTableIndex:
152 return getIndex() == Other.getIndex();
153 case MachineOperand::MO_GlobalAddress:
154 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
155 case MachineOperand::MO_ExternalSymbol:
156 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
157 getOffset() == Other.getOffset();
161 /// print - Print the specified machine operand.
163 void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
165 case MachineOperand::MO_Register:
166 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
167 OS << "%reg" << getReg();
169 // If the instruction is embedded into a basic block, we can find the
170 // target info for the instruction.
172 if (const MachineInstr *MI = getParent())
173 if (const MachineBasicBlock *MBB = MI->getParent())
174 if (const MachineFunction *MF = MBB->getParent())
175 TM = &MF->getTarget();
178 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
180 OS << "%mreg" << getReg();
183 if (isDef() || isKill() || isDead() || isImplicit()) {
185 bool NeedComma = false;
187 OS << (isDef() ? "imp-def" : "imp-use");
189 } else if (isDef()) {
193 if (isKill() || isDead()) {
194 if (NeedComma) OS << ",";
195 if (isKill()) OS << "kill";
196 if (isDead()) OS << "dead";
201 case MachineOperand::MO_Immediate:
204 case MachineOperand::MO_FPImmediate:
205 if (getFPImm()->getType() == Type::FloatTy) {
206 OS << getFPImm()->getValueAPF().convertToFloat();
208 OS << getFPImm()->getValueAPF().convertToDouble();
211 case MachineOperand::MO_MachineBasicBlock:
213 << ((Value*)getMBB()->getBasicBlock())->getName()
214 << "," << (void*)getMBB() << ">";
216 case MachineOperand::MO_FrameIndex:
217 OS << "<fi#" << getIndex() << ">";
219 case MachineOperand::MO_ConstantPoolIndex:
220 OS << "<cp#" << getIndex();
221 if (getOffset()) OS << "+" << getOffset();
224 case MachineOperand::MO_JumpTableIndex:
225 OS << "<jt#" << getIndex() << ">";
227 case MachineOperand::MO_GlobalAddress:
228 OS << "<ga:" << ((Value*)getGlobal())->getName();
229 if (getOffset()) OS << "+" << getOffset();
232 case MachineOperand::MO_ExternalSymbol:
233 OS << "<es:" << getSymbolName();
234 if (getOffset()) OS << "+" << getOffset();
238 assert(0 && "Unrecognized operand type");
242 //===----------------------------------------------------------------------===//
243 // MachineMemOperand Implementation
244 //===----------------------------------------------------------------------===//
246 MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
247 int64_t o, uint64_t s, unsigned int a)
248 : Offset(o), Size(s), V(v),
249 Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
252 //===----------------------------------------------------------------------===//
253 // MachineInstr Implementation
254 //===----------------------------------------------------------------------===//
256 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
257 /// TID NULL and no operands.
258 MachineInstr::MachineInstr()
259 : TID(0), NumImplicitOps(0), Parent(0) {
260 // Make sure that we get added to a machine basicblock
261 LeakDetector::addGarbageObject(this);
264 void MachineInstr::addImplicitDefUseOperands() {
265 if (TID->ImplicitDefs)
266 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
267 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
268 if (TID->ImplicitUses)
269 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
270 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
273 /// MachineInstr ctor - This constructor create a MachineInstr and add the
274 /// implicit operands. It reserves space for number of operands specified by
275 /// TargetInstrDesc or the numOperands if it is not zero. (for
276 /// instructions with variable number of operands).
277 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
278 : TID(&tid), NumImplicitOps(0), Parent(0) {
279 if (!NoImp && TID->getImplicitDefs())
280 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
282 if (!NoImp && TID->getImplicitUses())
283 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
285 Operands.reserve(NumImplicitOps + TID->getNumOperands());
287 addImplicitDefUseOperands();
288 // Make sure that we get added to a machine basicblock
289 LeakDetector::addGarbageObject(this);
292 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
293 /// MachineInstr is created and added to the end of the specified basic block.
295 MachineInstr::MachineInstr(MachineBasicBlock *MBB,
296 const TargetInstrDesc &tid)
297 : TID(&tid), NumImplicitOps(0), Parent(0) {
298 assert(MBB && "Cannot use inserting ctor with null basic block!");
299 if (TID->ImplicitDefs)
300 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
302 if (TID->ImplicitUses)
303 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
305 Operands.reserve(NumImplicitOps + TID->getNumOperands());
306 addImplicitDefUseOperands();
307 // Make sure that we get added to a machine basicblock
308 LeakDetector::addGarbageObject(this);
309 MBB->push_back(this); // Add instruction to end of basic block!
312 /// MachineInstr ctor - Copies MachineInstr arg exactly
314 MachineInstr::MachineInstr(const MachineInstr &MI) {
316 NumImplicitOps = MI.NumImplicitOps;
317 Operands.reserve(MI.getNumOperands());
318 MemOperands = MI.MemOperands;
321 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
322 Operands.push_back(MI.getOperand(i));
323 Operands.back().ParentMI = this;
326 // Set parent, next, and prev to null
333 MachineInstr::~MachineInstr() {
334 LeakDetector::removeGarbageObject(this);
336 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
337 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
338 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
339 "Reg operand def/use list corrupted");
344 /// getOpcode - Returns the opcode of this MachineInstr.
346 int MachineInstr::getOpcode() const {
350 /// getRegInfo - If this instruction is embedded into a MachineFunction,
351 /// return the MachineRegisterInfo object for the current function, otherwise
353 MachineRegisterInfo *MachineInstr::getRegInfo() {
354 if (MachineBasicBlock *MBB = getParent())
355 if (MachineFunction *MF = MBB->getParent())
356 return &MF->getRegInfo();
360 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
361 /// this instruction from their respective use lists. This requires that the
362 /// operands already be on their use lists.
363 void MachineInstr::RemoveRegOperandsFromUseLists() {
364 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
365 if (Operands[i].isReg())
366 Operands[i].RemoveRegOperandFromRegInfo();
370 /// AddRegOperandsToUseLists - Add all of the register operands in
371 /// this instruction from their respective use lists. This requires that the
372 /// operands not be on their use lists yet.
373 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
374 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
375 if (Operands[i].isReg())
376 Operands[i].AddRegOperandToRegInfo(&RegInfo);
381 /// addOperand - Add the specified operand to the instruction. If it is an
382 /// implicit operand, it is added to the end of the operand list. If it is
383 /// an explicit operand it is added at the end of the explicit operand list
384 /// (before the first implicit operand).
385 void MachineInstr::addOperand(const MachineOperand &Op) {
386 bool isImpReg = Op.isReg() && Op.isImplicit();
387 assert((isImpReg || !OperandsComplete()) &&
388 "Trying to add an operand to a machine instr that is already done!");
390 // If we are adding the operand to the end of the list, our job is simpler.
391 // This is true most of the time, so this is a reasonable optimization.
392 if (isImpReg || NumImplicitOps == 0) {
393 // We can only do this optimization if we know that the operand list won't
395 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
396 Operands.push_back(Op);
398 // Set the parent of the operand.
399 Operands.back().ParentMI = this;
401 // If the operand is a register, update the operand's use list.
403 Operands.back().AddRegOperandToRegInfo(getRegInfo());
408 // Otherwise, we have to insert a real operand before any implicit ones.
409 unsigned OpNo = Operands.size()-NumImplicitOps;
411 MachineRegisterInfo *RegInfo = getRegInfo();
413 // If this instruction isn't embedded into a function, then we don't need to
414 // update any operand lists.
416 // Simple insertion, no reginfo update needed for other register operands.
417 Operands.insert(Operands.begin()+OpNo, Op);
418 Operands[OpNo].ParentMI = this;
420 // Do explicitly set the reginfo for this operand though, to ensure the
421 // next/prev fields are properly nulled out.
422 if (Operands[OpNo].isReg())
423 Operands[OpNo].AddRegOperandToRegInfo(0);
425 } else if (Operands.size()+1 <= Operands.capacity()) {
426 // Otherwise, we have to remove register operands from their register use
427 // list, add the operand, then add the register operands back to their use
428 // list. This also must handle the case when the operand list reallocates
429 // to somewhere else.
431 // If insertion of this operand won't cause reallocation of the operand
432 // list, just remove the implicit operands, add the operand, then re-add all
433 // the rest of the operands.
434 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
435 assert(Operands[i].isReg() && "Should only be an implicit reg!");
436 Operands[i].RemoveRegOperandFromRegInfo();
439 // Add the operand. If it is a register, add it to the reg list.
440 Operands.insert(Operands.begin()+OpNo, Op);
441 Operands[OpNo].ParentMI = this;
443 if (Operands[OpNo].isReg())
444 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
446 // Re-add all the implicit ops.
447 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
448 assert(Operands[i].isReg() && "Should only be an implicit reg!");
449 Operands[i].AddRegOperandToRegInfo(RegInfo);
452 // Otherwise, we will be reallocating the operand list. Remove all reg
453 // operands from their list, then readd them after the operand list is
455 RemoveRegOperandsFromUseLists();
457 Operands.insert(Operands.begin()+OpNo, Op);
458 Operands[OpNo].ParentMI = this;
460 // Re-add all the operands.
461 AddRegOperandsToUseLists(*RegInfo);
465 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
466 /// fewer operand than it started with.
468 void MachineInstr::RemoveOperand(unsigned OpNo) {
469 assert(OpNo < Operands.size() && "Invalid operand number");
471 // Special case removing the last one.
472 if (OpNo == Operands.size()-1) {
473 // If needed, remove from the reg def/use list.
474 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
475 Operands.back().RemoveRegOperandFromRegInfo();
481 // Otherwise, we are removing an interior operand. If we have reginfo to
482 // update, remove all operands that will be shifted down from their reg lists,
483 // move everything down, then re-add them.
484 MachineRegisterInfo *RegInfo = getRegInfo();
486 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
487 if (Operands[i].isReg())
488 Operands[i].RemoveRegOperandFromRegInfo();
492 Operands.erase(Operands.begin()+OpNo);
495 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
496 if (Operands[i].isReg())
497 Operands[i].AddRegOperandToRegInfo(RegInfo);
503 /// removeFromParent - This method unlinks 'this' from the containing basic
504 /// block, and returns it, but does not delete it.
505 MachineInstr *MachineInstr::removeFromParent() {
506 assert(getParent() && "Not embedded in a basic block!");
507 getParent()->remove(this);
512 /// OperandComplete - Return true if it's illegal to add a new operand
514 bool MachineInstr::OperandsComplete() const {
515 unsigned short NumOperands = TID->getNumOperands();
516 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
517 return true; // Broken: we have all the operands of this instruction!
521 /// getNumExplicitOperands - Returns the number of non-implicit operands.
523 unsigned MachineInstr::getNumExplicitOperands() const {
524 unsigned NumOperands = TID->getNumOperands();
525 if (!TID->isVariadic())
528 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
529 const MachineOperand &MO = getOperand(NumOperands);
530 if (!MO.isRegister() || !MO.isImplicit())
537 /// isLabel - Returns true if the MachineInstr represents a label.
539 bool MachineInstr::isLabel() const {
540 return getOpcode() == TargetInstrInfo::DBG_LABEL ||
541 getOpcode() == TargetInstrInfo::EH_LABEL ||
542 getOpcode() == TargetInstrInfo::GC_LABEL;
545 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
547 bool MachineInstr::isDebugLabel() const {
548 return getOpcode() == TargetInstrInfo::DBG_LABEL;
551 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
552 /// the specific register or -1 if it is not found. It further tightening
553 /// the search criteria to a use that kills the register if isKill is true.
554 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
555 const TargetRegisterInfo *TRI) const {
556 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
557 const MachineOperand &MO = getOperand(i);
558 if (!MO.isRegister() || !MO.isUse())
560 unsigned MOReg = MO.getReg();
565 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
566 TargetRegisterInfo::isPhysicalRegister(Reg) &&
567 TRI->isSubRegister(MOReg, Reg)))
568 if (!isKill || MO.isKill())
574 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
575 /// the specified register or -1 if it is not found. If isDead is true, defs
576 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
577 /// also checks if there is a def of a super-register.
578 int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
579 const TargetRegisterInfo *TRI) const {
580 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
581 const MachineOperand &MO = getOperand(i);
582 if (!MO.isRegister() || !MO.isDef())
584 unsigned MOReg = MO.getReg();
587 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
588 TargetRegisterInfo::isPhysicalRegister(Reg) &&
589 TRI->isSubRegister(MOReg, Reg)))
590 if (!isDead || MO.isDead())
596 /// findFirstPredOperandIdx() - Find the index of the first operand in the
597 /// operand list that is used to represent the predicate. It returns -1 if
599 int MachineInstr::findFirstPredOperandIdx() const {
600 const TargetInstrDesc &TID = getDesc();
601 if (TID.isPredicable()) {
602 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
603 if (TID.OpInfo[i].isPredicate())
610 /// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
611 /// to two addr elimination.
612 bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
613 const TargetInstrDesc &TID = getDesc();
614 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
615 const MachineOperand &MO1 = getOperand(i);
616 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
617 for (unsigned j = i+1; j < e; ++j) {
618 const MachineOperand &MO2 = getOperand(j);
619 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
620 TID.getOperandConstraint(j, TOI::TIED_TO) == (int)i)
628 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
630 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
631 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
632 const MachineOperand &MO = MI->getOperand(i);
633 if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
635 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
636 MachineOperand &MOp = getOperand(j);
637 if (!MOp.isIdenticalTo(MO))
648 /// copyPredicates - Copies predicate operand(s) from MI.
649 void MachineInstr::copyPredicates(const MachineInstr *MI) {
650 const TargetInstrDesc &TID = MI->getDesc();
651 if (!TID.isPredicable())
653 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
654 if (TID.OpInfo[i].isPredicate()) {
655 // Predicated operands must be last operands.
656 addOperand(MI->getOperand(i));
661 /// isSafeToMove - Return true if it is safe to move this instruction. If
662 /// SawStore is set to true, it means that there is a store (or call) between
663 /// the instruction's location and its intended destination.
664 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, bool &SawStore) {
665 // Ignore stuff that we obviously can't move.
666 if (TID->mayStore() || TID->isCall()) {
670 if (TID->isReturn() || TID->isBranch() || TID->hasUnmodeledSideEffects())
673 // See if this instruction does a load. If so, we have to guarantee that the
674 // loaded value doesn't change between the load and the its intended
675 // destination. The check for isInvariantLoad gives the targe the chance to
676 // classify the load as always returning a constant, e.g. a constant pool
678 if (TID->mayLoad() && !TII->isInvariantLoad(this)) {
679 // Otherwise, this is a real load. If there is a store between the load and
680 // end of block, we can't sink the load.
682 // FIXME: we can't do this transformation until we know that the load is
683 // not volatile, and machineinstrs don't keep this info. :(
691 void MachineInstr::dump() const {
692 cerr << " " << *this;
695 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
696 // Specialize printing if op#0 is definition
697 unsigned StartOp = 0;
698 if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
699 getOperand(0).print(OS, TM);
701 ++StartOp; // Don't print this operand again!
704 OS << getDesc().getName();
706 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
710 getOperand(i).print(OS, TM);
713 if (getNumMemOperands() > 0) {
715 for (unsigned i = 0; i < getNumMemOperands(); i++) {
716 const MachineMemOperand &MRO = getMemOperand(i);
717 const Value *V = MRO.getValue();
719 assert((MRO.isLoad() || MRO.isStore()) &&
720 "SV has to be a load, store or both.");
722 if (MRO.isVolatile())
730 OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
734 else if (!V->getName().empty())
736 else if (isa<PseudoSourceValue>(V))
741 OS << " + " << MRO.getOffset() << "]";
748 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
749 const TargetRegisterInfo *RegInfo,
750 bool AddIfNotFound) {
751 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
752 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
753 SmallVector<unsigned,4> DeadOps;
754 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
755 MachineOperand &MO = getOperand(i);
756 if (!MO.isRegister() || !MO.isUse())
758 unsigned Reg = MO.getReg();
762 if (Reg == IncomingReg) {
766 if (hasAliases && MO.isKill() &&
767 TargetRegisterInfo::isPhysicalRegister(Reg)) {
768 // A super-register kill already exists.
769 if (RegInfo->isSuperRegister(IncomingReg, Reg))
771 if (RegInfo->isSubRegister(IncomingReg, Reg))
772 DeadOps.push_back(i);
776 // Trim unneeded kill operands.
777 while (!DeadOps.empty()) {
778 unsigned OpIdx = DeadOps.back();
779 if (getOperand(OpIdx).isImplicit())
780 RemoveOperand(OpIdx);
782 getOperand(OpIdx).setIsKill(false);
786 // If not found, this means an alias of one of the operands is killed. Add a
787 // new implicit operand if required.
789 addOperand(MachineOperand::CreateReg(IncomingReg,
798 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
799 const TargetRegisterInfo *RegInfo,
800 bool AddIfNotFound) {
801 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
802 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
803 SmallVector<unsigned,4> DeadOps;
804 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
805 MachineOperand &MO = getOperand(i);
806 if (!MO.isRegister() || !MO.isDef())
808 unsigned Reg = MO.getReg();
809 if (Reg == IncomingReg) {
813 if (hasAliases && MO.isDead() &&
814 TargetRegisterInfo::isPhysicalRegister(Reg)) {
815 // There exists a super-register that's marked dead.
816 if (RegInfo->isSuperRegister(IncomingReg, Reg))
818 if (RegInfo->isSubRegister(IncomingReg, Reg))
819 DeadOps.push_back(i);
823 // Trim unneeded dead operands.
824 while (!DeadOps.empty()) {
825 unsigned OpIdx = DeadOps.back();
826 if (getOperand(OpIdx).isImplicit())
827 RemoveOperand(OpIdx);
829 getOperand(OpIdx).setIsDead(false);
833 // If not found, this means an alias of one of the operand is dead. Add a
834 // new implicit operand.
836 addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/,
837 true/*IsImp*/,false/*IsKill*/,