1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 //===----------------------------------------------------------------------===//
5 #include "llvm/CodeGen/MachineInstr.h"
6 #include "llvm/CodeGen/MachineBasicBlock.h"
7 #include "llvm/Value.h"
8 #include "llvm/Target/MachineInstrInfo.h" // FIXME: shouldn't need this!
9 #include "llvm/Target/TargetMachine.h"
12 // Global variable holding an array of descriptors for machine instructions.
13 // The actual object needs to be created separately for each target machine.
14 // This variable is initialized and reset by class MachineInstrInfo.
16 // FIXME: This should be a property of the target so that more than one target
17 // at a time can be active...
19 extern const MachineInstrDescriptor *TargetInstrDescriptors;
21 // Constructor for instructions with fixed #operands (nearly all)
22 MachineInstr::MachineInstr(MachineOpCode _opCode)
24 operands(TargetInstrDescriptors[_opCode].numOperands, MachineOperand()),
27 assert(TargetInstrDescriptors[_opCode].numOperands >= 0);
30 // Constructor for instructions with variable #operands
31 MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
33 operands(numOperands, MachineOperand()),
38 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
39 /// not a resize for them. It is expected that if you use this that you call
40 /// add* methods below to fill up the operands, instead of the Set methods.
41 /// Eventually, the "resizing" ctors will be phased out.
43 MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
48 operands.reserve(numOperands);
51 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
52 /// MachineInstr is created and added to the end of the specified basic block.
54 MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
59 assert(MBB && "Cannot use inserting ctor with null basic block!");
60 operands.reserve(numOperands);
61 MBB->push_back(this); // Add instruction to end of basic block!
65 // OperandComplete - Return true if it's illegal to add a new operand
66 bool MachineInstr::OperandsComplete() const
68 int NumOperands = TargetInstrDescriptors[opCode].numOperands;
69 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
70 return true; // Broken!
76 // Support for replacing opcode and operands of a MachineInstr in place.
77 // This only resets the size of the operand vector and initializes it.
78 // The new operands must be set explicitly later.
80 void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
82 assert(getNumImplicitRefs() == 0 &&
83 "This is probably broken because implicit refs are going to be lost.");
86 operands.resize(numOperands, MachineOperand());
90 MachineInstr::SetMachineOperandVal(unsigned i,
91 MachineOperand::MachineOperandType opType,
96 assert(i < operands.size()); // may be explicit or implicit op
97 operands[i].opType = opType;
98 operands[i].value = V;
99 operands[i].regNum = -1;
100 operands[i].flags = 0;
102 if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
103 operands[i].markDef();
105 operands[i].markDefAndUse();
109 MachineInstr::SetMachineOperandConst(unsigned i,
110 MachineOperand::MachineOperandType operandType,
113 assert(i < getNumOperands()); // must be explicit op
114 assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
115 "immed. constant cannot be defined");
117 operands[i].opType = operandType;
118 operands[i].value = NULL;
119 operands[i].immedVal = intValue;
120 operands[i].regNum = -1;
121 operands[i].flags = 0;
125 MachineInstr::SetMachineOperandReg(unsigned i,
128 assert(i < getNumOperands()); // must be explicit op
130 operands[i].opType = MachineOperand::MO_MachineRegister;
131 operands[i].value = NULL;
132 operands[i].regNum = regNum;
133 operands[i].flags = 0;
135 if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
136 operands[i].markDef();
137 insertUsedReg(regNum);
141 MachineInstr::SetRegForOperand(unsigned i, int regNum)
143 assert(i < getNumOperands()); // must be explicit op
144 operands[i].setRegForValue(regNum);
145 insertUsedReg(regNum);
149 // Subsitute all occurrences of Value* oldVal with newVal in all operands
150 // and all implicit refs. If defsOnly == true, substitute defs only.
152 MachineInstr::substituteValue(const Value* oldVal, Value* newVal, bool defsOnly)
154 unsigned numSubst = 0;
156 // Subsitute operands
157 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
159 if (!defsOnly || O.isDef())
161 O.getMachineOperand().value = newVal;
165 // Subsitute implicit refs
166 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
167 if (getImplicitRef(i) == oldVal)
168 if (!defsOnly || implicitRefIsDefined(i))
170 getImplicitOp(i).value = newVal;
179 MachineInstr::dump() const
181 cerr << " " << *this;
184 static inline std::ostream&
185 OutputValue(std::ostream &os, const Value* val)
188 if (val && val->hasName())
189 return os << val->getName() << ")";
191 return os << (void*) val << ")"; // print address only
194 static inline std::ostream&
195 OutputReg(std::ostream &os, unsigned int regNum)
197 return os << "%mreg(" << regNum << ")";
200 static void print(const MachineOperand &MO, std::ostream &OS,
201 const TargetMachine &TM) {
202 bool CloseParen = true;
205 else if (MO.opLoBits32())
207 else if (MO.opHiBits64())
209 else if (MO.opLoBits64())
214 switch (MO.getType()) {
215 case MachineOperand::MO_VirtualRegister:
216 if (MO.getVRegValue()) {
218 OutputValue(OS, MO.getVRegValue());
219 if (MO.hasAllocatedReg())
222 if (MO.hasAllocatedReg())
223 OutputReg(OS, MO.getAllocatedRegNum());
225 case MachineOperand::MO_CCRegister:
227 OutputValue(OS, MO.getVRegValue());
228 if (MO.hasAllocatedReg()) {
230 OutputReg(OS, MO.getAllocatedRegNum());
233 case MachineOperand::MO_MachineRegister:
234 OutputReg(OS, MO.getMachineRegNum());
236 case MachineOperand::MO_SignExtendedImmed:
237 OS << (long)MO.getImmedValue();
239 case MachineOperand::MO_UnextendedImmed:
240 OS << (long)MO.getImmedValue();
242 case MachineOperand::MO_PCRelativeDisp: {
243 const Value* opVal = MO.getVRegValue();
244 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
245 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
246 if (opVal->hasName())
247 OS << opVal->getName();
249 OS << (const void*) opVal;
254 assert(0 && "Unrecognized operand type");
261 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) {
262 OS << TM.getInstrInfo().getName(getOpcode());
263 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
265 ::print(getOperand(i), OS, TM);
267 if (operandIsDefinedAndUsed(i))
269 else if (operandIsDefined(i))
273 // code for printing implict references
274 if (getNumImplicitRefs()) {
275 OS << "\tImplicitRefs: ";
276 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
278 OutputValue(OS, getImplicitRef(i));
279 if (implicitRefIsDefinedAndUsed(i))
281 else if (implicitRefIsDefined(i))
290 std::ostream &operator<<(std::ostream& os, const MachineInstr& minstr)
292 os << TargetInstrDescriptors[minstr.opCode].Name;
294 for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++) {
295 os << "\t" << minstr.getOperand(i);
296 if( minstr.operandIsDefined(i) )
298 if( minstr.operandIsDefinedAndUsed(i) )
302 // code for printing implict references
303 unsigned NumOfImpRefs = minstr.getNumImplicitRefs();
304 if( NumOfImpRefs > 0 ) {
305 os << "\tImplicit: ";
306 for(unsigned z=0; z < NumOfImpRefs; z++) {
307 OutputValue(os, minstr.getImplicitRef(z));
308 if( minstr.implicitRefIsDefined(z)) os << "*";
309 if( minstr.implicitRefIsDefinedAndUsed(z)) os << "*";
317 std::ostream &operator<<(std::ostream &os, const MachineOperand &mop)
319 if (mop.opHiBits32())
321 else if (mop.opLoBits32())
323 else if (mop.opHiBits64())
325 else if (mop.opLoBits64())
328 switch (mop.getType())
330 case MachineOperand::MO_VirtualRegister:
332 OutputValue(os, mop.getVRegValue());
333 if (mop.hasAllocatedReg()) {
335 OutputReg(os, mop.getAllocatedRegNum());
338 case MachineOperand::MO_CCRegister:
340 OutputValue(os, mop.getVRegValue());
341 if (mop.hasAllocatedReg()) {
343 OutputReg(os, mop.getAllocatedRegNum());
346 case MachineOperand::MO_MachineRegister:
347 OutputReg(os, mop.getMachineRegNum());
349 case MachineOperand::MO_SignExtendedImmed:
350 os << (long)mop.getImmedValue();
352 case MachineOperand::MO_UnextendedImmed:
353 os << (long)mop.getImmedValue();
355 case MachineOperand::MO_PCRelativeDisp:
357 const Value* opVal = mop.getVRegValue();
358 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
359 os << "%disp(" << (isLabel? "label " : "addr-of-val ");
360 if (opVal->hasName())
361 os << opVal->getName();
363 os << (const void*) opVal;
368 assert(0 && "Unrecognized operand type");
373 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
374 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))