1 //===-- llvm/CodeGen/MachineBasicBlock.cpp ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Collect the sequence of machine instructions for a basic block.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineBasicBlock.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallString.h"
17 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
18 #include "llvm/CodeGen/LiveVariables.h"
19 #include "llvm/CodeGen/MachineDominators.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SlotIndexes.h"
25 #include "llvm/IR/BasicBlock.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/ModuleSlotTracker.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCContext.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/Format.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetRegisterInfo.h"
36 #include "llvm/Target/TargetSubtargetInfo.h"
40 #define DEBUG_TYPE "codegen"
42 MachineBasicBlock::MachineBasicBlock(MachineFunction &mf, const BasicBlock *bb)
43 : BB(bb), Number(-1), xParent(&mf) {
47 MachineBasicBlock::~MachineBasicBlock() {
50 /// Return the MCSymbol for this basic block.
51 MCSymbol *MachineBasicBlock::getSymbol() const {
52 if (!CachedMCSymbol) {
53 const MachineFunction *MF = getParent();
54 MCContext &Ctx = MF->getContext();
55 const char *Prefix = Ctx.getAsmInfo()->getPrivateLabelPrefix();
56 CachedMCSymbol = Ctx.getOrCreateSymbol(Twine(Prefix) + "BB" +
57 Twine(MF->getFunctionNumber()) +
58 "_" + Twine(getNumber()));
61 return CachedMCSymbol;
65 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) {
70 /// When an MBB is added to an MF, we need to update the parent pointer of the
71 /// MBB, the MBB numbering, and any instructions in the MBB to be on the right
72 /// operand list for registers.
74 /// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
75 /// gets the next available unique MBB number. If it is removed from a
76 /// MachineFunction, it goes back to being #-1.
77 void ilist_traits<MachineBasicBlock>::addNodeToList(MachineBasicBlock *N) {
78 MachineFunction &MF = *N->getParent();
79 N->Number = MF.addToMBBNumbering(N);
81 // Make sure the instructions have their operands in the reginfo lists.
82 MachineRegisterInfo &RegInfo = MF.getRegInfo();
83 for (MachineBasicBlock::instr_iterator
84 I = N->instr_begin(), E = N->instr_end(); I != E; ++I)
85 I->AddRegOperandsToUseLists(RegInfo);
88 void ilist_traits<MachineBasicBlock>::removeNodeFromList(MachineBasicBlock *N) {
89 N->getParent()->removeFromMBBNumbering(N->Number);
93 /// When we add an instruction to a basic block list, we update its parent
94 /// pointer and add its operands from reg use/def lists if appropriate.
95 void ilist_traits<MachineInstr>::addNodeToList(MachineInstr *N) {
96 assert(!N->getParent() && "machine instruction already in a basic block");
99 // Add the instruction's register operands to their corresponding
101 MachineFunction *MF = Parent->getParent();
102 N->AddRegOperandsToUseLists(MF->getRegInfo());
105 /// When we remove an instruction from a basic block list, we update its parent
106 /// pointer and remove its operands from reg use/def lists if appropriate.
107 void ilist_traits<MachineInstr>::removeNodeFromList(MachineInstr *N) {
108 assert(N->getParent() && "machine instruction not in a basic block");
110 // Remove from the use/def lists.
111 if (MachineFunction *MF = N->getParent()->getParent())
112 N->RemoveRegOperandsFromUseLists(MF->getRegInfo());
114 N->setParent(nullptr);
117 /// When moving a range of instructions from one MBB list to another, we need to
118 /// update the parent pointers and the use/def lists.
119 void ilist_traits<MachineInstr>::
120 transferNodesFromList(ilist_traits<MachineInstr> &fromList,
121 ilist_iterator<MachineInstr> first,
122 ilist_iterator<MachineInstr> last) {
123 assert(Parent->getParent() == fromList.Parent->getParent() &&
124 "MachineInstr parent mismatch!");
126 // Splice within the same MBB -> no change.
127 if (Parent == fromList.Parent) return;
129 // If splicing between two blocks within the same function, just update the
131 for (; first != last; ++first)
132 first->setParent(Parent);
135 void ilist_traits<MachineInstr>::deleteNode(MachineInstr* MI) {
136 assert(!MI->getParent() && "MI is still in a block!");
137 Parent->getParent()->DeleteMachineInstr(MI);
140 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonPHI() {
141 instr_iterator I = instr_begin(), E = instr_end();
142 while (I != E && I->isPHI())
144 assert((I == E || !I->isInsideBundle()) &&
145 "First non-phi MI cannot be inside a bundle!");
149 MachineBasicBlock::iterator
150 MachineBasicBlock::SkipPHIsAndLabels(MachineBasicBlock::iterator I) {
152 while (I != E && (I->isPHI() || I->isPosition() || I->isDebugValue()))
154 // FIXME: This needs to change if we wish to bundle labels / dbg_values
155 // inside the bundle.
156 assert((I == E || !I->isInsideBundle()) &&
157 "First non-phi / non-label instruction is inside a bundle!");
161 MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
162 iterator B = begin(), E = end(), I = E;
163 while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
165 while (I != E && !I->isTerminator())
170 MachineBasicBlock::instr_iterator MachineBasicBlock::getFirstInstrTerminator() {
171 instr_iterator B = instr_begin(), E = instr_end(), I = E;
172 while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
174 while (I != E && !I->isTerminator())
179 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonDebugInstr() {
180 // Skip over begin-of-block dbg_value instructions.
181 iterator I = begin(), E = end();
182 while (I != E && I->isDebugValue())
187 MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() {
188 // Skip over end-of-block dbg_value instructions.
189 instr_iterator B = instr_begin(), I = instr_end();
192 // Return instruction that starts a bundle.
193 if (I->isDebugValue() || I->isInsideBundle())
197 // The block is all debug values.
201 const MachineBasicBlock *MachineBasicBlock::getLandingPadSuccessor() const {
202 // A block with a landing pad successor only has one other successor.
205 for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
211 bool MachineBasicBlock::hasEHPadSuccessor() const {
212 for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
218 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
219 void MachineBasicBlock::dump() const {
224 StringRef MachineBasicBlock::getName() const {
225 if (const BasicBlock *LBB = getBasicBlock())
226 return LBB->getName();
231 /// Return a hopefully unique identifier for this block.
232 std::string MachineBasicBlock::getFullName() const {
235 Name = (getParent()->getName() + ":").str();
237 Name += getBasicBlock()->getName();
239 Name += ("BB" + Twine(getNumber())).str();
243 void MachineBasicBlock::print(raw_ostream &OS, SlotIndexes *Indexes) const {
244 const MachineFunction *MF = getParent();
246 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
250 const Function *F = MF->getFunction();
251 const Module *M = F ? F->getParent() : nullptr;
252 ModuleSlotTracker MST(M);
253 print(OS, MST, Indexes);
256 void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
257 SlotIndexes *Indexes) const {
258 const MachineFunction *MF = getParent();
260 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
266 OS << Indexes->getMBBStartIdx(this) << '\t';
268 OS << "BB#" << getNumber() << ": ";
270 const char *Comma = "";
271 if (const BasicBlock *LBB = getBasicBlock()) {
272 OS << Comma << "derived from LLVM BB ";
273 LBB->printAsOperand(OS, /*PrintType=*/false, MST);
276 if (isEHPad()) { OS << Comma << "EH LANDING PAD"; Comma = ", "; }
277 if (hasAddressTaken()) { OS << Comma << "ADDRESS TAKEN"; Comma = ", "; }
279 OS << Comma << "Align " << Alignment << " (" << (1u << Alignment)
284 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
285 if (!livein_empty()) {
286 if (Indexes) OS << '\t';
288 for (const auto &LI : make_range(livein_begin(), livein_end())) {
289 OS << ' ' << PrintReg(LI.PhysReg, TRI);
290 if (LI.LaneMask != ~0u)
291 OS << format(":%08X", LI.LaneMask);
295 // Print the preds of this block according to the CFG.
297 if (Indexes) OS << '\t';
298 OS << " Predecessors according to CFG:";
299 for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI)
300 OS << " BB#" << (*PI)->getNumber();
304 for (const_instr_iterator I = instr_begin(); I != instr_end(); ++I) {
306 if (Indexes->hasIndex(I))
307 OS << Indexes->getInstructionIndex(I);
311 if (I->isInsideBundle())
316 // Print the successors of this block according to the CFG.
318 if (Indexes) OS << '\t';
319 OS << " Successors according to CFG:";
320 for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI) {
321 OS << " BB#" << (*SI)->getNumber();
322 if (!Weights.empty())
323 OS << '(' << *getWeightIterator(SI) << ')';
329 void MachineBasicBlock::printAsOperand(raw_ostream &OS,
330 bool /*PrintType*/) const {
331 OS << "BB#" << getNumber();
334 void MachineBasicBlock::removeLiveIn(MCPhysReg Reg, unsigned LaneMask) {
335 LiveInVector::iterator I = std::find_if(
336 LiveIns.begin(), LiveIns.end(),
337 [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
338 if (I == LiveIns.end())
341 I->LaneMask &= ~LaneMask;
342 if (I->LaneMask == 0)
346 bool MachineBasicBlock::isLiveIn(MCPhysReg Reg, unsigned LaneMask) const {
347 livein_iterator I = std::find_if(
348 LiveIns.begin(), LiveIns.end(),
349 [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
350 return I != livein_end() && (I->LaneMask & LaneMask) != 0;
353 void MachineBasicBlock::sortUniqueLiveIns() {
354 std::sort(LiveIns.begin(), LiveIns.end(),
355 [](const RegisterMaskPair &LI0, const RegisterMaskPair &LI1) {
356 return LI0.PhysReg < LI1.PhysReg;
358 // Liveins are sorted by physreg now we can merge their lanemasks.
359 LiveInVector::const_iterator I = LiveIns.begin();
360 LiveInVector::const_iterator J;
361 LiveInVector::iterator Out = LiveIns.begin();
362 for (; I != LiveIns.end(); ++Out, I = J) {
363 unsigned PhysReg = I->PhysReg;
364 unsigned LaneMask = I->LaneMask;
365 for (J = std::next(I); J != LiveIns.end() && J->PhysReg == PhysReg; ++J)
366 LaneMask |= J->LaneMask;
367 Out->PhysReg = PhysReg;
368 Out->LaneMask = LaneMask;
370 LiveIns.erase(Out, LiveIns.end());
374 MachineBasicBlock::addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC) {
375 assert(getParent() && "MBB must be inserted in function");
376 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg");
377 assert(RC && "Register class is required");
378 assert((isEHPad() || this == &getParent()->front()) &&
379 "Only the entry block and landing pads can have physreg live ins");
381 bool LiveIn = isLiveIn(PhysReg);
382 iterator I = SkipPHIsAndLabels(begin()), E = end();
383 MachineRegisterInfo &MRI = getParent()->getRegInfo();
384 const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo();
386 // Look for an existing copy.
388 for (;I != E && I->isCopy(); ++I)
389 if (I->getOperand(1).getReg() == PhysReg) {
390 unsigned VirtReg = I->getOperand(0).getReg();
391 if (!MRI.constrainRegClass(VirtReg, RC))
392 llvm_unreachable("Incompatible live-in register class.");
396 // No luck, create a virtual register.
397 unsigned VirtReg = MRI.createVirtualRegister(RC);
398 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
399 .addReg(PhysReg, RegState::Kill);
405 void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) {
406 getParent()->splice(NewAfter, this);
409 void MachineBasicBlock::moveAfter(MachineBasicBlock *NewBefore) {
410 MachineFunction::iterator BBI = NewBefore;
411 getParent()->splice(++BBI, this);
414 void MachineBasicBlock::updateTerminator() {
415 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
416 // A block with no successors has no concerns with fall-through edges.
417 if (this->succ_empty()) return;
419 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
420 SmallVector<MachineOperand, 4> Cond;
421 DebugLoc dl; // FIXME: this is nowhere
422 bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond);
424 assert(!B && "UpdateTerminators requires analyzable predecessors!");
427 // The block has an unconditional branch. If its successor is now
428 // its layout successor, delete the branch.
429 if (isLayoutSuccessor(TBB))
430 TII->RemoveBranch(*this);
432 // The block has an unconditional fallthrough. If its successor is not
433 // its layout successor, insert a branch. First we have to locate the
434 // only non-landing-pad successor, as that is the fallthrough block.
435 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
436 if ((*SI)->isEHPad())
438 assert(!TBB && "Found more than one non-landing-pad successor!");
442 // If there is no non-landing-pad successor, the block has no
443 // fall-through edges to be concerned with.
447 // Finally update the unconditional successor to be reached via a branch
448 // if it would not be reached by fallthrough.
449 if (!isLayoutSuccessor(TBB))
450 TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
454 // The block has a non-fallthrough conditional branch. If one of its
455 // successors is its layout successor, rewrite it to a fallthrough
456 // conditional branch.
457 if (isLayoutSuccessor(TBB)) {
458 if (TII->ReverseBranchCondition(Cond))
460 TII->RemoveBranch(*this);
461 TII->InsertBranch(*this, FBB, nullptr, Cond, dl);
462 } else if (isLayoutSuccessor(FBB)) {
463 TII->RemoveBranch(*this);
464 TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
467 // Walk through the successors and find the successor which is not
468 // a landing pad and is not the conditional branch destination (in TBB)
469 // as the fallthrough successor.
470 MachineBasicBlock *FallthroughBB = nullptr;
471 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
472 if ((*SI)->isEHPad() || *SI == TBB)
474 assert(!FallthroughBB && "Found more than one fallthrough successor.");
477 if (!FallthroughBB && canFallThrough()) {
478 // We fallthrough to the same basic block as the conditional jump
479 // targets. Remove the conditional jump, leaving unconditional
481 // FIXME: This does not seem like a reasonable pattern to support, but
482 // it has been seen in the wild coming out of degenerate ARM test cases.
483 TII->RemoveBranch(*this);
485 // Finally update the unconditional successor to be reached via a branch
486 // if it would not be reached by fallthrough.
487 if (!isLayoutSuccessor(TBB))
488 TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
492 // The block has a fallthrough conditional branch.
493 if (isLayoutSuccessor(TBB)) {
494 if (TII->ReverseBranchCondition(Cond)) {
495 // We can't reverse the condition, add an unconditional branch.
497 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, dl);
500 TII->RemoveBranch(*this);
501 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, dl);
502 } else if (!isLayoutSuccessor(FallthroughBB)) {
503 TII->RemoveBranch(*this);
504 TII->InsertBranch(*this, TBB, FallthroughBB, Cond, dl);
510 void MachineBasicBlock::addSuccessor(MachineBasicBlock *succ, uint32_t weight) {
512 // If we see non-zero value for the first time it means we actually use Weight
513 // list, so we fill all Weights with 0's.
514 if (weight != 0 && Weights.empty())
515 Weights.resize(Successors.size());
517 if (weight != 0 || !Weights.empty())
518 Weights.push_back(weight);
520 Successors.push_back(succ);
521 succ->addPredecessor(this);
524 void MachineBasicBlock::removeSuccessor(MachineBasicBlock *succ) {
525 succ->removePredecessor(this);
526 succ_iterator I = std::find(Successors.begin(), Successors.end(), succ);
527 assert(I != Successors.end() && "Not a current successor!");
529 // If Weight list is empty it means we don't use it (disabled optimization).
530 if (!Weights.empty()) {
531 weight_iterator WI = getWeightIterator(I);
538 MachineBasicBlock::succ_iterator
539 MachineBasicBlock::removeSuccessor(succ_iterator I) {
540 assert(I != Successors.end() && "Not a current successor!");
542 // If Weight list is empty it means we don't use it (disabled optimization).
543 if (!Weights.empty()) {
544 weight_iterator WI = getWeightIterator(I);
548 (*I)->removePredecessor(this);
549 return Successors.erase(I);
552 void MachineBasicBlock::replaceSuccessor(MachineBasicBlock *Old,
553 MachineBasicBlock *New) {
557 succ_iterator E = succ_end();
558 succ_iterator NewI = E;
559 succ_iterator OldI = E;
560 for (succ_iterator I = succ_begin(); I != E; ++I) {
572 assert(OldI != E && "Old is not a successor of this block");
573 Old->removePredecessor(this);
575 // If New isn't already a successor, let it take Old's place.
577 New->addPredecessor(this);
582 // New is already a successor.
583 // Update its weight instead of adding a duplicate edge.
584 if (!Weights.empty()) {
585 weight_iterator OldWI = getWeightIterator(OldI);
586 *getWeightIterator(NewI) += *OldWI;
587 Weights.erase(OldWI);
589 Successors.erase(OldI);
592 void MachineBasicBlock::addPredecessor(MachineBasicBlock *pred) {
593 Predecessors.push_back(pred);
596 void MachineBasicBlock::removePredecessor(MachineBasicBlock *pred) {
597 pred_iterator I = std::find(Predecessors.begin(), Predecessors.end(), pred);
598 assert(I != Predecessors.end() && "Pred is not a predecessor of this block!");
599 Predecessors.erase(I);
602 void MachineBasicBlock::transferSuccessors(MachineBasicBlock *fromMBB) {
606 while (!fromMBB->succ_empty()) {
607 MachineBasicBlock *Succ = *fromMBB->succ_begin();
610 // If Weight list is empty it means we don't use it (disabled optimization).
611 if (!fromMBB->Weights.empty())
612 Weight = *fromMBB->Weights.begin();
614 addSuccessor(Succ, Weight);
615 fromMBB->removeSuccessor(Succ);
620 MachineBasicBlock::transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB) {
624 while (!fromMBB->succ_empty()) {
625 MachineBasicBlock *Succ = *fromMBB->succ_begin();
627 if (!fromMBB->Weights.empty())
628 Weight = *fromMBB->Weights.begin();
629 addSuccessor(Succ, Weight);
630 fromMBB->removeSuccessor(Succ);
632 // Fix up any PHI nodes in the successor.
633 for (MachineBasicBlock::instr_iterator MI = Succ->instr_begin(),
634 ME = Succ->instr_end(); MI != ME && MI->isPHI(); ++MI)
635 for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) {
636 MachineOperand &MO = MI->getOperand(i);
637 if (MO.getMBB() == fromMBB)
643 bool MachineBasicBlock::isPredecessor(const MachineBasicBlock *MBB) const {
644 return std::find(pred_begin(), pred_end(), MBB) != pred_end();
647 bool MachineBasicBlock::isSuccessor(const MachineBasicBlock *MBB) const {
648 return std::find(succ_begin(), succ_end(), MBB) != succ_end();
651 bool MachineBasicBlock::isLayoutSuccessor(const MachineBasicBlock *MBB) const {
652 MachineFunction::const_iterator I(this);
653 return std::next(I) == MachineFunction::const_iterator(MBB);
656 bool MachineBasicBlock::canFallThrough() {
657 MachineFunction::iterator Fallthrough = this;
659 // If FallthroughBlock is off the end of the function, it can't fall through.
660 if (Fallthrough == getParent()->end())
663 // If FallthroughBlock isn't a successor, no fallthrough is possible.
664 if (!isSuccessor(Fallthrough))
667 // Analyze the branches, if any, at the end of the block.
668 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
669 SmallVector<MachineOperand, 4> Cond;
670 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
671 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) {
672 // If we couldn't analyze the branch, examine the last instruction.
673 // If the block doesn't end in a known control barrier, assume fallthrough
674 // is possible. The isPredicated check is needed because this code can be
675 // called during IfConversion, where an instruction which is normally a
676 // Barrier is predicated and thus no longer an actual control barrier.
677 return empty() || !back().isBarrier() || TII->isPredicated(&back());
680 // If there is no branch, control always falls through.
681 if (!TBB) return true;
683 // If there is some explicit branch to the fallthrough block, it can obviously
684 // reach, even though the branch should get folded to fall through implicitly.
685 if (MachineFunction::iterator(TBB) == Fallthrough ||
686 MachineFunction::iterator(FBB) == Fallthrough)
689 // If it's an unconditional branch to some block not the fall through, it
690 // doesn't fall through.
691 if (Cond.empty()) return false;
693 // Otherwise, if it is conditional and has no explicit false block, it falls
695 return FBB == nullptr;
699 MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) {
700 // Splitting the critical edge to a landing pad block is non-trivial. Don't do
701 // it in this generic function.
705 MachineFunction *MF = getParent();
706 DebugLoc dl; // FIXME: this is nowhere
708 // Performance might be harmed on HW that implements branching using exec mask
709 // where both sides of the branches are always executed.
710 if (MF->getTarget().requiresStructuredCFG())
713 // We may need to update this's terminator, but we can't do that if
714 // AnalyzeBranch fails. If this uses a jump table, we won't touch it.
715 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
716 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
717 SmallVector<MachineOperand, 4> Cond;
718 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond))
721 // Avoid bugpoint weirdness: A block may end with a conditional branch but
722 // jumps to the same MBB is either case. We have duplicate CFG edges in that
723 // case that we can't handle. Since this never happens in properly optimized
724 // code, just skip those edges.
725 if (TBB && TBB == FBB) {
726 DEBUG(dbgs() << "Won't split critical edge after degenerate BB#"
727 << getNumber() << '\n');
731 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
732 MF->insert(std::next(MachineFunction::iterator(this)), NMBB);
733 DEBUG(dbgs() << "Splitting critical edge:"
734 " BB#" << getNumber()
735 << " -- BB#" << NMBB->getNumber()
736 << " -- BB#" << Succ->getNumber() << '\n');
738 LiveIntervals *LIS = P->getAnalysisIfAvailable<LiveIntervals>();
739 SlotIndexes *Indexes = P->getAnalysisIfAvailable<SlotIndexes>();
741 LIS->insertMBBInMaps(NMBB);
743 Indexes->insertMBBInMaps(NMBB);
745 // On some targets like Mips, branches may kill virtual registers. Make sure
746 // that LiveVariables is properly updated after updateTerminator replaces the
748 LiveVariables *LV = P->getAnalysisIfAvailable<LiveVariables>();
750 // Collect a list of virtual registers killed by the terminators.
751 SmallVector<unsigned, 4> KilledRegs;
753 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
755 MachineInstr *MI = I;
756 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
757 OE = MI->operands_end(); OI != OE; ++OI) {
758 if (!OI->isReg() || OI->getReg() == 0 ||
759 !OI->isUse() || !OI->isKill() || OI->isUndef())
761 unsigned Reg = OI->getReg();
762 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
763 LV->getVarInfo(Reg).removeKill(MI)) {
764 KilledRegs.push_back(Reg);
765 DEBUG(dbgs() << "Removing terminator kill: " << *MI);
766 OI->setIsKill(false);
771 SmallVector<unsigned, 4> UsedRegs;
773 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
775 MachineInstr *MI = I;
777 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
778 OE = MI->operands_end(); OI != OE; ++OI) {
779 if (!OI->isReg() || OI->getReg() == 0)
782 unsigned Reg = OI->getReg();
783 if (std::find(UsedRegs.begin(), UsedRegs.end(), Reg) == UsedRegs.end())
784 UsedRegs.push_back(Reg);
789 ReplaceUsesOfBlockWith(Succ, NMBB);
791 // If updateTerminator() removes instructions, we need to remove them from
793 SmallVector<MachineInstr*, 4> Terminators;
795 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
797 Terminators.push_back(I);
803 SmallVector<MachineInstr*, 4> NewTerminators;
804 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
806 NewTerminators.push_back(I);
808 for (SmallVectorImpl<MachineInstr*>::iterator I = Terminators.begin(),
809 E = Terminators.end(); I != E; ++I) {
810 if (std::find(NewTerminators.begin(), NewTerminators.end(), *I) ==
811 NewTerminators.end())
812 Indexes->removeMachineInstrFromMaps(*I);
816 // Insert unconditional "jump Succ" instruction in NMBB if necessary.
817 NMBB->addSuccessor(Succ);
818 if (!NMBB->isLayoutSuccessor(Succ)) {
820 TII->InsertBranch(*NMBB, Succ, nullptr, Cond, dl);
823 for (instr_iterator I = NMBB->instr_begin(), E = NMBB->instr_end();
825 // Some instructions may have been moved to NMBB by updateTerminator(),
826 // so we first remove any instruction that already has an index.
827 if (Indexes->hasIndex(I))
828 Indexes->removeMachineInstrFromMaps(I);
829 Indexes->insertMachineInstrInMaps(I);
834 // Fix PHI nodes in Succ so they refer to NMBB instead of this
835 for (MachineBasicBlock::instr_iterator
836 i = Succ->instr_begin(),e = Succ->instr_end();
837 i != e && i->isPHI(); ++i)
838 for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
839 if (i->getOperand(ni+1).getMBB() == this)
840 i->getOperand(ni+1).setMBB(NMBB);
842 // Inherit live-ins from the successor
843 for (const auto &LI : Succ->liveins())
846 // Update LiveVariables.
847 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
849 // Restore kills of virtual registers that were killed by the terminators.
850 while (!KilledRegs.empty()) {
851 unsigned Reg = KilledRegs.pop_back_val();
852 for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) {
853 if (!(--I)->addRegisterKilled(Reg, TRI, /* addIfNotFound= */ false))
855 if (TargetRegisterInfo::isVirtualRegister(Reg))
856 LV->getVarInfo(Reg).Kills.push_back(I);
857 DEBUG(dbgs() << "Restored terminator kill: " << *I);
861 // Update relevant live-through information.
862 LV->addNewBlock(NMBB, this, Succ);
866 // After splitting the edge and updating SlotIndexes, live intervals may be
867 // in one of two situations, depending on whether this block was the last in
868 // the function. If the original block was the last in the function, all
869 // live intervals will end prior to the beginning of the new split block. If
870 // the original block was not at the end of the function, all live intervals
871 // will extend to the end of the new split block.
874 std::next(MachineFunction::iterator(NMBB)) == getParent()->end();
876 SlotIndex StartIndex = Indexes->getMBBEndIdx(this);
877 SlotIndex PrevIndex = StartIndex.getPrevSlot();
878 SlotIndex EndIndex = Indexes->getMBBEndIdx(NMBB);
880 // Find the registers used from NMBB in PHIs in Succ.
881 SmallSet<unsigned, 8> PHISrcRegs;
882 for (MachineBasicBlock::instr_iterator
883 I = Succ->instr_begin(), E = Succ->instr_end();
884 I != E && I->isPHI(); ++I) {
885 for (unsigned ni = 1, ne = I->getNumOperands(); ni != ne; ni += 2) {
886 if (I->getOperand(ni+1).getMBB() == NMBB) {
887 MachineOperand &MO = I->getOperand(ni);
888 unsigned Reg = MO.getReg();
889 PHISrcRegs.insert(Reg);
893 LiveInterval &LI = LIS->getInterval(Reg);
894 VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
896 "PHI sources should be live out of their predecessors.");
897 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
902 MachineRegisterInfo *MRI = &getParent()->getRegInfo();
903 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
904 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
905 if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg))
908 LiveInterval &LI = LIS->getInterval(Reg);
909 if (!LI.liveAt(PrevIndex))
912 bool isLiveOut = LI.liveAt(LIS->getMBBStartIdx(Succ));
913 if (isLiveOut && isLastMBB) {
914 VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
915 assert(VNI && "LiveInterval should have VNInfo where it is live.");
916 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
917 } else if (!isLiveOut && !isLastMBB) {
918 LI.removeSegment(StartIndex, EndIndex);
922 // Update all intervals for registers whose uses may have been modified by
923 // updateTerminator().
924 LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs);
927 if (MachineDominatorTree *MDT =
928 P->getAnalysisIfAvailable<MachineDominatorTree>())
929 MDT->recordSplitCriticalEdge(this, Succ, NMBB);
931 if (MachineLoopInfo *MLI = P->getAnalysisIfAvailable<MachineLoopInfo>())
932 if (MachineLoop *TIL = MLI->getLoopFor(this)) {
933 // If one or the other blocks were not in a loop, the new block is not
934 // either, and thus LI doesn't need to be updated.
935 if (MachineLoop *DestLoop = MLI->getLoopFor(Succ)) {
936 if (TIL == DestLoop) {
937 // Both in the same loop, the NMBB joins loop.
938 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
939 } else if (TIL->contains(DestLoop)) {
940 // Edge from an outer loop to an inner loop. Add to the outer loop.
941 TIL->addBasicBlockToLoop(NMBB, MLI->getBase());
942 } else if (DestLoop->contains(TIL)) {
943 // Edge from an inner loop to an outer loop. Add to the outer loop.
944 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
946 // Edge from two loops with no containment relation. Because these
947 // are natural loops, we know that the destination block must be the
948 // header of its loop (adding a branch into a loop elsewhere would
949 // create an irreducible loop).
950 assert(DestLoop->getHeader() == Succ &&
951 "Should not create irreducible loops!");
952 if (MachineLoop *P = DestLoop->getParentLoop())
953 P->addBasicBlockToLoop(NMBB, MLI->getBase());
961 /// Prepare MI to be removed from its bundle. This fixes bundle flags on MI's
962 /// neighboring instructions so the bundle won't be broken by removing MI.
963 static void unbundleSingleMI(MachineInstr *MI) {
964 // Removing the first instruction in a bundle.
965 if (MI->isBundledWithSucc() && !MI->isBundledWithPred())
966 MI->unbundleFromSucc();
967 // Removing the last instruction in a bundle.
968 if (MI->isBundledWithPred() && !MI->isBundledWithSucc())
969 MI->unbundleFromPred();
970 // If MI is not bundled, or if it is internal to a bundle, the neighbor flags
974 MachineBasicBlock::instr_iterator
975 MachineBasicBlock::erase(MachineBasicBlock::instr_iterator I) {
977 return Insts.erase(I);
980 MachineInstr *MachineBasicBlock::remove_instr(MachineInstr *MI) {
981 unbundleSingleMI(MI);
982 MI->clearFlag(MachineInstr::BundledPred);
983 MI->clearFlag(MachineInstr::BundledSucc);
984 return Insts.remove(MI);
987 MachineBasicBlock::instr_iterator
988 MachineBasicBlock::insert(instr_iterator I, MachineInstr *MI) {
989 assert(!MI->isBundledWithPred() && !MI->isBundledWithSucc() &&
990 "Cannot insert instruction with bundle flags");
991 // Set the bundle flags when inserting inside a bundle.
992 if (I != instr_end() && I->isBundledWithPred()) {
993 MI->setFlag(MachineInstr::BundledPred);
994 MI->setFlag(MachineInstr::BundledSucc);
996 return Insts.insert(I, MI);
999 /// This method unlinks 'this' from the containing function, and returns it, but
1000 /// does not delete it.
1001 MachineBasicBlock *MachineBasicBlock::removeFromParent() {
1002 assert(getParent() && "Not embedded in a function!");
1003 getParent()->remove(this);
1007 /// This method unlinks 'this' from the containing function, and deletes it.
1008 void MachineBasicBlock::eraseFromParent() {
1009 assert(getParent() && "Not embedded in a function!");
1010 getParent()->erase(this);
1013 /// Given a machine basic block that branched to 'Old', change the code and CFG
1014 /// so that it branches to 'New' instead.
1015 void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old,
1016 MachineBasicBlock *New) {
1017 assert(Old != New && "Cannot replace self with self!");
1019 MachineBasicBlock::instr_iterator I = instr_end();
1020 while (I != instr_begin()) {
1022 if (!I->isTerminator()) break;
1024 // Scan the operands of this machine instruction, replacing any uses of Old
1026 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1027 if (I->getOperand(i).isMBB() &&
1028 I->getOperand(i).getMBB() == Old)
1029 I->getOperand(i).setMBB(New);
1032 // Update the successor information.
1033 replaceSuccessor(Old, New);
1036 /// Various pieces of code can cause excess edges in the CFG to be inserted. If
1037 /// we have proven that MBB can only branch to DestA and DestB, remove any other
1038 /// MBB successors from the CFG. DestA and DestB can be null.
1040 /// Besides DestA and DestB, retain other edges leading to LandingPads
1041 /// (currently there can be only one; we don't check or require that here).
1042 /// Note it is possible that DestA and/or DestB are LandingPads.
1043 bool MachineBasicBlock::CorrectExtraCFGEdges(MachineBasicBlock *DestA,
1044 MachineBasicBlock *DestB,
1046 // The values of DestA and DestB frequently come from a call to the
1047 // 'TargetInstrInfo::AnalyzeBranch' method. We take our meaning of the initial
1048 // values from there.
1050 // 1. If both DestA and DestB are null, then the block ends with no branches
1051 // (it falls through to its successor).
1052 // 2. If DestA is set, DestB is null, and isCond is false, then the block ends
1053 // with only an unconditional branch.
1054 // 3. If DestA is set, DestB is null, and isCond is true, then the block ends
1055 // with a conditional branch that falls through to a successor (DestB).
1056 // 4. If DestA and DestB is set and isCond is true, then the block ends with a
1057 // conditional branch followed by an unconditional branch. DestA is the
1058 // 'true' destination and DestB is the 'false' destination.
1060 bool Changed = false;
1062 MachineFunction::iterator FallThru =
1063 std::next(MachineFunction::iterator(this));
1065 if (!DestA && !DestB) {
1066 // Block falls through to successor.
1069 } else if (DestA && !DestB) {
1071 // Block ends in conditional jump that falls through to successor.
1074 assert(DestA && DestB && isCond &&
1075 "CFG in a bad state. Cannot correct CFG edges");
1078 // Remove superfluous edges. I.e., those which aren't destinations of this
1079 // basic block, duplicate edges, or landing pads.
1080 SmallPtrSet<const MachineBasicBlock*, 8> SeenMBBs;
1081 MachineBasicBlock::succ_iterator SI = succ_begin();
1082 while (SI != succ_end()) {
1083 const MachineBasicBlock *MBB = *SI;
1084 if (!SeenMBBs.insert(MBB).second ||
1085 (MBB != DestA && MBB != DestB && !MBB->isEHPad())) {
1086 // This is a superfluous edge, remove it.
1087 SI = removeSuccessor(SI);
1097 /// Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE
1098 /// instructions. Return UnknownLoc if there is none.
1100 MachineBasicBlock::findDebugLoc(instr_iterator MBBI) {
1102 instr_iterator E = instr_end();
1106 // Skip debug declarations, we don't want a DebugLoc from them.
1107 while (MBBI != E && MBBI->isDebugValue())
1110 DL = MBBI->getDebugLoc();
1114 /// Return weight of the edge from this block to MBB.
1115 uint32_t MachineBasicBlock::getSuccWeight(const_succ_iterator Succ) const {
1116 if (Weights.empty())
1119 return *getWeightIterator(Succ);
1122 /// Set successor weight of a given iterator.
1123 void MachineBasicBlock::setSuccWeight(succ_iterator I, uint32_t weight) {
1124 if (Weights.empty())
1126 *getWeightIterator(I) = weight;
1129 /// Return wight iterator corresonding to the I successor iterator.
1130 MachineBasicBlock::weight_iterator MachineBasicBlock::
1131 getWeightIterator(MachineBasicBlock::succ_iterator I) {
1132 assert(Weights.size() == Successors.size() && "Async weight list!");
1133 size_t index = std::distance(Successors.begin(), I);
1134 assert(index < Weights.size() && "Not a current successor!");
1135 return Weights.begin() + index;
1138 /// Return wight iterator corresonding to the I successor iterator.
1139 MachineBasicBlock::const_weight_iterator MachineBasicBlock::
1140 getWeightIterator(MachineBasicBlock::const_succ_iterator I) const {
1141 assert(Weights.size() == Successors.size() && "Async weight list!");
1142 const size_t index = std::distance(Successors.begin(), I);
1143 assert(index < Weights.size() && "Not a current successor!");
1144 return Weights.begin() + index;
1147 /// Return whether (physical) register "Reg" has been <def>ined and not <kill>ed
1148 /// as of just before "MI".
1150 /// Search is localised to a neighborhood of
1151 /// Neighborhood instructions before (searching for defs or kills) and N
1152 /// instructions after (searching just for defs) MI.
1153 MachineBasicBlock::LivenessQueryResult
1154 MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
1155 unsigned Reg, const_iterator Before,
1156 unsigned Neighborhood) const {
1157 unsigned N = Neighborhood;
1159 // Start by searching backwards from Before, looking for kills, reads or defs.
1160 const_iterator I(Before);
1161 // If this is the first insn in the block, don't search backwards.
1166 MachineOperandIteratorBase::PhysRegInfo Analysis =
1167 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
1169 if (Analysis.Defines)
1170 // Outputs happen after inputs so they take precedence if both are
1172 return Analysis.DefinesDead ? LQR_Dead : LQR_Live;
1174 if (Analysis.Kills || Analysis.Clobbers)
1175 // Register killed, so isn't live.
1178 else if (Analysis.ReadsOverlap)
1179 // Defined or read without a previous kill - live.
1180 return Analysis.Reads ? LQR_Live : LQR_OverlappingLive;
1182 } while (I != begin() && --N > 0);
1185 // Did we get to the start of the block?
1187 // If so, the register's state is definitely defined by the live-in state.
1188 for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true);
1189 RAI.isValid(); ++RAI) {
1191 return (*RAI == Reg) ? LQR_Live : LQR_OverlappingLive;
1199 // Try searching forwards from Before, looking for reads or defs.
1200 I = const_iterator(Before);
1201 // If this is the last insn in the block, don't search forwards.
1203 for (++I; I != end() && N > 0; ++I, --N) {
1204 MachineOperandIteratorBase::PhysRegInfo Analysis =
1205 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
1207 if (Analysis.ReadsOverlap)
1208 // Used, therefore must have been live.
1209 return (Analysis.Reads) ?
1210 LQR_Live : LQR_OverlappingLive;
1212 else if (Analysis.Clobbers || Analysis.Defines)
1213 // Defined (but not read) therefore cannot have been live.
1218 // At this point we have no idea of the liveness of the register.