1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/MIRYamlMapping.h"
24 #include "llvm/IR/BasicBlock.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/Instructions.h"
27 #include "llvm/IR/IRPrintingPasses.h"
28 #include "llvm/IR/Module.h"
29 #include "llvm/IR/ModuleSlotTracker.h"
30 #include "llvm/Support/MemoryBuffer.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Support/YAMLTraits.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetSubtargetInfo.h"
40 /// This structure describes how to print out stack object references.
41 struct FrameIndexOperand {
46 FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
47 : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
49 /// Return an ordinary stack object reference.
50 static FrameIndexOperand create(StringRef Name, unsigned ID) {
51 return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
54 /// Return a fixed stack object reference.
55 static FrameIndexOperand createFixed(unsigned ID) {
56 return FrameIndexOperand("", ID, /*IsFixed=*/true);
60 } // end anonymous namespace
64 /// This class prints out the machine functions using the MIR serialization
68 DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
69 /// Maps from stack object indices to operand indices which will be used when
70 /// printing frame index machine operands.
71 DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
74 MIRPrinter(raw_ostream &OS) : OS(OS) {}
76 void print(const MachineFunction &MF);
78 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
79 const TargetRegisterInfo *TRI);
80 void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
81 const MachineFrameInfo &MFI);
82 void convert(yaml::MachineFunction &MF,
83 const MachineConstantPool &ConstantPool);
84 void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
85 const MachineJumpTableInfo &JTI);
86 void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,
87 const MachineBasicBlock &MBB);
88 void convertStackObjects(yaml::MachineFunction &MF,
89 const MachineFrameInfo &MFI,
90 const TargetRegisterInfo *TRI);
93 void initRegisterMaskIds(const MachineFunction &MF);
96 } // end namespace llvm
100 /// This class prints out the machine instructions using the MIR serialization
104 ModuleSlotTracker &MST;
105 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
106 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
109 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
110 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
111 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
112 : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
113 StackObjectOperandMapping(StackObjectOperandMapping) {}
115 void print(const MachineInstr &MI);
116 void printMBBReference(const MachineBasicBlock &MBB);
117 void printIRBlockReference(const BasicBlock &BB);
118 void printIRValueReference(const Value &V);
119 void printStackObjectReference(int FrameIndex);
120 void printOffset(int64_t Offset);
121 void printTargetFlags(const MachineOperand &Op);
122 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
123 void print(const MachineMemOperand &Op);
125 void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
128 } // end anonymous namespace
133 /// This struct serializes the LLVM IR module.
134 template <> struct BlockScalarTraits<Module> {
135 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
136 Mod.print(OS, nullptr);
138 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
139 llvm_unreachable("LLVM Module is supposed to be parsed separately");
144 } // end namespace yaml
145 } // end namespace llvm
147 static void printReg(unsigned Reg, raw_ostream &OS,
148 const TargetRegisterInfo *TRI) {
149 // TODO: Print Stack Slots.
152 else if (TargetRegisterInfo::isVirtualRegister(Reg))
153 OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
154 else if (Reg < TRI->getNumRegs())
155 OS << '%' << StringRef(TRI->getName(Reg)).lower();
157 llvm_unreachable("Can't print this kind of register yet");
160 static void printReg(unsigned Reg, yaml::StringValue &Dest,
161 const TargetRegisterInfo *TRI) {
162 raw_string_ostream OS(Dest.Value);
163 printReg(Reg, OS, TRI);
166 void MIRPrinter::print(const MachineFunction &MF) {
167 initRegisterMaskIds(MF);
169 yaml::MachineFunction YamlMF;
170 YamlMF.Name = MF.getName();
171 YamlMF.Alignment = MF.getAlignment();
172 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
173 YamlMF.HasInlineAsm = MF.hasInlineAsm();
174 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
175 ModuleSlotTracker MST(MF.getFunction()->getParent());
176 MST.incorporateFunction(*MF.getFunction());
177 convert(MST, YamlMF.FrameInfo, *MF.getFrameInfo());
178 convertStackObjects(YamlMF, *MF.getFrameInfo(),
179 MF.getSubtarget().getRegisterInfo());
180 if (const auto *ConstantPool = MF.getConstantPool())
181 convert(YamlMF, *ConstantPool);
182 if (const auto *JumpTableInfo = MF.getJumpTableInfo())
183 convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
184 for (const auto &MBB : MF) {
185 yaml::MachineBasicBlock YamlMBB;
186 convert(MST, YamlMBB, MBB);
187 YamlMF.BasicBlocks.push_back(YamlMBB);
189 yaml::Output Out(OS);
193 void MIRPrinter::convert(yaml::MachineFunction &MF,
194 const MachineRegisterInfo &RegInfo,
195 const TargetRegisterInfo *TRI) {
196 MF.IsSSA = RegInfo.isSSA();
197 MF.TracksRegLiveness = RegInfo.tracksLiveness();
198 MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
200 // Print the virtual register definitions.
201 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
202 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
203 yaml::VirtualRegisterDefinition VReg;
206 StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
207 unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
209 printReg(PreferredReg, VReg.PreferredRegister, TRI);
210 MF.VirtualRegisters.push_back(VReg);
213 // Print the live ins.
214 for (auto I = RegInfo.livein_begin(), E = RegInfo.livein_end(); I != E; ++I) {
215 yaml::MachineFunctionLiveIn LiveIn;
216 printReg(I->first, LiveIn.Register, TRI);
218 printReg(I->second, LiveIn.VirtualRegister, TRI);
219 MF.LiveIns.push_back(LiveIn);
223 void MIRPrinter::convert(ModuleSlotTracker &MST,
224 yaml::MachineFrameInfo &YamlMFI,
225 const MachineFrameInfo &MFI) {
226 YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
227 YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
228 YamlMFI.HasStackMap = MFI.hasStackMap();
229 YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
230 YamlMFI.StackSize = MFI.getStackSize();
231 YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
232 YamlMFI.MaxAlignment = MFI.getMaxAlignment();
233 YamlMFI.AdjustsStack = MFI.adjustsStack();
234 YamlMFI.HasCalls = MFI.hasCalls();
235 YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
236 YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
237 YamlMFI.HasVAStart = MFI.hasVAStart();
238 YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
239 if (MFI.getSavePoint()) {
240 raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
241 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
242 .printMBBReference(*MFI.getSavePoint());
244 if (MFI.getRestorePoint()) {
245 raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
246 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
247 .printMBBReference(*MFI.getRestorePoint());
251 void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF,
252 const MachineFrameInfo &MFI,
253 const TargetRegisterInfo *TRI) {
254 // Process fixed stack objects.
256 for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
257 if (MFI.isDeadObjectIndex(I))
260 yaml::FixedMachineStackObject YamlObject;
262 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
263 ? yaml::FixedMachineStackObject::SpillSlot
264 : yaml::FixedMachineStackObject::DefaultType;
265 YamlObject.Offset = MFI.getObjectOffset(I);
266 YamlObject.Size = MFI.getObjectSize(I);
267 YamlObject.Alignment = MFI.getObjectAlignment(I);
268 YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
269 YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
270 MF.FixedStackObjects.push_back(YamlObject);
271 StackObjectOperandMapping.insert(
272 std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
275 // Process ordinary stack objects.
277 for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
278 if (MFI.isDeadObjectIndex(I))
281 yaml::MachineStackObject YamlObject;
283 if (const auto *Alloca = MFI.getObjectAllocation(I))
284 YamlObject.Name.Value =
285 Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
286 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
287 ? yaml::MachineStackObject::SpillSlot
288 : MFI.isVariableSizedObjectIndex(I)
289 ? yaml::MachineStackObject::VariableSized
290 : yaml::MachineStackObject::DefaultType;
291 YamlObject.Offset = MFI.getObjectOffset(I);
292 YamlObject.Size = MFI.getObjectSize(I);
293 YamlObject.Alignment = MFI.getObjectAlignment(I);
295 MF.StackObjects.push_back(YamlObject);
296 StackObjectOperandMapping.insert(std::make_pair(
297 I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
300 for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
301 yaml::StringValue Reg;
302 printReg(CSInfo.getReg(), Reg, TRI);
303 auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
304 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
305 "Invalid stack object index");
306 const FrameIndexOperand &StackObject = StackObjectInfo->second;
307 if (StackObject.IsFixed)
308 MF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
310 MF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
314 void MIRPrinter::convert(yaml::MachineFunction &MF,
315 const MachineConstantPool &ConstantPool) {
317 for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
318 // TODO: Serialize target specific constant pool entries.
319 if (Constant.isMachineConstantPoolEntry())
320 llvm_unreachable("Can't print target specific constant pool entries yet");
322 yaml::MachineConstantPoolValue YamlConstant;
324 raw_string_ostream StrOS(Str);
325 Constant.Val.ConstVal->printAsOperand(StrOS);
326 YamlConstant.ID = ID++;
327 YamlConstant.Value = StrOS.str();
328 YamlConstant.Alignment = Constant.getAlignment();
329 MF.Constants.push_back(YamlConstant);
333 void MIRPrinter::convert(ModuleSlotTracker &MST,
334 yaml::MachineJumpTable &YamlJTI,
335 const MachineJumpTableInfo &JTI) {
336 YamlJTI.Kind = JTI.getEntryKind();
338 for (const auto &Table : JTI.getJumpTables()) {
340 yaml::MachineJumpTable::Entry Entry;
342 for (const auto *MBB : Table.MBBs) {
343 raw_string_ostream StrOS(Str);
344 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
345 .printMBBReference(*MBB);
346 Entry.Blocks.push_back(StrOS.str());
349 YamlJTI.Entries.push_back(Entry);
353 void MIRPrinter::convert(ModuleSlotTracker &MST,
354 yaml::MachineBasicBlock &YamlMBB,
355 const MachineBasicBlock &MBB) {
356 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
357 YamlMBB.ID = (unsigned)MBB.getNumber();
358 if (const auto *BB = MBB.getBasicBlock()) {
360 YamlMBB.Name.Value = BB->getName();
362 int Slot = MST.getLocalSlot(BB);
364 YamlMBB.IRBlock.Value = "<badref>";
366 YamlMBB.IRBlock.Value = (Twine("%ir-block.") + Twine(Slot)).str();
369 YamlMBB.Alignment = MBB.getAlignment();
370 YamlMBB.AddressTaken = MBB.hasAddressTaken();
371 YamlMBB.IsLandingPad = MBB.isLandingPad();
372 for (const auto *SuccMBB : MBB.successors()) {
374 raw_string_ostream StrOS(Str);
375 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
376 .printMBBReference(*SuccMBB);
377 YamlMBB.Successors.push_back(StrOS.str());
379 if (MBB.hasSuccessorWeights()) {
380 for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I)
381 YamlMBB.SuccessorWeights.push_back(
382 yaml::UnsignedValue(MBB.getSuccWeight(I)));
384 // Print the live in registers.
385 const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
386 assert(TRI && "Expected target register info");
387 for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
389 raw_string_ostream StrOS(Str);
390 printReg(*I, StrOS, TRI);
391 YamlMBB.LiveIns.push_back(StrOS.str());
393 // Print the machine instructions.
394 YamlMBB.Instructions.reserve(MBB.size());
396 for (const auto &MI : MBB) {
397 raw_string_ostream StrOS(Str);
398 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping).print(MI);
399 YamlMBB.Instructions.push_back(StrOS.str());
404 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
405 const auto *TRI = MF.getSubtarget().getRegisterInfo();
407 for (const uint32_t *Mask : TRI->getRegMasks())
408 RegisterMaskIds.insert(std::make_pair(Mask, I++));
411 void MIPrinter::print(const MachineInstr &MI) {
412 const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
413 const auto *TRI = SubTarget.getRegisterInfo();
414 assert(TRI && "Expected target register info");
415 const auto *TII = SubTarget.getInstrInfo();
416 assert(TII && "Expected target instruction info");
417 if (MI.isCFIInstruction())
418 assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
420 unsigned I = 0, E = MI.getNumOperands();
421 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
422 !MI.getOperand(I).isImplicit();
426 print(MI.getOperand(I), TRI);
431 if (MI.getFlag(MachineInstr::FrameSetup))
432 OS << "frame-setup ";
433 OS << TII->getName(MI.getOpcode());
434 // TODO: Print the bundling instruction flags.
438 bool NeedComma = false;
442 print(MI.getOperand(I), TRI);
446 if (MI.getDebugLoc()) {
449 OS << " debug-location ";
450 MI.getDebugLoc()->printAsOperand(OS, MST);
453 if (!MI.memoperands_empty()) {
455 bool NeedComma = false;
456 for (const auto *Op : MI.memoperands()) {
465 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
466 OS << "%bb." << MBB.getNumber();
467 if (const auto *BB = MBB.getBasicBlock()) {
469 OS << '.' << BB->getName();
473 void MIPrinter::printIRBlockReference(const BasicBlock &BB) {
476 printLLVMNameWithoutPrefix(OS, BB.getName());
479 const Function *F = BB.getParent();
481 if (F == MST.getCurrentFunction()) {
482 Slot = MST.getLocalSlot(&BB);
484 ModuleSlotTracker CustomMST(F->getParent(),
485 /*ShouldInitializeAllMetadata=*/false);
486 CustomMST.incorporateFunction(*F);
487 Slot = CustomMST.getLocalSlot(&BB);
495 void MIPrinter::printIRValueReference(const Value &V) {
498 printLLVMNameWithoutPrefix(OS, V.getName());
501 // TODO: Serialize the unnamed IR value references.
502 OS << "<unserializable ir value>";
505 void MIPrinter::printStackObjectReference(int FrameIndex) {
506 auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
507 assert(ObjectInfo != StackObjectOperandMapping.end() &&
508 "Invalid frame index");
509 const FrameIndexOperand &Operand = ObjectInfo->second;
510 if (Operand.IsFixed) {
511 OS << "%fixed-stack." << Operand.ID;
514 OS << "%stack." << Operand.ID;
515 if (!Operand.Name.empty())
516 OS << '.' << Operand.Name;
519 void MIPrinter::printOffset(int64_t Offset) {
523 OS << " - " << -Offset;
526 OS << " + " << Offset;
529 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
530 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
531 for (const auto &I : Flags) {
539 void MIPrinter::printTargetFlags(const MachineOperand &Op) {
540 if (!Op.getTargetFlags())
543 Op.getParent()->getParent()->getParent()->getSubtarget().getInstrInfo();
544 assert(TII && "expected instruction info");
545 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
546 OS << "target-flags(";
547 if (const auto *Name = getTargetFlagName(TII, Flags.first))
550 OS << "<unknown target flag>";
551 // TODO: Print the target's bit flags.
555 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
556 const auto *TII = MF.getSubtarget().getInstrInfo();
557 assert(TII && "expected instruction info");
558 auto Indices = TII->getSerializableTargetIndices();
559 for (const auto &I : Indices) {
560 if (I.first == Index) {
567 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
568 printTargetFlags(Op);
569 switch (Op.getType()) {
570 case MachineOperand::MO_Register:
571 // TODO: Print the other register flags.
573 OS << (Op.isDef() ? "implicit-def " : "implicit ");
580 if (Op.isEarlyClobber())
581 OS << "early-clobber ";
584 printReg(Op.getReg(), OS, TRI);
585 // Print the sub register.
586 if (Op.getSubReg() != 0)
587 OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());
589 case MachineOperand::MO_Immediate:
592 case MachineOperand::MO_CImmediate:
593 Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
595 case MachineOperand::MO_FPImmediate:
596 Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
598 case MachineOperand::MO_MachineBasicBlock:
599 printMBBReference(*Op.getMBB());
601 case MachineOperand::MO_FrameIndex:
602 printStackObjectReference(Op.getIndex());
604 case MachineOperand::MO_ConstantPoolIndex:
605 OS << "%const." << Op.getIndex();
606 printOffset(Op.getOffset());
608 case MachineOperand::MO_TargetIndex: {
609 OS << "target-index(";
610 if (const auto *Name = getTargetIndexName(
611 *Op.getParent()->getParent()->getParent(), Op.getIndex()))
616 printOffset(Op.getOffset());
619 case MachineOperand::MO_JumpTableIndex:
620 OS << "%jump-table." << Op.getIndex();
622 case MachineOperand::MO_ExternalSymbol:
624 printLLVMNameWithoutPrefix(OS, Op.getSymbolName());
625 printOffset(Op.getOffset());
627 case MachineOperand::MO_GlobalAddress:
628 Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
629 printOffset(Op.getOffset());
631 case MachineOperand::MO_BlockAddress:
632 OS << "blockaddress(";
633 Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
636 printIRBlockReference(*Op.getBlockAddress()->getBasicBlock());
638 printOffset(Op.getOffset());
640 case MachineOperand::MO_RegisterMask: {
641 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
642 if (RegMaskInfo != RegisterMaskIds.end())
643 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
645 llvm_unreachable("Can't print this machine register mask yet.");
648 case MachineOperand::MO_Metadata:
649 Op.getMetadata()->printAsOperand(OS, MST);
651 case MachineOperand::MO_CFIIndex: {
652 const auto &MMI = Op.getParent()->getParent()->getParent()->getMMI();
653 print(MMI.getFrameInstructions()[Op.getCFIIndex()], TRI);
657 // TODO: Print the other machine operands.
658 llvm_unreachable("Can't print this machine operand at the moment");
662 void MIPrinter::print(const MachineMemOperand &Op) {
664 // TODO: Print operand's target specific flags.
667 if (Op.isNonTemporal())
668 OS << "non-temporal ";
669 if (Op.isInvariant())
674 assert(Op.isStore() && "Non load machine operand must be a store");
677 OS << Op.getSize() << (Op.isLoad() ? " from " : " into ");
678 if (const Value *Val = Op.getValue())
679 printIRValueReference(*Val);
680 // TODO: Print PseudoSourceValue.
681 printOffset(Op.getOffset());
682 if (Op.getBaseAlignment() != Op.getSize())
683 OS << ", align " << Op.getBaseAlignment();
684 // TODO: Print the metadata attributes.
688 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
689 const TargetRegisterInfo *TRI) {
690 int Reg = TRI->getLLVMRegNum(DwarfReg, true);
695 printReg(Reg, OS, TRI);
698 void MIPrinter::print(const MCCFIInstruction &CFI,
699 const TargetRegisterInfo *TRI) {
700 switch (CFI.getOperation()) {
701 case MCCFIInstruction::OpOffset:
702 OS << ".cfi_offset ";
705 printCFIRegister(CFI.getRegister(), OS, TRI);
706 OS << ", " << CFI.getOffset();
708 case MCCFIInstruction::OpDefCfaRegister:
709 OS << ".cfi_def_cfa_register ";
712 printCFIRegister(CFI.getRegister(), OS, TRI);
714 case MCCFIInstruction::OpDefCfaOffset:
715 OS << ".cfi_def_cfa_offset ";
718 OS << CFI.getOffset();
720 case MCCFIInstruction::OpDefCfa:
721 OS << ".cfi_def_cfa ";
724 printCFIRegister(CFI.getRegister(), OS, TRI);
725 OS << ", " << CFI.getOffset();
728 // TODO: Print the other CFI Operations.
729 OS << "<unserializable cfi operation>";
734 void llvm::printMIR(raw_ostream &OS, const Module &M) {
735 yaml::Output Out(OS);
736 Out << const_cast<Module &>(M);
739 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
740 MIRPrinter Printer(OS);