1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/MIRYamlMapping.h"
21 #include "llvm/IR/BasicBlock.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/IR/ModuleSlotTracker.h"
24 #include "llvm/Support/MemoryBuffer.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Support/YAMLTraits.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetSubtargetInfo.h"
34 /// This class prints out the machine functions using the MIR serialization
38 DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
41 MIRPrinter(raw_ostream &OS) : OS(OS) {}
43 void print(const MachineFunction &MF);
45 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
46 const TargetRegisterInfo *TRI);
47 void convert(yaml::MachineFrameInfo &YamlMFI, const MachineFrameInfo &MFI);
48 void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,
49 const MachineBasicBlock &MBB);
50 void convertStackObjects(yaml::MachineFunction &MF,
51 const MachineFrameInfo &MFI);
54 void initRegisterMaskIds(const MachineFunction &MF);
57 /// This class prints out the machine instructions using the MIR serialization
61 ModuleSlotTracker &MST;
62 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
65 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
66 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds)
67 : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds) {}
69 void print(const MachineInstr &MI);
70 void printMBBReference(const MachineBasicBlock &MBB);
71 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
74 } // end anonymous namespace
79 /// This struct serializes the LLVM IR module.
80 template <> struct BlockScalarTraits<Module> {
81 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
82 Mod.print(OS, nullptr);
84 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
85 llvm_unreachable("LLVM Module is supposed to be parsed separately");
90 } // end namespace yaml
91 } // end namespace llvm
93 void MIRPrinter::print(const MachineFunction &MF) {
94 initRegisterMaskIds(MF);
96 yaml::MachineFunction YamlMF;
97 YamlMF.Name = MF.getName();
98 YamlMF.Alignment = MF.getAlignment();
99 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
100 YamlMF.HasInlineAsm = MF.hasInlineAsm();
101 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
102 convert(YamlMF.FrameInfo, *MF.getFrameInfo());
103 convertStackObjects(YamlMF, *MF.getFrameInfo());
106 ModuleSlotTracker MST(MF.getFunction()->getParent());
107 for (const auto &MBB : MF) {
108 // TODO: Allow printing of non sequentially numbered MBBs.
109 // This is currently needed as the basic block references get their index
110 // from MBB.getNumber(), thus it should be sequential so that the parser can
111 // map back to the correct MBBs when parsing the output.
112 assert(MBB.getNumber() == I++ &&
113 "Can't print MBBs that aren't sequentially numbered");
115 yaml::MachineBasicBlock YamlMBB;
116 convert(MST, YamlMBB, MBB);
117 YamlMF.BasicBlocks.push_back(YamlMBB);
119 yaml::Output Out(OS);
123 void MIRPrinter::convert(yaml::MachineFunction &MF,
124 const MachineRegisterInfo &RegInfo,
125 const TargetRegisterInfo *TRI) {
126 MF.IsSSA = RegInfo.isSSA();
127 MF.TracksRegLiveness = RegInfo.tracksLiveness();
128 MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
130 // Print the virtual register definitions.
131 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
132 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
133 yaml::VirtualRegisterDefinition VReg;
136 StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
137 MF.VirtualRegisters.push_back(VReg);
141 void MIRPrinter::convert(yaml::MachineFrameInfo &YamlMFI,
142 const MachineFrameInfo &MFI) {
143 YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
144 YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
145 YamlMFI.HasStackMap = MFI.hasStackMap();
146 YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
147 YamlMFI.StackSize = MFI.getStackSize();
148 YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
149 YamlMFI.MaxAlignment = MFI.getMaxAlignment();
150 YamlMFI.AdjustsStack = MFI.adjustsStack();
151 YamlMFI.HasCalls = MFI.hasCalls();
152 YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
153 YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
154 YamlMFI.HasVAStart = MFI.hasVAStart();
155 YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
158 void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF,
159 const MachineFrameInfo &MFI) {
160 // Process fixed stack objects.
162 for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
163 if (MFI.isDeadObjectIndex(I))
166 yaml::FixedMachineStackObject YamlObject;
167 YamlObject.ID = ID++;
168 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
169 ? yaml::FixedMachineStackObject::SpillSlot
170 : yaml::FixedMachineStackObject::DefaultType;
171 YamlObject.Offset = MFI.getObjectOffset(I);
172 YamlObject.Size = MFI.getObjectSize(I);
173 YamlObject.Alignment = MFI.getObjectAlignment(I);
174 YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
175 YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
176 MF.FixedStackObjects.push_back(YamlObject);
177 // TODO: Store the mapping between fixed object IDs and object indices to
178 // print the fixed stack object references correctly.
181 // Process ordinary stack objects.
183 for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
184 if (MFI.isDeadObjectIndex(I))
187 yaml::MachineStackObject YamlObject;
188 YamlObject.ID = ID++;
189 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
190 ? yaml::MachineStackObject::SpillSlot
191 : MFI.isVariableSizedObjectIndex(I)
192 ? yaml::MachineStackObject::VariableSized
193 : yaml::MachineStackObject::DefaultType;
194 YamlObject.Offset = MFI.getObjectOffset(I);
195 YamlObject.Size = MFI.getObjectSize(I);
196 YamlObject.Alignment = MFI.getObjectAlignment(I);
198 MF.StackObjects.push_back(YamlObject);
199 // TODO: Store the mapping between object IDs and object indices to print
200 // the stack object references correctly.
204 void MIRPrinter::convert(ModuleSlotTracker &MST,
205 yaml::MachineBasicBlock &YamlMBB,
206 const MachineBasicBlock &MBB) {
207 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
208 YamlMBB.ID = (unsigned)MBB.getNumber();
209 // TODO: Serialize unnamed BB references.
210 if (const auto *BB = MBB.getBasicBlock())
211 YamlMBB.Name.Value = BB->hasName() ? BB->getName() : "<unnamed bb>";
213 YamlMBB.Name.Value = "";
214 YamlMBB.Alignment = MBB.getAlignment();
215 YamlMBB.AddressTaken = MBB.hasAddressTaken();
216 YamlMBB.IsLandingPad = MBB.isLandingPad();
217 for (const auto *SuccMBB : MBB.successors()) {
219 raw_string_ostream StrOS(Str);
220 MIPrinter(StrOS, MST, RegisterMaskIds).printMBBReference(*SuccMBB);
221 YamlMBB.Successors.push_back(StrOS.str());
224 // Print the machine instructions.
225 YamlMBB.Instructions.reserve(MBB.size());
227 for (const auto &MI : MBB) {
228 raw_string_ostream StrOS(Str);
229 MIPrinter(StrOS, MST, RegisterMaskIds).print(MI);
230 YamlMBB.Instructions.push_back(StrOS.str());
235 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
236 const auto *TRI = MF.getSubtarget().getRegisterInfo();
238 for (const uint32_t *Mask : TRI->getRegMasks())
239 RegisterMaskIds.insert(std::make_pair(Mask, I++));
242 void MIPrinter::print(const MachineInstr &MI) {
243 const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
244 const auto *TRI = SubTarget.getRegisterInfo();
245 assert(TRI && "Expected target register info");
246 const auto *TII = SubTarget.getInstrInfo();
247 assert(TII && "Expected target instruction info");
249 unsigned I = 0, E = MI.getNumOperands();
250 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
251 !MI.getOperand(I).isImplicit();
255 print(MI.getOperand(I), TRI);
260 OS << TII->getName(MI.getOpcode());
261 // TODO: Print the instruction flags, machine mem operands.
265 bool NeedComma = false;
269 print(MI.getOperand(I), TRI);
274 static void printReg(unsigned Reg, raw_ostream &OS,
275 const TargetRegisterInfo *TRI) {
276 // TODO: Print Stack Slots.
279 else if (TargetRegisterInfo::isVirtualRegister(Reg))
280 OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
281 else if (Reg < TRI->getNumRegs())
282 OS << '%' << StringRef(TRI->getName(Reg)).lower();
284 llvm_unreachable("Can't print this kind of register yet");
287 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
288 OS << "%bb." << MBB.getNumber();
289 if (const auto *BB = MBB.getBasicBlock()) {
291 OS << '.' << BB->getName();
295 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
296 switch (Op.getType()) {
297 case MachineOperand::MO_Register:
298 // TODO: Print the other register flags.
300 OS << (Op.isDef() ? "implicit-def " : "implicit ");
307 printReg(Op.getReg(), OS, TRI);
308 // Print the sub register.
309 if (Op.getSubReg() != 0)
310 OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());
312 case MachineOperand::MO_Immediate:
315 case MachineOperand::MO_MachineBasicBlock:
316 printMBBReference(*Op.getMBB());
318 case MachineOperand::MO_GlobalAddress:
319 Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
320 // TODO: Print offset and target flags.
322 case MachineOperand::MO_RegisterMask: {
323 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
324 if (RegMaskInfo != RegisterMaskIds.end())
325 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
327 llvm_unreachable("Can't print this machine register mask yet.");
331 // TODO: Print the other machine operands.
332 llvm_unreachable("Can't print this machine operand at the moment");
336 void llvm::printMIR(raw_ostream &OS, const Module &M) {
337 yaml::Output Out(OS);
338 Out << const_cast<Module &>(M);
341 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
342 MIRPrinter Printer(OS);