1 //===- MIParser.cpp - Machine instructions parser implementation ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the parsing of machine instructions.
12 //===----------------------------------------------------------------------===//
16 #include "llvm/ADT/StringMap.h"
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "llvm/Support/SourceMgr.h"
22 #include "llvm/Target/TargetSubtargetInfo.h"
23 #include "llvm/Target/TargetInstrInfo.h"
33 StringRef Source, CurrentSource;
35 /// Maps from instruction names to op codes.
36 StringMap<unsigned> Names2InstrOpCodes;
37 /// Maps from register names to registers.
38 StringMap<unsigned> Names2Regs;
41 MIParser(SourceMgr &SM, MachineFunction &MF, SMDiagnostic &Error,
46 /// Report an error at the current location with the given message.
48 /// This function always return true.
49 bool error(const Twine &Msg);
51 /// Report an error at the given location with the given message.
53 /// This function always return true.
54 bool error(StringRef::iterator Loc, const Twine &Msg);
56 MachineInstr *parse();
58 bool parseRegister(unsigned &Reg);
59 bool parseRegisterOperand(MachineOperand &Dest, bool IsDef = false);
60 bool parseMachineOperand(MachineOperand &Dest);
63 void initNames2InstrOpCodes();
65 /// Try to convert an instruction name to an opcode. Return true if the
66 /// instruction name is invalid.
67 bool parseInstrName(StringRef InstrName, unsigned &OpCode);
69 bool parseInstruction(unsigned &OpCode);
71 void initNames2Regs();
73 /// Try to convert a register name to a register number. Return true if the
74 /// register name is invalid.
75 bool getRegisterByName(StringRef RegName, unsigned &Reg);
78 } // end anonymous namespace
80 MIParser::MIParser(SourceMgr &SM, MachineFunction &MF, SMDiagnostic &Error,
82 : SM(SM), MF(MF), Error(Error), Source(Source), CurrentSource(Source),
83 Token(MIToken::Error, StringRef()) {}
85 void MIParser::lex() {
86 CurrentSource = lexMIToken(
88 [this](StringRef::iterator Loc, const Twine &Msg) { error(Loc, Msg); });
91 bool MIParser::error(const Twine &Msg) { return error(Token.location(), Msg); }
93 bool MIParser::error(StringRef::iterator Loc, const Twine &Msg) {
94 // TODO: Get the proper location in the MIR file, not just a location inside
96 assert(Loc >= Source.data() && Loc <= (Source.data() + Source.size()));
99 SM.getMemoryBuffer(SM.getMainFileID())->getBufferIdentifier(), 1,
100 Loc - Source.data(), SourceMgr::DK_Error, Msg.str(), Source, None, None);
104 MachineInstr *MIParser::parse() {
107 // Parse any register operands before '='
108 // TODO: Allow parsing of multiple operands before '='
109 MachineOperand MO = MachineOperand::CreateImm(0);
110 SmallVector<MachineOperand, 8> Operands;
111 if (Token.isRegister()) {
112 if (parseRegisterOperand(MO, /*IsDef=*/true))
114 Operands.push_back(MO);
115 if (Token.isNot(MIToken::equal)) {
116 error("expected '='");
123 if (Token.isError() || parseInstruction(OpCode))
126 // TODO: Parse the instruction flags and memory operands.
128 // Parse the remaining machine operands.
129 while (Token.isNot(MIToken::Eof)) {
130 if (parseMachineOperand(MO))
132 Operands.push_back(MO);
133 if (Token.is(MIToken::Eof))
135 if (Token.isNot(MIToken::comma)) {
136 error("expected ',' before the next machine operand");
142 const auto &MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
144 // Verify machine operands.
145 if (!MCID.isVariadic()) {
146 for (size_t I = 0, E = Operands.size(); I < E; ++I) {
147 if (I < MCID.getNumOperands())
149 // Mark this register as implicit to prevent an assertion when it's added
150 // to an instruction. This is a temporary workaround until the implicit
151 // register flag can be parsed.
152 Operands[I].setImplicit();
156 // TODO: Determine the implicit behaviour when implicit register flags are
158 auto *MI = MF.CreateMachineInstr(MCID, DebugLoc(), /*NoImplicit=*/true);
159 for (const auto &Operand : Operands)
160 MI->addOperand(MF, Operand);
164 bool MIParser::parseInstruction(unsigned &OpCode) {
165 if (Token.isNot(MIToken::Identifier))
166 return error("expected a machine instruction");
167 StringRef InstrName = Token.stringValue();
168 if (parseInstrName(InstrName, OpCode))
169 return error(Twine("unknown machine instruction name '") + InstrName + "'");
174 bool MIParser::parseRegister(unsigned &Reg) {
175 switch (Token.kind()) {
176 case MIToken::NamedRegister: {
177 StringRef Name = Token.stringValue().drop_front(1); // Drop the '%'
178 if (getRegisterByName(Name, Reg))
179 return error(Twine("unknown register name '") + Name + "'");
182 // TODO: Parse other register kinds.
184 llvm_unreachable("The current token should be a register");
189 bool MIParser::parseRegisterOperand(MachineOperand &Dest, bool IsDef) {
191 // TODO: Parse register flags.
192 if (parseRegister(Reg))
195 // TODO: Parse subregister.
196 Dest = MachineOperand::CreateReg(Reg, IsDef);
200 bool MIParser::parseMachineOperand(MachineOperand &Dest) {
201 switch (Token.kind()) {
202 case MIToken::NamedRegister:
203 return parseRegisterOperand(Dest);
207 // TODO: parse the other machine operands.
208 return error("expected a machine operand");
213 void MIParser::initNames2InstrOpCodes() {
214 if (!Names2InstrOpCodes.empty())
216 const auto *TII = MF.getSubtarget().getInstrInfo();
217 assert(TII && "Expected target instruction info");
218 for (unsigned I = 0, E = TII->getNumOpcodes(); I < E; ++I)
219 Names2InstrOpCodes.insert(std::make_pair(StringRef(TII->getName(I)), I));
222 bool MIParser::parseInstrName(StringRef InstrName, unsigned &OpCode) {
223 initNames2InstrOpCodes();
224 auto InstrInfo = Names2InstrOpCodes.find(InstrName);
225 if (InstrInfo == Names2InstrOpCodes.end())
227 OpCode = InstrInfo->getValue();
231 void MIParser::initNames2Regs() {
232 if (!Names2Regs.empty())
234 const auto *TRI = MF.getSubtarget().getRegisterInfo();
235 assert(TRI && "Expected target register info");
236 for (unsigned I = 0, E = TRI->getNumRegs(); I < E; ++I) {
238 Names2Regs.insert(std::make_pair(StringRef(TRI->getName(I)).lower(), I))
241 assert(WasInserted && "Expected registers to be unique case-insensitively");
245 bool MIParser::getRegisterByName(StringRef RegName, unsigned &Reg) {
247 auto RegInfo = Names2Regs.find(RegName);
248 if (RegInfo == Names2Regs.end())
250 Reg = RegInfo->getValue();
254 MachineInstr *llvm::parseMachineInstr(SourceMgr &SM, MachineFunction &MF,
255 StringRef Src, SMDiagnostic &Error) {
256 return MIParser(SM, MF, Error, Src).parse();