1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a MachineFunction pass which runs after register
11 // allocation that turns subreg insert/extract instructions into register
12 // copies, as needed. This ensures correct codegen even if the coalescer
13 // isn't able to remove all subreg instructions.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "lowersubregs"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/raw_ostream.h"
32 struct LowerSubregsInstructionPass : public MachineFunctionPass {
34 const TargetRegisterInfo *TRI;
35 const TargetInstrInfo *TII;
38 static char ID; // Pass identification, replacement for typeid
39 LowerSubregsInstructionPass() : MachineFunctionPass(&ID) {}
41 const char *getPassName() const {
42 return "Subregister lowering instruction pass";
45 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
47 AU.addPreservedID(MachineLoopInfoID);
48 AU.addPreservedID(MachineDominatorsID);
49 MachineFunctionPass::getAnalysisUsage(AU);
52 /// runOnMachineFunction - pass entry point
53 bool runOnMachineFunction(MachineFunction&);
56 bool LowerExtract(MachineInstr *MI);
57 bool LowerInsert(MachineInstr *MI);
58 bool LowerSubregToReg(MachineInstr *MI);
59 bool LowerCopy(MachineInstr *MI);
61 void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
62 const TargetRegisterInfo *TRI);
63 void TransferKillFlag(MachineInstr *MI, unsigned SrcReg,
64 const TargetRegisterInfo *TRI,
65 bool AddIfNotFound = false);
66 void TransferImplicitDefs(MachineInstr *MI);
69 char LowerSubregsInstructionPass::ID = 0;
72 FunctionPass *llvm::createLowerSubregsPass() {
73 return new LowerSubregsInstructionPass();
76 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
77 /// and the lowered replacement instructions immediately precede it.
78 /// Mark the replacement instructions with the dead flag.
80 LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
82 const TargetRegisterInfo *TRI) {
83 for (MachineBasicBlock::iterator MII =
84 prior(MachineBasicBlock::iterator(MI)); ; --MII) {
85 if (MII->addRegisterDead(DstReg, TRI))
87 assert(MII != MI->getParent()->begin() &&
88 "copyRegToReg output doesn't reference destination register!");
92 /// TransferKillFlag - MI is a pseudo-instruction with SrcReg killed,
93 /// and the lowered replacement instructions immediately precede it.
94 /// Mark the replacement instructions with the kill flag.
96 LowerSubregsInstructionPass::TransferKillFlag(MachineInstr *MI,
98 const TargetRegisterInfo *TRI,
100 for (MachineBasicBlock::iterator MII =
101 prior(MachineBasicBlock::iterator(MI)); ; --MII) {
102 if (MII->addRegisterKilled(SrcReg, TRI, AddIfNotFound))
104 assert(MII != MI->getParent()->begin() &&
105 "copyRegToReg output doesn't reference source register!");
109 /// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
110 /// replacement instructions immediately precede it. Copy any implicit-def
111 /// operands from MI to the replacement instruction.
113 LowerSubregsInstructionPass::TransferImplicitDefs(MachineInstr *MI) {
114 MachineBasicBlock::iterator CopyMI = MI;
117 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
118 MachineOperand &MO = MI->getOperand(i);
119 if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
121 CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
125 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
126 MachineBasicBlock *MBB = MI->getParent();
128 assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
129 MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
130 MI->getOperand(2).isImm() && "Malformed extract_subreg");
132 unsigned DstReg = MI->getOperand(0).getReg();
133 unsigned SuperReg = MI->getOperand(1).getReg();
134 unsigned SubIdx = MI->getOperand(2).getImm();
135 unsigned SrcReg = TRI->getSubReg(SuperReg, SubIdx);
137 assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
138 "Extract supperg source must be a physical register");
139 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
140 "Extract destination must be in a physical register");
141 assert(SrcReg && "invalid subregister index for register");
143 DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
145 if (SrcReg == DstReg) {
146 // No need to insert an identity copy instruction.
147 if (MI->getOperand(1).isKill()) {
148 // We must make sure the super-register gets killed. Replace the
149 // instruction with KILL.
150 MI->setDesc(TII->get(TargetOpcode::KILL));
151 MI->RemoveOperand(2); // SubIdx
152 DEBUG(dbgs() << "subreg: replace by: " << *MI);
156 DEBUG(dbgs() << "subreg: eliminated!");
159 const TargetRegisterClass *TRCS = TRI->getPhysicalRegisterRegClass(DstReg);
160 const TargetRegisterClass *TRCD = TRI->getPhysicalRegisterRegClass(SrcReg);
161 bool Emitted = TII->copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS,
164 assert(Emitted && "Subreg and Dst must be of compatible register class");
165 // Transfer the kill/dead flags, if needed.
166 if (MI->getOperand(0).isDead())
167 TransferDeadFlag(MI, DstReg, TRI);
168 if (MI->getOperand(1).isKill())
169 TransferKillFlag(MI, SuperReg, TRI, true);
170 TransferImplicitDefs(MI);
172 MachineBasicBlock::iterator dMI = MI;
173 dbgs() << "subreg: " << *(--dMI);
177 DEBUG(dbgs() << '\n');
182 bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
183 MachineBasicBlock *MBB = MI->getParent();
184 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
185 MI->getOperand(1).isImm() &&
186 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
187 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
189 unsigned DstReg = MI->getOperand(0).getReg();
190 unsigned InsReg = MI->getOperand(2).getReg();
191 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
192 unsigned SubIdx = MI->getOperand(3).getImm();
194 assert(SubIdx != 0 && "Invalid index for insert_subreg");
195 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
197 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
198 "Insert destination must be in a physical register");
199 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
200 "Inserted value must be in a physical register");
202 DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
204 if (DstSubReg == InsReg) {
205 // No need to insert an identify copy instruction.
206 // Watch out for case like this:
207 // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
208 // We must leave %RAX live.
209 if (DstReg != InsReg) {
210 MI->setDesc(TII->get(TargetOpcode::KILL));
211 MI->RemoveOperand(3); // SubIdx
212 MI->RemoveOperand(1); // Imm
213 DEBUG(dbgs() << "subreg: replace by: " << *MI);
216 DEBUG(dbgs() << "subreg: eliminated!");
218 // Insert sub-register copy
219 const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg);
220 const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg);
221 bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1,
224 assert(Emitted && "Subreg and Dst must be of compatible register class");
225 // Transfer the kill/dead flags, if needed.
226 if (MI->getOperand(0).isDead())
227 TransferDeadFlag(MI, DstSubReg, TRI);
228 if (MI->getOperand(2).isKill())
229 TransferKillFlag(MI, InsReg, TRI);
231 MachineBasicBlock::iterator dMI = MI;
232 dbgs() << "subreg: " << *(--dMI);
236 DEBUG(dbgs() << '\n');
241 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
242 MachineBasicBlock *MBB = MI->getParent();
243 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
244 (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) &&
245 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
246 MI->getOperand(3).isImm() && "Invalid insert_subreg");
248 unsigned DstReg = MI->getOperand(0).getReg();
250 unsigned SrcReg = MI->getOperand(1).getReg();
252 unsigned InsReg = MI->getOperand(2).getReg();
253 unsigned SubIdx = MI->getOperand(3).getImm();
255 assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
256 assert(SubIdx != 0 && "Invalid index for insert_subreg");
257 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
258 assert(DstSubReg && "invalid subregister index for register");
259 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
260 "Insert superreg source must be in a physical register");
261 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
262 "Inserted value must be in a physical register");
264 DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
266 if (DstSubReg == InsReg) {
267 // No need to insert an identity copy instruction. If the SrcReg was
268 // <undef>, we need to make sure it is alive by inserting a KILL
269 if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) {
270 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
271 TII->get(TargetOpcode::KILL), DstReg);
272 if (MI->getOperand(2).isUndef())
273 MIB.addReg(InsReg, RegState::Undef);
275 MIB.addReg(InsReg, RegState::Kill);
277 DEBUG(dbgs() << "subreg: eliminated!\n");
282 // Insert sub-register copy
283 const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg);
284 const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg);
285 if (MI->getOperand(2).isUndef())
286 // If the source register being inserted is undef, then this becomes a
288 BuildMI(*MBB, MI, MI->getDebugLoc(),
289 TII->get(TargetOpcode::KILL), DstSubReg);
291 bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1,
294 assert(Emitted && "Subreg and Dst must be of compatible register class");
296 MachineBasicBlock::iterator CopyMI = MI;
299 // INSERT_SUBREG is a two-address instruction so it implicitly kills SrcReg.
300 if (!MI->getOperand(1).isUndef())
301 CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true));
303 // Transfer the kill/dead flags, if needed.
304 if (MI->getOperand(0).isDead()) {
305 TransferDeadFlag(MI, DstSubReg, TRI);
307 // Make sure the full DstReg is live after this replacement.
308 CopyMI->addOperand(MachineOperand::CreateReg(DstReg, true, true));
311 // Make sure the inserted register gets killed
312 if (MI->getOperand(2).isKill() && !MI->getOperand(2).isUndef())
313 TransferKillFlag(MI, InsReg, TRI);
317 MachineBasicBlock::iterator dMI = MI;
318 dbgs() << "subreg: " << *(--dMI) << "\n";
325 bool LowerSubregsInstructionPass::LowerCopy(MachineInstr *MI) {
326 MachineOperand &DstMO = MI->getOperand(0);
327 MachineOperand &SrcMO = MI->getOperand(1);
329 if (SrcMO.getReg() == DstMO.getReg()) {
330 DEBUG(dbgs() << "identity copy: " << *MI);
331 // No need to insert an identity copy instruction, but replace with a KILL
332 // if liveness is changed.
333 if (DstMO.isDead() || SrcMO.isUndef() || MI->getNumOperands() > 2) {
334 // We must make sure the super-register gets killed. Replace the
335 // instruction with KILL.
336 MI->setDesc(TII->get(TargetOpcode::KILL));
337 DEBUG(dbgs() << "replaced by: " << *MI);
340 // Vanilla identity copy.
341 MI->eraseFromParent();
345 DEBUG(dbgs() << "real copy: " << *MI);
346 // Ask target for a lowered copy instruction.
347 const TargetRegisterClass *DstRC =
348 TRI->getPhysicalRegisterRegClass(DstMO.getReg());
349 const TargetRegisterClass *SrcRC =
350 TRI->getPhysicalRegisterRegClass(SrcMO.getReg());
351 bool Emitted = TII->copyRegToReg(*MI->getParent(), MI,
352 DstMO.getReg(), SrcMO.getReg(),
353 DstRC, SrcRC, MI->getDebugLoc());
355 assert(Emitted && "Cannot emit copy");
358 TransferDeadFlag(MI, DstMO.getReg(), TRI);
360 TransferKillFlag(MI, SrcMO.getReg(), TRI, true);
361 if (MI->getNumOperands() > 2)
362 TransferImplicitDefs(MI);
364 MachineBasicBlock::iterator dMI = MI;
365 dbgs() << "replaced by: " << *(--dMI);
367 MI->eraseFromParent();
371 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
374 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
375 DEBUG(dbgs() << "Machine Function\n"
376 << "********** LOWERING SUBREG INSTRS **********\n"
377 << "********** Function: "
378 << MF.getFunction()->getName() << '\n');
379 TRI = MF.getTarget().getRegisterInfo();
380 TII = MF.getTarget().getInstrInfo();
382 bool MadeChange = false;
384 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
385 mbbi != mbbe; ++mbbi) {
386 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
388 MachineBasicBlock::iterator nmi = llvm::next(mi);
389 MachineInstr *MI = mi;
390 if (MI->isExtractSubreg()) {
391 MadeChange |= LowerExtract(MI);
392 } else if (MI->isInsertSubreg()) {
393 MadeChange |= LowerInsert(MI);
394 } else if (MI->isSubregToReg()) {
395 MadeChange |= LowerSubregToReg(MI);
396 } else if (MI->isCopy()) {
397 MadeChange |= LowerCopy(MI);