1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/Target/MRegisterInfo.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "Support/DepthFirstIterator.h"
35 #include "Support/STLExtras.h"
38 static RegisterAnalysis<LiveVariables> X("livevars", "Live Variable Analysis");
40 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
41 assert(MRegisterInfo::isVirtualRegister(RegIdx) &&
42 "getVarInfo: not a virtual register!");
43 RegIdx -= MRegisterInfo::FirstVirtualRegister;
44 if (RegIdx >= VirtRegInfo.size()) {
45 if (RegIdx >= 2*VirtRegInfo.size())
46 VirtRegInfo.resize(RegIdx*2);
48 VirtRegInfo.resize(2*VirtRegInfo.size());
50 return VirtRegInfo[RegIdx];
55 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
56 MachineBasicBlock *MBB) {
57 unsigned BBNum = MBB->getNumber();
59 // Check to see if this basic block is one of the killing blocks. If so,
61 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
62 if (VRInfo.Kills[i].first == MBB) {
63 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
67 if (MBB == VRInfo.DefBlock) return; // Terminate recursion
69 if (VRInfo.AliveBlocks.size() <= BBNum)
70 VRInfo.AliveBlocks.resize(BBNum+1); // Make space...
72 if (VRInfo.AliveBlocks[BBNum])
73 return; // We already know the block is live
75 // Mark the variable known alive in this bb
76 VRInfo.AliveBlocks[BBNum] = true;
78 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
79 E = MBB->pred_end(); PI != E; ++PI)
80 MarkVirtRegAliveInBlock(VRInfo, *PI);
83 void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
85 // Check to see if this basic block is already a kill block...
86 if (!VRInfo.Kills.empty() && VRInfo.Kills.back().first == MBB) {
87 // Yes, this register is killed in this basic block already. Increase the
88 // live range by updating the kill instruction.
89 VRInfo.Kills.back().second = MI;
94 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
95 assert(VRInfo.Kills[i].first != MBB && "entry should be at end!");
98 assert(MBB != VRInfo.DefBlock && "Should have kill for defblock!");
100 // Add a new kill entry for this basic block.
101 VRInfo.Kills.push_back(std::make_pair(MBB, MI));
103 // Update all dominating blocks to mark them known live.
104 const BasicBlock *BB = MBB->getBasicBlock();
105 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
106 E = MBB->pred_end(); PI != E; ++PI)
107 MarkVirtRegAliveInBlock(VRInfo, *PI);
110 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
111 PhysRegInfo[Reg] = MI;
112 PhysRegUsed[Reg] = true;
114 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
115 unsigned Alias = *AliasSet; ++AliasSet) {
116 PhysRegInfo[Alias] = MI;
117 PhysRegUsed[Alias] = true;
121 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
122 // Does this kill a previous version of this register?
123 if (MachineInstr *LastUse = PhysRegInfo[Reg]) {
124 if (PhysRegUsed[Reg])
125 RegistersKilled.insert(std::make_pair(LastUse, Reg));
127 RegistersDead.insert(std::make_pair(LastUse, Reg));
129 PhysRegInfo[Reg] = MI;
130 PhysRegUsed[Reg] = false;
132 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
133 unsigned Alias = *AliasSet; ++AliasSet) {
134 if (MachineInstr *LastUse = PhysRegInfo[Alias]) {
135 if (PhysRegUsed[Alias])
136 RegistersKilled.insert(std::make_pair(LastUse, Alias));
138 RegistersDead.insert(std::make_pair(LastUse, Alias));
140 PhysRegInfo[Alias] = MI;
141 PhysRegUsed[Alias] = false;
145 bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
146 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
147 RegInfo = MF.getTarget().getRegisterInfo();
148 assert(RegInfo && "Target doesn't have register information?");
150 // First time though, initialize AllocatablePhysicalRegisters for the target
151 if (AllocatablePhysicalRegisters.empty()) {
152 // Make space, initializing to false...
153 AllocatablePhysicalRegisters.resize(RegInfo->getNumRegs());
155 // Loop over all of the register classes...
156 for (MRegisterInfo::regclass_iterator RCI = RegInfo->regclass_begin(),
157 E = RegInfo->regclass_end(); RCI != E; ++RCI)
158 // Loop over all of the allocatable registers in the function...
159 for (TargetRegisterClass::iterator I = (*RCI)->allocation_order_begin(MF),
160 E = (*RCI)->allocation_order_end(MF); I != E; ++I)
161 AllocatablePhysicalRegisters[*I] = true; // The reg is allocatable!
164 // PhysRegInfo - Keep track of which instruction was the last use of a
165 // physical register. This is a purely local property, because all physical
166 // register references as presumed dead across basic blocks.
168 MachineInstr *PhysRegInfoA[RegInfo->getNumRegs()];
169 bool PhysRegUsedA[RegInfo->getNumRegs()];
170 std::fill(PhysRegInfoA, PhysRegInfoA+RegInfo->getNumRegs(), (MachineInstr*)0);
171 PhysRegInfo = PhysRegInfoA;
172 PhysRegUsed = PhysRegUsedA;
174 /// Get some space for a respectable number of registers...
175 VirtRegInfo.resize(64);
177 // Calculate live variable information in depth first order on the CFG of the
178 // function. This guarantees that we will see the definition of a virtual
179 // register before its uses due to dominance properties of SSA (except for PHI
180 // nodes, which are treated as a special case).
182 MachineBasicBlock *Entry = MF.begin();
183 std::set<MachineBasicBlock*> Visited;
184 for (df_ext_iterator<MachineBasicBlock*> DFI = df_ext_begin(Entry, Visited),
185 E = df_ext_end(Entry, Visited); DFI != E; ++DFI) {
186 MachineBasicBlock *MBB = *DFI;
187 unsigned BBNum = MBB->getNumber();
189 // Loop over all of the instructions, processing them.
190 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
192 MachineInstr *MI = I;
193 const TargetInstrDescriptor &MID = TII.get(MI->getOpcode());
195 // Process all of the operands of the instruction...
196 unsigned NumOperandsToProcess = MI->getNumOperands();
198 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
199 // of the uses. They will be handled in other basic blocks.
200 if (MI->getOpcode() == TargetInstrInfo::PHI)
201 NumOperandsToProcess = 1;
203 // Loop over implicit uses, using them.
204 for (const unsigned *ImplicitUses = MID.ImplicitUses;
205 *ImplicitUses; ++ImplicitUses)
206 HandlePhysRegUse(*ImplicitUses, MI);
208 // Process all explicit uses...
209 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
210 MachineOperand &MO = MI->getOperand(i);
211 if (MO.isUse() && MO.isRegister() && MO.getReg()) {
212 if (MRegisterInfo::isVirtualRegister(MO.getReg())){
213 HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
214 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
215 AllocatablePhysicalRegisters[MO.getReg()]) {
216 HandlePhysRegUse(MO.getReg(), MI);
221 // Loop over implicit defs, defining them.
222 for (const unsigned *ImplicitDefs = MID.ImplicitDefs;
223 *ImplicitDefs; ++ImplicitDefs)
224 HandlePhysRegDef(*ImplicitDefs, MI);
226 // Process all explicit defs...
227 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
228 MachineOperand &MO = MI->getOperand(i);
229 if (MO.isDef() && MO.isRegister() && MO.getReg()) {
230 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
231 VarInfo &VRInfo = getVarInfo(MO.getReg());
233 assert(VRInfo.DefBlock == 0 && "Variable multiply defined!");
234 VRInfo.DefBlock = MBB; // Created here...
236 VRInfo.Kills.push_back(std::make_pair(MBB, MI)); // Defaults to dead
237 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
238 AllocatablePhysicalRegisters[MO.getReg()]) {
239 HandlePhysRegDef(MO.getReg(), MI);
245 // Handle any virtual assignments from PHI nodes which might be at the
246 // bottom of this basic block. We check all of our successor blocks to see
247 // if they have PHI nodes, and if so, we simulate an assignment at the end
248 // of the current block.
249 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
250 E = MBB->succ_end(); SI != E; ++SI) {
251 MachineBasicBlock *Succ = *SI;
253 // PHI nodes are guaranteed to be at the top of the block...
254 for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end();
255 MI != ME && MI->getOpcode() == TargetInstrInfo::PHI; ++MI) {
256 for (unsigned i = 1; ; i += 2) {
257 assert(MI->getNumOperands() > i+1 &&
258 "Didn't find an entry for our predecessor??");
259 if (MI->getOperand(i+1).getMachineBasicBlock() == MBB) {
260 MachineOperand &MO = MI->getOperand(i);
261 if (!MO.getVRegValueOrNull()) {
262 VarInfo &VRInfo = getVarInfo(MO.getReg());
264 // Only mark it alive only in the block we are representing...
265 MarkVirtRegAliveInBlock(VRInfo, MBB);
266 break; // Found the PHI entry for this block...
273 // Loop over PhysRegInfo, killing any registers that are available at the
274 // end of the basic block. This also resets the PhysRegInfo map.
275 for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
277 HandlePhysRegDef(i, 0);
280 // Convert the information we have gathered into VirtRegInfo and transform it
281 // into a form usable by RegistersKilled.
283 for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i)
284 for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) {
285 if (VirtRegInfo[i].Kills[j].second == VirtRegInfo[i].DefInst)
286 RegistersDead.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
287 i + MRegisterInfo::FirstVirtualRegister));
290 RegistersKilled.insert(std::make_pair(VirtRegInfo[i].Kills[j].second,
291 i + MRegisterInfo::FirstVirtualRegister));
294 // Check to make sure there are no unreachable blocks in the MC CFG for the
295 // function. If so, it is due to a bug in the instruction selector or some
296 // other part of the code generator if this happens.
298 for(MachineFunction::iterator i = MF.begin(), e = MF.end(); i != e; ++i)
299 assert(Visited.count(&*i) != 0 && "unreachable basic block found");
305 /// instructionChanged - When the address of an instruction changes, this
306 /// method should be called so that live variables can update its internal
307 /// data structures. This removes the records for OldMI, transfering them to
308 /// the records for NewMI.
309 void LiveVariables::instructionChanged(MachineInstr *OldMI,
310 MachineInstr *NewMI) {
311 // If the instruction defines any virtual registers, update the VarInfo for
313 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
314 MachineOperand &MO = OldMI->getOperand(i);
315 if (MO.isRegister() && MO.isDef() && MO.getReg() &&
316 MRegisterInfo::isVirtualRegister(MO.getReg())) {
317 unsigned Reg = MO.getReg();
318 VarInfo &VI = getVarInfo(Reg);
319 if (VI.DefInst == OldMI)
324 // Move the killed information over...
325 killed_iterator I, E;
326 tie(I, E) = killed_range(OldMI);
327 std::vector<unsigned> Regs;
328 for (killed_iterator A = I; A != E; ++A)
329 Regs.push_back(A->second);
330 RegistersKilled.erase(I, E);
332 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
333 RegistersKilled.insert(std::make_pair(NewMI, Regs[i]));
336 // Move the dead information over...
337 tie(I, E) = dead_range(OldMI);
338 for (killed_iterator A = I; A != E; ++A)
339 Regs.push_back(A->second);
340 RegistersDead.erase(I, E);
342 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
343 RegistersDead.insert(std::make_pair(NewMI, Regs[i]));