1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/ADT/DepthFirstIterator.h"
36 #include "llvm/ADT/SmallPtrSet.h"
37 #include "llvm/ADT/STLExtras.h"
38 #include "llvm/Config/alloca.h"
42 char LiveVariables::ID = 0;
43 static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
45 void LiveVariables::VarInfo::dump() const {
46 cerr << " Alive in blocks: ";
47 for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i)
48 if (AliveBlocks[i]) cerr << i << ", ";
49 cerr << " Used in blocks: ";
50 for (unsigned i = 0, e = UsedBlocks.size(); i != e; ++i)
51 if (UsedBlocks[i]) cerr << i << ", ";
52 cerr << "\n Killed by:";
54 cerr << " No instructions.\n";
56 for (unsigned i = 0, e = Kills.size(); i != e; ++i)
57 cerr << "\n #" << i << ": " << *Kills[i];
62 /// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
63 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
64 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
65 "getVarInfo: not a virtual register!");
66 RegIdx -= TargetRegisterInfo::FirstVirtualRegister;
67 if (RegIdx >= VirtRegInfo.size()) {
68 if (RegIdx >= 2*VirtRegInfo.size())
69 VirtRegInfo.resize(RegIdx*2);
71 VirtRegInfo.resize(2*VirtRegInfo.size());
73 VarInfo &VI = VirtRegInfo[RegIdx];
74 VI.AliveBlocks.resize(MF->getNumBlockIDs());
75 VI.UsedBlocks.resize(MF->getNumBlockIDs());
79 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
80 MachineBasicBlock *DefBlock,
81 MachineBasicBlock *MBB,
82 std::vector<MachineBasicBlock*> &WorkList) {
83 unsigned BBNum = MBB->getNumber();
85 // Check to see if this basic block is one of the killing blocks. If so,
87 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
88 if (VRInfo.Kills[i]->getParent() == MBB) {
89 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
93 if (MBB == DefBlock) return; // Terminate recursion
95 if (VRInfo.AliveBlocks[BBNum])
96 return; // We already know the block is live
98 // Mark the variable known alive in this bb
99 VRInfo.AliveBlocks[BBNum] = true;
101 for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(),
102 E = MBB->pred_rend(); PI != E; ++PI)
103 WorkList.push_back(*PI);
106 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
107 MachineBasicBlock *DefBlock,
108 MachineBasicBlock *MBB) {
109 std::vector<MachineBasicBlock*> WorkList;
110 MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
112 while (!WorkList.empty()) {
113 MachineBasicBlock *Pred = WorkList.back();
115 MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
119 void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
121 const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
122 assert(MRI.getVRegDef(reg) && "Register use before def!");
124 unsigned BBNum = MBB->getNumber();
126 VarInfo& VRInfo = getVarInfo(reg);
127 VRInfo.UsedBlocks[BBNum] = true;
130 // Check to see if this basic block is already a kill block.
131 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
132 // Yes, this register is killed in this basic block already. Increase the
133 // live range by updating the kill instruction.
134 VRInfo.Kills.back() = MI;
139 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
140 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
143 assert(MBB != MRI.getVRegDef(reg)->getParent() &&
144 "Should have kill for defblock!");
146 // Add a new kill entry for this basic block. If this virtual register is
147 // already marked as alive in this basic block, that means it is alive in at
148 // least one of the successor blocks, it's not a kill.
149 if (!VRInfo.AliveBlocks[BBNum])
150 VRInfo.Kills.push_back(MI);
152 // Update all dominating blocks to mark them as "known live".
153 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
154 E = MBB->pred_end(); PI != E; ++PI)
155 MarkVirtRegAliveInBlock(VRInfo, MRI.getVRegDef(reg)->getParent(), *PI);
158 /// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
159 /// implicit defs to a machine instruction if there was an earlier def of its
161 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
162 // Turn previous partial def's into read/mod/write.
163 for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) {
164 MachineInstr *Def = PhysRegPartDef[Reg][i];
166 // First one is just a def. This means the use is reading some undef bits.
168 Def->addOperand(MachineOperand::CreateReg(Reg,
173 Def->addOperand(MachineOperand::CreateReg(Reg,
178 PhysRegPartDef[Reg].clear();
180 // There was an earlier def of a super-register. Add implicit def to that MI.
185 // Add implicit def to A.
186 if (PhysRegInfo[Reg] && PhysRegInfo[Reg] != PhysRegPartUse[Reg] &&
188 MachineInstr *Def = PhysRegInfo[Reg];
190 if (!Def->modifiesRegister(Reg))
191 Def->addOperand(MachineOperand::CreateReg(Reg,
196 // There is a now a proper use, forget about the last partial use.
197 PhysRegPartUse[Reg] = NULL;
198 PhysRegInfo[Reg] = MI;
199 PhysRegUsed[Reg] = true;
201 // Now reset the use information for the sub-registers.
202 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
203 unsigned SubReg = *SubRegs; ++SubRegs) {
204 PhysRegPartUse[SubReg] = NULL;
205 PhysRegInfo[SubReg] = MI;
206 PhysRegUsed[SubReg] = true;
209 for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg);
210 unsigned SuperReg = *SuperRegs; ++SuperRegs) {
211 // Remember the partial use of this super-register if it was previously
213 bool HasPrevDef = PhysRegInfo[SuperReg] != NULL;
216 // No need to go up more levels. A def of a register also sets its sub-
217 // registers. So if PhysRegInfo[SuperReg] is NULL, it means SuperReg's
218 // super-registers are not previously defined.
219 for (const unsigned *SSRegs = TRI->getSuperRegisters(SuperReg);
220 unsigned SSReg = *SSRegs; ++SSRegs)
221 if (PhysRegInfo[SSReg] != NULL) {
227 PhysRegInfo[SuperReg] = MI;
228 PhysRegPartUse[SuperReg] = MI;
233 /// addRegisterKills - For all of a register's sub-registers that are killed in
234 /// at this machine instruction, mark them as "killed". (If the machine operand
235 /// isn't found, add it first.)
236 void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI,
237 SmallSet<unsigned, 4> &SubKills) {
238 if (SubKills.count(Reg) == 0) {
239 MI->addRegisterKilled(Reg, TRI, true);
243 for (const unsigned *SubRegs = TRI->getImmediateSubRegisters(Reg);
244 unsigned SubReg = *SubRegs; ++SubRegs)
245 addRegisterKills(SubReg, MI, SubKills);
248 /// HandlePhysRegKill - The recursive version of HandlePhysRegKill. Returns true
251 /// - The register has no sub-registers and the machine instruction is the
252 /// last def/use of the register, or
253 /// - The register has sub-registers and none of them are killed elsewhere.
255 /// SubKills is filled with the set of sub-registers that are killed elsewhere.
256 bool LiveVariables::HandlePhysRegKill(unsigned Reg, const MachineInstr *RefMI,
257 SmallSet<unsigned, 4> &SubKills) {
258 const unsigned *SubRegs = TRI->getImmediateSubRegisters(Reg);
260 for (; unsigned SubReg = *SubRegs; ++SubRegs) {
261 const MachineInstr *LastRef = PhysRegInfo[SubReg];
263 if (LastRef != RefMI ||
264 !HandlePhysRegKill(SubReg, RefMI, SubKills))
265 SubKills.insert(SubReg);
269 // No sub-registers, just check if reg is killed by RefMI.
270 if (PhysRegInfo[Reg] == RefMI)
272 } else if (SubKills.empty()) {
273 // None of the sub-registers are killed elsewhere.
280 /// HandlePhysRegKill - Returns true if the whole register is killed in the
281 /// machine instruction. If only some of its sub-registers are killed in this
282 /// machine instruction, then mark those as killed and return false.
283 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) {
284 SmallSet<unsigned, 4> SubKills;
286 if (HandlePhysRegKill(Reg, RefMI, SubKills)) {
287 // This machine instruction kills this register.
288 RefMI->addRegisterKilled(Reg, TRI, true);
292 // Some sub-registers are killed by another machine instruction.
293 for (const unsigned *SubRegs = TRI->getImmediateSubRegisters(Reg);
294 unsigned SubReg = *SubRegs; ++SubRegs)
295 addRegisterKills(SubReg, RefMI, SubKills);
300 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
301 // Does this kill a previous version of this register?
302 if (MachineInstr *LastRef = PhysRegInfo[Reg]) {
303 if (PhysRegUsed[Reg]) {
304 if (!HandlePhysRegKill(Reg, LastRef)) {
305 if (PhysRegPartUse[Reg])
306 PhysRegPartUse[Reg]->addRegisterKilled(Reg, TRI, true);
308 } else if (PhysRegPartUse[Reg]) {
309 // Add implicit use / kill to last partial use.
310 PhysRegPartUse[Reg]->addRegisterKilled(Reg, TRI, true);
311 } else if (LastRef != MI) {
312 // Defined, but not used. However, watch out for cases where a super-reg
313 // is also defined on the same MI.
314 LastRef->addRegisterDead(Reg, TRI);
318 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
319 unsigned SubReg = *SubRegs; ++SubRegs) {
320 if (MachineInstr *LastRef = PhysRegInfo[SubReg]) {
321 if (PhysRegUsed[SubReg]) {
322 if (!HandlePhysRegKill(SubReg, LastRef)) {
323 if (PhysRegPartUse[SubReg])
324 PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, TRI, true);
326 } else if (PhysRegPartUse[SubReg]) {
327 // Add implicit use / kill to last use of a sub-register.
328 PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, TRI, true);
329 } else if (LastRef != MI) {
330 // This must be a def of the subreg on the same MI.
331 LastRef->addRegisterDead(SubReg, TRI);
337 for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg);
338 unsigned SuperReg = *SuperRegs; ++SuperRegs) {
339 if (PhysRegInfo[SuperReg] && PhysRegInfo[SuperReg] != MI) {
340 // The larger register is previously defined. Now a smaller part is
341 // being re-defined. Treat it as read/mod/write.
343 // AX = EAX<imp-use,kill>, EAX<imp-def>
344 MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/,
345 true/*IsImp*/,true/*IsKill*/));
346 MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/,
348 PhysRegInfo[SuperReg] = MI;
349 PhysRegUsed[SuperReg] = false;
350 PhysRegPartUse[SuperReg] = NULL;
352 // Remember this partial def.
353 PhysRegPartDef[SuperReg].push_back(MI);
357 PhysRegInfo[Reg] = MI;
358 PhysRegUsed[Reg] = false;
359 PhysRegPartDef[Reg].clear();
360 PhysRegPartUse[Reg] = NULL;
362 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
363 unsigned SubReg = *SubRegs; ++SubRegs) {
364 PhysRegInfo[SubReg] = MI;
365 PhysRegUsed[SubReg] = false;
366 PhysRegPartDef[SubReg].clear();
367 PhysRegPartUse[SubReg] = NULL;
372 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
374 TRI = MF->getTarget().getRegisterInfo();
375 MachineRegisterInfo& MRI = mf.getRegInfo();
377 ReservedRegisters = TRI->getReservedRegs(mf);
379 unsigned NumRegs = TRI->getNumRegs();
380 PhysRegInfo = new MachineInstr*[NumRegs];
381 PhysRegUsed = new bool[NumRegs];
382 PhysRegPartUse = new MachineInstr*[NumRegs];
383 PhysRegPartDef = new SmallVector<MachineInstr*,4>[NumRegs];
384 PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
385 std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
386 std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
387 std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
389 /// Get some space for a respectable number of registers.
390 VirtRegInfo.resize(64);
394 // Calculate live variable information in depth first order on the CFG of the
395 // function. This guarantees that we will see the definition of a virtual
396 // register before its uses due to dominance properties of SSA (except for PHI
397 // nodes, which are treated as a special case).
398 MachineBasicBlock *Entry = MF->begin();
399 SmallPtrSet<MachineBasicBlock*,16> Visited;
401 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
402 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
404 MachineBasicBlock *MBB = *DFI;
406 // Mark live-in registers as live-in.
407 for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
408 EE = MBB->livein_end(); II != EE; ++II) {
409 assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
410 "Cannot have a live-in virtual register!");
411 HandlePhysRegDef(*II, 0);
414 // Loop over all of the instructions, processing them.
415 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
417 MachineInstr *MI = I;
419 // Process all of the operands of the instruction...
420 unsigned NumOperandsToProcess = MI->getNumOperands();
422 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
423 // of the uses. They will be handled in other basic blocks.
424 if (MI->getOpcode() == TargetInstrInfo::PHI)
425 NumOperandsToProcess = 1;
428 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
429 const MachineOperand &MO = MI->getOperand(i);
431 if (MO.isRegister() && MO.isUse() && MO.getReg()) {
432 unsigned MOReg = MO.getReg();
434 if (TargetRegisterInfo::isVirtualRegister(MOReg))
435 HandleVirtRegUse(MOReg, MBB, MI);
436 else if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
437 !ReservedRegisters[MOReg])
438 HandlePhysRegUse(MOReg, MI);
443 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
444 const MachineOperand &MO = MI->getOperand(i);
446 if (MO.isRegister() && MO.isDef() && MO.getReg()) {
447 unsigned MOReg = MO.getReg();
449 if (TargetRegisterInfo::isVirtualRegister(MOReg)) {
450 VarInfo &VRInfo = getVarInfo(MOReg);
452 if (VRInfo.AliveBlocks.none())
453 // If vr is not alive in any block, then defaults to dead.
454 VRInfo.Kills.push_back(MI);
455 } else if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
456 !ReservedRegisters[MOReg]) {
457 HandlePhysRegDef(MOReg, MI);
463 // Handle any virtual assignments from PHI nodes which might be at the
464 // bottom of this basic block. We check all of our successor blocks to see
465 // if they have PHI nodes, and if so, we simulate an assignment at the end
466 // of the current block.
467 if (!PHIVarInfo[MBB->getNumber()].empty()) {
468 SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
470 for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
471 E = VarInfoVec.end(); I != E; ++I)
472 // Mark it alive only in the block we are representing.
473 MarkVirtRegAliveInBlock(getVarInfo(*I), MRI.getVRegDef(*I)->getParent(),
477 // Finally, if the last instruction in the block is a return, make sure to
478 // mark it as using all of the live-out values in the function.
479 if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
480 MachineInstr *Ret = &MBB->back();
482 for (MachineRegisterInfo::liveout_iterator
483 I = MF->getRegInfo().liveout_begin(),
484 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
485 assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
486 "Cannot have a live-in virtual register!");
487 HandlePhysRegUse(*I, Ret);
489 // Add live-out registers as implicit uses.
490 if (!Ret->readsRegister(*I))
491 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
495 // Loop over PhysRegInfo, killing any registers that are available at the
496 // end of the basic block. This also resets the PhysRegInfo map.
497 for (unsigned i = 0; i != NumRegs; ++i)
499 HandlePhysRegDef(i, 0);
501 // Clear some states between BB's. These are purely local information.
502 for (unsigned i = 0; i != NumRegs; ++i)
503 PhysRegPartDef[i].clear();
505 std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
506 std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
507 std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
510 // Convert and transfer the dead / killed information we have gathered into
511 // VirtRegInfo onto MI's.
512 for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
513 for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j)
514 if (VirtRegInfo[i].Kills[j] ==
515 MRI.getVRegDef(i + TargetRegisterInfo::FirstVirtualRegister))
517 .Kills[j]->addRegisterDead(i +
518 TargetRegisterInfo::FirstVirtualRegister,
522 .Kills[j]->addRegisterKilled(i +
523 TargetRegisterInfo::FirstVirtualRegister,
526 // Check to make sure there are no unreachable blocks in the MC CFG for the
527 // function. If so, it is due to a bug in the instruction selector or some
528 // other part of the code generator if this happens.
530 for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
531 assert(Visited.count(&*i) != 0 && "unreachable basic block found");
534 delete[] PhysRegInfo;
535 delete[] PhysRegUsed;
536 delete[] PhysRegPartUse;
537 delete[] PhysRegPartDef;
543 /// instructionChanged - When the address of an instruction changes, this method
544 /// should be called so that live variables can update its internal data
545 /// structures. This removes the records for OldMI, transfering them to the
546 /// records for NewMI.
547 void LiveVariables::instructionChanged(MachineInstr *OldMI,
548 MachineInstr *NewMI) {
549 // If the instruction defines any virtual registers, update the VarInfo,
550 // kill and dead information for the instruction.
551 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
552 MachineOperand &MO = OldMI->getOperand(i);
553 if (MO.isRegister() && MO.getReg() &&
554 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
555 unsigned Reg = MO.getReg();
556 VarInfo &VI = getVarInfo(Reg);
560 addVirtualRegisterDead(Reg, NewMI);
565 addVirtualRegisterKilled(Reg, NewMI);
567 // If this is a kill of the value, update the VI kills list.
568 if (VI.removeKill(OldMI))
569 VI.Kills.push_back(NewMI); // Yes, there was a kill of it
574 /// removeVirtualRegistersKilled - Remove all killed info for the specified
576 void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
577 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
578 MachineOperand &MO = MI->getOperand(i);
579 if (MO.isRegister() && MO.isKill()) {
581 unsigned Reg = MO.getReg();
582 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
583 bool removed = getVarInfo(Reg).removeKill(MI);
584 assert(removed && "kill not in register's VarInfo?");
590 /// removeVirtualRegistersDead - Remove all of the dead registers for the
591 /// specified instruction from the live variable information.
592 void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
593 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
594 MachineOperand &MO = MI->getOperand(i);
595 if (MO.isRegister() && MO.isDead()) {
597 unsigned Reg = MO.getReg();
598 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
599 bool removed = getVarInfo(Reg).removeKill(MI);
600 assert(removed && "kill not in register's VarInfo?");
606 /// analyzePHINodes - Gather information about the PHI nodes in here. In
607 /// particular, we want to map the variable information of a virtual register
608 /// which is used in a PHI node. We map that to the BB the vreg is coming from.
610 void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
611 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
613 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
614 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
615 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
616 PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()]
617 .push_back(BBI->getOperand(i).getReg());