1 //===-- LiveIntervalUnion.h - Live interval union data struct --*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // LiveIntervalUnion is a union of live segments across multiple live virtual
11 // registers. This may be used during coalescing to represent a congruence
12 // class, or during register allocation to model liveness of a physical
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_CODEGEN_LIVEINTERVALUNION
18 #define LLVM_CODEGEN_LIVEINTERVALUNION
20 #include "llvm/ADT/IntervalMap.h"
21 #include "llvm/CodeGen/LiveInterval.h"
26 // forward declaration
27 template <unsigned Element> class SparseBitVector;
28 typedef SparseBitVector<128> LiveVirtRegBitSet;
31 /// Abstraction to provide info for the representative register.
32 class AbstractRegisterDescription {
34 virtual const char *getName(unsigned Reg) const = 0;
35 virtual ~AbstractRegisterDescription() {}
38 /// Compare a live virtual register segment to a LiveIntervalUnion segment.
40 overlap(const LiveRange &VRSeg,
41 const IntervalMap<SlotIndex, LiveInterval*>::const_iterator &LUSeg) {
42 return VRSeg.start < LUSeg.stop() && LUSeg.start() < VRSeg.end;
45 /// Union of live intervals that are strong candidates for coalescing into a
46 /// single register (either physical or virtual depending on the context). We
47 /// expect the constituent live intervals to be disjoint, although we may
48 /// eventually make exceptions to handle value-based interference.
49 class LiveIntervalUnion {
50 // A set of live virtual register segments that supports fast insertion,
51 // intersection, and removal.
52 // Mapping SlotIndex intervals to virtual register numbers.
53 typedef IntervalMap<SlotIndex, LiveInterval*> LiveSegments;
56 // SegmentIter can advance to the next segment ordered by starting position
57 // which may belong to a different live virtual register. We also must be able
58 // to reach the current segment's containing virtual register.
59 typedef LiveSegments::iterator SegmentIter;
61 // LiveIntervalUnions share an external allocator.
62 typedef LiveSegments::Allocator Allocator;
64 class InterferenceResult;
68 const unsigned RepReg; // representative register number
69 LiveSegments Segments; // union of virtual reg segments
72 LiveIntervalUnion(unsigned r, Allocator &a) : RepReg(r), Segments(a) {}
74 // Iterate over all segments in the union of live virtual registers ordered
75 // by their starting position.
76 SegmentIter begin() { return Segments.begin(); }
77 SegmentIter end() { return Segments.end(); }
78 SegmentIter find(SlotIndex x) { return Segments.find(x); }
79 bool empty() { return Segments.empty(); }
80 SlotIndex startIndex() { return Segments.start(); }
82 // Add a live virtual register to this union and merge its segments.
83 void unify(LiveInterval &VirtReg);
85 // Remove a live virtual register's segments from this union.
86 void extract(LiveInterval &VirtReg);
88 void dump(const AbstractRegisterDescription *RegDesc) const;
90 // If tri != NULL, use it to decode RepReg
91 void print(raw_ostream &OS, const AbstractRegisterDescription *RegDesc) const;
94 // Verify the live intervals in this union and add them to the visited set.
95 void verify(LiveVirtRegBitSet& VisitedVRegs);
98 /// Cache a single interference test result in the form of two intersecting
99 /// segments. This allows efficiently iterating over the interferences. The
100 /// iteration logic is handled by LiveIntervalUnion::Query which may
101 /// filter interferences depending on the type of query.
102 class InterferenceResult {
105 LiveInterval::iterator VirtRegI; // current position in VirtReg
106 SegmentIter LiveUnionI; // current position in LiveUnion
109 InterferenceResult(LiveInterval::iterator VRegI, SegmentIter UnionI)
110 : VirtRegI(VRegI), LiveUnionI(UnionI) {}
113 // Public default ctor.
114 InterferenceResult(): VirtRegI(), LiveUnionI() {}
116 // Note: this interface provides raw access to the iterators because the
117 // result has no way to tell if it's valid to dereference them.
119 // Access the VirtReg segment.
120 LiveInterval::iterator virtRegPos() const { return VirtRegI; }
122 // Access the LiveUnion segment.
123 const SegmentIter &liveUnionPos() const { return LiveUnionI; }
125 bool operator==(const InterferenceResult &IR) const {
126 return VirtRegI == IR.VirtRegI && LiveUnionI == IR.LiveUnionI;
128 bool operator!=(const InterferenceResult &IR) const {
129 return !operator==(IR);
133 /// Query interferences between a single live virtual register and a live
136 LiveIntervalUnion *LiveUnion;
137 LiveInterval *VirtReg;
138 InterferenceResult FirstInterference;
139 SmallVector<LiveInterval*,4> InterferingVRegs;
140 bool CheckedFirstInterference;
141 bool SeenAllInterferences;
142 bool SeenUnspillableVReg;
145 Query(): LiveUnion(), VirtReg() {}
147 Query(LiveInterval *VReg, LiveIntervalUnion *LIU):
148 LiveUnion(LIU), VirtReg(VReg), SeenAllInterferences(false),
149 SeenUnspillableVReg(false)
155 InterferingVRegs.clear();
156 CheckedFirstInterference = false;
157 SeenAllInterferences = false;
158 SeenUnspillableVReg = false;
161 void init(LiveInterval *VReg, LiveIntervalUnion *LIU) {
162 if (VirtReg == VReg && LiveUnion == LIU) {
163 // Retain cached results, e.g. firstInterference.
171 LiveInterval &virtReg() const {
172 assert(VirtReg && "uninitialized");
176 bool isInterference(const InterferenceResult &IR) const {
177 if (IR.VirtRegI != VirtReg->end()) {
178 assert(overlap(*IR.VirtRegI, IR.LiveUnionI) &&
179 "invalid segment iterators");
185 // Does this live virtual register interfere with the union?
186 bool checkInterference() { return isInterference(firstInterference()); }
188 // Get the first pair of interfering segments, or a noninterfering result.
189 // This initializes the firstInterference_ cache.
190 const InterferenceResult &firstInterference();
192 // Treat the result as an iterator and advance to the next interfering pair
193 // of segments. Visiting each unique interfering pairs means that the same
194 // VirtReg or LiveUnion segment may be visited multiple times.
195 bool nextInterference(InterferenceResult &IR) const;
197 // Count the virtual registers in this union that interfere with this
198 // query's live virtual register, up to maxInterferingRegs.
199 unsigned collectInterferingVRegs(unsigned MaxInterferingRegs = UINT_MAX);
201 // Was this virtual register visited during collectInterferingVRegs?
202 bool isSeenInterference(LiveInterval *VReg) const;
204 // Did collectInterferingVRegs collect all interferences?
205 bool seenAllInterferences() const { return SeenAllInterferences; }
207 // Did collectInterferingVRegs encounter an unspillable vreg?
208 bool seenUnspillableVReg() const { return SeenUnspillableVReg; }
210 // Vector generated by collectInterferingVRegs.
211 const SmallVectorImpl<LiveInterval*> &interferingVRegs() const {
212 return InterferingVRegs;
216 Query(const Query&); // DO NOT IMPLEMENT
217 void operator=(const Query&); // DO NOT IMPLEMENT
219 // Private interface for queries
220 void findIntersection(InterferenceResult &IR) const;
224 } // end namespace llvm
226 #endif // !defined(LLVM_CODEGEN_LIVEINTERVALUNION)