1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "LiveRangeCalc.h"
20 #include "llvm/ADT/DenseSet.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/IR/Value.h"
31 #include "llvm/Support/BlockFrequency.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/Format.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
45 #define DEBUG_TYPE "regalloc"
47 char LiveIntervals::ID = 0;
48 char &llvm::LiveIntervalsID = LiveIntervals::ID;
49 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
50 "Live Interval Analysis", false, false)
51 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
52 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
53 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
54 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
55 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
56 "Live Interval Analysis", false, false)
59 static cl::opt<bool> EnablePrecomputePhysRegs(
60 "precompute-phys-liveness", cl::Hidden,
61 cl::desc("Eagerly compute live intervals for all physreg units."));
63 static bool EnablePrecomputePhysRegs = false;
66 static cl::opt<bool> EnableSubRegLiveness(
67 "enable-subreg-liveness", cl::Hidden, cl::init(true),
68 cl::desc("Enable subregister liveness tracking."));
71 cl::opt<bool> UseSegmentSetForPhysRegs(
72 "use-segment-set-for-physregs", cl::Hidden, cl::init(true),
74 "Use segment set for the computation of the live ranges of physregs."));
77 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
79 AU.addRequired<AAResultsWrapperPass>();
80 AU.addPreserved<AAResultsWrapperPass>();
81 // LiveVariables isn't really required by this analysis, it is only required
82 // here to make sure it is live during TwoAddressInstructionPass and
83 // PHIElimination. This is temporary.
84 AU.addRequired<LiveVariables>();
85 AU.addPreserved<LiveVariables>();
86 AU.addPreservedID(MachineLoopInfoID);
87 AU.addRequiredTransitiveID(MachineDominatorsID);
88 AU.addPreservedID(MachineDominatorsID);
89 AU.addPreserved<SlotIndexes>();
90 AU.addRequiredTransitive<SlotIndexes>();
91 MachineFunctionPass::getAnalysisUsage(AU);
94 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
95 DomTree(nullptr), LRCalc(nullptr) {
96 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
99 LiveIntervals::~LiveIntervals() {
103 void LiveIntervals::releaseMemory() {
104 // Free the live intervals themselves.
105 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
106 delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
107 VirtRegIntervals.clear();
108 RegMaskSlots.clear();
110 RegMaskBlocks.clear();
112 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
113 delete RegUnitRanges[i];
114 RegUnitRanges.clear();
116 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
117 VNInfoAllocator.Reset();
120 /// runOnMachineFunction - calculates LiveIntervals
122 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
124 MRI = &MF->getRegInfo();
125 TRI = MF->getSubtarget().getRegisterInfo();
126 TII = MF->getSubtarget().getInstrInfo();
127 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
128 Indexes = &getAnalysis<SlotIndexes>();
129 DomTree = &getAnalysis<MachineDominatorTree>();
131 if (EnableSubRegLiveness && MF->getSubtarget().enableSubRegLiveness())
132 MRI->enableSubRegLiveness(true);
135 LRCalc = new LiveRangeCalc();
137 // Allocate space for all virtual registers.
138 VirtRegIntervals.resize(MRI->getNumVirtRegs());
142 computeLiveInRegUnits();
144 if (EnablePrecomputePhysRegs) {
145 // For stress testing, precompute live ranges of all physical register
146 // units, including reserved registers.
147 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
154 /// print - Implement the dump method.
155 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
156 OS << "********** INTERVALS **********\n";
158 // Dump the regunits.
159 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
160 if (LiveRange *LR = RegUnitRanges[i])
161 OS << PrintRegUnit(i, TRI) << ' ' << *LR << '\n';
163 // Dump the virtregs.
164 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
165 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
166 if (hasInterval(Reg))
167 OS << getInterval(Reg) << '\n';
171 for (unsigned i = 0, e = RegMaskSlots.size(); i != e; ++i)
172 OS << ' ' << RegMaskSlots[i];
178 void LiveIntervals::printInstrs(raw_ostream &OS) const {
179 OS << "********** MACHINEINSTRS **********\n";
180 MF->print(OS, Indexes);
183 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
184 void LiveIntervals::dumpInstrs() const {
189 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
190 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
191 llvm::huge_valf : 0.0F;
192 return new LiveInterval(reg, Weight);
196 /// computeVirtRegInterval - Compute the live interval of a virtual register,
197 /// based on defs and uses.
198 void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
199 assert(LRCalc && "LRCalc not initialized.");
200 assert(LI.empty() && "Should only compute empty intervals.");
201 bool ShouldTrackSubRegLiveness = MRI->shouldTrackSubRegLiveness(LI.reg);
202 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
203 LRCalc->calculate(LI, ShouldTrackSubRegLiveness);
204 bool SeparatedComponents = computeDeadValues(LI, nullptr);
205 if (SeparatedComponents) {
206 assert(ShouldTrackSubRegLiveness
207 && "Separated components should only occur for unused subreg defs");
208 SmallVector<LiveInterval*, 8> SplitLIs;
209 splitSeparateComponents(LI, SplitLIs);
213 void LiveIntervals::computeVirtRegs() {
214 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
215 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
216 if (MRI->reg_nodbg_empty(Reg))
218 createAndComputeVirtRegInterval(Reg);
222 void LiveIntervals::computeRegMasks() {
223 RegMaskBlocks.resize(MF->getNumBlockIDs());
225 // Find all instructions with regmask operands.
226 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
228 MachineBasicBlock *MBB = MBBI;
229 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
230 RMB.first = RegMaskSlots.size();
231 for (MachineBasicBlock::iterator MI = MBB->begin(), ME = MBB->end();
233 for (const MachineOperand &MO : MI->operands()) {
236 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
237 RegMaskBits.push_back(MO.getRegMask());
239 // Compute the number of register mask instructions in this block.
240 RMB.second = RegMaskSlots.size() - RMB.first;
244 //===----------------------------------------------------------------------===//
245 // Register Unit Liveness
246 //===----------------------------------------------------------------------===//
248 // Fixed interference typically comes from ABI boundaries: Function arguments
249 // and return values are passed in fixed registers, and so are exception
250 // pointers entering landing pads. Certain instructions require values to be
251 // present in specific registers. That is also represented through fixed
255 /// computeRegUnitInterval - Compute the live range of a register unit, based
256 /// on the uses and defs of aliasing registers. The range should be empty,
257 /// or contain only dead phi-defs from ABI blocks.
258 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
259 assert(LRCalc && "LRCalc not initialized.");
260 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
262 // The physregs aliasing Unit are the roots and their super-registers.
263 // Create all values as dead defs before extending to uses. Note that roots
264 // may share super-registers. That's OK because createDeadDefs() is
265 // idempotent. It is very rare for a register unit to have multiple roots, so
266 // uniquing super-registers is probably not worthwhile.
267 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
268 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
269 Supers.isValid(); ++Supers) {
270 if (!MRI->reg_empty(*Supers))
271 LRCalc->createDeadDefs(LR, *Supers);
275 // Now extend LR to reach all uses.
276 // Ignore uses of reserved registers. We only track defs of those.
277 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
278 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
279 Supers.isValid(); ++Supers) {
280 unsigned Reg = *Supers;
281 if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg))
282 LRCalc->extendToUses(LR, Reg);
286 // Flush the segment set to the segment vector.
287 if (UseSegmentSetForPhysRegs)
288 LR.flushSegmentSet();
292 /// computeLiveInRegUnits - Precompute the live ranges of any register units
293 /// that are live-in to an ABI block somewhere. Register values can appear
294 /// without a corresponding def when entering the entry block or a landing pad.
296 void LiveIntervals::computeLiveInRegUnits() {
297 RegUnitRanges.resize(TRI->getNumRegUnits());
298 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
300 // Keep track of the live range sets allocated.
301 SmallVector<unsigned, 8> NewRanges;
303 // Check all basic blocks for live-ins.
304 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
306 const MachineBasicBlock *MBB = MFI;
308 // We only care about ABI blocks: Entry + landing pads.
309 if ((MFI != MF->begin() && !MBB->isEHPad()) || MBB->livein_empty())
312 // Create phi-defs at Begin for all live-in registers.
313 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
314 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
315 for (const auto &LI : MBB->liveins()) {
316 for (MCRegUnitIterator Units(LI.PhysReg, TRI); Units.isValid(); ++Units) {
317 unsigned Unit = *Units;
318 LiveRange *LR = RegUnitRanges[Unit];
320 // Use segment set to speed-up initial computation of the live range.
321 LR = RegUnitRanges[Unit] = new LiveRange(UseSegmentSetForPhysRegs);
322 NewRanges.push_back(Unit);
324 VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
326 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
329 DEBUG(dbgs() << '\n');
331 DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");
333 // Compute the 'normal' part of the ranges.
334 for (unsigned i = 0, e = NewRanges.size(); i != e; ++i) {
335 unsigned Unit = NewRanges[i];
336 computeRegUnitRange(*RegUnitRanges[Unit], Unit);
341 static void createSegmentsForValues(LiveRange &LR,
342 iterator_range<LiveInterval::vni_iterator> VNIs) {
343 for (auto VNI : VNIs) {
346 SlotIndex Def = VNI->def;
347 LR.addSegment(LiveRange::Segment(Def, Def.getDeadSlot(), VNI));
351 typedef SmallVector<std::pair<SlotIndex, VNInfo*>, 16> ShrinkToUsesWorkList;
353 static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes,
354 ShrinkToUsesWorkList &WorkList,
355 const LiveRange &OldRange) {
356 // Keep track of the PHIs that are in use.
357 SmallPtrSet<VNInfo*, 8> UsedPHIs;
358 // Blocks that have already been added to WorkList as live-out.
359 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
361 // Extend intervals to reach all uses in WorkList.
362 while (!WorkList.empty()) {
363 SlotIndex Idx = WorkList.back().first;
364 VNInfo *VNI = WorkList.back().second;
366 const MachineBasicBlock *MBB = Indexes.getMBBFromIndex(Idx.getPrevSlot());
367 SlotIndex BlockStart = Indexes.getMBBStartIdx(MBB);
369 // Extend the live range for VNI to be live at Idx.
370 if (VNInfo *ExtVNI = LR.extendInBlock(BlockStart, Idx)) {
371 assert(ExtVNI == VNI && "Unexpected existing value number");
373 // Is this a PHIDef we haven't seen before?
374 if (!VNI->isPHIDef() || VNI->def != BlockStart ||
375 !UsedPHIs.insert(VNI).second)
377 // The PHI is live, make sure the predecessors are live-out.
378 for (auto &Pred : MBB->predecessors()) {
379 if (!LiveOut.insert(Pred).second)
381 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
382 // A predecessor is not required to have a live-out value for a PHI.
383 if (VNInfo *PVNI = OldRange.getVNInfoBefore(Stop))
384 WorkList.push_back(std::make_pair(Stop, PVNI));
389 // VNI is live-in to MBB.
390 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
391 LR.addSegment(LiveRange::Segment(BlockStart, Idx, VNI));
393 // Make sure VNI is live-out from the predecessors.
394 for (auto &Pred : MBB->predecessors()) {
395 if (!LiveOut.insert(Pred).second)
397 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
398 assert(OldRange.getVNInfoBefore(Stop) == VNI &&
399 "Wrong value out of predecessor");
400 WorkList.push_back(std::make_pair(Stop, VNI));
405 bool LiveIntervals::shrinkToUses(LiveInterval *li,
406 SmallVectorImpl<MachineInstr*> *dead) {
407 DEBUG(dbgs() << "Shrink: " << *li << '\n');
408 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
409 && "Can only shrink virtual registers");
411 // Shrink subregister live ranges.
412 bool NeedsCleanup = false;
413 for (LiveInterval::SubRange &S : li->subranges()) {
414 shrinkToUses(S, li->reg);
419 li->removeEmptySubRanges();
421 // Find all the values used, including PHI kills.
422 ShrinkToUsesWorkList WorkList;
424 // Visit all instructions reading li->reg.
425 for (MachineRegisterInfo::reg_instr_iterator
426 I = MRI->reg_instr_begin(li->reg), E = MRI->reg_instr_end();
428 MachineInstr *UseMI = &*(I++);
429 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
431 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
432 LiveQueryResult LRQ = li->Query(Idx);
433 VNInfo *VNI = LRQ.valueIn();
435 // This shouldn't happen: readsVirtualRegister returns true, but there is
436 // no live value. It is likely caused by a target getting <undef> flags
438 DEBUG(dbgs() << Idx << '\t' << *UseMI
439 << "Warning: Instr claims to read non-existent value in "
443 // Special case: An early-clobber tied operand reads and writes the
444 // register one slot early.
445 if (VNInfo *DefVNI = LRQ.valueDefined())
448 WorkList.push_back(std::make_pair(Idx, VNI));
451 // Create new live ranges with only minimal live segments per def.
453 createSegmentsForValues(NewLR, make_range(li->vni_begin(), li->vni_end()));
454 extendSegmentsToUses(NewLR, *Indexes, WorkList, *li);
456 // Move the trimmed segments back.
457 li->segments.swap(NewLR.segments);
459 // Handle dead values.
460 bool CanSeparate = computeDeadValues(*li, dead);
461 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
465 bool LiveIntervals::computeDeadValues(LiveInterval &LI,
466 SmallVectorImpl<MachineInstr*> *dead) {
467 bool MayHaveSplitComponents = false;
468 for (auto VNI : LI.valnos) {
471 SlotIndex Def = VNI->def;
472 LiveRange::iterator I = LI.FindSegmentContaining(Def);
473 assert(I != LI.end() && "Missing segment for VNI");
475 // Is the register live before? Otherwise we may have to add a read-undef
476 // flag for subregister defs.
477 bool DeadBeforeDef = false;
478 unsigned VReg = LI.reg;
479 if (MRI->shouldTrackSubRegLiveness(VReg)) {
480 if ((I == LI.begin() || std::prev(I)->end < Def) && !VNI->isPHIDef()) {
481 MachineInstr *MI = getInstructionFromIndex(Def);
482 MI->addRegisterDefReadUndef(VReg);
483 DeadBeforeDef = true;
487 if (I->end != Def.getDeadSlot())
489 if (VNI->isPHIDef()) {
490 // This is a dead PHI. Remove it.
493 DEBUG(dbgs() << "Dead PHI at " << Def << " may separate interval\n");
494 MayHaveSplitComponents = true;
496 // This is a dead def. Make sure the instruction knows.
497 MachineInstr *MI = getInstructionFromIndex(Def);
498 assert(MI && "No instruction defining live value");
499 MI->addRegisterDead(VReg, TRI);
501 // If we have a dead def that is completely separate from the rest of
502 // the liverange then we rewrite it to use a different VReg to not violate
503 // the rule that the liveness of a virtual register forms a connected
504 // component. This should only happen if subregister liveness is tracked.
506 MayHaveSplitComponents = true;
508 if (dead && MI->allDefsAreDead()) {
509 DEBUG(dbgs() << "All defs dead: " << Def << '\t' << *MI);
514 return MayHaveSplitComponents;
517 void LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg)
519 DEBUG(dbgs() << "Shrink: " << SR << '\n');
520 assert(TargetRegisterInfo::isVirtualRegister(Reg)
521 && "Can only shrink virtual registers");
522 // Find all the values used, including PHI kills.
523 ShrinkToUsesWorkList WorkList;
525 // Visit all instructions reading Reg.
527 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
528 MachineInstr *UseMI = MO.getParent();
529 if (UseMI->isDebugValue())
531 // Maybe the operand is for a subregister we don't care about.
532 unsigned SubReg = MO.getSubReg();
534 unsigned SubRegMask = TRI->getSubRegIndexLaneMask(SubReg);
535 if ((SubRegMask & SR.LaneMask) == 0)
538 // We only need to visit each instruction once.
539 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
544 LiveQueryResult LRQ = SR.Query(Idx);
545 VNInfo *VNI = LRQ.valueIn();
546 // For Subranges it is possible that only undef values are left in that
547 // part of the subregister, so there is no real liverange at the use
551 // Special case: An early-clobber tied operand reads and writes the
552 // register one slot early.
553 if (VNInfo *DefVNI = LRQ.valueDefined())
556 WorkList.push_back(std::make_pair(Idx, VNI));
559 // Create a new live ranges with only minimal live segments per def.
561 createSegmentsForValues(NewLR, make_range(SR.vni_begin(), SR.vni_end()));
562 extendSegmentsToUses(NewLR, *Indexes, WorkList, SR);
564 // Move the trimmed ranges back.
565 SR.segments.swap(NewLR.segments);
567 // Remove dead PHI value numbers
568 for (auto VNI : SR.valnos) {
571 const LiveRange::Segment *Segment = SR.getSegmentContaining(VNI->def);
572 assert(Segment != nullptr && "Missing segment for VNI");
573 if (Segment->end != VNI->def.getDeadSlot())
575 if (VNI->isPHIDef()) {
576 // This is a dead PHI. Remove it.
578 SR.removeSegment(*Segment);
579 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
583 DEBUG(dbgs() << "Shrunk: " << SR << '\n');
586 void LiveIntervals::extendToIndices(LiveRange &LR,
587 ArrayRef<SlotIndex> Indices) {
588 assert(LRCalc && "LRCalc not initialized.");
589 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
590 for (unsigned i = 0, e = Indices.size(); i != e; ++i)
591 LRCalc->extend(LR, Indices[i]);
594 void LiveIntervals::pruneValue(LiveRange &LR, SlotIndex Kill,
595 SmallVectorImpl<SlotIndex> *EndPoints) {
596 LiveQueryResult LRQ = LR.Query(Kill);
597 VNInfo *VNI = LRQ.valueOutOrDead();
601 MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill);
602 SlotIndex MBBEnd = Indexes->getMBBEndIdx(KillMBB);
604 // If VNI isn't live out from KillMBB, the value is trivially pruned.
605 if (LRQ.endPoint() < MBBEnd) {
606 LR.removeSegment(Kill, LRQ.endPoint());
607 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
611 // VNI is live out of KillMBB.
612 LR.removeSegment(Kill, MBBEnd);
613 if (EndPoints) EndPoints->push_back(MBBEnd);
615 // Find all blocks that are reachable from KillMBB without leaving VNI's live
616 // range. It is possible that KillMBB itself is reachable, so start a DFS
617 // from each successor.
618 typedef SmallPtrSet<MachineBasicBlock*, 9> VisitedTy;
620 for (MachineBasicBlock::succ_iterator
621 SuccI = KillMBB->succ_begin(), SuccE = KillMBB->succ_end();
622 SuccI != SuccE; ++SuccI) {
623 for (df_ext_iterator<MachineBasicBlock*, VisitedTy>
624 I = df_ext_begin(*SuccI, Visited), E = df_ext_end(*SuccI, Visited);
626 MachineBasicBlock *MBB = *I;
628 // Check if VNI is live in to MBB.
629 SlotIndex MBBStart, MBBEnd;
630 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);
631 LiveQueryResult LRQ = LR.Query(MBBStart);
632 if (LRQ.valueIn() != VNI) {
633 // This block isn't part of the VNI segment. Prune the search.
638 // Prune the search if VNI is killed in MBB.
639 if (LRQ.endPoint() < MBBEnd) {
640 LR.removeSegment(MBBStart, LRQ.endPoint());
641 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
646 // VNI is live through MBB.
647 LR.removeSegment(MBBStart, MBBEnd);
648 if (EndPoints) EndPoints->push_back(MBBEnd);
654 //===----------------------------------------------------------------------===//
655 // Register allocator hooks.
658 void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
659 // Keep track of regunit ranges.
660 SmallVector<std::pair<const LiveRange*, LiveRange::const_iterator>, 8> RU;
661 // Keep track of subregister ranges.
662 SmallVector<std::pair<const LiveInterval::SubRange*,
663 LiveRange::const_iterator>, 4> SRs;
665 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
666 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
667 if (MRI->reg_nodbg_empty(Reg))
669 const LiveInterval &LI = getInterval(Reg);
673 // Find the regunit intervals for the assigned register. They may overlap
674 // the virtual register live range, cancelling any kills.
676 for (MCRegUnitIterator Units(VRM->getPhys(Reg), TRI); Units.isValid();
678 const LiveRange &RURange = getRegUnit(*Units);
681 RU.push_back(std::make_pair(&RURange, RURange.find(LI.begin()->end)));
684 if (MRI->subRegLivenessEnabled()) {
686 for (const LiveInterval::SubRange &SR : LI.subranges()) {
687 SRs.push_back(std::make_pair(&SR, SR.find(LI.begin()->end)));
691 // Every instruction that kills Reg corresponds to a segment range end
693 for (LiveInterval::const_iterator RI = LI.begin(), RE = LI.end(); RI != RE;
695 // A block index indicates an MBB edge.
696 if (RI->end.isBlock())
698 MachineInstr *MI = getInstructionFromIndex(RI->end);
702 // Check if any of the regunits are live beyond the end of RI. That could
703 // happen when a physreg is defined as a copy of a virtreg:
705 // %EAX = COPY %vreg5
706 // FOO %vreg5 <--- MI, cancel kill because %EAX is live.
709 // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX.
710 for (auto &RUP : RU) {
711 const LiveRange &RURange = *RUP.first;
712 LiveRange::const_iterator &I = RUP.second;
713 if (I == RURange.end())
715 I = RURange.advanceTo(I, RI->end);
716 if (I == RURange.end() || I->start >= RI->end)
718 // I is overlapping RI.
722 if (MRI->subRegLivenessEnabled()) {
723 // When reading a partial undefined value we must not add a kill flag.
724 // The regalloc might have used the undef lane for something else.
726 // %vreg1 = ... ; R32: %vreg1
727 // %vreg2:high16 = ... ; R64: %vreg2
728 // = read %vreg2<kill> ; R64: %vreg2
729 // = read %vreg1 ; R32: %vreg1
730 // The <kill> flag is correct for %vreg2, but the register allocator may
731 // assign R0L to %vreg1, and R0 to %vreg2 because the low 32bits of R0
732 // are actually never written by %vreg2. After assignment the <kill>
733 // flag at the read instruction is invalid.
734 unsigned DefinedLanesMask;
736 // Compute a mask of lanes that are defined.
737 DefinedLanesMask = 0;
738 for (auto &SRP : SRs) {
739 const LiveInterval::SubRange &SR = *SRP.first;
740 LiveRange::const_iterator &I = SRP.second;
743 I = SR.advanceTo(I, RI->end);
744 if (I == SR.end() || I->start >= RI->end)
746 // I is overlapping RI
747 DefinedLanesMask |= SR.LaneMask;
750 DefinedLanesMask = ~0u;
752 bool IsFullWrite = false;
753 for (const MachineOperand &MO : MI->operands()) {
754 if (!MO.isReg() || MO.getReg() != Reg)
757 // Reading any undefined lanes?
758 unsigned UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
759 if ((UseMask & ~DefinedLanesMask) != 0)
761 } else if (MO.getSubReg() == 0) {
762 // Writing to the full register?
768 // If an instruction writes to a subregister, a new segment starts in
769 // the LiveInterval. But as this is only overriding part of the register
770 // adding kill-flags is not correct here after registers have been
773 // Next segment has to be adjacent in the subregister write case.
774 LiveRange::const_iterator N = std::next(RI);
775 if (N != LI.end() && N->start == RI->end)
780 MI->addRegisterKilled(Reg, nullptr);
783 MI->clearRegisterKills(Reg, nullptr);
789 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
790 // A local live range must be fully contained inside the block, meaning it is
791 // defined and killed at instructions, not at block boundaries. It is not
792 // live in or or out of any block.
794 // It is technically possible to have a PHI-defined live range identical to a
795 // single block, but we are going to return false in that case.
797 SlotIndex Start = LI.beginIndex();
801 SlotIndex Stop = LI.endIndex();
805 // getMBBFromIndex doesn't need to search the MBB table when both indexes
806 // belong to proper instructions.
807 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
808 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
809 return MBB1 == MBB2 ? MBB1 : nullptr;
813 LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
814 for (const VNInfo *PHI : LI.valnos) {
815 if (PHI->isUnused() || !PHI->isPHIDef())
817 const MachineBasicBlock *PHIMBB = getMBBFromIndex(PHI->def);
818 // Conservatively return true instead of scanning huge predecessor lists.
819 if (PHIMBB->pred_size() > 100)
821 for (MachineBasicBlock::const_pred_iterator
822 PI = PHIMBB->pred_begin(), PE = PHIMBB->pred_end(); PI != PE; ++PI)
823 if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(*PI)))
830 LiveIntervals::getSpillWeight(bool isDef, bool isUse,
831 const MachineBlockFrequencyInfo *MBFI,
832 const MachineInstr *MI) {
833 BlockFrequency Freq = MBFI->getBlockFreq(MI->getParent());
834 const float Scale = 1.0f / MBFI->getEntryFreq();
835 return (isDef + isUse) * (Freq.getFrequency() * Scale);
839 LiveIntervals::addSegmentToEndOfBlock(unsigned reg, MachineInstr* startInst) {
840 LiveInterval& Interval = createEmptyInterval(reg);
841 VNInfo* VN = Interval.getNextValue(
842 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
843 getVNInfoAllocator());
844 LiveRange::Segment S(
845 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
846 getMBBEndIdx(startInst->getParent()), VN);
847 Interval.addSegment(S);
853 //===----------------------------------------------------------------------===//
854 // Register mask functions
855 //===----------------------------------------------------------------------===//
857 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
858 BitVector &UsableRegs) {
861 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
863 // Use a smaller arrays for local live ranges.
864 ArrayRef<SlotIndex> Slots;
865 ArrayRef<const uint32_t*> Bits;
866 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
867 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
868 Bits = getRegMaskBitsInBlock(MBB->getNumber());
870 Slots = getRegMaskSlots();
871 Bits = getRegMaskBits();
874 // We are going to enumerate all the register mask slots contained in LI.
875 // Start with a binary search of RegMaskSlots to find a starting point.
876 ArrayRef<SlotIndex>::iterator SlotI =
877 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
878 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
880 // No slots in range, LI begins after the last call.
886 assert(*SlotI >= LiveI->start);
887 // Loop over all slots overlapping this segment.
888 while (*SlotI < LiveI->end) {
889 // *SlotI overlaps LI. Collect mask bits.
891 // This is the first overlap. Initialize UsableRegs to all ones.
893 UsableRegs.resize(TRI->getNumRegs(), true);
896 // Remove usable registers clobbered by this mask.
897 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
898 if (++SlotI == SlotE)
901 // *SlotI is beyond the current LI segment.
902 LiveI = LI.advanceTo(LiveI, *SlotI);
905 // Advance SlotI until it overlaps.
906 while (*SlotI < LiveI->start)
907 if (++SlotI == SlotE)
912 //===----------------------------------------------------------------------===//
913 // IntervalUpdate class.
914 //===----------------------------------------------------------------------===//
916 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
917 class LiveIntervals::HMEditor {
920 const MachineRegisterInfo& MRI;
921 const TargetRegisterInfo& TRI;
924 SmallPtrSet<LiveRange*, 8> Updated;
928 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
929 const TargetRegisterInfo& TRI,
930 SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)
931 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),
932 UpdateFlags(UpdateFlags) {}
934 // FIXME: UpdateFlags is a workaround that creates live intervals for all
935 // physregs, even those that aren't needed for regalloc, in order to update
936 // kill flags. This is wasteful. Eventually, LiveVariables will strip all kill
937 // flags, and postRA passes will use a live register utility instead.
938 LiveRange *getRegUnitLI(unsigned Unit) {
940 return &LIS.getRegUnit(Unit);
941 return LIS.getCachedRegUnit(Unit);
944 /// Update all live ranges touched by MI, assuming a move from OldIdx to
946 void updateAllRanges(MachineInstr *MI) {
947 DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " << *MI);
948 bool hasRegMask = false;
949 for (MachineOperand &MO : MI->operands()) {
954 // Aggressively clear all kill flags.
955 // They are reinserted by VirtRegRewriter.
959 unsigned Reg = MO.getReg();
962 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
963 LiveInterval &LI = LIS.getInterval(Reg);
964 if (LI.hasSubRanges()) {
965 unsigned SubReg = MO.getSubReg();
966 unsigned LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
967 for (LiveInterval::SubRange &S : LI.subranges()) {
968 if ((S.LaneMask & LaneMask) == 0)
970 updateRange(S, Reg, S.LaneMask);
973 updateRange(LI, Reg, 0);
977 // For physregs, only update the regunits that actually have a
978 // precomputed live range.
979 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
980 if (LiveRange *LR = getRegUnitLI(*Units))
981 updateRange(*LR, *Units, 0);
984 updateRegMaskSlots();
988 /// Update a single live range, assuming an instruction has been moved from
989 /// OldIdx to NewIdx.
990 void updateRange(LiveRange &LR, unsigned Reg, unsigned LaneMask) {
991 if (!Updated.insert(&LR).second)
995 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
996 dbgs() << PrintReg(Reg);
998 dbgs() << format(" L%04X", LaneMask);
1000 dbgs() << PrintRegUnit(Reg, &TRI);
1002 dbgs() << ":\t" << LR << '\n';
1004 if (SlotIndex::isEarlierInstr(OldIdx, NewIdx))
1007 handleMoveUp(LR, Reg, LaneMask);
1008 DEBUG(dbgs() << " -->\t" << LR << '\n');
1012 /// Update LR to reflect an instruction has been moved downwards from OldIdx
1015 /// 1. Live def at OldIdx:
1016 /// Move def to NewIdx, assert endpoint after NewIdx.
1018 /// 2. Live def at OldIdx, killed at NewIdx:
1019 /// Change to dead def at NewIdx.
1020 /// (Happens when bundling def+kill together).
1022 /// 3. Dead def at OldIdx:
1023 /// Move def to NewIdx, possibly across another live value.
1025 /// 4. Def at OldIdx AND at NewIdx:
1026 /// Remove segment [OldIdx;NewIdx) and value defined at OldIdx.
1027 /// (Happens when bundling multiple defs together).
1029 /// 5. Value read at OldIdx, killed before NewIdx:
1030 /// Extend kill to NewIdx.
1032 void handleMoveDown(LiveRange &LR) {
1033 // First look for a kill at OldIdx.
1034 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
1035 LiveRange::iterator E = LR.end();
1036 // Is LR even live at OldIdx?
1037 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
1040 // Handle a live-in value.
1041 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1042 bool isKill = SlotIndex::isSameInstr(OldIdx, I->end);
1043 // If the live-in value already extends to NewIdx, there is nothing to do.
1044 if (!SlotIndex::isEarlierInstr(I->end, NewIdx))
1046 // Aggressively remove all kill flags from the old kill point.
1047 // Kill flags shouldn't be used while live intervals exist, they will be
1048 // reinserted by VirtRegRewriter.
1049 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(I->end))
1050 for (MIBundleOperands MO(KillMI); MO.isValid(); ++MO)
1051 if (MO->isReg() && MO->isUse())
1052 MO->setIsKill(false);
1053 // Adjust I->end to reach NewIdx. This may temporarily make LR invalid by
1054 // overlapping ranges. Case 5 above.
1055 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1056 // If this was a kill, there may also be a def. Otherwise we're done.
1062 // Check for a def at OldIdx.
1063 if (I == E || !SlotIndex::isSameInstr(OldIdx, I->start))
1065 // We have a def at OldIdx.
1066 VNInfo *DefVNI = I->valno;
1067 assert(DefVNI->def == I->start && "Inconsistent def");
1068 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1069 // If the defined value extends beyond NewIdx, just move the def down.
1070 // This is case 1 above.
1071 if (SlotIndex::isEarlierInstr(NewIdx, I->end)) {
1072 I->start = DefVNI->def;
1075 // The remaining possibilities are now:
1076 // 2. Live def at OldIdx, killed at NewIdx: isSameInstr(I->end, NewIdx).
1077 // 3. Dead def at OldIdx: I->end = OldIdx.getDeadSlot().
1078 // In either case, it is possible that there is an existing def at NewIdx.
1079 assert((I->end == OldIdx.getDeadSlot() ||
1080 SlotIndex::isSameInstr(I->end, NewIdx)) &&
1081 "Cannot move def below kill");
1082 LiveRange::iterator NewI = LR.advanceTo(I, NewIdx.getRegSlot());
1083 if (NewI != E && SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1084 // There is an existing def at NewIdx, case 4 above. The def at OldIdx is
1085 // coalesced into that value.
1086 assert(NewI->valno != DefVNI && "Multiple defs of value?");
1087 LR.removeValNo(DefVNI);
1090 // There was no existing def at NewIdx. Turn *I into a dead def at NewIdx.
1091 // If the def at OldIdx was dead, we allow it to be moved across other LR
1092 // values. The new range should be placed immediately before NewI, move any
1093 // intermediate ranges up.
1094 assert(NewI != I && "Inconsistent iterators");
1095 std::copy(std::next(I), NewI, I);
1097 = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1100 /// Update LR to reflect an instruction has been moved upwards from OldIdx
1103 /// 1. Live def at OldIdx:
1104 /// Hoist def to NewIdx.
1106 /// 2. Dead def at OldIdx:
1107 /// Hoist def+end to NewIdx, possibly move across other values.
1109 /// 3. Dead def at OldIdx AND existing def at NewIdx:
1110 /// Remove value defined at OldIdx, coalescing it with existing value.
1112 /// 4. Live def at OldIdx AND existing def at NewIdx:
1113 /// Remove value defined at NewIdx, hoist OldIdx def to NewIdx.
1114 /// (Happens when bundling multiple defs together).
1116 /// 5. Value killed at OldIdx:
1117 /// Hoist kill to NewIdx, then scan for last kill between NewIdx and
1120 void handleMoveUp(LiveRange &LR, unsigned Reg, unsigned LaneMask) {
1121 // First look for a kill at OldIdx.
1122 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
1123 LiveRange::iterator E = LR.end();
1124 // Is LR even live at OldIdx?
1125 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
1128 // Handle a live-in value.
1129 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1130 // If the live-in value isn't killed here, there is nothing to do.
1131 if (!SlotIndex::isSameInstr(OldIdx, I->end))
1133 // Adjust I->end to end at NewIdx. If we are hoisting a kill above
1134 // another use, we need to search for that use. Case 5 above.
1135 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1137 // If OldIdx also defines a value, there couldn't have been another use.
1138 if (I == E || !SlotIndex::isSameInstr(I->start, OldIdx)) {
1139 // No def, search for the new kill.
1140 // This can never be an early clobber kill since there is no def.
1141 std::prev(I)->end = findLastUseBefore(Reg, LaneMask).getRegSlot();
1146 // Now deal with the def at OldIdx.
1147 assert(I != E && SlotIndex::isSameInstr(I->start, OldIdx) && "No def?");
1148 VNInfo *DefVNI = I->valno;
1149 assert(DefVNI->def == I->start && "Inconsistent def");
1150 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1152 // Check for an existing def at NewIdx.
1153 LiveRange::iterator NewI = LR.find(NewIdx.getRegSlot());
1154 if (SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1155 assert(NewI->valno != DefVNI && "Same value defined more than once?");
1156 // There is an existing def at NewIdx.
1157 if (I->end.isDead()) {
1158 // Case 3: Remove the dead def at OldIdx.
1159 LR.removeValNo(DefVNI);
1162 // Case 4: Replace def at NewIdx with live def at OldIdx.
1163 I->start = DefVNI->def;
1164 LR.removeValNo(NewI->valno);
1168 // There is no existing def at NewIdx. Hoist DefVNI.
1169 if (!I->end.isDead()) {
1170 // Leave the end point of a live def.
1171 I->start = DefVNI->def;
1175 // DefVNI is a dead def. It may have been moved across other values in LR,
1176 // so move I up to NewI. Slide [NewI;I) down one position.
1177 std::copy_backward(NewI, I, std::next(I));
1178 *NewI = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1181 void updateRegMaskSlots() {
1182 SmallVectorImpl<SlotIndex>::iterator RI =
1183 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1185 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&
1186 "No RegMask at OldIdx.");
1187 *RI = NewIdx.getRegSlot();
1188 assert((RI == LIS.RegMaskSlots.begin() ||
1189 SlotIndex::isEarlierInstr(*std::prev(RI), *RI)) &&
1190 "Cannot move regmask instruction above another call");
1191 assert((std::next(RI) == LIS.RegMaskSlots.end() ||
1192 SlotIndex::isEarlierInstr(*RI, *std::next(RI))) &&
1193 "Cannot move regmask instruction below another call");
1196 // Return the last use of reg between NewIdx and OldIdx.
1197 SlotIndex findLastUseBefore(unsigned Reg, unsigned LaneMask) {
1199 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1200 SlotIndex LastUse = NewIdx;
1201 for (MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
1202 unsigned SubReg = MO.getSubReg();
1203 if (SubReg != 0 && LaneMask != 0
1204 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask) == 0)
1207 const MachineInstr *MI = MO.getParent();
1208 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1209 if (InstSlot > LastUse && InstSlot < OldIdx)
1215 // This is a regunit interval, so scanning the use list could be very
1216 // expensive. Scan upwards from OldIdx instead.
1217 assert(NewIdx < OldIdx && "Expected upwards move");
1218 SlotIndexes *Indexes = LIS.getSlotIndexes();
1219 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(NewIdx);
1221 // OldIdx may not correspond to an instruction any longer, so set MII to
1222 // point to the next instruction after OldIdx, or MBB->end().
1223 MachineBasicBlock::iterator MII = MBB->end();
1224 if (MachineInstr *MI = Indexes->getInstructionFromIndex(
1225 Indexes->getNextNonNullIndex(OldIdx)))
1226 if (MI->getParent() == MBB)
1229 MachineBasicBlock::iterator Begin = MBB->begin();
1230 while (MII != Begin) {
1231 if ((--MII)->isDebugValue())
1233 SlotIndex Idx = Indexes->getInstructionIndex(MII);
1235 // Stop searching when NewIdx is reached.
1236 if (!SlotIndex::isEarlierInstr(NewIdx, Idx))
1239 // Check if MII uses Reg.
1240 for (MIBundleOperands MO(MII); MO.isValid(); ++MO)
1242 TargetRegisterInfo::isPhysicalRegister(MO->getReg()) &&
1243 TRI.hasRegUnit(MO->getReg(), Reg))
1246 // Didn't reach NewIdx. It must be the first instruction in the block.
1251 void LiveIntervals::handleMove(MachineInstr* MI, bool UpdateFlags) {
1252 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1253 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1254 Indexes->removeMachineInstrFromMaps(MI);
1255 SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
1256 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1257 OldIndex < getMBBEndIdx(MI->getParent()) &&
1258 "Cannot handle moves across basic block boundaries.");
1260 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1261 HME.updateAllRanges(MI);
1264 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1265 MachineInstr* BundleStart,
1267 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1268 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1269 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1270 HME.updateAllRanges(MI);
1273 void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
1274 const MachineBasicBlock::iterator End,
1275 const SlotIndex endIdx,
1276 LiveRange &LR, const unsigned Reg,
1277 const unsigned LaneMask) {
1278 LiveInterval::iterator LII = LR.find(endIdx);
1279 SlotIndex lastUseIdx;
1280 if (LII != LR.end() && LII->start < endIdx)
1281 lastUseIdx = LII->end;
1285 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1287 MachineInstr *MI = I;
1288 if (MI->isDebugValue())
1291 SlotIndex instrIdx = getInstructionIndex(MI);
1292 bool isStartValid = getInstructionFromIndex(LII->start);
1293 bool isEndValid = getInstructionFromIndex(LII->end);
1295 // FIXME: This doesn't currently handle early-clobber or multiple removed
1296 // defs inside of the region to repair.
1297 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
1298 OE = MI->operands_end(); OI != OE; ++OI) {
1299 const MachineOperand &MO = *OI;
1300 if (!MO.isReg() || MO.getReg() != Reg)
1303 unsigned SubReg = MO.getSubReg();
1304 unsigned Mask = TRI->getSubRegIndexLaneMask(SubReg);
1305 if ((Mask & LaneMask) == 0)
1309 if (!isStartValid) {
1310 if (LII->end.isDead()) {
1311 SlotIndex prevStart;
1312 if (LII != LR.begin())
1313 prevStart = std::prev(LII)->start;
1315 // FIXME: This could be more efficient if there was a
1316 // removeSegment method that returned an iterator.
1317 LR.removeSegment(*LII, true);
1318 if (prevStart.isValid())
1319 LII = LR.find(prevStart);
1323 LII->start = instrIdx.getRegSlot();
1324 LII->valno->def = instrIdx.getRegSlot();
1325 if (MO.getSubReg() && !MO.isUndef())
1326 lastUseIdx = instrIdx.getRegSlot();
1328 lastUseIdx = SlotIndex();
1333 if (!lastUseIdx.isValid()) {
1334 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1335 LiveRange::Segment S(instrIdx.getRegSlot(),
1336 instrIdx.getDeadSlot(), VNI);
1337 LII = LR.addSegment(S);
1338 } else if (LII->start != instrIdx.getRegSlot()) {
1339 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1340 LiveRange::Segment S(instrIdx.getRegSlot(), lastUseIdx, VNI);
1341 LII = LR.addSegment(S);
1344 if (MO.getSubReg() && !MO.isUndef())
1345 lastUseIdx = instrIdx.getRegSlot();
1347 lastUseIdx = SlotIndex();
1348 } else if (MO.isUse()) {
1349 // FIXME: This should probably be handled outside of this branch,
1350 // either as part of the def case (for defs inside of the region) or
1351 // after the loop over the region.
1352 if (!isEndValid && !LII->end.isBlock())
1353 LII->end = instrIdx.getRegSlot();
1354 if (!lastUseIdx.isValid())
1355 lastUseIdx = instrIdx.getRegSlot();
1362 LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
1363 MachineBasicBlock::iterator Begin,
1364 MachineBasicBlock::iterator End,
1365 ArrayRef<unsigned> OrigRegs) {
1366 // Find anchor points, which are at the beginning/end of blocks or at
1367 // instructions that already have indexes.
1368 while (Begin != MBB->begin() && !Indexes->hasIndex(Begin))
1370 while (End != MBB->end() && !Indexes->hasIndex(End))
1374 if (End == MBB->end())
1375 endIdx = getMBBEndIdx(MBB).getPrevSlot();
1377 endIdx = getInstructionIndex(End);
1379 Indexes->repairIndexesInRange(MBB, Begin, End);
1381 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1383 MachineInstr *MI = I;
1384 if (MI->isDebugValue())
1386 for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
1387 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
1389 TargetRegisterInfo::isVirtualRegister(MOI->getReg()) &&
1390 !hasInterval(MOI->getReg())) {
1391 createAndComputeVirtRegInterval(MOI->getReg());
1396 for (unsigned i = 0, e = OrigRegs.size(); i != e; ++i) {
1397 unsigned Reg = OrigRegs[i];
1398 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1401 LiveInterval &LI = getInterval(Reg);
1402 // FIXME: Should we support undefs that gain defs?
1403 if (!LI.hasAtLeastOneValue())
1406 for (LiveInterval::SubRange &S : LI.subranges()) {
1407 repairOldRegInRange(Begin, End, endIdx, S, Reg, S.LaneMask);
1409 repairOldRegInRange(Begin, End, endIdx, LI, Reg);
1413 void LiveIntervals::removePhysRegDefAt(unsigned Reg, SlotIndex Pos) {
1414 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
1415 if (LiveRange *LR = getCachedRegUnit(*Units))
1416 if (VNInfo *VNI = LR->getVNInfoAt(Pos))
1417 LR->removeValNo(VNI);
1421 void LiveIntervals::removeVRegDefAt(LiveInterval &LI, SlotIndex Pos) {
1422 VNInfo *VNI = LI.getVNInfoAt(Pos);
1425 LI.removeValNo(VNI);
1427 // Also remove the value in subranges.
1428 for (LiveInterval::SubRange &S : LI.subranges()) {
1429 if (VNInfo *SVNI = S.getVNInfoAt(Pos))
1430 S.removeValNo(SVNI);
1432 LI.removeEmptySubRanges();
1435 void LiveIntervals::splitSeparateComponents(LiveInterval &LI,
1436 SmallVectorImpl<LiveInterval*> &SplitLIs) {
1437 ConnectedVNInfoEqClasses ConEQ(*this);
1438 unsigned NumComp = ConEQ.Classify(&LI);
1441 DEBUG(dbgs() << " Split " << NumComp << " components: " << LI << '\n');
1442 unsigned Reg = LI.reg;
1443 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
1444 for (unsigned I = 1; I < NumComp; ++I) {
1445 unsigned NewVReg = MRI->createVirtualRegister(RegClass);
1446 LiveInterval &NewLI = createEmptyInterval(NewVReg);
1447 SplitLIs.push_back(&NewLI);
1449 ConEQ.Distribute(LI, SplitLIs.data(), *MRI);