1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "LiveRangeCalc.h"
20 #include "llvm/ADT/DenseSet.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/IR/Value.h"
31 #include "llvm/Support/BlockFrequency.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/Format.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
45 #define DEBUG_TYPE "regalloc"
47 char LiveIntervals::ID = 0;
48 char &llvm::LiveIntervalsID = LiveIntervals::ID;
49 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
50 "Live Interval Analysis", false, false)
51 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
52 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
53 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
54 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
55 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
56 "Live Interval Analysis", false, false)
59 static cl::opt<bool> EnablePrecomputePhysRegs(
60 "precompute-phys-liveness", cl::Hidden,
61 cl::desc("Eagerly compute live intervals for all physreg units."));
63 static bool EnablePrecomputePhysRegs = false;
66 static cl::opt<bool> EnableSubRegLiveness(
67 "enable-subreg-liveness", cl::Hidden, cl::init(true),
68 cl::desc("Enable subregister liveness tracking."));
70 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
72 AU.addRequired<AliasAnalysis>();
73 AU.addPreserved<AliasAnalysis>();
74 // LiveVariables isn't really required by this analysis, it is only required
75 // here to make sure it is live during TwoAddressInstructionPass and
76 // PHIElimination. This is temporary.
77 AU.addRequired<LiveVariables>();
78 AU.addPreserved<LiveVariables>();
79 AU.addPreservedID(MachineLoopInfoID);
80 AU.addRequiredTransitiveID(MachineDominatorsID);
81 AU.addPreservedID(MachineDominatorsID);
82 AU.addPreserved<SlotIndexes>();
83 AU.addRequiredTransitive<SlotIndexes>();
84 MachineFunctionPass::getAnalysisUsage(AU);
87 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
88 DomTree(nullptr), LRCalc(nullptr) {
89 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
92 LiveIntervals::~LiveIntervals() {
96 void LiveIntervals::releaseMemory() {
97 // Free the live intervals themselves.
98 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
99 delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
100 VirtRegIntervals.clear();
101 RegMaskSlots.clear();
103 RegMaskBlocks.clear();
105 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
106 delete RegUnitRanges[i];
107 RegUnitRanges.clear();
109 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
110 VNInfoAllocator.Reset();
113 /// runOnMachineFunction - calculates LiveIntervals
115 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
117 MRI = &MF->getRegInfo();
118 TRI = MF->getSubtarget().getRegisterInfo();
119 TII = MF->getSubtarget().getInstrInfo();
120 AA = &getAnalysis<AliasAnalysis>();
121 Indexes = &getAnalysis<SlotIndexes>();
122 DomTree = &getAnalysis<MachineDominatorTree>();
124 if (EnableSubRegLiveness && MF->getSubtarget().enableSubRegLiveness())
125 MRI->enableSubRegLiveness(true);
128 LRCalc = new LiveRangeCalc();
130 // Allocate space for all virtual registers.
131 VirtRegIntervals.resize(MRI->getNumVirtRegs());
135 computeLiveInRegUnits();
137 if (EnablePrecomputePhysRegs) {
138 // For stress testing, precompute live ranges of all physical register
139 // units, including reserved registers.
140 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
147 /// print - Implement the dump method.
148 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
149 OS << "********** INTERVALS **********\n";
151 // Dump the regunits.
152 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
153 if (LiveRange *LR = RegUnitRanges[i])
154 OS << PrintRegUnit(i, TRI) << ' ' << *LR << '\n';
156 // Dump the virtregs.
157 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
158 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
159 if (hasInterval(Reg))
160 OS << getInterval(Reg) << '\n';
164 for (unsigned i = 0, e = RegMaskSlots.size(); i != e; ++i)
165 OS << ' ' << RegMaskSlots[i];
171 void LiveIntervals::printInstrs(raw_ostream &OS) const {
172 OS << "********** MACHINEINSTRS **********\n";
173 MF->print(OS, Indexes);
176 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
177 void LiveIntervals::dumpInstrs() const {
182 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
183 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
184 llvm::huge_valf : 0.0F;
185 return new LiveInterval(reg, Weight);
189 /// computeVirtRegInterval - Compute the live interval of a virtual register,
190 /// based on defs and uses.
191 void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
192 assert(LRCalc && "LRCalc not initialized.");
193 assert(LI.empty() && "Should only compute empty intervals.");
194 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
195 LRCalc->calculate(LI);
196 computeDeadValues(LI, nullptr);
199 void LiveIntervals::computeVirtRegs() {
200 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
201 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
202 if (MRI->reg_nodbg_empty(Reg))
204 createAndComputeVirtRegInterval(Reg);
208 void LiveIntervals::computeRegMasks() {
209 RegMaskBlocks.resize(MF->getNumBlockIDs());
211 // Find all instructions with regmask operands.
212 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
214 MachineBasicBlock *MBB = MBBI;
215 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
216 RMB.first = RegMaskSlots.size();
217 for (MachineBasicBlock::iterator MI = MBB->begin(), ME = MBB->end();
219 for (MIOperands MO(MI); MO.isValid(); ++MO) {
220 if (!MO->isRegMask())
222 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
223 RegMaskBits.push_back(MO->getRegMask());
225 // Compute the number of register mask instructions in this block.
226 RMB.second = RegMaskSlots.size() - RMB.first;
230 //===----------------------------------------------------------------------===//
231 // Register Unit Liveness
232 //===----------------------------------------------------------------------===//
234 // Fixed interference typically comes from ABI boundaries: Function arguments
235 // and return values are passed in fixed registers, and so are exception
236 // pointers entering landing pads. Certain instructions require values to be
237 // present in specific registers. That is also represented through fixed
241 /// computeRegUnitInterval - Compute the live range of a register unit, based
242 /// on the uses and defs of aliasing registers. The range should be empty,
243 /// or contain only dead phi-defs from ABI blocks.
244 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
245 assert(LRCalc && "LRCalc not initialized.");
246 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
248 // The physregs aliasing Unit are the roots and their super-registers.
249 // Create all values as dead defs before extending to uses. Note that roots
250 // may share super-registers. That's OK because createDeadDefs() is
251 // idempotent. It is very rare for a register unit to have multiple roots, so
252 // uniquing super-registers is probably not worthwhile.
253 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
254 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
255 Supers.isValid(); ++Supers) {
256 if (!MRI->reg_empty(*Supers))
257 LRCalc->createDeadDefs(LR, *Supers);
261 // Now extend LR to reach all uses.
262 // Ignore uses of reserved registers. We only track defs of those.
263 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
264 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
265 Supers.isValid(); ++Supers) {
266 unsigned Reg = *Supers;
267 if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg))
268 LRCalc->extendToUses(LR, Reg);
274 /// computeLiveInRegUnits - Precompute the live ranges of any register units
275 /// that are live-in to an ABI block somewhere. Register values can appear
276 /// without a corresponding def when entering the entry block or a landing pad.
278 void LiveIntervals::computeLiveInRegUnits() {
279 RegUnitRanges.resize(TRI->getNumRegUnits());
280 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
282 // Keep track of the live range sets allocated.
283 SmallVector<unsigned, 8> NewRanges;
285 // Check all basic blocks for live-ins.
286 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
288 const MachineBasicBlock *MBB = MFI;
290 // We only care about ABI blocks: Entry + landing pads.
291 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
294 // Create phi-defs at Begin for all live-in registers.
295 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
296 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
297 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
298 LIE = MBB->livein_end(); LII != LIE; ++LII) {
299 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
300 unsigned Unit = *Units;
301 LiveRange *LR = RegUnitRanges[Unit];
303 LR = RegUnitRanges[Unit] = new LiveRange();
304 NewRanges.push_back(Unit);
306 VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
308 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
311 DEBUG(dbgs() << '\n');
313 DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");
315 // Compute the 'normal' part of the ranges.
316 for (unsigned i = 0, e = NewRanges.size(); i != e; ++i) {
317 unsigned Unit = NewRanges[i];
318 computeRegUnitRange(*RegUnitRanges[Unit], Unit);
323 static void createSegmentsForValues(LiveRange &LR,
324 iterator_range<LiveInterval::vni_iterator> VNIs) {
325 for (auto VNI : VNIs) {
328 SlotIndex Def = VNI->def;
329 LR.addSegment(LiveRange::Segment(Def, Def.getDeadSlot(), VNI));
333 typedef SmallVector<std::pair<SlotIndex, VNInfo*>, 16> ShrinkToUsesWorkList;
335 static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes,
336 ShrinkToUsesWorkList &WorkList,
337 const LiveRange &OldRange) {
338 // Keep track of the PHIs that are in use.
339 SmallPtrSet<VNInfo*, 8> UsedPHIs;
340 // Blocks that have already been added to WorkList as live-out.
341 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
343 // Extend intervals to reach all uses in WorkList.
344 while (!WorkList.empty()) {
345 SlotIndex Idx = WorkList.back().first;
346 VNInfo *VNI = WorkList.back().second;
348 const MachineBasicBlock *MBB = Indexes.getMBBFromIndex(Idx.getPrevSlot());
349 SlotIndex BlockStart = Indexes.getMBBStartIdx(MBB);
351 // Extend the live range for VNI to be live at Idx.
352 if (VNInfo *ExtVNI = LR.extendInBlock(BlockStart, Idx)) {
353 assert(ExtVNI == VNI && "Unexpected existing value number");
355 // Is this a PHIDef we haven't seen before?
356 if (!VNI->isPHIDef() || VNI->def != BlockStart ||
357 !UsedPHIs.insert(VNI).second)
359 // The PHI is live, make sure the predecessors are live-out.
360 for (auto &Pred : MBB->predecessors()) {
361 if (!LiveOut.insert(Pred).second)
363 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
364 // A predecessor is not required to have a live-out value for a PHI.
365 if (VNInfo *PVNI = OldRange.getVNInfoBefore(Stop))
366 WorkList.push_back(std::make_pair(Stop, PVNI));
371 // VNI is live-in to MBB.
372 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
373 LR.addSegment(LiveRange::Segment(BlockStart, Idx, VNI));
375 // Make sure VNI is live-out from the predecessors.
376 for (auto &Pred : MBB->predecessors()) {
377 if (!LiveOut.insert(Pred).second)
379 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
380 assert(OldRange.getVNInfoBefore(Stop) == VNI &&
381 "Wrong value out of predecessor");
382 WorkList.push_back(std::make_pair(Stop, VNI));
387 /// shrinkToUses - After removing some uses of a register, shrink its live
388 /// range to just the remaining uses. This method does not compute reaching
389 /// defs for new uses, and it doesn't remove dead defs.
390 bool LiveIntervals::shrinkToUses(LiveInterval *li,
391 SmallVectorImpl<MachineInstr*> *dead) {
392 DEBUG(dbgs() << "Shrink: " << *li << '\n');
393 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
394 && "Can only shrink virtual registers");
396 // Shrink subregister live ranges.
397 for (LiveInterval::SubRange &S : li->subranges()) {
398 shrinkToUses(S, li->reg);
401 // Find all the values used, including PHI kills.
402 ShrinkToUsesWorkList WorkList;
404 // Visit all instructions reading li->reg.
405 for (MachineRegisterInfo::reg_instr_iterator
406 I = MRI->reg_instr_begin(li->reg), E = MRI->reg_instr_end();
408 MachineInstr *UseMI = &*(I++);
409 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
411 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
412 LiveQueryResult LRQ = li->Query(Idx);
413 VNInfo *VNI = LRQ.valueIn();
415 // This shouldn't happen: readsVirtualRegister returns true, but there is
416 // no live value. It is likely caused by a target getting <undef> flags
418 DEBUG(dbgs() << Idx << '\t' << *UseMI
419 << "Warning: Instr claims to read non-existent value in "
423 // Special case: An early-clobber tied operand reads and writes the
424 // register one slot early.
425 if (VNInfo *DefVNI = LRQ.valueDefined())
428 WorkList.push_back(std::make_pair(Idx, VNI));
431 // Create new live ranges with only minimal live segments per def.
433 createSegmentsForValues(NewLR, make_range(li->vni_begin(), li->vni_end()));
434 extendSegmentsToUses(NewLR, *Indexes, WorkList, *li);
436 // Move the trimmed segments back.
437 li->segments.swap(NewLR.segments);
439 // Handle dead values.
440 bool CanSeparate = computeDeadValues(*li, dead);
441 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
445 bool LiveIntervals::computeDeadValues(LiveInterval &LI,
446 SmallVectorImpl<MachineInstr*> *dead) {
447 bool PHIRemoved = false;
448 for (auto VNI : LI.valnos) {
451 LiveRange::iterator I = LI.FindSegmentContaining(VNI->def);
452 assert(I != LI.end() && "Missing segment for VNI");
453 if (I->end != VNI->def.getDeadSlot())
455 if (VNI->isPHIDef()) {
456 // This is a dead PHI. Remove it.
459 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
462 // This is a dead def. Make sure the instruction knows.
463 MachineInstr *MI = getInstructionFromIndex(VNI->def);
464 assert(MI && "No instruction defining live value");
465 MI->addRegisterDead(LI.reg, TRI);
466 if (dead && MI->allDefsAreDead()) {
467 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
475 void LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg)
477 DEBUG(dbgs() << "Shrink: " << SR << '\n');
478 assert(TargetRegisterInfo::isVirtualRegister(Reg)
479 && "Can only shrink virtual registers");
480 // Find all the values used, including PHI kills.
481 ShrinkToUsesWorkList WorkList;
483 // Visit all instructions reading Reg.
485 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
486 MachineInstr *UseMI = MO.getParent();
487 if (UseMI->isDebugValue())
489 // Maybe the operand is for a subregister we don't care about.
490 unsigned SubReg = MO.getSubReg();
492 unsigned SubRegMask = TRI->getSubRegIndexLaneMask(SubReg);
493 if ((SubRegMask & SR.LaneMask) == 0)
496 // We only need to visit each instruction once.
497 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
502 LiveQueryResult LRQ = SR.Query(Idx);
503 VNInfo *VNI = LRQ.valueIn();
504 // For Subranges it is possible that only undef values are left in that
505 // part of the subregister, so there is no real liverange at the use
509 // Special case: An early-clobber tied operand reads and writes the
510 // register one slot early.
511 if (VNInfo *DefVNI = LRQ.valueDefined())
514 WorkList.push_back(std::make_pair(Idx, VNI));
517 // Create a new live ranges with only minimal live segments per def.
519 createSegmentsForValues(NewLR, make_range(SR.vni_begin(), SR.vni_end()));
520 extendSegmentsToUses(NewLR, *Indexes, WorkList, SR);
522 // Move the trimmed ranges back.
523 SR.segments.swap(NewLR.segments);
525 // Remove dead PHI value numbers
526 for (auto VNI : SR.valnos) {
529 const LiveRange::Segment *Segment = SR.getSegmentContaining(VNI->def);
530 assert(Segment != nullptr && "Missing segment for VNI");
531 if (Segment->end != VNI->def.getDeadSlot())
533 if (VNI->isPHIDef()) {
534 // This is a dead PHI. Remove it.
536 SR.removeSegment(*Segment);
537 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
541 DEBUG(dbgs() << "Shrunk: " << SR << '\n');
544 void LiveIntervals::extendToIndices(LiveRange &LR,
545 ArrayRef<SlotIndex> Indices) {
546 assert(LRCalc && "LRCalc not initialized.");
547 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
548 for (unsigned i = 0, e = Indices.size(); i != e; ++i)
549 LRCalc->extend(LR, Indices[i]);
552 void LiveIntervals::pruneValue(LiveRange &LR, SlotIndex Kill,
553 SmallVectorImpl<SlotIndex> *EndPoints) {
554 LiveQueryResult LRQ = LR.Query(Kill);
555 VNInfo *VNI = LRQ.valueOutOrDead();
559 MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill);
560 SlotIndex MBBEnd = Indexes->getMBBEndIdx(KillMBB);
562 // If VNI isn't live out from KillMBB, the value is trivially pruned.
563 if (LRQ.endPoint() < MBBEnd) {
564 LR.removeSegment(Kill, LRQ.endPoint());
565 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
569 // VNI is live out of KillMBB.
570 LR.removeSegment(Kill, MBBEnd);
571 if (EndPoints) EndPoints->push_back(MBBEnd);
573 // Find all blocks that are reachable from KillMBB without leaving VNI's live
574 // range. It is possible that KillMBB itself is reachable, so start a DFS
575 // from each successor.
576 typedef SmallPtrSet<MachineBasicBlock*, 9> VisitedTy;
578 for (MachineBasicBlock::succ_iterator
579 SuccI = KillMBB->succ_begin(), SuccE = KillMBB->succ_end();
580 SuccI != SuccE; ++SuccI) {
581 for (df_ext_iterator<MachineBasicBlock*, VisitedTy>
582 I = df_ext_begin(*SuccI, Visited), E = df_ext_end(*SuccI, Visited);
584 MachineBasicBlock *MBB = *I;
586 // Check if VNI is live in to MBB.
587 SlotIndex MBBStart, MBBEnd;
588 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);
589 LiveQueryResult LRQ = LR.Query(MBBStart);
590 if (LRQ.valueIn() != VNI) {
591 // This block isn't part of the VNI segment. Prune the search.
596 // Prune the search if VNI is killed in MBB.
597 if (LRQ.endPoint() < MBBEnd) {
598 LR.removeSegment(MBBStart, LRQ.endPoint());
599 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
604 // VNI is live through MBB.
605 LR.removeSegment(MBBStart, MBBEnd);
606 if (EndPoints) EndPoints->push_back(MBBEnd);
612 //===----------------------------------------------------------------------===//
613 // Register allocator hooks.
616 void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
617 // Keep track of regunit ranges.
618 SmallVector<std::pair<const LiveRange*, LiveRange::const_iterator>, 8> RU;
619 // Keep track of subregister ranges.
620 SmallVector<std::pair<const LiveInterval::SubRange*,
621 LiveRange::const_iterator>, 4> SRs;
623 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
624 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
625 if (MRI->reg_nodbg_empty(Reg))
627 const LiveInterval &LI = getInterval(Reg);
631 // Find the regunit intervals for the assigned register. They may overlap
632 // the virtual register live range, cancelling any kills.
634 for (MCRegUnitIterator Units(VRM->getPhys(Reg), TRI); Units.isValid();
636 const LiveRange &RURange = getRegUnit(*Units);
639 RU.push_back(std::make_pair(&RURange, RURange.find(LI.begin()->end)));
642 if (MRI->tracksSubRegLiveness()) {
644 for (const LiveInterval::SubRange &SR : LI.subranges()) {
645 SRs.push_back(std::make_pair(&SR, SR.find(LI.begin()->end)));
649 // Every instruction that kills Reg corresponds to a segment range end
651 for (LiveInterval::const_iterator RI = LI.begin(), RE = LI.end(); RI != RE;
653 // A block index indicates an MBB edge.
654 if (RI->end.isBlock())
656 MachineInstr *MI = getInstructionFromIndex(RI->end);
660 // Check if any of the regunits are live beyond the end of RI. That could
661 // happen when a physreg is defined as a copy of a virtreg:
663 // %EAX = COPY %vreg5
664 // FOO %vreg5 <--- MI, cancel kill because %EAX is live.
667 // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX.
668 for (auto &RUP : RU) {
669 const LiveRange &RURange = *RUP.first;
670 LiveRange::const_iterator &I = RUP.second;
671 if (I == RURange.end())
673 I = RURange.advanceTo(I, RI->end);
674 if (I == RURange.end() || I->start >= RI->end)
676 // I is overlapping RI.
680 if (MRI->tracksSubRegLiveness()) {
681 // When reading a partial undefined value we must not add a kill flag.
682 // The regalloc might have used the undef lane for something else.
684 // %vreg1 = ... ; R32: %vreg1
685 // %vreg2:high16 = ... ; R64: %vreg2
686 // = read %vreg2<kill> ; R64: %vreg2
687 // = read %vreg1 ; R32: %vreg1
688 // The <kill> flag is correct for %vreg2, but the register allocator may
689 // assign R0L to %vreg1, and R0 to %vreg2 because the low 32bits of R0
690 // are actually never written by %vreg2. After assignment the <kill>
691 // flag at the read instruction is invalid.
692 unsigned DefinedLanesMask;
694 // Compute a mask of lanes that are defined.
695 DefinedLanesMask = 0;
696 for (auto &SRP : SRs) {
697 const LiveInterval::SubRange &SR = *SRP.first;
698 LiveRange::const_iterator &I = SRP.second;
701 I = SR.advanceTo(I, RI->end);
702 if (I == SR.end() || I->start >= RI->end)
704 // I is overlapping RI
705 DefinedLanesMask |= SR.LaneMask;
708 DefinedLanesMask = ~0u;
710 bool IsFullWrite = false;
711 for (const MachineOperand &MO : MI->operands()) {
712 if (!MO.isReg() || MO.getReg() != Reg)
715 // Reading any undefined lanes?
716 unsigned UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
717 if ((UseMask & ~DefinedLanesMask) != 0)
719 } else if (MO.getSubReg() == 0) {
720 // Writing to the full register?
726 // If an instruction writes to a subregister, a new segment starts in
727 // the LiveInterval. But as this is only overriding part of the register
728 // adding kill-flags is not correct here after registers have been
731 // Next segment has to be adjacent in the subregister write case.
732 LiveRange::const_iterator N = std::next(RI);
733 if (N != LI.end() && N->start == RI->end)
738 MI->addRegisterKilled(Reg, nullptr);
741 MI->clearRegisterKills(Reg, nullptr);
747 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
748 // A local live range must be fully contained inside the block, meaning it is
749 // defined and killed at instructions, not at block boundaries. It is not
750 // live in or or out of any block.
752 // It is technically possible to have a PHI-defined live range identical to a
753 // single block, but we are going to return false in that case.
755 SlotIndex Start = LI.beginIndex();
759 SlotIndex Stop = LI.endIndex();
763 // getMBBFromIndex doesn't need to search the MBB table when both indexes
764 // belong to proper instructions.
765 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
766 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
767 return MBB1 == MBB2 ? MBB1 : nullptr;
771 LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
772 for (const VNInfo *PHI : LI.valnos) {
773 if (PHI->isUnused() || !PHI->isPHIDef())
775 const MachineBasicBlock *PHIMBB = getMBBFromIndex(PHI->def);
776 // Conservatively return true instead of scanning huge predecessor lists.
777 if (PHIMBB->pred_size() > 100)
779 for (MachineBasicBlock::const_pred_iterator
780 PI = PHIMBB->pred_begin(), PE = PHIMBB->pred_end(); PI != PE; ++PI)
781 if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(*PI)))
788 LiveIntervals::getSpillWeight(bool isDef, bool isUse,
789 const MachineBlockFrequencyInfo *MBFI,
790 const MachineInstr *MI) {
791 BlockFrequency Freq = MBFI->getBlockFreq(MI->getParent());
792 const float Scale = 1.0f / MBFI->getEntryFreq();
793 return (isDef + isUse) * (Freq.getFrequency() * Scale);
797 LiveIntervals::addSegmentToEndOfBlock(unsigned reg, MachineInstr* startInst) {
798 LiveInterval& Interval = createEmptyInterval(reg);
799 VNInfo* VN = Interval.getNextValue(
800 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
801 getVNInfoAllocator());
802 LiveRange::Segment S(
803 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
804 getMBBEndIdx(startInst->getParent()), VN);
805 Interval.addSegment(S);
811 //===----------------------------------------------------------------------===//
812 // Register mask functions
813 //===----------------------------------------------------------------------===//
815 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
816 BitVector &UsableRegs) {
819 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
821 // Use a smaller arrays for local live ranges.
822 ArrayRef<SlotIndex> Slots;
823 ArrayRef<const uint32_t*> Bits;
824 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
825 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
826 Bits = getRegMaskBitsInBlock(MBB->getNumber());
828 Slots = getRegMaskSlots();
829 Bits = getRegMaskBits();
832 // We are going to enumerate all the register mask slots contained in LI.
833 // Start with a binary search of RegMaskSlots to find a starting point.
834 ArrayRef<SlotIndex>::iterator SlotI =
835 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
836 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
838 // No slots in range, LI begins after the last call.
844 assert(*SlotI >= LiveI->start);
845 // Loop over all slots overlapping this segment.
846 while (*SlotI < LiveI->end) {
847 // *SlotI overlaps LI. Collect mask bits.
849 // This is the first overlap. Initialize UsableRegs to all ones.
851 UsableRegs.resize(TRI->getNumRegs(), true);
854 // Remove usable registers clobbered by this mask.
855 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
856 if (++SlotI == SlotE)
859 // *SlotI is beyond the current LI segment.
860 LiveI = LI.advanceTo(LiveI, *SlotI);
863 // Advance SlotI until it overlaps.
864 while (*SlotI < LiveI->start)
865 if (++SlotI == SlotE)
870 //===----------------------------------------------------------------------===//
871 // IntervalUpdate class.
872 //===----------------------------------------------------------------------===//
874 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
875 class LiveIntervals::HMEditor {
878 const MachineRegisterInfo& MRI;
879 const TargetRegisterInfo& TRI;
882 SmallPtrSet<LiveRange*, 8> Updated;
886 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
887 const TargetRegisterInfo& TRI,
888 SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)
889 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),
890 UpdateFlags(UpdateFlags) {}
892 // FIXME: UpdateFlags is a workaround that creates live intervals for all
893 // physregs, even those that aren't needed for regalloc, in order to update
894 // kill flags. This is wasteful. Eventually, LiveVariables will strip all kill
895 // flags, and postRA passes will use a live register utility instead.
896 LiveRange *getRegUnitLI(unsigned Unit) {
898 return &LIS.getRegUnit(Unit);
899 return LIS.getCachedRegUnit(Unit);
902 /// Update all live ranges touched by MI, assuming a move from OldIdx to
904 void updateAllRanges(MachineInstr *MI) {
905 DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " << *MI);
906 bool hasRegMask = false;
907 for (MIOperands MO(MI); MO.isValid(); ++MO) {
912 // Aggressively clear all kill flags.
913 // They are reinserted by VirtRegRewriter.
915 MO->setIsKill(false);
917 unsigned Reg = MO->getReg();
920 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
921 LiveInterval &LI = LIS.getInterval(Reg);
922 if (LI.hasSubRanges()) {
923 unsigned SubReg = MO->getSubReg();
924 unsigned LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
925 for (LiveInterval::SubRange &S : LI.subranges()) {
926 if ((S.LaneMask & LaneMask) == 0)
928 updateRange(S, Reg, S.LaneMask);
931 updateRange(LI, Reg, 0);
935 // For physregs, only update the regunits that actually have a
936 // precomputed live range.
937 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
938 if (LiveRange *LR = getRegUnitLI(*Units))
939 updateRange(*LR, *Units, 0);
942 updateRegMaskSlots();
946 /// Update a single live range, assuming an instruction has been moved from
947 /// OldIdx to NewIdx.
948 void updateRange(LiveRange &LR, unsigned Reg, unsigned LaneMask) {
949 if (!Updated.insert(&LR).second)
953 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
954 dbgs() << PrintReg(Reg);
956 dbgs() << format(" L%04X", LaneMask);
958 dbgs() << PrintRegUnit(Reg, &TRI);
960 dbgs() << ":\t" << LR << '\n';
962 if (SlotIndex::isEarlierInstr(OldIdx, NewIdx))
965 handleMoveUp(LR, Reg, LaneMask);
966 DEBUG(dbgs() << " -->\t" << LR << '\n');
970 /// Update LR to reflect an instruction has been moved downwards from OldIdx
973 /// 1. Live def at OldIdx:
974 /// Move def to NewIdx, assert endpoint after NewIdx.
976 /// 2. Live def at OldIdx, killed at NewIdx:
977 /// Change to dead def at NewIdx.
978 /// (Happens when bundling def+kill together).
980 /// 3. Dead def at OldIdx:
981 /// Move def to NewIdx, possibly across another live value.
983 /// 4. Def at OldIdx AND at NewIdx:
984 /// Remove segment [OldIdx;NewIdx) and value defined at OldIdx.
985 /// (Happens when bundling multiple defs together).
987 /// 5. Value read at OldIdx, killed before NewIdx:
988 /// Extend kill to NewIdx.
990 void handleMoveDown(LiveRange &LR) {
991 // First look for a kill at OldIdx.
992 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
993 LiveRange::iterator E = LR.end();
994 // Is LR even live at OldIdx?
995 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
998 // Handle a live-in value.
999 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1000 bool isKill = SlotIndex::isSameInstr(OldIdx, I->end);
1001 // If the live-in value already extends to NewIdx, there is nothing to do.
1002 if (!SlotIndex::isEarlierInstr(I->end, NewIdx))
1004 // Aggressively remove all kill flags from the old kill point.
1005 // Kill flags shouldn't be used while live intervals exist, they will be
1006 // reinserted by VirtRegRewriter.
1007 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(I->end))
1008 for (MIBundleOperands MO(KillMI); MO.isValid(); ++MO)
1009 if (MO->isReg() && MO->isUse())
1010 MO->setIsKill(false);
1011 // Adjust I->end to reach NewIdx. This may temporarily make LR invalid by
1012 // overlapping ranges. Case 5 above.
1013 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1014 // If this was a kill, there may also be a def. Otherwise we're done.
1020 // Check for a def at OldIdx.
1021 if (I == E || !SlotIndex::isSameInstr(OldIdx, I->start))
1023 // We have a def at OldIdx.
1024 VNInfo *DefVNI = I->valno;
1025 assert(DefVNI->def == I->start && "Inconsistent def");
1026 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1027 // If the defined value extends beyond NewIdx, just move the def down.
1028 // This is case 1 above.
1029 if (SlotIndex::isEarlierInstr(NewIdx, I->end)) {
1030 I->start = DefVNI->def;
1033 // The remaining possibilities are now:
1034 // 2. Live def at OldIdx, killed at NewIdx: isSameInstr(I->end, NewIdx).
1035 // 3. Dead def at OldIdx: I->end = OldIdx.getDeadSlot().
1036 // In either case, it is possible that there is an existing def at NewIdx.
1037 assert((I->end == OldIdx.getDeadSlot() ||
1038 SlotIndex::isSameInstr(I->end, NewIdx)) &&
1039 "Cannot move def below kill");
1040 LiveRange::iterator NewI = LR.advanceTo(I, NewIdx.getRegSlot());
1041 if (NewI != E && SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1042 // There is an existing def at NewIdx, case 4 above. The def at OldIdx is
1043 // coalesced into that value.
1044 assert(NewI->valno != DefVNI && "Multiple defs of value?");
1045 LR.removeValNo(DefVNI);
1048 // There was no existing def at NewIdx. Turn *I into a dead def at NewIdx.
1049 // If the def at OldIdx was dead, we allow it to be moved across other LR
1050 // values. The new range should be placed immediately before NewI, move any
1051 // intermediate ranges up.
1052 assert(NewI != I && "Inconsistent iterators");
1053 std::copy(std::next(I), NewI, I);
1055 = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1058 /// Update LR to reflect an instruction has been moved upwards from OldIdx
1061 /// 1. Live def at OldIdx:
1062 /// Hoist def to NewIdx.
1064 /// 2. Dead def at OldIdx:
1065 /// Hoist def+end to NewIdx, possibly move across other values.
1067 /// 3. Dead def at OldIdx AND existing def at NewIdx:
1068 /// Remove value defined at OldIdx, coalescing it with existing value.
1070 /// 4. Live def at OldIdx AND existing def at NewIdx:
1071 /// Remove value defined at NewIdx, hoist OldIdx def to NewIdx.
1072 /// (Happens when bundling multiple defs together).
1074 /// 5. Value killed at OldIdx:
1075 /// Hoist kill to NewIdx, then scan for last kill between NewIdx and
1078 void handleMoveUp(LiveRange &LR, unsigned Reg, unsigned LaneMask) {
1079 // First look for a kill at OldIdx.
1080 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
1081 LiveRange::iterator E = LR.end();
1082 // Is LR even live at OldIdx?
1083 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
1086 // Handle a live-in value.
1087 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1088 // If the live-in value isn't killed here, there is nothing to do.
1089 if (!SlotIndex::isSameInstr(OldIdx, I->end))
1091 // Adjust I->end to end at NewIdx. If we are hoisting a kill above
1092 // another use, we need to search for that use. Case 5 above.
1093 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1095 // If OldIdx also defines a value, there couldn't have been another use.
1096 if (I == E || !SlotIndex::isSameInstr(I->start, OldIdx)) {
1097 // No def, search for the new kill.
1098 // This can never be an early clobber kill since there is no def.
1099 std::prev(I)->end = findLastUseBefore(Reg, LaneMask).getRegSlot();
1104 // Now deal with the def at OldIdx.
1105 assert(I != E && SlotIndex::isSameInstr(I->start, OldIdx) && "No def?");
1106 VNInfo *DefVNI = I->valno;
1107 assert(DefVNI->def == I->start && "Inconsistent def");
1108 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1110 // Check for an existing def at NewIdx.
1111 LiveRange::iterator NewI = LR.find(NewIdx.getRegSlot());
1112 if (SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1113 assert(NewI->valno != DefVNI && "Same value defined more than once?");
1114 // There is an existing def at NewIdx.
1115 if (I->end.isDead()) {
1116 // Case 3: Remove the dead def at OldIdx.
1117 LR.removeValNo(DefVNI);
1120 // Case 4: Replace def at NewIdx with live def at OldIdx.
1121 I->start = DefVNI->def;
1122 LR.removeValNo(NewI->valno);
1126 // There is no existing def at NewIdx. Hoist DefVNI.
1127 if (!I->end.isDead()) {
1128 // Leave the end point of a live def.
1129 I->start = DefVNI->def;
1133 // DefVNI is a dead def. It may have been moved across other values in LR,
1134 // so move I up to NewI. Slide [NewI;I) down one position.
1135 std::copy_backward(NewI, I, std::next(I));
1136 *NewI = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1139 void updateRegMaskSlots() {
1140 SmallVectorImpl<SlotIndex>::iterator RI =
1141 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1143 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&
1144 "No RegMask at OldIdx.");
1145 *RI = NewIdx.getRegSlot();
1146 assert((RI == LIS.RegMaskSlots.begin() ||
1147 SlotIndex::isEarlierInstr(*std::prev(RI), *RI)) &&
1148 "Cannot move regmask instruction above another call");
1149 assert((std::next(RI) == LIS.RegMaskSlots.end() ||
1150 SlotIndex::isEarlierInstr(*RI, *std::next(RI))) &&
1151 "Cannot move regmask instruction below another call");
1154 // Return the last use of reg between NewIdx and OldIdx.
1155 SlotIndex findLastUseBefore(unsigned Reg, unsigned LaneMask) {
1157 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1158 SlotIndex LastUse = NewIdx;
1159 for (MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
1160 unsigned SubReg = MO.getSubReg();
1161 if (SubReg != 0 && LaneMask != 0
1162 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask) == 0)
1165 const MachineInstr *MI = MO.getParent();
1166 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1167 if (InstSlot > LastUse && InstSlot < OldIdx)
1173 // This is a regunit interval, so scanning the use list could be very
1174 // expensive. Scan upwards from OldIdx instead.
1175 assert(NewIdx < OldIdx && "Expected upwards move");
1176 SlotIndexes *Indexes = LIS.getSlotIndexes();
1177 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(NewIdx);
1179 // OldIdx may not correspond to an instruction any longer, so set MII to
1180 // point to the next instruction after OldIdx, or MBB->end().
1181 MachineBasicBlock::iterator MII = MBB->end();
1182 if (MachineInstr *MI = Indexes->getInstructionFromIndex(
1183 Indexes->getNextNonNullIndex(OldIdx)))
1184 if (MI->getParent() == MBB)
1187 MachineBasicBlock::iterator Begin = MBB->begin();
1188 while (MII != Begin) {
1189 if ((--MII)->isDebugValue())
1191 SlotIndex Idx = Indexes->getInstructionIndex(MII);
1193 // Stop searching when NewIdx is reached.
1194 if (!SlotIndex::isEarlierInstr(NewIdx, Idx))
1197 // Check if MII uses Reg.
1198 for (MIBundleOperands MO(MII); MO.isValid(); ++MO)
1200 TargetRegisterInfo::isPhysicalRegister(MO->getReg()) &&
1201 TRI.hasRegUnit(MO->getReg(), Reg))
1204 // Didn't reach NewIdx. It must be the first instruction in the block.
1209 void LiveIntervals::handleMove(MachineInstr* MI, bool UpdateFlags) {
1210 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1211 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1212 Indexes->removeMachineInstrFromMaps(MI);
1213 SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
1214 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1215 OldIndex < getMBBEndIdx(MI->getParent()) &&
1216 "Cannot handle moves across basic block boundaries.");
1218 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1219 HME.updateAllRanges(MI);
1222 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1223 MachineInstr* BundleStart,
1225 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1226 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1227 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1228 HME.updateAllRanges(MI);
1231 void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
1232 const MachineBasicBlock::iterator End,
1233 const SlotIndex endIdx,
1234 LiveRange &LR, const unsigned Reg,
1235 const unsigned LaneMask) {
1236 LiveInterval::iterator LII = LR.find(endIdx);
1237 SlotIndex lastUseIdx;
1238 if (LII != LR.end() && LII->start < endIdx)
1239 lastUseIdx = LII->end;
1243 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1245 MachineInstr *MI = I;
1246 if (MI->isDebugValue())
1249 SlotIndex instrIdx = getInstructionIndex(MI);
1250 bool isStartValid = getInstructionFromIndex(LII->start);
1251 bool isEndValid = getInstructionFromIndex(LII->end);
1253 // FIXME: This doesn't currently handle early-clobber or multiple removed
1254 // defs inside of the region to repair.
1255 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
1256 OE = MI->operands_end(); OI != OE; ++OI) {
1257 const MachineOperand &MO = *OI;
1258 if (!MO.isReg() || MO.getReg() != Reg)
1261 unsigned SubReg = MO.getSubReg();
1262 unsigned Mask = TRI->getSubRegIndexLaneMask(SubReg);
1263 if ((Mask & LaneMask) == 0)
1267 if (!isStartValid) {
1268 if (LII->end.isDead()) {
1269 SlotIndex prevStart;
1270 if (LII != LR.begin())
1271 prevStart = std::prev(LII)->start;
1273 // FIXME: This could be more efficient if there was a
1274 // removeSegment method that returned an iterator.
1275 LR.removeSegment(*LII, true);
1276 if (prevStart.isValid())
1277 LII = LR.find(prevStart);
1281 LII->start = instrIdx.getRegSlot();
1282 LII->valno->def = instrIdx.getRegSlot();
1283 if (MO.getSubReg() && !MO.isUndef())
1284 lastUseIdx = instrIdx.getRegSlot();
1286 lastUseIdx = SlotIndex();
1291 if (!lastUseIdx.isValid()) {
1292 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1293 LiveRange::Segment S(instrIdx.getRegSlot(),
1294 instrIdx.getDeadSlot(), VNI);
1295 LII = LR.addSegment(S);
1296 } else if (LII->start != instrIdx.getRegSlot()) {
1297 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1298 LiveRange::Segment S(instrIdx.getRegSlot(), lastUseIdx, VNI);
1299 LII = LR.addSegment(S);
1302 if (MO.getSubReg() && !MO.isUndef())
1303 lastUseIdx = instrIdx.getRegSlot();
1305 lastUseIdx = SlotIndex();
1306 } else if (MO.isUse()) {
1307 // FIXME: This should probably be handled outside of this branch,
1308 // either as part of the def case (for defs inside of the region) or
1309 // after the loop over the region.
1310 if (!isEndValid && !LII->end.isBlock())
1311 LII->end = instrIdx.getRegSlot();
1312 if (!lastUseIdx.isValid())
1313 lastUseIdx = instrIdx.getRegSlot();
1320 LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
1321 MachineBasicBlock::iterator Begin,
1322 MachineBasicBlock::iterator End,
1323 ArrayRef<unsigned> OrigRegs) {
1324 // Find anchor points, which are at the beginning/end of blocks or at
1325 // instructions that already have indexes.
1326 while (Begin != MBB->begin() && !Indexes->hasIndex(Begin))
1328 while (End != MBB->end() && !Indexes->hasIndex(End))
1332 if (End == MBB->end())
1333 endIdx = getMBBEndIdx(MBB).getPrevSlot();
1335 endIdx = getInstructionIndex(End);
1337 Indexes->repairIndexesInRange(MBB, Begin, End);
1339 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1341 MachineInstr *MI = I;
1342 if (MI->isDebugValue())
1344 for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
1345 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
1347 TargetRegisterInfo::isVirtualRegister(MOI->getReg()) &&
1348 !hasInterval(MOI->getReg())) {
1349 createAndComputeVirtRegInterval(MOI->getReg());
1354 for (unsigned i = 0, e = OrigRegs.size(); i != e; ++i) {
1355 unsigned Reg = OrigRegs[i];
1356 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1359 LiveInterval &LI = getInterval(Reg);
1360 // FIXME: Should we support undefs that gain defs?
1361 if (!LI.hasAtLeastOneValue())
1364 for (LiveInterval::SubRange &S : LI.subranges()) {
1365 repairOldRegInRange(Begin, End, endIdx, S, Reg, S.LaneMask);
1367 repairOldRegInRange(Begin, End, endIdx, LI, Reg);
1371 void LiveIntervals::removePhysRegDefAt(unsigned Reg, SlotIndex Pos) {
1372 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
1373 if (LiveRange *LR = getCachedRegUnit(*Units))
1374 if (VNInfo *VNI = LR->getVNInfoAt(Pos))
1375 LR->removeValNo(VNI);
1379 void LiveIntervals::removeVRegDefAt(LiveInterval &LI, SlotIndex Pos) {
1380 VNInfo *VNI = LI.getVNInfoAt(Pos);
1383 LI.removeValNo(VNI);
1385 // Also remove the value in subranges.
1386 for (LiveInterval::SubRange &S : LI.subranges()) {
1387 if (VNInfo *SVNI = S.getVNInfoAt(Pos))
1388 S.removeValNo(SVNI);
1390 LI.removeEmptySubRanges();