1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "LiveRangeCalc.h"
20 #include "llvm/ADT/DenseSet.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/IR/Value.h"
31 #include "llvm/Support/BlockFrequency.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetRegisterInfo.h"
38 #include "llvm/Target/TargetSubtargetInfo.h"
44 #define DEBUG_TYPE "regalloc"
46 char LiveIntervals::ID = 0;
47 char &llvm::LiveIntervalsID = LiveIntervals::ID;
48 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
49 "Live Interval Analysis", false, false)
50 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
51 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
52 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
53 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
54 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
55 "Live Interval Analysis", false, false)
58 static cl::opt<bool> EnablePrecomputePhysRegs(
59 "precompute-phys-liveness", cl::Hidden,
60 cl::desc("Eagerly compute live intervals for all physreg units."));
62 static bool EnablePrecomputePhysRegs = false;
65 static cl::opt<bool> EnableSubRegLiveness(
66 "enable-subreg-liveness", cl::Hidden, cl::init(true),
67 cl::desc("Enable subregister liveness tracking."));
70 cl::opt<bool> UseSegmentSetForPhysRegs(
71 "use-segment-set-for-physregs", cl::Hidden, cl::init(true),
73 "Use segment set for the computation of the live ranges of physregs."));
76 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
78 AU.addRequired<AAResultsWrapperPass>();
79 AU.addPreserved<AAResultsWrapperPass>();
80 // LiveVariables isn't really required by this analysis, it is only required
81 // here to make sure it is live during TwoAddressInstructionPass and
82 // PHIElimination. This is temporary.
83 AU.addRequired<LiveVariables>();
84 AU.addPreserved<LiveVariables>();
85 AU.addPreservedID(MachineLoopInfoID);
86 AU.addRequiredTransitiveID(MachineDominatorsID);
87 AU.addPreservedID(MachineDominatorsID);
88 AU.addPreserved<SlotIndexes>();
89 AU.addRequiredTransitive<SlotIndexes>();
90 MachineFunctionPass::getAnalysisUsage(AU);
93 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
94 DomTree(nullptr), LRCalc(nullptr) {
95 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
98 LiveIntervals::~LiveIntervals() {
102 void LiveIntervals::releaseMemory() {
103 // Free the live intervals themselves.
104 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
105 delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
106 VirtRegIntervals.clear();
107 RegMaskSlots.clear();
109 RegMaskBlocks.clear();
111 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
112 delete RegUnitRanges[i];
113 RegUnitRanges.clear();
115 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
116 VNInfoAllocator.Reset();
119 /// runOnMachineFunction - calculates LiveIntervals
121 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
123 MRI = &MF->getRegInfo();
124 TRI = MF->getSubtarget().getRegisterInfo();
125 TII = MF->getSubtarget().getInstrInfo();
126 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
127 Indexes = &getAnalysis<SlotIndexes>();
128 DomTree = &getAnalysis<MachineDominatorTree>();
130 if (EnableSubRegLiveness && MF->getSubtarget().enableSubRegLiveness())
131 MRI->enableSubRegLiveness(true);
134 LRCalc = new LiveRangeCalc();
136 // Allocate space for all virtual registers.
137 VirtRegIntervals.resize(MRI->getNumVirtRegs());
141 computeLiveInRegUnits();
143 if (EnablePrecomputePhysRegs) {
144 // For stress testing, precompute live ranges of all physical register
145 // units, including reserved registers.
146 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
153 /// print - Implement the dump method.
154 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
155 OS << "********** INTERVALS **********\n";
157 // Dump the regunits.
158 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
159 if (LiveRange *LR = RegUnitRanges[i])
160 OS << PrintRegUnit(i, TRI) << ' ' << *LR << '\n';
162 // Dump the virtregs.
163 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
164 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
165 if (hasInterval(Reg))
166 OS << getInterval(Reg) << '\n';
170 for (unsigned i = 0, e = RegMaskSlots.size(); i != e; ++i)
171 OS << ' ' << RegMaskSlots[i];
177 void LiveIntervals::printInstrs(raw_ostream &OS) const {
178 OS << "********** MACHINEINSTRS **********\n";
179 MF->print(OS, Indexes);
182 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
183 void LiveIntervals::dumpInstrs() const {
188 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
189 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
190 llvm::huge_valf : 0.0F;
191 return new LiveInterval(reg, Weight);
195 /// computeVirtRegInterval - Compute the live interval of a virtual register,
196 /// based on defs and uses.
197 void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
198 assert(LRCalc && "LRCalc not initialized.");
199 assert(LI.empty() && "Should only compute empty intervals.");
200 bool ShouldTrackSubRegLiveness = MRI->shouldTrackSubRegLiveness(LI.reg);
201 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
202 LRCalc->calculate(LI, ShouldTrackSubRegLiveness);
203 bool SeparatedComponents = computeDeadValues(LI, nullptr);
204 if (SeparatedComponents) {
205 assert(ShouldTrackSubRegLiveness
206 && "Separated components should only occur for unused subreg defs");
207 SmallVector<LiveInterval*, 8> SplitLIs;
208 splitSeparateComponents(LI, SplitLIs);
212 void LiveIntervals::computeVirtRegs() {
213 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
214 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
215 if (MRI->reg_nodbg_empty(Reg))
217 createAndComputeVirtRegInterval(Reg);
221 void LiveIntervals::computeRegMasks() {
222 RegMaskBlocks.resize(MF->getNumBlockIDs());
224 // Find all instructions with regmask operands.
225 for (MachineBasicBlock &MBB : *MF) {
226 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB.getNumber()];
227 RMB.first = RegMaskSlots.size();
228 for (MachineInstr &MI : MBB) {
229 for (const MachineOperand &MO : MI.operands()) {
232 RegMaskSlots.push_back(Indexes->getInstructionIndex(&MI).getRegSlot());
233 RegMaskBits.push_back(MO.getRegMask());
236 // Compute the number of register mask instructions in this block.
237 RMB.second = RegMaskSlots.size() - RMB.first;
241 //===----------------------------------------------------------------------===//
242 // Register Unit Liveness
243 //===----------------------------------------------------------------------===//
245 // Fixed interference typically comes from ABI boundaries: Function arguments
246 // and return values are passed in fixed registers, and so are exception
247 // pointers entering landing pads. Certain instructions require values to be
248 // present in specific registers. That is also represented through fixed
252 /// computeRegUnitInterval - Compute the live range of a register unit, based
253 /// on the uses and defs of aliasing registers. The range should be empty,
254 /// or contain only dead phi-defs from ABI blocks.
255 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
256 assert(LRCalc && "LRCalc not initialized.");
257 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
259 // The physregs aliasing Unit are the roots and their super-registers.
260 // Create all values as dead defs before extending to uses. Note that roots
261 // may share super-registers. That's OK because createDeadDefs() is
262 // idempotent. It is very rare for a register unit to have multiple roots, so
263 // uniquing super-registers is probably not worthwhile.
264 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
265 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
266 Supers.isValid(); ++Supers) {
267 if (!MRI->reg_empty(*Supers))
268 LRCalc->createDeadDefs(LR, *Supers);
272 // Now extend LR to reach all uses.
273 // Ignore uses of reserved registers. We only track defs of those.
274 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
275 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
276 Supers.isValid(); ++Supers) {
277 unsigned Reg = *Supers;
278 if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg))
279 LRCalc->extendToUses(LR, Reg);
283 // Flush the segment set to the segment vector.
284 if (UseSegmentSetForPhysRegs)
285 LR.flushSegmentSet();
289 /// computeLiveInRegUnits - Precompute the live ranges of any register units
290 /// that are live-in to an ABI block somewhere. Register values can appear
291 /// without a corresponding def when entering the entry block or a landing pad.
293 void LiveIntervals::computeLiveInRegUnits() {
294 RegUnitRanges.resize(TRI->getNumRegUnits());
295 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
297 // Keep track of the live range sets allocated.
298 SmallVector<unsigned, 8> NewRanges;
300 // Check all basic blocks for live-ins.
301 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
303 const MachineBasicBlock *MBB = &*MFI;
305 // We only care about ABI blocks: Entry + landing pads.
306 if ((MFI != MF->begin() && !MBB->isEHPad()) || MBB->livein_empty())
309 // Create phi-defs at Begin for all live-in registers.
310 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
311 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
312 for (const auto &LI : MBB->liveins()) {
313 for (MCRegUnitIterator Units(LI.PhysReg, TRI); Units.isValid(); ++Units) {
314 unsigned Unit = *Units;
315 LiveRange *LR = RegUnitRanges[Unit];
317 // Use segment set to speed-up initial computation of the live range.
318 LR = RegUnitRanges[Unit] = new LiveRange(UseSegmentSetForPhysRegs);
319 NewRanges.push_back(Unit);
321 VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
323 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
326 DEBUG(dbgs() << '\n');
328 DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");
330 // Compute the 'normal' part of the ranges.
331 for (unsigned i = 0, e = NewRanges.size(); i != e; ++i) {
332 unsigned Unit = NewRanges[i];
333 computeRegUnitRange(*RegUnitRanges[Unit], Unit);
338 static void createSegmentsForValues(LiveRange &LR,
339 iterator_range<LiveInterval::vni_iterator> VNIs) {
340 for (auto VNI : VNIs) {
343 SlotIndex Def = VNI->def;
344 LR.addSegment(LiveRange::Segment(Def, Def.getDeadSlot(), VNI));
348 typedef SmallVector<std::pair<SlotIndex, VNInfo*>, 16> ShrinkToUsesWorkList;
350 static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes,
351 ShrinkToUsesWorkList &WorkList,
352 const LiveRange &OldRange) {
353 // Keep track of the PHIs that are in use.
354 SmallPtrSet<VNInfo*, 8> UsedPHIs;
355 // Blocks that have already been added to WorkList as live-out.
356 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
358 // Extend intervals to reach all uses in WorkList.
359 while (!WorkList.empty()) {
360 SlotIndex Idx = WorkList.back().first;
361 VNInfo *VNI = WorkList.back().second;
363 const MachineBasicBlock *MBB = Indexes.getMBBFromIndex(Idx.getPrevSlot());
364 SlotIndex BlockStart = Indexes.getMBBStartIdx(MBB);
366 // Extend the live range for VNI to be live at Idx.
367 if (VNInfo *ExtVNI = LR.extendInBlock(BlockStart, Idx)) {
368 assert(ExtVNI == VNI && "Unexpected existing value number");
370 // Is this a PHIDef we haven't seen before?
371 if (!VNI->isPHIDef() || VNI->def != BlockStart ||
372 !UsedPHIs.insert(VNI).second)
374 // The PHI is live, make sure the predecessors are live-out.
375 for (auto &Pred : MBB->predecessors()) {
376 if (!LiveOut.insert(Pred).second)
378 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
379 // A predecessor is not required to have a live-out value for a PHI.
380 if (VNInfo *PVNI = OldRange.getVNInfoBefore(Stop))
381 WorkList.push_back(std::make_pair(Stop, PVNI));
386 // VNI is live-in to MBB.
387 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
388 LR.addSegment(LiveRange::Segment(BlockStart, Idx, VNI));
390 // Make sure VNI is live-out from the predecessors.
391 for (auto &Pred : MBB->predecessors()) {
392 if (!LiveOut.insert(Pred).second)
394 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
395 assert(OldRange.getVNInfoBefore(Stop) == VNI &&
396 "Wrong value out of predecessor");
397 WorkList.push_back(std::make_pair(Stop, VNI));
402 bool LiveIntervals::shrinkToUses(LiveInterval *li,
403 SmallVectorImpl<MachineInstr*> *dead) {
404 DEBUG(dbgs() << "Shrink: " << *li << '\n');
405 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
406 && "Can only shrink virtual registers");
408 // Shrink subregister live ranges.
409 bool NeedsCleanup = false;
410 for (LiveInterval::SubRange &S : li->subranges()) {
411 shrinkToUses(S, li->reg);
416 li->removeEmptySubRanges();
418 // Find all the values used, including PHI kills.
419 ShrinkToUsesWorkList WorkList;
421 // Visit all instructions reading li->reg.
422 for (MachineRegisterInfo::reg_instr_iterator
423 I = MRI->reg_instr_begin(li->reg), E = MRI->reg_instr_end();
425 MachineInstr *UseMI = &*(I++);
426 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
428 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
429 LiveQueryResult LRQ = li->Query(Idx);
430 VNInfo *VNI = LRQ.valueIn();
432 // This shouldn't happen: readsVirtualRegister returns true, but there is
433 // no live value. It is likely caused by a target getting <undef> flags
435 DEBUG(dbgs() << Idx << '\t' << *UseMI
436 << "Warning: Instr claims to read non-existent value in "
440 // Special case: An early-clobber tied operand reads and writes the
441 // register one slot early.
442 if (VNInfo *DefVNI = LRQ.valueDefined())
445 WorkList.push_back(std::make_pair(Idx, VNI));
448 // Create new live ranges with only minimal live segments per def.
450 createSegmentsForValues(NewLR, make_range(li->vni_begin(), li->vni_end()));
451 extendSegmentsToUses(NewLR, *Indexes, WorkList, *li);
453 // Move the trimmed segments back.
454 li->segments.swap(NewLR.segments);
456 // Handle dead values.
457 bool CanSeparate = computeDeadValues(*li, dead);
458 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
462 bool LiveIntervals::computeDeadValues(LiveInterval &LI,
463 SmallVectorImpl<MachineInstr*> *dead) {
464 bool MayHaveSplitComponents = false;
465 for (auto VNI : LI.valnos) {
468 SlotIndex Def = VNI->def;
469 LiveRange::iterator I = LI.FindSegmentContaining(Def);
470 assert(I != LI.end() && "Missing segment for VNI");
472 // Is the register live before? Otherwise we may have to add a read-undef
473 // flag for subregister defs.
474 bool DeadBeforeDef = false;
475 unsigned VReg = LI.reg;
476 if (MRI->shouldTrackSubRegLiveness(VReg)) {
477 if ((I == LI.begin() || std::prev(I)->end < Def) && !VNI->isPHIDef()) {
478 MachineInstr *MI = getInstructionFromIndex(Def);
479 MI->addRegisterDefReadUndef(VReg);
480 DeadBeforeDef = true;
484 if (I->end != Def.getDeadSlot())
486 if (VNI->isPHIDef()) {
487 // This is a dead PHI. Remove it.
490 DEBUG(dbgs() << "Dead PHI at " << Def << " may separate interval\n");
491 MayHaveSplitComponents = true;
493 // This is a dead def. Make sure the instruction knows.
494 MachineInstr *MI = getInstructionFromIndex(Def);
495 assert(MI && "No instruction defining live value");
496 MI->addRegisterDead(VReg, TRI);
498 // If we have a dead def that is completely separate from the rest of
499 // the liverange then we rewrite it to use a different VReg to not violate
500 // the rule that the liveness of a virtual register forms a connected
501 // component. This should only happen if subregister liveness is tracked.
503 MayHaveSplitComponents = true;
505 if (dead && MI->allDefsAreDead()) {
506 DEBUG(dbgs() << "All defs dead: " << Def << '\t' << *MI);
511 return MayHaveSplitComponents;
514 void LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg)
516 DEBUG(dbgs() << "Shrink: " << SR << '\n');
517 assert(TargetRegisterInfo::isVirtualRegister(Reg)
518 && "Can only shrink virtual registers");
519 // Find all the values used, including PHI kills.
520 ShrinkToUsesWorkList WorkList;
522 // Visit all instructions reading Reg.
524 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
525 MachineInstr *UseMI = MO.getParent();
526 if (UseMI->isDebugValue())
528 // Maybe the operand is for a subregister we don't care about.
529 unsigned SubReg = MO.getSubReg();
531 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg);
532 if ((LaneMask & SR.LaneMask) == 0)
535 // We only need to visit each instruction once.
536 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
541 LiveQueryResult LRQ = SR.Query(Idx);
542 VNInfo *VNI = LRQ.valueIn();
543 // For Subranges it is possible that only undef values are left in that
544 // part of the subregister, so there is no real liverange at the use
548 // Special case: An early-clobber tied operand reads and writes the
549 // register one slot early.
550 if (VNInfo *DefVNI = LRQ.valueDefined())
553 WorkList.push_back(std::make_pair(Idx, VNI));
556 // Create a new live ranges with only minimal live segments per def.
558 createSegmentsForValues(NewLR, make_range(SR.vni_begin(), SR.vni_end()));
559 extendSegmentsToUses(NewLR, *Indexes, WorkList, SR);
561 // Move the trimmed ranges back.
562 SR.segments.swap(NewLR.segments);
564 // Remove dead PHI value numbers
565 for (auto VNI : SR.valnos) {
568 const LiveRange::Segment *Segment = SR.getSegmentContaining(VNI->def);
569 assert(Segment != nullptr && "Missing segment for VNI");
570 if (Segment->end != VNI->def.getDeadSlot())
572 if (VNI->isPHIDef()) {
573 // This is a dead PHI. Remove it.
575 SR.removeSegment(*Segment);
576 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
580 DEBUG(dbgs() << "Shrunk: " << SR << '\n');
583 void LiveIntervals::extendToIndices(LiveRange &LR,
584 ArrayRef<SlotIndex> Indices) {
585 assert(LRCalc && "LRCalc not initialized.");
586 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
587 for (unsigned i = 0, e = Indices.size(); i != e; ++i)
588 LRCalc->extend(LR, Indices[i]);
591 void LiveIntervals::pruneValue(LiveRange &LR, SlotIndex Kill,
592 SmallVectorImpl<SlotIndex> *EndPoints) {
593 LiveQueryResult LRQ = LR.Query(Kill);
594 VNInfo *VNI = LRQ.valueOutOrDead();
598 MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill);
599 SlotIndex MBBEnd = Indexes->getMBBEndIdx(KillMBB);
601 // If VNI isn't live out from KillMBB, the value is trivially pruned.
602 if (LRQ.endPoint() < MBBEnd) {
603 LR.removeSegment(Kill, LRQ.endPoint());
604 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
608 // VNI is live out of KillMBB.
609 LR.removeSegment(Kill, MBBEnd);
610 if (EndPoints) EndPoints->push_back(MBBEnd);
612 // Find all blocks that are reachable from KillMBB without leaving VNI's live
613 // range. It is possible that KillMBB itself is reachable, so start a DFS
614 // from each successor.
615 typedef SmallPtrSet<MachineBasicBlock*, 9> VisitedTy;
617 for (MachineBasicBlock::succ_iterator
618 SuccI = KillMBB->succ_begin(), SuccE = KillMBB->succ_end();
619 SuccI != SuccE; ++SuccI) {
620 for (df_ext_iterator<MachineBasicBlock*, VisitedTy>
621 I = df_ext_begin(*SuccI, Visited), E = df_ext_end(*SuccI, Visited);
623 MachineBasicBlock *MBB = *I;
625 // Check if VNI is live in to MBB.
626 SlotIndex MBBStart, MBBEnd;
627 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);
628 LiveQueryResult LRQ = LR.Query(MBBStart);
629 if (LRQ.valueIn() != VNI) {
630 // This block isn't part of the VNI segment. Prune the search.
635 // Prune the search if VNI is killed in MBB.
636 if (LRQ.endPoint() < MBBEnd) {
637 LR.removeSegment(MBBStart, LRQ.endPoint());
638 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
643 // VNI is live through MBB.
644 LR.removeSegment(MBBStart, MBBEnd);
645 if (EndPoints) EndPoints->push_back(MBBEnd);
651 //===----------------------------------------------------------------------===//
652 // Register allocator hooks.
655 void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
656 // Keep track of regunit ranges.
657 SmallVector<std::pair<const LiveRange*, LiveRange::const_iterator>, 8> RU;
658 // Keep track of subregister ranges.
659 SmallVector<std::pair<const LiveInterval::SubRange*,
660 LiveRange::const_iterator>, 4> SRs;
662 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
663 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
664 if (MRI->reg_nodbg_empty(Reg))
666 const LiveInterval &LI = getInterval(Reg);
670 // Find the regunit intervals for the assigned register. They may overlap
671 // the virtual register live range, cancelling any kills.
673 for (MCRegUnitIterator Units(VRM->getPhys(Reg), TRI); Units.isValid();
675 const LiveRange &RURange = getRegUnit(*Units);
678 RU.push_back(std::make_pair(&RURange, RURange.find(LI.begin()->end)));
681 if (MRI->subRegLivenessEnabled()) {
683 for (const LiveInterval::SubRange &SR : LI.subranges()) {
684 SRs.push_back(std::make_pair(&SR, SR.find(LI.begin()->end)));
688 // Every instruction that kills Reg corresponds to a segment range end
690 for (LiveInterval::const_iterator RI = LI.begin(), RE = LI.end(); RI != RE;
692 // A block index indicates an MBB edge.
693 if (RI->end.isBlock())
695 MachineInstr *MI = getInstructionFromIndex(RI->end);
699 // Check if any of the regunits are live beyond the end of RI. That could
700 // happen when a physreg is defined as a copy of a virtreg:
702 // %EAX = COPY %vreg5
703 // FOO %vreg5 <--- MI, cancel kill because %EAX is live.
706 // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX.
707 for (auto &RUP : RU) {
708 const LiveRange &RURange = *RUP.first;
709 LiveRange::const_iterator &I = RUP.second;
710 if (I == RURange.end())
712 I = RURange.advanceTo(I, RI->end);
713 if (I == RURange.end() || I->start >= RI->end)
715 // I is overlapping RI.
719 if (MRI->subRegLivenessEnabled()) {
720 // When reading a partial undefined value we must not add a kill flag.
721 // The regalloc might have used the undef lane for something else.
723 // %vreg1 = ... ; R32: %vreg1
724 // %vreg2:high16 = ... ; R64: %vreg2
725 // = read %vreg2<kill> ; R64: %vreg2
726 // = read %vreg1 ; R32: %vreg1
727 // The <kill> flag is correct for %vreg2, but the register allocator may
728 // assign R0L to %vreg1, and R0 to %vreg2 because the low 32bits of R0
729 // are actually never written by %vreg2. After assignment the <kill>
730 // flag at the read instruction is invalid.
731 LaneBitmask DefinedLanesMask;
733 // Compute a mask of lanes that are defined.
734 DefinedLanesMask = 0;
735 for (auto &SRP : SRs) {
736 const LiveInterval::SubRange &SR = *SRP.first;
737 LiveRange::const_iterator &I = SRP.second;
740 I = SR.advanceTo(I, RI->end);
741 if (I == SR.end() || I->start >= RI->end)
743 // I is overlapping RI
744 DefinedLanesMask |= SR.LaneMask;
747 DefinedLanesMask = ~0u;
749 bool IsFullWrite = false;
750 for (const MachineOperand &MO : MI->operands()) {
751 if (!MO.isReg() || MO.getReg() != Reg)
754 // Reading any undefined lanes?
755 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
756 if ((UseMask & ~DefinedLanesMask) != 0)
758 } else if (MO.getSubReg() == 0) {
759 // Writing to the full register?
765 // If an instruction writes to a subregister, a new segment starts in
766 // the LiveInterval. But as this is only overriding part of the register
767 // adding kill-flags is not correct here after registers have been
770 // Next segment has to be adjacent in the subregister write case.
771 LiveRange::const_iterator N = std::next(RI);
772 if (N != LI.end() && N->start == RI->end)
777 MI->addRegisterKilled(Reg, nullptr);
780 MI->clearRegisterKills(Reg, nullptr);
786 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
787 // A local live range must be fully contained inside the block, meaning it is
788 // defined and killed at instructions, not at block boundaries. It is not
789 // live in or or out of any block.
791 // It is technically possible to have a PHI-defined live range identical to a
792 // single block, but we are going to return false in that case.
794 SlotIndex Start = LI.beginIndex();
798 SlotIndex Stop = LI.endIndex();
802 // getMBBFromIndex doesn't need to search the MBB table when both indexes
803 // belong to proper instructions.
804 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
805 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
806 return MBB1 == MBB2 ? MBB1 : nullptr;
810 LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
811 for (const VNInfo *PHI : LI.valnos) {
812 if (PHI->isUnused() || !PHI->isPHIDef())
814 const MachineBasicBlock *PHIMBB = getMBBFromIndex(PHI->def);
815 // Conservatively return true instead of scanning huge predecessor lists.
816 if (PHIMBB->pred_size() > 100)
818 for (MachineBasicBlock::const_pred_iterator
819 PI = PHIMBB->pred_begin(), PE = PHIMBB->pred_end(); PI != PE; ++PI)
820 if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(*PI)))
827 LiveIntervals::getSpillWeight(bool isDef, bool isUse,
828 const MachineBlockFrequencyInfo *MBFI,
829 const MachineInstr *MI) {
830 BlockFrequency Freq = MBFI->getBlockFreq(MI->getParent());
831 const float Scale = 1.0f / MBFI->getEntryFreq();
832 return (isDef + isUse) * (Freq.getFrequency() * Scale);
836 LiveIntervals::addSegmentToEndOfBlock(unsigned reg, MachineInstr* startInst) {
837 LiveInterval& Interval = createEmptyInterval(reg);
838 VNInfo* VN = Interval.getNextValue(
839 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
840 getVNInfoAllocator());
841 LiveRange::Segment S(
842 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
843 getMBBEndIdx(startInst->getParent()), VN);
844 Interval.addSegment(S);
850 //===----------------------------------------------------------------------===//
851 // Register mask functions
852 //===----------------------------------------------------------------------===//
854 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
855 BitVector &UsableRegs) {
858 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
860 // Use a smaller arrays for local live ranges.
861 ArrayRef<SlotIndex> Slots;
862 ArrayRef<const uint32_t*> Bits;
863 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
864 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
865 Bits = getRegMaskBitsInBlock(MBB->getNumber());
867 Slots = getRegMaskSlots();
868 Bits = getRegMaskBits();
871 // We are going to enumerate all the register mask slots contained in LI.
872 // Start with a binary search of RegMaskSlots to find a starting point.
873 ArrayRef<SlotIndex>::iterator SlotI =
874 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
875 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
877 // No slots in range, LI begins after the last call.
883 assert(*SlotI >= LiveI->start);
884 // Loop over all slots overlapping this segment.
885 while (*SlotI < LiveI->end) {
886 // *SlotI overlaps LI. Collect mask bits.
888 // This is the first overlap. Initialize UsableRegs to all ones.
890 UsableRegs.resize(TRI->getNumRegs(), true);
893 // Remove usable registers clobbered by this mask.
894 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
895 if (++SlotI == SlotE)
898 // *SlotI is beyond the current LI segment.
899 LiveI = LI.advanceTo(LiveI, *SlotI);
902 // Advance SlotI until it overlaps.
903 while (*SlotI < LiveI->start)
904 if (++SlotI == SlotE)
909 //===----------------------------------------------------------------------===//
910 // IntervalUpdate class.
911 //===----------------------------------------------------------------------===//
913 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
914 class LiveIntervals::HMEditor {
917 const MachineRegisterInfo& MRI;
918 const TargetRegisterInfo& TRI;
921 SmallPtrSet<LiveRange*, 8> Updated;
925 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
926 const TargetRegisterInfo& TRI,
927 SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)
928 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),
929 UpdateFlags(UpdateFlags) {}
931 // FIXME: UpdateFlags is a workaround that creates live intervals for all
932 // physregs, even those that aren't needed for regalloc, in order to update
933 // kill flags. This is wasteful. Eventually, LiveVariables will strip all kill
934 // flags, and postRA passes will use a live register utility instead.
935 LiveRange *getRegUnitLI(unsigned Unit) {
937 return &LIS.getRegUnit(Unit);
938 return LIS.getCachedRegUnit(Unit);
941 /// Update all live ranges touched by MI, assuming a move from OldIdx to
943 void updateAllRanges(MachineInstr *MI) {
944 DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " << *MI);
945 bool hasRegMask = false;
946 for (MachineOperand &MO : MI->operands()) {
951 // Aggressively clear all kill flags.
952 // They are reinserted by VirtRegRewriter.
956 unsigned Reg = MO.getReg();
959 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
960 LiveInterval &LI = LIS.getInterval(Reg);
961 if (LI.hasSubRanges()) {
962 unsigned SubReg = MO.getSubReg();
963 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
964 for (LiveInterval::SubRange &S : LI.subranges()) {
965 if ((S.LaneMask & LaneMask) == 0)
967 updateRange(S, Reg, S.LaneMask);
970 updateRange(LI, Reg, 0);
974 // For physregs, only update the regunits that actually have a
975 // precomputed live range.
976 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
977 if (LiveRange *LR = getRegUnitLI(*Units))
978 updateRange(*LR, *Units, 0);
981 updateRegMaskSlots();
985 /// Update a single live range, assuming an instruction has been moved from
986 /// OldIdx to NewIdx.
987 void updateRange(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask) {
988 if (!Updated.insert(&LR).second)
992 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
993 dbgs() << PrintReg(Reg);
995 dbgs() << " L" << PrintLaneMask(LaneMask);
997 dbgs() << PrintRegUnit(Reg, &TRI);
999 dbgs() << ":\t" << LR << '\n';
1001 if (SlotIndex::isEarlierInstr(OldIdx, NewIdx))
1004 handleMoveUp(LR, Reg, LaneMask);
1005 DEBUG(dbgs() << " -->\t" << LR << '\n');
1009 /// Update LR to reflect an instruction has been moved downwards from OldIdx
1012 /// 1. Live def at OldIdx:
1013 /// Move def to NewIdx, assert endpoint after NewIdx.
1015 /// 2. Live def at OldIdx, killed at NewIdx:
1016 /// Change to dead def at NewIdx.
1017 /// (Happens when bundling def+kill together).
1019 /// 3. Dead def at OldIdx:
1020 /// Move def to NewIdx, possibly across another live value.
1022 /// 4. Def at OldIdx AND at NewIdx:
1023 /// Remove segment [OldIdx;NewIdx) and value defined at OldIdx.
1024 /// (Happens when bundling multiple defs together).
1026 /// 5. Value read at OldIdx, killed before NewIdx:
1027 /// Extend kill to NewIdx.
1029 void handleMoveDown(LiveRange &LR) {
1030 // First look for a kill at OldIdx.
1031 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
1032 LiveRange::iterator E = LR.end();
1033 // Is LR even live at OldIdx?
1034 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
1037 // Handle a live-in value.
1038 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1039 bool isKill = SlotIndex::isSameInstr(OldIdx, I->end);
1040 // If the live-in value already extends to NewIdx, there is nothing to do.
1041 if (!SlotIndex::isEarlierInstr(I->end, NewIdx))
1043 // Aggressively remove all kill flags from the old kill point.
1044 // Kill flags shouldn't be used while live intervals exist, they will be
1045 // reinserted by VirtRegRewriter.
1046 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(I->end))
1047 for (MIBundleOperands MO(KillMI); MO.isValid(); ++MO)
1048 if (MO->isReg() && MO->isUse())
1049 MO->setIsKill(false);
1050 // Adjust I->end to reach NewIdx. This may temporarily make LR invalid by
1051 // overlapping ranges. Case 5 above.
1052 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1053 // If this was a kill, there may also be a def. Otherwise we're done.
1059 // Check for a def at OldIdx.
1060 if (I == E || !SlotIndex::isSameInstr(OldIdx, I->start))
1062 // We have a def at OldIdx.
1063 VNInfo *DefVNI = I->valno;
1064 assert(DefVNI->def == I->start && "Inconsistent def");
1065 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1066 // If the defined value extends beyond NewIdx, just move the def down.
1067 // This is case 1 above.
1068 if (SlotIndex::isEarlierInstr(NewIdx, I->end)) {
1069 I->start = DefVNI->def;
1072 // The remaining possibilities are now:
1073 // 2. Live def at OldIdx, killed at NewIdx: isSameInstr(I->end, NewIdx).
1074 // 3. Dead def at OldIdx: I->end = OldIdx.getDeadSlot().
1075 // In either case, it is possible that there is an existing def at NewIdx.
1076 assert((I->end == OldIdx.getDeadSlot() ||
1077 SlotIndex::isSameInstr(I->end, NewIdx)) &&
1078 "Cannot move def below kill");
1079 LiveRange::iterator NewI = LR.advanceTo(I, NewIdx.getRegSlot());
1080 if (NewI != E && SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1081 // There is an existing def at NewIdx, case 4 above. The def at OldIdx is
1082 // coalesced into that value.
1083 assert(NewI->valno != DefVNI && "Multiple defs of value?");
1084 LR.removeValNo(DefVNI);
1087 // There was no existing def at NewIdx. Turn *I into a dead def at NewIdx.
1088 // If the def at OldIdx was dead, we allow it to be moved across other LR
1089 // values. The new range should be placed immediately before NewI, move any
1090 // intermediate ranges up.
1091 assert(NewI != I && "Inconsistent iterators");
1092 std::copy(std::next(I), NewI, I);
1094 = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1097 /// Update LR to reflect an instruction has been moved upwards from OldIdx
1100 /// 1. Live def at OldIdx:
1101 /// Hoist def to NewIdx.
1103 /// 2. Dead def at OldIdx:
1104 /// Hoist def+end to NewIdx, possibly move across other values.
1106 /// 3. Dead def at OldIdx AND existing def at NewIdx:
1107 /// Remove value defined at OldIdx, coalescing it with existing value.
1109 /// 4. Live def at OldIdx AND existing def at NewIdx:
1110 /// Remove value defined at NewIdx, hoist OldIdx def to NewIdx.
1111 /// (Happens when bundling multiple defs together).
1113 /// 5. Value killed at OldIdx:
1114 /// Hoist kill to NewIdx, then scan for last kill between NewIdx and
1117 void handleMoveUp(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask) {
1118 // First look for a kill at OldIdx.
1119 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
1120 LiveRange::iterator E = LR.end();
1121 // Is LR even live at OldIdx?
1122 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
1125 // Handle a live-in value.
1126 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1127 // If the live-in value isn't killed here, there is nothing to do.
1128 if (!SlotIndex::isSameInstr(OldIdx, I->end))
1130 // Adjust I->end to end at NewIdx. If we are hoisting a kill above
1131 // another use, we need to search for that use. Case 5 above.
1132 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1134 // If OldIdx also defines a value, there couldn't have been another use.
1135 if (I == E || !SlotIndex::isSameInstr(I->start, OldIdx)) {
1136 // No def, search for the new kill.
1137 // This can never be an early clobber kill since there is no def.
1138 std::prev(I)->end = findLastUseBefore(Reg, LaneMask).getRegSlot();
1143 // Now deal with the def at OldIdx.
1144 assert(I != E && SlotIndex::isSameInstr(I->start, OldIdx) && "No def?");
1145 VNInfo *DefVNI = I->valno;
1146 assert(DefVNI->def == I->start && "Inconsistent def");
1147 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1149 // Check for an existing def at NewIdx.
1150 LiveRange::iterator NewI = LR.find(NewIdx.getRegSlot());
1151 if (SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1152 assert(NewI->valno != DefVNI && "Same value defined more than once?");
1153 // There is an existing def at NewIdx.
1154 if (I->end.isDead()) {
1155 // Case 3: Remove the dead def at OldIdx.
1156 LR.removeValNo(DefVNI);
1159 // Case 4: Replace def at NewIdx with live def at OldIdx.
1160 I->start = DefVNI->def;
1161 LR.removeValNo(NewI->valno);
1165 // There is no existing def at NewIdx. Hoist DefVNI.
1166 if (!I->end.isDead()) {
1167 // Leave the end point of a live def.
1168 I->start = DefVNI->def;
1172 // DefVNI is a dead def. It may have been moved across other values in LR,
1173 // so move I up to NewI. Slide [NewI;I) down one position.
1174 std::copy_backward(NewI, I, std::next(I));
1175 *NewI = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1178 void updateRegMaskSlots() {
1179 SmallVectorImpl<SlotIndex>::iterator RI =
1180 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1182 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&
1183 "No RegMask at OldIdx.");
1184 *RI = NewIdx.getRegSlot();
1185 assert((RI == LIS.RegMaskSlots.begin() ||
1186 SlotIndex::isEarlierInstr(*std::prev(RI), *RI)) &&
1187 "Cannot move regmask instruction above another call");
1188 assert((std::next(RI) == LIS.RegMaskSlots.end() ||
1189 SlotIndex::isEarlierInstr(*RI, *std::next(RI))) &&
1190 "Cannot move regmask instruction below another call");
1193 // Return the last use of reg between NewIdx and OldIdx.
1194 SlotIndex findLastUseBefore(unsigned Reg, LaneBitmask LaneMask) {
1196 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1197 SlotIndex LastUse = NewIdx;
1198 for (MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
1199 unsigned SubReg = MO.getSubReg();
1200 if (SubReg != 0 && LaneMask != 0
1201 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask) == 0)
1204 const MachineInstr *MI = MO.getParent();
1205 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1206 if (InstSlot > LastUse && InstSlot < OldIdx)
1212 // This is a regunit interval, so scanning the use list could be very
1213 // expensive. Scan upwards from OldIdx instead.
1214 assert(NewIdx < OldIdx && "Expected upwards move");
1215 SlotIndexes *Indexes = LIS.getSlotIndexes();
1216 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(NewIdx);
1218 // OldIdx may not correspond to an instruction any longer, so set MII to
1219 // point to the next instruction after OldIdx, or MBB->end().
1220 MachineBasicBlock::iterator MII = MBB->end();
1221 if (MachineInstr *MI = Indexes->getInstructionFromIndex(
1222 Indexes->getNextNonNullIndex(OldIdx)))
1223 if (MI->getParent() == MBB)
1226 MachineBasicBlock::iterator Begin = MBB->begin();
1227 while (MII != Begin) {
1228 if ((--MII)->isDebugValue())
1230 SlotIndex Idx = Indexes->getInstructionIndex(MII);
1232 // Stop searching when NewIdx is reached.
1233 if (!SlotIndex::isEarlierInstr(NewIdx, Idx))
1236 // Check if MII uses Reg.
1237 for (MIBundleOperands MO(MII); MO.isValid(); ++MO)
1239 TargetRegisterInfo::isPhysicalRegister(MO->getReg()) &&
1240 TRI.hasRegUnit(MO->getReg(), Reg))
1243 // Didn't reach NewIdx. It must be the first instruction in the block.
1248 void LiveIntervals::handleMove(MachineInstr* MI, bool UpdateFlags) {
1249 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1250 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1251 Indexes->removeMachineInstrFromMaps(MI);
1252 SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
1253 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1254 OldIndex < getMBBEndIdx(MI->getParent()) &&
1255 "Cannot handle moves across basic block boundaries.");
1257 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1258 HME.updateAllRanges(MI);
1261 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1262 MachineInstr* BundleStart,
1264 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1265 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1266 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1267 HME.updateAllRanges(MI);
1270 void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
1271 const MachineBasicBlock::iterator End,
1272 const SlotIndex endIdx,
1273 LiveRange &LR, const unsigned Reg,
1274 LaneBitmask LaneMask) {
1275 LiveInterval::iterator LII = LR.find(endIdx);
1276 SlotIndex lastUseIdx;
1277 if (LII != LR.end() && LII->start < endIdx)
1278 lastUseIdx = LII->end;
1282 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1284 MachineInstr *MI = I;
1285 if (MI->isDebugValue())
1288 SlotIndex instrIdx = getInstructionIndex(MI);
1289 bool isStartValid = getInstructionFromIndex(LII->start);
1290 bool isEndValid = getInstructionFromIndex(LII->end);
1292 // FIXME: This doesn't currently handle early-clobber or multiple removed
1293 // defs inside of the region to repair.
1294 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
1295 OE = MI->operands_end(); OI != OE; ++OI) {
1296 const MachineOperand &MO = *OI;
1297 if (!MO.isReg() || MO.getReg() != Reg)
1300 unsigned SubReg = MO.getSubReg();
1301 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg);
1302 if ((Mask & LaneMask) == 0)
1306 if (!isStartValid) {
1307 if (LII->end.isDead()) {
1308 SlotIndex prevStart;
1309 if (LII != LR.begin())
1310 prevStart = std::prev(LII)->start;
1312 // FIXME: This could be more efficient if there was a
1313 // removeSegment method that returned an iterator.
1314 LR.removeSegment(*LII, true);
1315 if (prevStart.isValid())
1316 LII = LR.find(prevStart);
1320 LII->start = instrIdx.getRegSlot();
1321 LII->valno->def = instrIdx.getRegSlot();
1322 if (MO.getSubReg() && !MO.isUndef())
1323 lastUseIdx = instrIdx.getRegSlot();
1325 lastUseIdx = SlotIndex();
1330 if (!lastUseIdx.isValid()) {
1331 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1332 LiveRange::Segment S(instrIdx.getRegSlot(),
1333 instrIdx.getDeadSlot(), VNI);
1334 LII = LR.addSegment(S);
1335 } else if (LII->start != instrIdx.getRegSlot()) {
1336 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1337 LiveRange::Segment S(instrIdx.getRegSlot(), lastUseIdx, VNI);
1338 LII = LR.addSegment(S);
1341 if (MO.getSubReg() && !MO.isUndef())
1342 lastUseIdx = instrIdx.getRegSlot();
1344 lastUseIdx = SlotIndex();
1345 } else if (MO.isUse()) {
1346 // FIXME: This should probably be handled outside of this branch,
1347 // either as part of the def case (for defs inside of the region) or
1348 // after the loop over the region.
1349 if (!isEndValid && !LII->end.isBlock())
1350 LII->end = instrIdx.getRegSlot();
1351 if (!lastUseIdx.isValid())
1352 lastUseIdx = instrIdx.getRegSlot();
1359 LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
1360 MachineBasicBlock::iterator Begin,
1361 MachineBasicBlock::iterator End,
1362 ArrayRef<unsigned> OrigRegs) {
1363 // Find anchor points, which are at the beginning/end of blocks or at
1364 // instructions that already have indexes.
1365 while (Begin != MBB->begin() && !Indexes->hasIndex(Begin))
1367 while (End != MBB->end() && !Indexes->hasIndex(End))
1371 if (End == MBB->end())
1372 endIdx = getMBBEndIdx(MBB).getPrevSlot();
1374 endIdx = getInstructionIndex(End);
1376 Indexes->repairIndexesInRange(MBB, Begin, End);
1378 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1380 MachineInstr *MI = I;
1381 if (MI->isDebugValue())
1383 for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
1384 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
1386 TargetRegisterInfo::isVirtualRegister(MOI->getReg()) &&
1387 !hasInterval(MOI->getReg())) {
1388 createAndComputeVirtRegInterval(MOI->getReg());
1393 for (unsigned i = 0, e = OrigRegs.size(); i != e; ++i) {
1394 unsigned Reg = OrigRegs[i];
1395 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1398 LiveInterval &LI = getInterval(Reg);
1399 // FIXME: Should we support undefs that gain defs?
1400 if (!LI.hasAtLeastOneValue())
1403 for (LiveInterval::SubRange &S : LI.subranges()) {
1404 repairOldRegInRange(Begin, End, endIdx, S, Reg, S.LaneMask);
1406 repairOldRegInRange(Begin, End, endIdx, LI, Reg);
1410 void LiveIntervals::removePhysRegDefAt(unsigned Reg, SlotIndex Pos) {
1411 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
1412 if (LiveRange *LR = getCachedRegUnit(*Units))
1413 if (VNInfo *VNI = LR->getVNInfoAt(Pos))
1414 LR->removeValNo(VNI);
1418 void LiveIntervals::removeVRegDefAt(LiveInterval &LI, SlotIndex Pos) {
1419 VNInfo *VNI = LI.getVNInfoAt(Pos);
1422 LI.removeValNo(VNI);
1424 // Also remove the value in subranges.
1425 for (LiveInterval::SubRange &S : LI.subranges()) {
1426 if (VNInfo *SVNI = S.getVNInfoAt(Pos))
1427 S.removeValNo(SVNI);
1429 LI.removeEmptySubRanges();
1432 void LiveIntervals::splitSeparateComponents(LiveInterval &LI,
1433 SmallVectorImpl<LiveInterval*> &SplitLIs) {
1434 ConnectedVNInfoEqClasses ConEQ(*this);
1435 unsigned NumComp = ConEQ.Classify(&LI);
1438 DEBUG(dbgs() << " Split " << NumComp << " components: " << LI << '\n');
1439 unsigned Reg = LI.reg;
1440 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
1441 for (unsigned I = 1; I < NumComp; ++I) {
1442 unsigned NewVReg = MRI->createVirtualRegister(RegClass);
1443 LiveInterval &NewLI = createEmptyInterval(NewVReg);
1444 SplitLIs.push_back(&NewLI);
1446 ConEQ.Distribute(LI, SplitLIs.data(), *MRI);