1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "regalloc"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/Value.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/ADT/DenseSet.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "LiveRangeCalc.h"
41 char LiveIntervals::ID = 0;
42 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
43 "Live Interval Analysis", false, false)
44 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
45 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
46 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
47 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
48 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
49 "Live Interval Analysis", false, false)
51 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
53 AU.addRequired<AliasAnalysis>();
54 AU.addPreserved<AliasAnalysis>();
55 AU.addRequired<LiveVariables>();
56 AU.addPreserved<LiveVariables>();
57 AU.addPreservedID(MachineLoopInfoID);
58 AU.addRequiredTransitiveID(MachineDominatorsID);
59 AU.addPreservedID(MachineDominatorsID);
60 AU.addPreserved<SlotIndexes>();
61 AU.addRequiredTransitive<SlotIndexes>();
62 MachineFunctionPass::getAnalysisUsage(AU);
65 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
66 DomTree(0), LRCalc(0) {
67 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
70 LiveIntervals::~LiveIntervals() {
74 void LiveIntervals::releaseMemory() {
75 // Free the live intervals themselves.
76 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
77 delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
78 VirtRegIntervals.clear();
81 RegMaskBlocks.clear();
83 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
84 delete RegUnitIntervals[i];
85 RegUnitIntervals.clear();
87 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
88 VNInfoAllocator.Reset();
91 /// runOnMachineFunction - Register allocate the whole function
93 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
95 MRI = &MF->getRegInfo();
97 TRI = TM->getRegisterInfo();
98 TII = TM->getInstrInfo();
99 AA = &getAnalysis<AliasAnalysis>();
100 LV = &getAnalysis<LiveVariables>();
101 Indexes = &getAnalysis<SlotIndexes>();
102 DomTree = &getAnalysis<MachineDominatorTree>();
104 LRCalc = new LiveRangeCalc();
105 AllocatableRegs = TRI->getAllocatableSet(fn);
106 ReservedRegs = TRI->getReservedRegs(fn);
109 computeLiveInRegUnits();
115 /// print - Implement the dump method.
116 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
117 OS << "********** INTERVALS **********\n";
119 // Dump the regunits.
120 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
121 if (LiveInterval *LI = RegUnitIntervals[i])
122 OS << PrintRegUnit(i, TRI) << " = " << *LI << '\n';
124 // Dump the virtregs.
125 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
126 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
127 if (hasInterval(Reg))
128 OS << PrintReg(Reg) << " = " << getInterval(Reg) << '\n';
134 void LiveIntervals::printInstrs(raw_ostream &OS) const {
135 OS << "********** MACHINEINSTRS **********\n";
136 MF->print(OS, Indexes);
139 void LiveIntervals::dumpInstrs() const {
144 bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
145 unsigned Reg = MI.getOperand(MOIdx).getReg();
146 for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
147 const MachineOperand &MO = MI.getOperand(i);
150 if (MO.getReg() == Reg && MO.isDef()) {
151 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
152 MI.getOperand(MOIdx).getSubReg() &&
153 (MO.getSubReg() || MO.isImplicit()));
160 /// isPartialRedef - Return true if the specified def at the specific index is
161 /// partially re-defining the specified live interval. A common case of this is
162 /// a definition of the sub-register.
163 bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
164 LiveInterval &interval) {
165 if (!MO.getSubReg() || MO.isEarlyClobber())
168 SlotIndex RedefIndex = MIIdx.getRegSlot();
169 const LiveRange *OldLR =
170 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
171 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
173 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
178 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
179 MachineBasicBlock::iterator mi,
183 LiveInterval &interval) {
184 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, TRI));
186 // Virtual registers may be defined multiple times (due to phi
187 // elimination and 2-addr elimination). Much of what we do only has to be
188 // done once for the vreg. We use an empty interval to detect the first
189 // time we see a vreg.
190 LiveVariables::VarInfo& vi = LV->getVarInfo(interval.reg);
191 if (interval.empty()) {
192 // Get the Idx of the defining instructions.
193 SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
195 // Make sure the first definition is not a partial redefinition.
196 assert(!MO.readsReg() && "First def cannot also read virtual register "
197 "missing <undef> flag?");
199 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
200 assert(ValNo->id == 0 && "First value in interval is not 0?");
202 // Loop over all of the blocks that the vreg is defined in. There are
203 // two cases we have to handle here. The most common case is a vreg
204 // whose lifetime is contained within a basic block. In this case there
205 // will be a single kill, in MBB, which comes after the definition.
206 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
207 // FIXME: what about dead vars?
209 if (vi.Kills[0] != mi)
210 killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
212 killIdx = defIndex.getDeadSlot();
214 // If the kill happens after the definition, we have an intra-block
216 if (killIdx > defIndex) {
217 assert(vi.AliveBlocks.empty() &&
218 "Shouldn't be alive across any blocks!");
219 LiveRange LR(defIndex, killIdx, ValNo);
220 interval.addRange(LR);
221 DEBUG(dbgs() << " +" << LR << "\n");
226 // The other case we handle is when a virtual register lives to the end
227 // of the defining block, potentially live across some blocks, then is
228 // live into some number of blocks, but gets killed. Start by adding a
229 // range that goes from this definition to the end of the defining block.
230 LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
231 DEBUG(dbgs() << " +" << NewLR);
232 interval.addRange(NewLR);
234 bool PHIJoin = LV->isPHIJoin(interval.reg);
237 // A phi join register is killed at the end of the MBB and revived as a
238 // new valno in the killing blocks.
239 assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
240 DEBUG(dbgs() << " phi-join");
241 ValNo->setHasPHIKill(true);
243 // Iterate over all of the blocks that the variable is completely
244 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
246 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
247 E = vi.AliveBlocks.end(); I != E; ++I) {
248 MachineBasicBlock *aliveBlock = MF->getBlockNumbered(*I);
249 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock),
251 interval.addRange(LR);
252 DEBUG(dbgs() << " +" << LR);
256 // Finally, this virtual register is live from the start of any killing
257 // block to the 'use' slot of the killing instruction.
258 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
259 MachineInstr *Kill = vi.Kills[i];
260 SlotIndex Start = getMBBStartIdx(Kill->getParent());
261 SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
263 // Create interval with one of a NEW value number. Note that this value
264 // number isn't actually defined by an instruction, weird huh? :)
266 assert(getInstructionFromIndex(Start) == 0 &&
267 "PHI def index points at actual instruction.");
268 ValNo = interval.getNextValue(Start, VNInfoAllocator);
269 ValNo->setIsPHIDef(true);
271 LiveRange LR(Start, killIdx, ValNo);
272 interval.addRange(LR);
273 DEBUG(dbgs() << " +" << LR);
277 if (MultipleDefsBySameMI(*mi, MOIdx))
278 // Multiple defs of the same virtual register by the same instruction.
279 // e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
280 // This is likely due to elimination of REG_SEQUENCE instructions. Return
281 // here since there is nothing to do.
284 // If this is the second time we see a virtual register definition, it
285 // must be due to phi elimination or two addr elimination. If this is
286 // the result of two address elimination, then the vreg is one of the
287 // def-and-use register operand.
289 // It may also be partial redef like this:
290 // 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
291 // 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
292 bool PartReDef = isPartialRedef(MIIdx, MO, interval);
293 if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
294 // If this is a two-address definition, then we have already processed
295 // the live range. The only problem is that we didn't realize there
296 // are actually two values in the live interval. Because of this we
297 // need to take the LiveRegion that defines this register and split it
299 SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
301 const LiveRange *OldLR =
302 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
303 VNInfo *OldValNo = OldLR->valno;
304 SlotIndex DefIndex = OldValNo->def.getRegSlot();
306 // Delete the previous value, which should be short and continuous,
307 // because the 2-addr copy must be in the same MBB as the redef.
308 interval.removeRange(DefIndex, RedefIndex);
310 // The new value number (#1) is defined by the instruction we claimed
312 VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
314 // Value#0 is now defined by the 2-addr instruction.
315 OldValNo->def = RedefIndex;
317 // Add the new live interval which replaces the range for the input copy.
318 LiveRange LR(DefIndex, RedefIndex, ValNo);
319 DEBUG(dbgs() << " replace range with " << LR);
320 interval.addRange(LR);
322 // If this redefinition is dead, we need to add a dummy unit live
323 // range covering the def slot.
325 interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
328 DEBUG(dbgs() << " RESULT: " << interval);
329 } else if (LV->isPHIJoin(interval.reg)) {
330 // In the case of PHI elimination, each variable definition is only
331 // live until the end of the block. We've already taken care of the
332 // rest of the live range.
334 SlotIndex defIndex = MIIdx.getRegSlot();
335 if (MO.isEarlyClobber())
336 defIndex = MIIdx.getRegSlot(true);
338 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
340 SlotIndex killIndex = getMBBEndIdx(mbb);
341 LiveRange LR(defIndex, killIndex, ValNo);
342 interval.addRange(LR);
343 ValNo->setHasPHIKill(true);
344 DEBUG(dbgs() << " phi-join +" << LR);
346 llvm_unreachable("Multiply defined register");
350 DEBUG(dbgs() << '\n');
353 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
354 MachineBasicBlock::iterator MI,
358 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
359 handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
360 getOrCreateInterval(MO.getReg()));
363 /// computeIntervals - computes the live intervals for virtual
364 /// registers. for some ordering of the machine instructions [1,N] a
365 /// live interval is an interval [i, j) where 1 <= i <= j < N for
366 /// which a variable is live
367 void LiveIntervals::computeIntervals() {
368 DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
369 << "********** Function: "
370 << ((Value*)MF->getFunction())->getName() << '\n');
372 RegMaskBlocks.resize(MF->getNumBlockIDs());
374 SmallVector<unsigned, 8> UndefUses;
375 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
377 MachineBasicBlock *MBB = MBBI;
378 RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size();
383 // Track the index of the current machine instr.
384 SlotIndex MIIndex = getMBBStartIdx(MBB);
385 DEBUG(dbgs() << "BB#" << MBB->getNumber()
386 << ":\t\t# derived from " << MBB->getName() << "\n");
388 // Skip over empty initial indices.
389 if (getInstructionFromIndex(MIIndex) == 0)
390 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
392 for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
394 DEBUG(dbgs() << MIIndex << "\t" << *MI);
395 if (MI->isDebugValue())
397 assert(Indexes->getInstructionFromIndex(MIIndex) == MI &&
398 "Lost SlotIndex synchronization");
401 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
402 MachineOperand &MO = MI->getOperand(i);
404 // Collect register masks.
405 if (MO.isRegMask()) {
406 RegMaskSlots.push_back(MIIndex.getRegSlot());
407 RegMaskBits.push_back(MO.getRegMask());
411 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
414 // handle register defs - build intervals
416 handleRegisterDef(MBB, MI, MIIndex, MO, i);
417 else if (MO.isUndef())
418 UndefUses.push_back(MO.getReg());
421 // Move to the next instr slot.
422 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
425 // Compute the number of register mask instructions in this block.
426 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
427 RMB.second = RegMaskSlots.size() - RMB.first;;
430 // Create empty intervals for registers defined by implicit_def's (except
431 // for those implicit_def that define values which are liveout of their
433 for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
434 unsigned UndefReg = UndefUses[i];
435 (void)getOrCreateInterval(UndefReg);
439 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
440 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
441 return new LiveInterval(reg, Weight);
445 //===----------------------------------------------------------------------===//
446 // Register Unit Liveness
447 //===----------------------------------------------------------------------===//
449 // Fixed interference typically comes from ABI boundaries: Function arguments
450 // and return values are passed in fixed registers, and so are exception
451 // pointers entering landing pads. Certain instructions require values to be
452 // present in specific registers. That is also represented through fixed
456 /// computeRegUnitInterval - Compute the live interval of a register unit, based
457 /// on the uses and defs of aliasing registers. The interval should be empty,
458 /// or contain only dead phi-defs from ABI blocks.
459 void LiveIntervals::computeRegUnitInterval(LiveInterval *LI) {
460 unsigned Unit = LI->reg;
462 assert(LRCalc && "LRCalc not initialized.");
463 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
465 // The physregs aliasing Unit are the roots and their super-registers.
466 // Create all values as dead defs before extending to uses. Note that roots
467 // may share super-registers. That's OK because createDeadDefs() is
468 // idempotent. It is very rare for a register unit to have multiple roots, so
469 // uniquing super-registers is probably not worthwhile.
470 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
471 unsigned Root = *Roots;
472 if (!MRI->reg_empty(Root))
473 LRCalc->createDeadDefs(LI, Root);
474 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
475 if (!MRI->reg_empty(*Supers))
476 LRCalc->createDeadDefs(LI, *Supers);
480 // Now extend LI to reach all uses.
481 // Ignore uses of reserved registers. We only track defs of those.
482 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
483 unsigned Root = *Roots;
484 if (!isReserved(Root) && !MRI->reg_empty(Root))
485 LRCalc->extendToUses(LI, Root);
486 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
487 unsigned Reg = *Supers;
488 if (!isReserved(Reg) && !MRI->reg_empty(Reg))
489 LRCalc->extendToUses(LI, Reg);
495 /// computeLiveInRegUnits - Precompute the live ranges of any register units
496 /// that are live-in to an ABI block somewhere. Register values can appear
497 /// without a corresponding def when entering the entry block or a landing pad.
499 void LiveIntervals::computeLiveInRegUnits() {
500 RegUnitIntervals.resize(TRI->getNumRegUnits());
501 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
503 // Keep track of the intervals allocated.
504 SmallVector<LiveInterval*, 8> NewIntvs;
506 // Check all basic blocks for live-ins.
507 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
509 const MachineBasicBlock *MBB = MFI;
511 // We only care about ABI blocks: Entry + landing pads.
512 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
515 // Create phi-defs at Begin for all live-in registers.
516 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
517 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
518 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
519 LIE = MBB->livein_end(); LII != LIE; ++LII) {
520 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
521 unsigned Unit = *Units;
522 LiveInterval *Intv = RegUnitIntervals[Unit];
524 Intv = RegUnitIntervals[Unit] = new LiveInterval(Unit, HUGE_VALF);
525 NewIntvs.push_back(Intv);
527 VNInfo *VNI = Intv->createDeadDef(Begin, getVNInfoAllocator());
529 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
532 DEBUG(dbgs() << '\n');
534 DEBUG(dbgs() << "Created " << NewIntvs.size() << " new intervals.\n");
536 // Compute the 'normal' part of the intervals.
537 for (unsigned i = 0, e = NewIntvs.size(); i != e; ++i)
538 computeRegUnitInterval(NewIntvs[i]);
542 /// shrinkToUses - After removing some uses of a register, shrink its live
543 /// range to just the remaining uses. This method does not compute reaching
544 /// defs for new uses, and it doesn't remove dead defs.
545 bool LiveIntervals::shrinkToUses(LiveInterval *li,
546 SmallVectorImpl<MachineInstr*> *dead) {
547 DEBUG(dbgs() << "Shrink: " << *li << '\n');
548 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
549 && "Can only shrink virtual registers");
550 // Find all the values used, including PHI kills.
551 SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
553 // Blocks that have already been added to WorkList as live-out.
554 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
556 // Visit all instructions reading li->reg.
557 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(li->reg);
558 MachineInstr *UseMI = I.skipInstruction();) {
559 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
561 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
562 LiveRangeQuery LRQ(*li, Idx);
563 VNInfo *VNI = LRQ.valueIn();
565 // This shouldn't happen: readsVirtualRegister returns true, but there is
566 // no live value. It is likely caused by a target getting <undef> flags
568 DEBUG(dbgs() << Idx << '\t' << *UseMI
569 << "Warning: Instr claims to read non-existent value in "
573 // Special case: An early-clobber tied operand reads and writes the
574 // register one slot early.
575 if (VNInfo *DefVNI = LRQ.valueDefined())
578 WorkList.push_back(std::make_pair(Idx, VNI));
581 // Create a new live interval with only minimal live segments per def.
582 LiveInterval NewLI(li->reg, 0);
583 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
588 NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
591 // Keep track of the PHIs that are in use.
592 SmallPtrSet<VNInfo*, 8> UsedPHIs;
594 // Extend intervals to reach all uses in WorkList.
595 while (!WorkList.empty()) {
596 SlotIndex Idx = WorkList.back().first;
597 VNInfo *VNI = WorkList.back().second;
599 const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
600 SlotIndex BlockStart = getMBBStartIdx(MBB);
602 // Extend the live range for VNI to be live at Idx.
603 if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
605 assert(ExtVNI == VNI && "Unexpected existing value number");
606 // Is this a PHIDef we haven't seen before?
607 if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
609 // The PHI is live, make sure the predecessors are live-out.
610 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
611 PE = MBB->pred_end(); PI != PE; ++PI) {
612 if (!LiveOut.insert(*PI))
614 SlotIndex Stop = getMBBEndIdx(*PI);
615 // A predecessor is not required to have a live-out value for a PHI.
616 if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
617 WorkList.push_back(std::make_pair(Stop, PVNI));
622 // VNI is live-in to MBB.
623 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
624 NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
626 // Make sure VNI is live-out from the predecessors.
627 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
628 PE = MBB->pred_end(); PI != PE; ++PI) {
629 if (!LiveOut.insert(*PI))
631 SlotIndex Stop = getMBBEndIdx(*PI);
632 assert(li->getVNInfoBefore(Stop) == VNI &&
633 "Wrong value out of predecessor");
634 WorkList.push_back(std::make_pair(Stop, VNI));
638 // Handle dead values.
639 bool CanSeparate = false;
640 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
645 LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
646 assert(LII != NewLI.end() && "Missing live range for PHI");
647 if (LII->end != VNI->def.getDeadSlot())
649 if (VNI->isPHIDef()) {
650 // This is a dead PHI. Remove it.
651 VNI->setIsUnused(true);
652 NewLI.removeRange(*LII);
653 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
656 // This is a dead def. Make sure the instruction knows.
657 MachineInstr *MI = getInstructionFromIndex(VNI->def);
658 assert(MI && "No instruction defining live value");
659 MI->addRegisterDead(li->reg, TRI);
660 if (dead && MI->allDefsAreDead()) {
661 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
667 // Move the trimmed ranges back.
668 li->ranges.swap(NewLI.ranges);
669 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
674 //===----------------------------------------------------------------------===//
675 // Register allocator hooks.
678 void LiveIntervals::addKillFlags() {
679 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
680 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
681 if (MRI->reg_nodbg_empty(Reg))
683 LiveInterval *LI = &getInterval(Reg);
685 // Every instruction that kills Reg corresponds to a live range end point.
686 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
688 // A block index indicates an MBB edge.
689 if (RI->end.isBlock())
691 MachineInstr *MI = getInstructionFromIndex(RI->end);
694 MI->addRegisterKilled(Reg, NULL);
700 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
701 // A local live range must be fully contained inside the block, meaning it is
702 // defined and killed at instructions, not at block boundaries. It is not
703 // live in or or out of any block.
705 // It is technically possible to have a PHI-defined live range identical to a
706 // single block, but we are going to return false in that case.
708 SlotIndex Start = LI.beginIndex();
712 SlotIndex Stop = LI.endIndex();
716 // getMBBFromIndex doesn't need to search the MBB table when both indexes
717 // belong to proper instructions.
718 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
719 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
720 return MBB1 == MBB2 ? MBB1 : NULL;
724 LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
725 // Limit the loop depth ridiculousness.
729 // The loop depth is used to roughly estimate the number of times the
730 // instruction is executed. Something like 10^d is simple, but will quickly
731 // overflow a float. This expression behaves like 10^d for small d, but is
732 // more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
733 // headroom before overflow.
734 // By the way, powf() might be unavailable here. For consistency,
735 // We may take pow(double,double).
736 float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
738 return (isDef + isUse) * lc;
741 LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
742 MachineInstr* startInst) {
743 LiveInterval& Interval = getOrCreateInterval(reg);
744 VNInfo* VN = Interval.getNextValue(
745 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
746 getVNInfoAllocator());
747 VN->setHasPHIKill(true);
749 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
750 getMBBEndIdx(startInst->getParent()), VN);
751 Interval.addRange(LR);
757 //===----------------------------------------------------------------------===//
758 // Register mask functions
759 //===----------------------------------------------------------------------===//
761 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
762 BitVector &UsableRegs) {
765 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
767 // Use a smaller arrays for local live ranges.
768 ArrayRef<SlotIndex> Slots;
769 ArrayRef<const uint32_t*> Bits;
770 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
771 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
772 Bits = getRegMaskBitsInBlock(MBB->getNumber());
774 Slots = getRegMaskSlots();
775 Bits = getRegMaskBits();
778 // We are going to enumerate all the register mask slots contained in LI.
779 // Start with a binary search of RegMaskSlots to find a starting point.
780 ArrayRef<SlotIndex>::iterator SlotI =
781 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
782 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
784 // No slots in range, LI begins after the last call.
790 assert(*SlotI >= LiveI->start);
791 // Loop over all slots overlapping this segment.
792 while (*SlotI < LiveI->end) {
793 // *SlotI overlaps LI. Collect mask bits.
795 // This is the first overlap. Initialize UsableRegs to all ones.
797 UsableRegs.resize(TRI->getNumRegs(), true);
800 // Remove usable registers clobbered by this mask.
801 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
802 if (++SlotI == SlotE)
805 // *SlotI is beyond the current LI segment.
806 LiveI = LI.advanceTo(LiveI, *SlotI);
809 // Advance SlotI until it overlaps.
810 while (*SlotI < LiveI->start)
811 if (++SlotI == SlotE)
816 //===----------------------------------------------------------------------===//
817 // IntervalUpdate class.
818 //===----------------------------------------------------------------------===//
820 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
821 class LiveIntervals::HMEditor {
824 const MachineRegisterInfo& MRI;
825 const TargetRegisterInfo& TRI;
828 typedef std::pair<LiveInterval*, LiveRange*> IntRangePair;
829 typedef DenseSet<IntRangePair> RangeSet;
836 RegRanges() : Use(0), EC(0), Dead(0), Def(0) {}
838 typedef DenseMap<unsigned, RegRanges> BundleRanges;
841 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
842 const TargetRegisterInfo& TRI, SlotIndex NewIdx)
843 : LIS(LIS), MRI(MRI), TRI(TRI), NewIdx(NewIdx) {}
845 // Update intervals for all operands of MI from OldIdx to NewIdx.
846 // This assumes that MI used to be at OldIdx, and now resides at
848 void moveAllRangesFrom(MachineInstr* MI, SlotIndex OldIdx) {
849 assert(NewIdx != OldIdx && "No-op move? That's a bit strange.");
851 // Collect the operands.
852 RangeSet Entering, Internal, Exiting;
853 bool hasRegMaskOp = false;
854 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
856 // To keep the LiveRanges valid within an interval, move the ranges closest
857 // to the destination first. This prevents ranges from overlapping, to that
858 // APIs like removeRange still work.
859 if (NewIdx < OldIdx) {
860 moveAllEnteringFrom(OldIdx, Entering);
861 moveAllInternalFrom(OldIdx, Internal);
862 moveAllExitingFrom(OldIdx, Exiting);
865 moveAllExitingFrom(OldIdx, Exiting);
866 moveAllInternalFrom(OldIdx, Internal);
867 moveAllEnteringFrom(OldIdx, Entering);
871 updateRegMaskSlots(OldIdx);
874 LIValidator validator;
875 validator = std::for_each(Entering.begin(), Entering.end(), validator);
876 validator = std::for_each(Internal.begin(), Internal.end(), validator);
877 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
878 assert(validator.rangesOk() && "moveAllOperandsFrom broke liveness.");
883 // Update intervals for all operands of MI to refer to BundleStart's
885 void moveAllRangesInto(MachineInstr* MI, MachineInstr* BundleStart) {
886 if (MI == BundleStart)
887 return; // Bundling instr with itself - nothing to do.
889 SlotIndex OldIdx = LIS.getSlotIndexes()->getInstructionIndex(MI);
890 assert(LIS.getSlotIndexes()->getInstructionFromIndex(OldIdx) == MI &&
891 "SlotIndex <-> Instruction mapping broken for MI");
893 // Collect all ranges already in the bundle.
894 MachineBasicBlock::instr_iterator BII(BundleStart);
895 RangeSet Entering, Internal, Exiting;
896 bool hasRegMaskOp = false;
897 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
898 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
899 for (++BII; &*BII == MI || BII->isInsideBundle(); ++BII) {
902 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
903 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
906 BundleRanges BR = createBundleRanges(Entering, Internal, Exiting);
911 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
912 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
914 DEBUG(dbgs() << "Entering: " << Entering.size() << "\n");
915 DEBUG(dbgs() << "Internal: " << Internal.size() << "\n");
916 DEBUG(dbgs() << "Exiting: " << Exiting.size() << "\n");
918 moveAllEnteringFromInto(OldIdx, Entering, BR);
919 moveAllInternalFromInto(OldIdx, Internal, BR);
920 moveAllExitingFromInto(OldIdx, Exiting, BR);
924 LIValidator validator;
925 validator = std::for_each(Entering.begin(), Entering.end(), validator);
926 validator = std::for_each(Internal.begin(), Internal.end(), validator);
927 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
928 assert(validator.rangesOk() && "moveAllOperandsInto broke liveness.");
937 DenseSet<const LiveInterval*> Checked, Bogus;
939 void operator()(const IntRangePair& P) {
940 const LiveInterval* LI = P.first;
941 if (Checked.count(LI))
946 SlotIndex LastEnd = LI->begin()->start;
947 for (LiveInterval::const_iterator LRI = LI->begin(), LRE = LI->end();
949 const LiveRange& LR = *LRI;
950 if (LastEnd > LR.start || LR.start >= LR.end)
956 bool rangesOk() const {
957 return Bogus.empty();
962 // Collect IntRangePairs for all operands of MI that may need fixing.
963 // Treat's MI's index as OldIdx (regardless of what it is in SlotIndexes'
965 void collectRanges(MachineInstr* MI, RangeSet& Entering, RangeSet& Internal,
966 RangeSet& Exiting, bool& hasRegMaskOp, SlotIndex OldIdx) {
967 hasRegMaskOp = false;
968 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
969 MOE = MI->operands_end();
971 const MachineOperand& MO = *MOI;
973 if (MO.isRegMask()) {
978 if (!MO.isReg() || MO.getReg() == 0)
981 unsigned Reg = MO.getReg();
983 // TODO: Currently we're skipping uses that are reserved or have no
984 // interval, but we're not updating their kills. This should be
986 if (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg))
989 // Collect ranges for register units. These live ranges are computed on
990 // demand, so just skip any that haven't been computed yet.
991 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
992 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
993 if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))
994 collectRanges(MO, LI, Entering, Internal, Exiting, OldIdx);
996 // Collect ranges for individual virtual registers.
997 collectRanges(MO, &LIS.getInterval(Reg),
998 Entering, Internal, Exiting, OldIdx);
1003 void collectRanges(const MachineOperand &MO, LiveInterval *LI,
1004 RangeSet &Entering, RangeSet &Internal, RangeSet &Exiting,
1006 if (MO.readsReg()) {
1007 LiveRange* LR = LI->getLiveRangeContaining(OldIdx);
1009 Entering.insert(std::make_pair(LI, LR));
1012 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot());
1013 assert(LR != 0 && "No live range for def?");
1014 if (LR->end > OldIdx.getDeadSlot())
1015 Exiting.insert(std::make_pair(LI, LR));
1017 Internal.insert(std::make_pair(LI, LR));
1021 BundleRanges createBundleRanges(RangeSet& Entering,
1023 RangeSet& Exiting) {
1026 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1028 LiveInterval* LI = EI->first;
1029 LiveRange* LR = EI->second;
1030 BR[LI->reg].Use = LR;
1033 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1035 LiveInterval* LI = II->first;
1036 LiveRange* LR = II->second;
1037 if (LR->end.isDead()) {
1038 BR[LI->reg].Dead = LR;
1040 BR[LI->reg].EC = LR;
1044 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1046 LiveInterval* LI = EI->first;
1047 LiveRange* LR = EI->second;
1048 BR[LI->reg].Def = LR;
1054 void moveKillFlags(unsigned reg, SlotIndex OldIdx, SlotIndex newKillIdx) {
1055 MachineInstr* OldKillMI = LIS.getInstructionFromIndex(OldIdx);
1056 if (!OldKillMI->killsRegister(reg))
1057 return; // Bail out if we don't have kill flags on the old register.
1058 MachineInstr* NewKillMI = LIS.getInstructionFromIndex(newKillIdx);
1059 assert(OldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill.");
1060 assert(!NewKillMI->killsRegister(reg) &&
1061 "New kill instr is already a kill.");
1062 OldKillMI->clearRegisterKills(reg, &TRI);
1063 NewKillMI->addRegisterKilled(reg, &TRI);
1066 void updateRegMaskSlots(SlotIndex OldIdx) {
1067 SmallVectorImpl<SlotIndex>::iterator RI =
1068 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1070 assert(*RI == OldIdx && "No RegMask at OldIdx.");
1072 assert(*prior(RI) < *RI && *RI < *next(RI) &&
1073 "RegSlots out of order. Did you move one call across another?");
1076 // Return the last use of reg between NewIdx and OldIdx.
1077 SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) {
1078 SlotIndex LastUse = NewIdx;
1079 for (MachineRegisterInfo::use_nodbg_iterator
1080 UI = MRI.use_nodbg_begin(Reg),
1081 UE = MRI.use_nodbg_end();
1082 UI != UE; UI.skipInstruction()) {
1083 const MachineInstr* MI = &*UI;
1084 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1085 if (InstSlot > LastUse && InstSlot < OldIdx)
1091 void moveEnteringUpFrom(SlotIndex OldIdx, IntRangePair& P) {
1092 LiveInterval* LI = P.first;
1093 LiveRange* LR = P.second;
1094 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1097 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1098 if (LastUse != NewIdx)
1099 moveKillFlags(LI->reg, NewIdx, LastUse);
1100 LR->end = LastUse.getRegSlot();
1103 void moveEnteringDownFrom(SlotIndex OldIdx, IntRangePair& P) {
1104 LiveInterval* LI = P.first;
1105 LiveRange* LR = P.second;
1106 // Extend the LiveRange if NewIdx is past the end.
1107 if (NewIdx > LR->end) {
1108 // Move kill flags if OldIdx was not originally the end
1109 // (otherwise LR->end points to an invalid slot).
1110 if (LR->end.getRegSlot() != OldIdx.getRegSlot()) {
1111 assert(LR->end > OldIdx && "LiveRange does not cover original slot");
1112 moveKillFlags(LI->reg, LR->end, NewIdx);
1114 LR->end = NewIdx.getRegSlot();
1118 void moveAllEnteringFrom(SlotIndex OldIdx, RangeSet& Entering) {
1119 bool GoingUp = NewIdx < OldIdx;
1122 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1124 moveEnteringUpFrom(OldIdx, *EI);
1126 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1128 moveEnteringDownFrom(OldIdx, *EI);
1132 void moveInternalFrom(SlotIndex OldIdx, IntRangePair& P) {
1133 LiveInterval* LI = P.first;
1134 LiveRange* LR = P.second;
1135 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1136 LR->end <= OldIdx.getDeadSlot() &&
1137 "Range should be internal to OldIdx.");
1139 Tmp.start = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1140 Tmp.valno->def = Tmp.start;
1141 Tmp.end = LR->end.isDead() ? NewIdx.getDeadSlot() : NewIdx.getRegSlot();
1142 LI->removeRange(*LR);
1146 void moveAllInternalFrom(SlotIndex OldIdx, RangeSet& Internal) {
1147 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1149 moveInternalFrom(OldIdx, *II);
1152 void moveExitingFrom(SlotIndex OldIdx, IntRangePair& P) {
1153 LiveRange* LR = P.second;
1154 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1155 "Range should start in OldIdx.");
1156 assert(LR->end > OldIdx.getDeadSlot() && "Range should exit OldIdx.");
1157 SlotIndex NewStart = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1158 LR->start = NewStart;
1159 LR->valno->def = NewStart;
1162 void moveAllExitingFrom(SlotIndex OldIdx, RangeSet& Exiting) {
1163 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1165 moveExitingFrom(OldIdx, *EI);
1168 void moveEnteringUpFromInto(SlotIndex OldIdx, IntRangePair& P,
1170 LiveInterval* LI = P.first;
1171 LiveRange* LR = P.second;
1172 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1174 assert((LR->start < NewIdx || BR[LI->reg].Def == LR) &&
1175 "Def in bundle should be def range.");
1176 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1177 "If bundle has use for this reg it should be LR.");
1178 BR[LI->reg].Use = LR;
1182 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1183 moveKillFlags(LI->reg, OldIdx, LastUse);
1185 if (LR->start < NewIdx) {
1186 // Becoming a new entering range.
1187 assert(BR[LI->reg].Dead == 0 && BR[LI->reg].Def == 0 &&
1188 "Bundle shouldn't be re-defining reg mid-range.");
1189 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1190 "Bundle shouldn't have different use range for same reg.");
1191 LR->end = LastUse.getRegSlot();
1192 BR[LI->reg].Use = LR;
1194 // Becoming a new Dead-def.
1195 assert(LR->start == NewIdx.getRegSlot(LR->start.isEarlyClobber()) &&
1196 "Live range starting at unexpected slot.");
1197 assert(BR[LI->reg].Def == LR && "Reg should have def range.");
1198 assert(BR[LI->reg].Dead == 0 &&
1199 "Can't have def and dead def of same reg in a bundle.");
1200 LR->end = LastUse.getDeadSlot();
1201 BR[LI->reg].Dead = BR[LI->reg].Def;
1202 BR[LI->reg].Def = 0;
1206 void moveEnteringDownFromInto(SlotIndex OldIdx, IntRangePair& P,
1208 LiveInterval* LI = P.first;
1209 LiveRange* LR = P.second;
1210 if (NewIdx > LR->end) {
1211 // Range extended to bundle. Add to bundle uses.
1212 // Note: Currently adds kill flags to bundle start.
1213 assert(BR[LI->reg].Use == 0 &&
1214 "Bundle already has use range for reg.");
1215 moveKillFlags(LI->reg, LR->end, NewIdx);
1216 LR->end = NewIdx.getRegSlot();
1217 BR[LI->reg].Use = LR;
1219 assert(BR[LI->reg].Use != 0 &&
1220 "Bundle should already have a use range for reg.");
1224 void moveAllEnteringFromInto(SlotIndex OldIdx, RangeSet& Entering,
1226 bool GoingUp = NewIdx < OldIdx;
1229 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1231 moveEnteringUpFromInto(OldIdx, *EI, BR);
1233 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1235 moveEnteringDownFromInto(OldIdx, *EI, BR);
1239 void moveInternalFromInto(SlotIndex OldIdx, IntRangePair& P,
1241 // TODO: Sane rules for moving ranges into bundles.
1244 void moveAllInternalFromInto(SlotIndex OldIdx, RangeSet& Internal,
1246 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1248 moveInternalFromInto(OldIdx, *II, BR);
1251 void moveExitingFromInto(SlotIndex OldIdx, IntRangePair& P,
1253 LiveInterval* LI = P.first;
1254 LiveRange* LR = P.second;
1256 assert(LR->start.isRegister() &&
1257 "Don't know how to merge exiting ECs into bundles yet.");
1259 if (LR->end > NewIdx.getDeadSlot()) {
1260 // This range is becoming an exiting range on the bundle.
1261 // If there was an old dead-def of this reg, delete it.
1262 if (BR[LI->reg].Dead != 0) {
1263 LI->removeRange(*BR[LI->reg].Dead);
1264 BR[LI->reg].Dead = 0;
1266 assert(BR[LI->reg].Def == 0 &&
1267 "Can't have two defs for the same variable exiting a bundle.");
1268 LR->start = NewIdx.getRegSlot();
1269 LR->valno->def = LR->start;
1270 BR[LI->reg].Def = LR;
1272 // This range is becoming internal to the bundle.
1273 assert(LR->end == NewIdx.getRegSlot() &&
1274 "Can't bundle def whose kill is before the bundle");
1275 if (BR[LI->reg].Dead || BR[LI->reg].Def) {
1276 // Already have a def for this. Just delete range.
1277 LI->removeRange(*LR);
1279 // Make range dead, record.
1280 LR->end = NewIdx.getDeadSlot();
1281 BR[LI->reg].Dead = LR;
1282 assert(BR[LI->reg].Use == LR &&
1283 "Range becoming dead should currently be use.");
1285 // In both cases the range is no longer a use on the bundle.
1286 BR[LI->reg].Use = 0;
1290 void moveAllExitingFromInto(SlotIndex OldIdx, RangeSet& Exiting,
1292 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1294 moveExitingFromInto(OldIdx, *EI, BR);
1299 void LiveIntervals::handleMove(MachineInstr* MI) {
1300 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1301 Indexes->removeMachineInstrFromMaps(MI);
1302 SlotIndex NewIndex = MI->isInsideBundle() ?
1303 Indexes->getInstructionIndex(MI) :
1304 Indexes->insertMachineInstrInMaps(MI);
1305 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1306 OldIndex < getMBBEndIdx(MI->getParent()) &&
1307 "Cannot handle moves across basic block boundaries.");
1308 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1310 HMEditor HME(*this, *MRI, *TRI, NewIndex);
1311 HME.moveAllRangesFrom(MI, OldIndex);
1314 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1315 MachineInstr* BundleStart) {
1316 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1317 HMEditor HME(*this, *MRI, *TRI, NewIndex);
1318 HME.moveAllRangesInto(MI, BundleStart);