1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "liveintervals"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "VirtRegMap.h"
21 #include "llvm/Value.h"
22 #include "llvm/Analysis/LoopInfo.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/MRegisterInfo.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
41 RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis");
43 static Statistic<> numIntervals
44 ("liveintervals", "Number of original intervals");
46 static Statistic<> numIntervalsAfter
47 ("liveintervals", "Number of intervals after coalescing");
49 static Statistic<> numJoins
50 ("liveintervals", "Number of interval joins performed");
52 static Statistic<> numPeep
53 ("liveintervals", "Number of identity moves eliminated after coalescing");
55 static Statistic<> numFolded
56 ("liveintervals", "Number of loads/stores folded into instructions");
59 EnableJoining("join-liveintervals",
60 cl::desc("Join compatible live intervals"),
64 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
65 AU.addRequired<LiveVariables>();
66 AU.addPreservedID(PHIEliminationID);
67 AU.addRequiredID(PHIEliminationID);
68 AU.addRequiredID(TwoAddressInstructionPassID);
69 AU.addRequired<LoopInfo>();
70 MachineFunctionPass::getAnalysisUsage(AU);
73 void LiveIntervals::releaseMemory() {
81 static bool isZeroLengthInterval(LiveInterval *li) {
82 for (LiveInterval::Ranges::const_iterator
83 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
84 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
90 /// runOnMachineFunction - Register allocate the whole function
92 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
94 tm_ = &fn.getTarget();
95 mri_ = tm_->getRegisterInfo();
96 tii_ = tm_->getInstrInfo();
97 lv_ = &getAnalysis<LiveVariables>();
98 allocatableRegs_ = mri_->getAllocatableSet(fn);
99 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
101 // If this function has any live ins, insert a dummy instruction at the
102 // beginning of the function that we will pretend "defines" the values. This
103 // is to make the interval analysis simpler by providing a number.
104 if (fn.livein_begin() != fn.livein_end()) {
105 unsigned FirstLiveIn = fn.livein_begin()->first;
107 // Find a reg class that contains this live in.
108 const TargetRegisterClass *RC = 0;
109 for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(),
110 E = mri_->regclass_end(); RCI != E; ++RCI)
111 if ((*RCI)->contains(FirstLiveIn)) {
116 MachineInstr *OldFirstMI = fn.begin()->begin();
117 mri_->copyRegToReg(*fn.begin(), fn.begin()->begin(),
118 FirstLiveIn, FirstLiveIn, RC);
119 assert(OldFirstMI != fn.begin()->begin() &&
120 "copyRetToReg didn't insert anything!");
123 // number MachineInstrs
124 unsigned miIndex = 0;
125 for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end();
126 mbb != mbbEnd; ++mbb)
127 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
129 bool inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second;
130 assert(inserted && "multiple MachineInstr -> index mappings");
131 i2miMap_.push_back(mi);
132 miIndex += InstrSlots::NUM;
135 // Note intervals due to live-in values.
136 if (fn.livein_begin() != fn.livein_end()) {
137 MachineBasicBlock *Entry = fn.begin();
138 for (MachineFunction::livein_iterator I = fn.livein_begin(),
139 E = fn.livein_end(); I != E; ++I) {
140 handlePhysicalRegisterDef(Entry, Entry->begin(), 0,
141 getOrCreateInterval(I->first), 0);
142 for (const unsigned* AS = mri_->getAliasSet(I->first); *AS; ++AS)
143 handlePhysicalRegisterDef(Entry, Entry->begin(), 0,
144 getOrCreateInterval(*AS), 0);
150 numIntervals += getNumIntervals();
152 DEBUG(std::cerr << "********** INTERVALS **********\n";
153 for (iterator I = begin(), E = end(); I != E; ++I) {
154 I->second.print(std::cerr, mri_);
158 // join intervals if requested
159 if (EnableJoining) joinIntervals();
161 numIntervalsAfter += getNumIntervals();
163 // perform a final pass over the instructions and compute spill
164 // weights, coalesce virtual registers and remove identity moves.
165 const LoopInfo& loopInfo = getAnalysis<LoopInfo>();
167 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
168 mbbi != mbbe; ++mbbi) {
169 MachineBasicBlock* mbb = mbbi;
170 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
172 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
174 // if the move will be an identity move delete it
175 unsigned srcReg, dstReg, RegRep;
176 if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
177 (RegRep = rep(srcReg)) == rep(dstReg)) {
178 // remove from def list
179 LiveInterval &interval = getOrCreateInterval(RegRep);
180 RemoveMachineInstrFromMaps(mii);
181 mii = mbbi->erase(mii);
185 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
186 const MachineOperand &mop = mii->getOperand(i);
187 if (mop.isRegister() && mop.getReg() &&
188 MRegisterInfo::isVirtualRegister(mop.getReg())) {
189 // replace register with representative register
190 unsigned reg = rep(mop.getReg());
191 mii->getOperand(i).setReg(reg);
193 LiveInterval &RegInt = getInterval(reg);
195 (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth);
203 for (iterator I = begin(), E = end(); I != E; ++I) {
204 LiveInterval &li = I->second;
205 if (MRegisterInfo::isVirtualRegister(li.reg)) {
206 // If the live interval length is essentially zero, i.e. in every live
207 // range the use follows def immediately, it doesn't make sense to spill
208 // it and hope it will be easier to allocate for this li.
209 if (isZeroLengthInterval(&li))
210 li.weight = float(HUGE_VAL);
218 /// print - Implement the dump method.
219 void LiveIntervals::print(std::ostream &O, const Module* ) const {
220 O << "********** INTERVALS **********\n";
221 for (const_iterator I = begin(), E = end(); I != E; ++I) {
222 I->second.print(std::cerr, mri_);
226 O << "********** MACHINEINSTRS **********\n";
227 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
228 mbbi != mbbe; ++mbbi) {
229 O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
230 for (MachineBasicBlock::iterator mii = mbbi->begin(),
231 mie = mbbi->end(); mii != mie; ++mii) {
232 O << getInstructionIndex(mii) << '\t' << *mii;
237 std::vector<LiveInterval*> LiveIntervals::
238 addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
239 // since this is called after the analysis is done we don't know if
240 // LiveVariables is available
241 lv_ = getAnalysisToUpdate<LiveVariables>();
243 std::vector<LiveInterval*> added;
245 assert(li.weight != HUGE_VAL &&
246 "attempt to spill already spilled interval!");
248 DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: ";
249 li.print(std::cerr, mri_); std::cerr << '\n');
251 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
253 for (LiveInterval::Ranges::const_iterator
254 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
255 unsigned index = getBaseIndex(i->start);
256 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM;
257 for (; index != end; index += InstrSlots::NUM) {
258 // skip deleted instructions
259 while (index != end && !getInstructionFromIndex(index))
260 index += InstrSlots::NUM;
261 if (index == end) break;
263 MachineInstr *MI = getInstructionFromIndex(index);
265 // NewRegLiveIn - This instruction might have multiple uses of the spilled
266 // register. In this case, for the first use, keep track of the new vreg
267 // that we reload it into. If we see a second use, reuse this vreg
268 // instead of creating live ranges for two reloads.
269 unsigned NewRegLiveIn = 0;
272 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
273 MachineOperand& mop = MI->getOperand(i);
274 if (mop.isRegister() && mop.getReg() == li.reg) {
275 if (NewRegLiveIn && mop.isUse()) {
276 // We already emitted a reload of this value, reuse it for
277 // subsequent operands.
278 MI->getOperand(i).setReg(NewRegLiveIn);
279 DEBUG(std::cerr << "\t\t\t\treused reload into reg" << NewRegLiveIn
280 << " for operand #" << i << '\n');
281 } else if (MachineInstr* fmi = mri_->foldMemoryOperand(MI, i, slot)) {
282 // Attempt to fold the memory reference into the instruction. If we
283 // can do this, we don't need to insert spill code.
285 lv_->instructionChanged(MI, fmi);
286 MachineBasicBlock &MBB = *MI->getParent();
287 vrm.virtFolded(li.reg, MI, i, fmi);
289 i2miMap_[index/InstrSlots::NUM] = fmi;
290 mi2iMap_[fmi] = index;
291 MI = MBB.insert(MBB.erase(MI), fmi);
293 // Folding the load/store can completely change the instruction in
294 // unpredictable ways, rescan it from the beginning.
297 // This is tricky. We need to add information in the interval about
298 // the spill code so we have to use our extra load/store slots.
300 // If we have a use we are going to have a load so we start the
301 // interval from the load slot onwards. Otherwise we start from the
303 unsigned start = (mop.isUse() ?
304 getLoadIndex(index) :
306 // If we have a def we are going to have a store right after it so
307 // we end the interval after the use of the next
308 // instruction. Otherwise we end after the use of this instruction.
309 unsigned end = 1 + (mop.isDef() ?
310 getStoreIndex(index) :
313 // create a new register for this spill
314 NewRegLiveIn = mf_->getSSARegMap()->createVirtualRegister(rc);
315 MI->getOperand(i).setReg(NewRegLiveIn);
317 vrm.assignVirt2StackSlot(NewRegLiveIn, slot);
318 LiveInterval& nI = getOrCreateInterval(NewRegLiveIn);
321 // the spill weight is now infinity as it
322 // cannot be spilled again
323 nI.weight = float(HUGE_VAL);
324 LiveRange LR(start, end, nI.getNextValue(~0U, 0));
325 DEBUG(std::cerr << " +" << LR);
327 added.push_back(&nI);
329 // update live variables if it is available
331 lv_->addVirtualRegisterKilled(NewRegLiveIn, MI);
333 // If this is a live in, reuse it for subsequent live-ins. If it's
334 // a def, we can't do this.
335 if (!mop.isUse()) NewRegLiveIn = 0;
337 DEBUG(std::cerr << "\t\t\t\tadded new interval: ";
338 nI.print(std::cerr, mri_); std::cerr << '\n');
348 void LiveIntervals::printRegName(unsigned reg) const {
349 if (MRegisterInfo::isPhysicalRegister(reg))
350 std::cerr << mri_->getName(reg);
352 std::cerr << "%reg" << reg;
355 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
356 MachineBasicBlock::iterator mi,
358 LiveInterval &interval) {
359 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
360 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
362 // Virtual registers may be defined multiple times (due to phi
363 // elimination and 2-addr elimination). Much of what we do only has to be
364 // done once for the vreg. We use an empty interval to detect the first
365 // time we see a vreg.
366 if (interval.empty()) {
367 // Get the Idx of the defining instructions.
368 unsigned defIndex = getDefIndex(MIIdx);
371 unsigned SrcReg, DstReg;
372 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
373 ValNum = interval.getNextValue(~0U, 0);
375 ValNum = interval.getNextValue(defIndex, SrcReg);
377 assert(ValNum == 0 && "First value in interval is not 0?");
378 ValNum = 0; // Clue in the optimizer.
380 // Loop over all of the blocks that the vreg is defined in. There are
381 // two cases we have to handle here. The most common case is a vreg
382 // whose lifetime is contained within a basic block. In this case there
383 // will be a single kill, in MBB, which comes after the definition.
384 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
385 // FIXME: what about dead vars?
387 if (vi.Kills[0] != mi)
388 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
390 killIdx = defIndex+1;
392 // If the kill happens after the definition, we have an intra-block
394 if (killIdx > defIndex) {
395 assert(vi.AliveBlocks.empty() &&
396 "Shouldn't be alive across any blocks!");
397 LiveRange LR(defIndex, killIdx, ValNum);
398 interval.addRange(LR);
399 DEBUG(std::cerr << " +" << LR << "\n");
404 // The other case we handle is when a virtual register lives to the end
405 // of the defining block, potentially live across some blocks, then is
406 // live into some number of blocks, but gets killed. Start by adding a
407 // range that goes from this definition to the end of the defining block.
408 LiveRange NewLR(defIndex,
409 getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
411 DEBUG(std::cerr << " +" << NewLR);
412 interval.addRange(NewLR);
414 // Iterate over all of the blocks that the variable is completely
415 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
417 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
418 if (vi.AliveBlocks[i]) {
419 MachineBasicBlock* mbb = mf_->getBlockNumbered(i);
421 LiveRange LR(getInstructionIndex(&mbb->front()),
422 getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
424 interval.addRange(LR);
425 DEBUG(std::cerr << " +" << LR);
430 // Finally, this virtual register is live from the start of any killing
431 // block to the 'use' slot of the killing instruction.
432 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
433 MachineInstr *Kill = vi.Kills[i];
434 LiveRange LR(getInstructionIndex(Kill->getParent()->begin()),
435 getUseIndex(getInstructionIndex(Kill))+1,
437 interval.addRange(LR);
438 DEBUG(std::cerr << " +" << LR);
442 // If this is the second time we see a virtual register definition, it
443 // must be due to phi elimination or two addr elimination. If this is
444 // the result of two address elimination, then the vreg is the first
445 // operand, and is a def-and-use.
446 if (mi->getOperand(0).isRegister() &&
447 mi->getOperand(0).getReg() == interval.reg &&
448 mi->getOperand(0).isDef() && mi->getOperand(0).isUse()) {
449 // If this is a two-address definition, then we have already processed
450 // the live range. The only problem is that we didn't realize there
451 // are actually two values in the live interval. Because of this we
452 // need to take the LiveRegion that defines this register and split it
454 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst));
455 unsigned RedefIndex = getDefIndex(MIIdx);
457 // Delete the initial value, which should be short and continuous,
458 // because the 2-addr copy must be in the same MBB as the redef.
459 interval.removeRange(DefIndex, RedefIndex);
461 // Two-address vregs should always only be redefined once. This means
462 // that at this point, there should be exactly one value number in it.
463 assert(interval.containsOneValue() && "Unexpected 2-addr liveint!");
465 // The new value number (#1) is defined by the instruction we claimed
467 unsigned ValNo = interval.getNextValue(0, 0);
468 interval.setValueNumberInfo(1, interval.getValNumInfo(0));
470 // Value#0 is now defined by the 2-addr instruction.
471 interval.setValueNumberInfo(0, std::make_pair(~0U, 0U));
473 // Add the new live interval which replaces the range for the input copy.
474 LiveRange LR(DefIndex, RedefIndex, ValNo);
475 DEBUG(std::cerr << " replace range with " << LR);
476 interval.addRange(LR);
478 // If this redefinition is dead, we need to add a dummy unit live
479 // range covering the def slot.
480 if (lv_->RegisterDefIsDead(mi, interval.reg))
481 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
483 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_));
486 // Otherwise, this must be because of phi elimination. If this is the
487 // first redefinition of the vreg that we have seen, go back and change
488 // the live range in the PHI block to be a different value number.
489 if (interval.containsOneValue()) {
490 assert(vi.Kills.size() == 1 &&
491 "PHI elimination vreg should have one kill, the PHI itself!");
493 // Remove the old range that we now know has an incorrect number.
494 MachineInstr *Killer = vi.Kills[0];
495 unsigned Start = getInstructionIndex(Killer->getParent()->begin());
496 unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
497 DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: ";
498 interval.print(std::cerr, mri_); std::cerr << "\n");
499 interval.removeRange(Start, End);
500 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_));
502 // Replace the interval with one of a NEW value number. Note that this
503 // value number isn't actually defined by an instruction, weird huh? :)
504 LiveRange LR(Start, End, interval.getNextValue(~0U, 0));
505 DEBUG(std::cerr << " replace range with " << LR);
506 interval.addRange(LR);
507 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_));
510 // In the case of PHI elimination, each variable definition is only
511 // live until the end of the block. We've already taken care of the
512 // rest of the live range.
513 unsigned defIndex = getDefIndex(MIIdx);
516 unsigned SrcReg, DstReg;
517 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
518 ValNum = interval.getNextValue(~0U, 0);
520 ValNum = interval.getNextValue(defIndex, SrcReg);
522 LiveRange LR(defIndex,
523 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, ValNum);
524 interval.addRange(LR);
525 DEBUG(std::cerr << " +" << LR);
529 DEBUG(std::cerr << '\n');
532 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
533 MachineBasicBlock::iterator mi,
535 LiveInterval &interval,
537 // A physical register cannot be live across basic block, so its
538 // lifetime must end somewhere in its defining basic block.
539 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
540 typedef LiveVariables::killed_iterator KillIter;
542 unsigned baseIndex = MIIdx;
543 unsigned start = getDefIndex(baseIndex);
544 unsigned end = start;
546 // If it is not used after definition, it is considered dead at
547 // the instruction defining it. Hence its interval is:
548 // [defSlot(def), defSlot(def)+1)
549 if (lv_->RegisterDefIsDead(mi, interval.reg)) {
550 DEBUG(std::cerr << " dead");
551 end = getDefIndex(start) + 1;
555 // If it is not dead on definition, it must be killed by a
556 // subsequent instruction. Hence its interval is:
557 // [defSlot(def), useSlot(kill)+1)
558 while (++mi != MBB->end()) {
559 baseIndex += InstrSlots::NUM;
560 if (lv_->KillsRegister(mi, interval.reg)) {
561 DEBUG(std::cerr << " killed");
562 end = getUseIndex(baseIndex) + 1;
567 // The only case we should have a dead physreg here without a killing or
568 // instruction where we know it's dead is if it is live-in to the function
570 assert(!SrcReg && "physreg was not killed in defining block!");
571 end = getDefIndex(start) + 1; // It's dead.
574 assert(start < end && "did not find end of interval?");
576 LiveRange LR(start, end, interval.getNextValue(SrcReg != 0 ? start : ~0U,
578 interval.addRange(LR);
579 DEBUG(std::cerr << " +" << LR << '\n');
582 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
583 MachineBasicBlock::iterator MI,
586 if (MRegisterInfo::isVirtualRegister(reg))
587 handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg));
588 else if (allocatableRegs_[reg]) {
589 unsigned SrcReg, DstReg;
590 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg))
592 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg);
593 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS)
594 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
598 /// computeIntervals - computes the live intervals for virtual
599 /// registers. for some ordering of the machine instructions [1,N] a
600 /// live interval is an interval [i, j) where 1 <= i <= j < N for
601 /// which a variable is live
602 void LiveIntervals::computeIntervals() {
603 DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n");
604 DEBUG(std::cerr << "********** Function: "
605 << ((Value*)mf_->getFunction())->getName() << '\n');
606 bool IgnoreFirstInstr = mf_->livein_begin() != mf_->livein_end();
608 // Track the index of the current machine instr.
609 unsigned MIIndex = 0;
610 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
612 MachineBasicBlock* mbb = I;
613 DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n");
615 MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
616 if (IgnoreFirstInstr) {
618 IgnoreFirstInstr = false;
619 MIIndex += InstrSlots::NUM;
622 for (; mi != miEnd; ++mi) {
623 const TargetInstrDescriptor& tid =
624 tm_->getInstrInfo()->get(mi->getOpcode());
625 DEBUG(std::cerr << MIIndex << "\t" << *mi);
627 // handle implicit defs
628 if (tid.ImplicitDefs) {
629 for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
630 handleRegisterDef(mbb, mi, MIIndex, *id);
633 // handle explicit defs
634 for (int i = mi->getNumOperands() - 1; i >= 0; --i) {
635 MachineOperand& mop = mi->getOperand(i);
636 // handle register defs - build intervals
637 if (mop.isRegister() && mop.getReg() && mop.isDef())
638 handleRegisterDef(mbb, mi, MIIndex, mop.getReg());
641 MIIndex += InstrSlots::NUM;
646 /// AdjustCopiesBackFrom - We found a non-trivially-coallescable copy with IntA
647 /// being the source and IntB being the dest, thus this defines a value number
648 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
649 /// see if we can merge these two pieces of B into a single value number,
650 /// eliminating a copy. For example:
654 /// B1 = A3 <- this copy
656 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
657 /// value number to be replaced with B0 (which simplifies the B liveinterval).
659 /// This returns true if an interval was modified.
661 bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
662 MachineInstr *CopyMI) {
663 unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI));
665 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
666 // the example above.
667 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
668 unsigned BValNo = BLR->ValId;
670 // Get the location that B is defined at. Two options: either this value has
671 // an unknown definition point or it is defined at CopyIdx. If unknown, we
673 unsigned BValNoDefIdx = IntB.getInstForValNum(BValNo);
674 if (BValNoDefIdx == ~0U) return false;
675 assert(BValNoDefIdx == CopyIdx &&
676 "Copy doesn't define the value?");
678 // AValNo is the value number in A that defines the copy, A0 in the example.
679 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1);
680 unsigned AValNo = AValLR->ValId;
682 // If AValNo is defined as a copy from IntB, we can potentially process this.
684 // Get the instruction that defines this value number.
685 unsigned SrcReg = IntA.getSrcRegForValNum(AValNo);
686 if (!SrcReg) return false; // Not defined by a copy.
688 // If the value number is not defined by a copy instruction, ignore it.
690 // If the source register comes from an interval other than IntB, we can't
692 if (rep(SrcReg) != IntB.reg) return false;
694 // Get the LiveRange in IntB that this value number starts with.
695 unsigned AValNoInstIdx = IntA.getInstForValNum(AValNo);
696 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNoInstIdx-1);
698 // Make sure that the end of the live range is inside the same block as
700 MachineInstr *ValLREndInst = getInstructionFromIndex(ValLR->end-1);
702 ValLREndInst->getParent() != CopyMI->getParent()) return false;
704 // Okay, we now know that ValLR ends in the same block that the CopyMI
705 // live-range starts. If there are no intervening live ranges between them in
706 // IntB, we can merge them.
707 if (ValLR+1 != BLR) return false;
709 DEBUG(std::cerr << "\nExtending: "; IntB.print(std::cerr, mri_));
711 // We are about to delete CopyMI, so need to remove it as the 'instruction
712 // that defines this value #'.
713 IntB.setValueNumberInfo(BValNo, std::make_pair(~0U, 0));
715 // Okay, we can merge them. We need to insert a new liverange:
716 // [ValLR.end, BLR.begin) of either value number, then we merge the
717 // two value numbers.
718 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
719 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
721 // If the IntB live range is assigned to a physical register, and if that
722 // physreg has aliases,
723 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) {
724 for (const unsigned *AS = mri_->getAliasSet(IntB.reg); *AS; ++AS) {
725 LiveInterval &AliasLI = getInterval(*AS);
726 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
727 AliasLI.getNextValue(~0U, 0)));
731 // Okay, merge "B1" into the same value number as "B0".
732 if (BValNo != ValLR->ValId)
733 IntB.MergeValueNumberInto(BValNo, ValLR->ValId);
734 DEBUG(std::cerr << " result = "; IntB.print(std::cerr, mri_);
737 // Finally, delete the copy instruction.
738 RemoveMachineInstrFromMaps(CopyMI);
739 CopyMI->eraseFromParent();
745 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
746 /// which are the src/dst of the copy instruction CopyMI. This returns true
747 /// if the copy was successfully coallesced away, or if it is never possible
748 /// to coallesce these this copy, due to register constraints. It returns
749 /// false if it is not currently possible to coallesce this interval, but
750 /// it may be possible if other things get coallesced.
751 bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
752 unsigned SrcReg, unsigned DstReg) {
755 DEBUG(std::cerr << getInstructionIndex(CopyMI) << '\t' << *CopyMI);
757 // Get representative registers.
758 SrcReg = rep(SrcReg);
759 DstReg = rep(DstReg);
761 // If they are already joined we continue.
762 if (SrcReg == DstReg) {
763 DEBUG(std::cerr << "\tCopy already coallesced.\n");
764 return true; // Not coallescable.
767 // If they are both physical registers, we cannot join them.
768 if (MRegisterInfo::isPhysicalRegister(SrcReg) &&
769 MRegisterInfo::isPhysicalRegister(DstReg)) {
770 DEBUG(std::cerr << "\tCan not coallesce physregs.\n");
771 return true; // Not coallescable.
774 // We only join virtual registers with allocatable physical registers.
775 if (MRegisterInfo::isPhysicalRegister(SrcReg) && !allocatableRegs_[SrcReg]){
776 DEBUG(std::cerr << "\tSrc reg is unallocatable physreg.\n");
777 return true; // Not coallescable.
779 if (MRegisterInfo::isPhysicalRegister(DstReg) && !allocatableRegs_[DstReg]){
780 DEBUG(std::cerr << "\tDst reg is unallocatable physreg.\n");
781 return true; // Not coallescable.
784 // If they are not of the same register class, we cannot join them.
785 if (differingRegisterClasses(SrcReg, DstReg)) {
786 DEBUG(std::cerr << "\tSrc/Dest are different register classes.\n");
787 return true; // Not coallescable.
790 LiveInterval &SrcInt = getInterval(SrcReg);
791 LiveInterval &DestInt = getInterval(DstReg);
792 assert(SrcInt.reg == SrcReg && DestInt.reg == DstReg &&
793 "Register mapping is horribly broken!");
795 DEBUG(std::cerr << "\t\tInspecting "; SrcInt.print(std::cerr, mri_);
796 std::cerr << " and "; DestInt.print(std::cerr, mri_);
799 // Okay, attempt to join these two intervals. On failure, this returns false.
800 // Otherwise, if one of the intervals being joined is a physreg, this method
801 // always canonicalizes DestInt to be it. The output "SrcInt" will not have
802 // been modified, so we can use this information below to update aliases.
803 if (!JoinIntervals(DestInt, SrcInt)) {
804 // Coallescing failed.
806 // If we can eliminate the copy without merging the live ranges, do so now.
807 if (AdjustCopiesBackFrom(SrcInt, DestInt, CopyMI))
810 // Otherwise, we are unable to join the intervals.
811 DEBUG(std::cerr << "Interference!\n");
815 bool Swapped = SrcReg == DestInt.reg;
817 std::swap(SrcReg, DstReg);
818 assert(MRegisterInfo::isVirtualRegister(SrcReg) &&
819 "LiveInterval::join didn't work right!");
821 // If we're about to merge live ranges into a physical register live range,
822 // we have to update any aliased register's live ranges to indicate that they
823 // have clobbered values for this range.
824 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
825 for (const unsigned *AS = mri_->getAliasSet(DstReg); *AS; ++AS)
826 getInterval(*AS).MergeInClobberRanges(SrcInt);
829 DEBUG(std::cerr << "\n\t\tJoined. Result = "; DestInt.print(std::cerr, mri_);
832 // If the intervals were swapped by Join, swap them back so that the register
833 // mapping (in the r2i map) is correct.
834 if (Swapped) SrcInt.swap(DestInt);
835 r2iMap_.erase(SrcReg);
836 r2rMap_[SrcReg] = DstReg;
838 // Finally, delete the copy instruction.
839 RemoveMachineInstrFromMaps(CopyMI);
840 CopyMI->eraseFromParent();
846 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
847 /// compute what the resultant value numbers for each value in the input two
848 /// ranges will be. This is complicated by copies between the two which can
849 /// and will commonly cause multiple value numbers to be merged into one.
851 /// VN is the value number that we're trying to resolve. InstDefiningValue
852 /// keeps track of the new InstDefiningValue assignment for the result
853 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
854 /// whether a value in this or other is a copy from the opposite set.
855 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
856 /// already been assigned.
858 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
859 /// contains the value number the copy is from.
861 static unsigned ComputeUltimateVN(unsigned VN,
862 SmallVector<std::pair<unsigned,
863 unsigned>, 16> &ValueNumberInfo,
864 SmallVector<int, 16> &ThisFromOther,
865 SmallVector<int, 16> &OtherFromThis,
866 SmallVector<int, 16> &ThisValNoAssignments,
867 SmallVector<int, 16> &OtherValNoAssignments,
868 LiveInterval &ThisLI, LiveInterval &OtherLI) {
869 // If the VN has already been computed, just return it.
870 if (ThisValNoAssignments[VN] >= 0)
871 return ThisValNoAssignments[VN];
872 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
874 // If this val is not a copy from the other val, then it must be a new value
875 // number in the destination.
876 int OtherValNo = ThisFromOther[VN];
877 if (OtherValNo == -1) {
878 ValueNumberInfo.push_back(ThisLI.getValNumInfo(VN));
879 return ThisValNoAssignments[VN] = ValueNumberInfo.size()-1;
882 // Otherwise, this *is* a copy from the RHS. If the other side has already
883 // been computed, return it.
884 if (OtherValNoAssignments[OtherValNo] >= 0)
885 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo];
887 // Mark this value number as currently being computed, then ask what the
888 // ultimate value # of the other value is.
889 ThisValNoAssignments[VN] = -2;
890 unsigned UltimateVN =
891 ComputeUltimateVN(OtherValNo, ValueNumberInfo,
892 OtherFromThis, ThisFromOther,
893 OtherValNoAssignments, ThisValNoAssignments,
895 return ThisValNoAssignments[VN] = UltimateVN;
898 static bool InVector(unsigned Val, const SmallVector<unsigned, 8> &V) {
899 return std::find(V.begin(), V.end(), Val) != V.end();
902 /// SimpleJoin - Attempt to joint the specified interval into this one. The
903 /// caller of this method must guarantee that the RHS only contains a single
904 /// value number and that the RHS is not defined by a copy from this
905 /// interval. This returns false if the intervals are not joinable, or it
906 /// joins them and returns true.
907 bool LiveIntervals::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) {
908 assert(RHS.containsOneValue());
910 // Some number (potentially more than one) value numbers in the current
911 // interval may be defined as copies from the RHS. Scan the overlapping
912 // portions of the LHS and RHS, keeping track of this and looking for
913 // overlapping live ranges that are NOT defined as copies. If these exist, we
916 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
917 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
919 if (LHSIt->start < RHSIt->start) {
920 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
921 if (LHSIt != LHS.begin()) --LHSIt;
922 } else if (RHSIt->start < LHSIt->start) {
923 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
924 if (RHSIt != RHS.begin()) --RHSIt;
927 SmallVector<unsigned, 8> EliminatedLHSVals;
930 // Determine if these live intervals overlap.
931 bool Overlaps = false;
932 if (LHSIt->start <= RHSIt->start)
933 Overlaps = LHSIt->end > RHSIt->start;
935 Overlaps = RHSIt->end > LHSIt->start;
937 // If the live intervals overlap, there are two interesting cases: if the
938 // LHS interval is defined by a copy from the RHS, it's ok and we record
939 // that the LHS value # is the same as the RHS. If it's not, then we cannot
940 // coallesce these live ranges and we bail out.
942 // If we haven't already recorded that this value # is safe, check it.
943 if (!InVector(LHSIt->ValId, EliminatedLHSVals)) {
944 // Copy from the RHS?
945 unsigned SrcReg = LHS.getSrcRegForValNum(LHSIt->ValId);
946 if (rep(SrcReg) != RHS.reg)
947 return false; // Nope, bail out.
949 EliminatedLHSVals.push_back(LHSIt->ValId);
952 // We know this entire LHS live range is okay, so skip it now.
953 if (++LHSIt == LHSEnd) break;
957 if (LHSIt->end < RHSIt->end) {
958 if (++LHSIt == LHSEnd) break;
960 // One interesting case to check here. It's possible that we have
961 // something like "X3 = Y" which defines a new value number in the LHS,
962 // and is the last use of this liverange of the RHS. In this case, we
963 // want to notice this copy (so that it gets coallesced away) even though
964 // the live ranges don't actually overlap.
965 if (LHSIt->start == RHSIt->end) {
966 if (InVector(LHSIt->ValId, EliminatedLHSVals)) {
967 // We already know that this value number is going to be merged in
968 // if coallescing succeeds. Just skip the liverange.
969 if (++LHSIt == LHSEnd) break;
971 // Otherwise, if this is a copy from the RHS, mark it as being merged
973 if (rep(LHS.getSrcRegForValNum(LHSIt->ValId)) == RHS.reg) {
974 EliminatedLHSVals.push_back(LHSIt->ValId);
976 // We know this entire LHS live range is okay, so skip it now.
977 if (++LHSIt == LHSEnd) break;
982 if (++RHSIt == RHSEnd) break;
986 // If we got here, we know that the coallescing will be successful and that
987 // the value numbers in EliminatedLHSVals will all be merged together. Since
988 // the most common case is that EliminatedLHSVals has a single number, we
989 // optimize for it: if there is more than one value, we merge them all into
990 // the lowest numbered one, then handle the interval as if we were merging
991 // with one value number.
993 if (EliminatedLHSVals.size() > 1) {
994 // Loop through all the equal value numbers merging them into the smallest
996 unsigned Smallest = EliminatedLHSVals[0];
997 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
998 if (EliminatedLHSVals[i] < Smallest) {
999 // Merge the current notion of the smallest into the smaller one.
1000 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
1001 Smallest = EliminatedLHSVals[i];
1003 // Merge into the smallest.
1004 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
1007 LHSValNo = Smallest;
1009 assert(!EliminatedLHSVals.empty() && "No copies from the RHS?");
1010 LHSValNo = EliminatedLHSVals[0];
1013 // Okay, now that there is a single LHS value number that we're merging the
1014 // RHS into, update the value number info for the LHS to indicate that the
1015 // value number is defined where the RHS value number was.
1016 LHS.setValueNumberInfo(LHSValNo, RHS.getValNumInfo(0));
1018 // Okay, the final step is to loop over the RHS live intervals, adding them to
1020 LHS.MergeRangesInAsValue(RHS, LHSValNo);
1021 LHS.weight += RHS.weight;
1026 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1027 /// returns false. Otherwise, if one of the intervals being joined is a
1028 /// physreg, this method always canonicalizes LHS to be it. The output
1029 /// "RHS" will not have been modified, so we can use this information
1030 /// below to update aliases.
1031 bool LiveIntervals::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS) {
1032 // Compute the final value assignment, assuming that the live ranges can be
1034 SmallVector<int, 16> LHSValNoAssignments;
1035 SmallVector<int, 16> RHSValNoAssignments;
1036 SmallVector<std::pair<unsigned,unsigned>, 16> ValueNumberInfo;
1038 // Compute ultimate value numbers for the LHS and RHS values.
1039 if (RHS.containsOneValue()) {
1040 // Copies from a liveinterval with a single value are simple to handle and
1041 // very common, handle the special case here. This is important, because
1042 // often RHS is small and LHS is large (e.g. a physreg).
1044 // Find out if the RHS is defined as a copy from some value in the LHS.
1046 std::pair<unsigned,unsigned> RHSValNoInfo;
1047 unsigned RHSSrcReg = RHS.getSrcRegForValNum(0);
1048 if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) {
1049 // If RHS is not defined as a copy from the LHS, we can use simpler and
1050 // faster checks to see if the live ranges are coallescable. This joiner
1051 // can't swap the LHS/RHS intervals though.
1052 if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) {
1053 return SimpleJoin(LHS, RHS);
1055 RHSValNoInfo = RHS.getValNumInfo(0);
1058 // It was defined as a copy from the LHS, find out what value # it is.
1059 unsigned ValInst = RHS.getInstForValNum(0);
1060 RHSValID = LHS.getLiveRangeContaining(ValInst-1)->ValId;
1061 RHSValNoInfo = LHS.getValNumInfo(RHSValID);
1064 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1065 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1066 ValueNumberInfo.resize(LHS.getNumValNums());
1068 // Okay, *all* of the values in LHS that are defined as a copy from RHS
1069 // should now get updated.
1070 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1071 if (unsigned LHSSrcReg = LHS.getSrcRegForValNum(VN)) {
1072 if (rep(LHSSrcReg) != RHS.reg) {
1073 // If this is not a copy from the RHS, its value number will be
1074 // unmodified by the coallescing.
1075 ValueNumberInfo[VN] = LHS.getValNumInfo(VN);
1076 LHSValNoAssignments[VN] = VN;
1077 } else if (RHSValID == -1) {
1078 // Otherwise, it is a copy from the RHS, and we don't already have a
1079 // value# for it. Keep the current value number, but remember it.
1080 LHSValNoAssignments[VN] = RHSValID = VN;
1081 ValueNumberInfo[VN] = RHSValNoInfo;
1083 // Otherwise, use the specified value #.
1084 LHSValNoAssignments[VN] = RHSValID;
1085 if (VN != (unsigned)RHSValID)
1086 ValueNumberInfo[VN].first = ~1U;
1088 ValueNumberInfo[VN] = RHSValNoInfo;
1091 ValueNumberInfo[VN] = LHS.getValNumInfo(VN);
1092 LHSValNoAssignments[VN] = VN;
1096 assert(RHSValID != -1 && "Didn't find value #?");
1097 RHSValNoAssignments[0] = RHSValID;
1100 // Loop over the value numbers of the LHS, seeing if any are defined from
1102 SmallVector<int, 16> LHSValsDefinedFromRHS;
1103 LHSValsDefinedFromRHS.resize(LHS.getNumValNums(), -1);
1104 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1105 unsigned ValSrcReg = LHS.getSrcRegForValNum(VN);
1106 if (ValSrcReg == 0) // Src not defined by a copy?
1109 // DstReg is known to be a register in the LHS interval. If the src is
1110 // from the RHS interval, we can use its value #.
1111 if (rep(ValSrcReg) != RHS.reg)
1114 // Figure out the value # from the RHS.
1115 unsigned ValInst = LHS.getInstForValNum(VN);
1116 LHSValsDefinedFromRHS[VN] = RHS.getLiveRangeContaining(ValInst-1)->ValId;
1119 // Loop over the value numbers of the RHS, seeing if any are defined from
1121 SmallVector<int, 16> RHSValsDefinedFromLHS;
1122 RHSValsDefinedFromLHS.resize(RHS.getNumValNums(), -1);
1123 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) {
1124 unsigned ValSrcReg = RHS.getSrcRegForValNum(VN);
1125 if (ValSrcReg == 0) // Src not defined by a copy?
1128 // DstReg is known to be a register in the RHS interval. If the src is
1129 // from the LHS interval, we can use its value #.
1130 if (rep(ValSrcReg) != LHS.reg)
1133 // Figure out the value # from the LHS.
1134 unsigned ValInst = RHS.getInstForValNum(VN);
1135 RHSValsDefinedFromLHS[VN] = LHS.getLiveRangeContaining(ValInst-1)->ValId;
1138 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1139 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1140 ValueNumberInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1142 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) {
1143 if (LHSValNoAssignments[VN] >= 0 || LHS.getInstForValNum(VN) == ~2U)
1145 ComputeUltimateVN(VN, ValueNumberInfo,
1146 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1147 LHSValNoAssignments, RHSValNoAssignments, LHS, RHS);
1149 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) {
1150 if (RHSValNoAssignments[VN] >= 0 || RHS.getInstForValNum(VN) == ~2U)
1152 // If this value number isn't a copy from the LHS, it's a new number.
1153 if (RHSValsDefinedFromLHS[VN] == -1) {
1154 ValueNumberInfo.push_back(RHS.getValNumInfo(VN));
1155 RHSValNoAssignments[VN] = ValueNumberInfo.size()-1;
1159 ComputeUltimateVN(VN, ValueNumberInfo,
1160 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1161 RHSValNoAssignments, LHSValNoAssignments, RHS, LHS);
1165 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1166 // interval lists to see if these intervals are coallescable.
1167 LiveInterval::const_iterator I = LHS.begin();
1168 LiveInterval::const_iterator IE = LHS.end();
1169 LiveInterval::const_iterator J = RHS.begin();
1170 LiveInterval::const_iterator JE = RHS.end();
1172 // Skip ahead until the first place of potential sharing.
1173 if (I->start < J->start) {
1174 I = std::upper_bound(I, IE, J->start);
1175 if (I != LHS.begin()) --I;
1176 } else if (J->start < I->start) {
1177 J = std::upper_bound(J, JE, I->start);
1178 if (J != RHS.begin()) --J;
1182 // Determine if these two live ranges overlap.
1184 if (I->start < J->start) {
1185 Overlaps = I->end > J->start;
1187 Overlaps = J->end > I->start;
1190 // If so, check value # info to determine if they are really different.
1192 // If the live range overlap will map to the same value number in the
1193 // result liverange, we can still coallesce them. If not, we can't.
1194 if (LHSValNoAssignments[I->ValId] != RHSValNoAssignments[J->ValId])
1198 if (I->end < J->end) {
1207 // If we get here, we know that we can coallesce the live ranges. Ask the
1208 // intervals to coallesce themselves now.
1209 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0],
1216 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1217 // depth of the basic block (the unsigned), and then on the MBB number.
1218 struct DepthMBBCompare {
1219 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1220 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1221 if (LHS.first > RHS.first) return true; // Deeper loops first
1222 return LHS.first == RHS.first &&
1223 LHS.second->getNumber() < RHS.second->getNumber();
1229 void LiveIntervals::CopyCoallesceInMBB(MachineBasicBlock *MBB,
1230 std::vector<CopyRec> &TryAgain) {
1231 DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
1233 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1235 MachineInstr *Inst = MII++;
1237 // If this isn't a copy, we can't join intervals.
1238 unsigned SrcReg, DstReg;
1239 if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue;
1241 if (!JoinCopy(Inst, SrcReg, DstReg))
1242 TryAgain.push_back(getCopyRec(Inst, SrcReg, DstReg));
1247 void LiveIntervals::joinIntervals() {
1248 DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n");
1250 std::vector<CopyRec> TryAgainList;
1252 const LoopInfo &LI = getAnalysis<LoopInfo>();
1253 if (LI.begin() == LI.end()) {
1254 // If there are no loops in the function, join intervals in function order.
1255 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1257 CopyCoallesceInMBB(I, TryAgainList);
1259 // Otherwise, join intervals in inner loops before other intervals.
1260 // Unfortunately we can't just iterate over loop hierarchy here because
1261 // there may be more MBB's than BB's. Collect MBB's for sorting.
1262 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1263 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1265 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
1267 // Sort by loop depth.
1268 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1270 // Finally, join intervals in loop nest order.
1271 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1272 CopyCoallesceInMBB(MBBs[i].second, TryAgainList);
1275 // Joining intervals can allow other intervals to be joined. Iteratively join
1276 // until we make no progress.
1277 bool ProgressMade = true;
1278 while (ProgressMade) {
1279 ProgressMade = false;
1281 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1282 CopyRec &TheCopy = TryAgainList[i];
1284 JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) {
1285 TheCopy.MI = 0; // Mark this one as done.
1286 ProgressMade = true;
1291 DEBUG(std::cerr << "*** Register mapping ***\n");
1292 DEBUG(for (int i = 0, e = r2rMap_.size(); i != e; ++i)
1294 std::cerr << " reg " << i << " -> ";
1295 printRegName(r2rMap_[i]);
1300 /// Return true if the two specified registers belong to different register
1301 /// classes. The registers may be either phys or virt regs.
1302 bool LiveIntervals::differingRegisterClasses(unsigned RegA,
1303 unsigned RegB) const {
1305 // Get the register classes for the first reg.
1306 if (MRegisterInfo::isPhysicalRegister(RegA)) {
1307 assert(MRegisterInfo::isVirtualRegister(RegB) &&
1308 "Shouldn't consider two physregs!");
1309 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
1312 // Compare against the regclass for the second reg.
1313 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
1314 if (MRegisterInfo::isVirtualRegister(RegB))
1315 return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
1317 return !RegClass->contains(RegB);
1320 LiveInterval LiveIntervals::createInterval(unsigned reg) {
1321 float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
1322 (float)HUGE_VAL : 0.0F;
1323 return LiveInterval(reg, Weight);