1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "liveintervals"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "VirtRegMap.h"
21 #include "llvm/Value.h"
22 #include "llvm/Analysis/LoopInfo.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/MRegisterInfo.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
41 RegisterAnalysis<LiveIntervals> X("liveintervals", "Live Interval Analysis");
43 static Statistic<> numIntervals
44 ("liveintervals", "Number of original intervals");
46 static Statistic<> numIntervalsAfter
47 ("liveintervals", "Number of intervals after coalescing");
49 static Statistic<> numJoins
50 ("liveintervals", "Number of interval joins performed");
52 static Statistic<> numPeep
53 ("liveintervals", "Number of identity moves eliminated after coalescing");
55 static Statistic<> numFolded
56 ("liveintervals", "Number of loads/stores folded into instructions");
59 EnableJoining("join-liveintervals",
60 cl::desc("Join compatible live intervals"),
64 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
65 AU.addRequired<LiveVariables>();
66 AU.addPreservedID(PHIEliminationID);
67 AU.addRequiredID(PHIEliminationID);
68 AU.addRequiredID(TwoAddressInstructionPassID);
69 AU.addRequired<LoopInfo>();
70 MachineFunctionPass::getAnalysisUsage(AU);
73 void LiveIntervals::releaseMemory() {
81 static bool isZeroLengthInterval(LiveInterval *li) {
82 for (LiveInterval::Ranges::const_iterator
83 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
84 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
90 /// runOnMachineFunction - Register allocate the whole function
92 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
94 tm_ = &fn.getTarget();
95 mri_ = tm_->getRegisterInfo();
96 tii_ = tm_->getInstrInfo();
97 lv_ = &getAnalysis<LiveVariables>();
98 allocatableRegs_ = mri_->getAllocatableSet(fn);
99 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg());
101 // If this function has any live ins, insert a dummy instruction at the
102 // beginning of the function that we will pretend "defines" the values. This
103 // is to make the interval analysis simpler by providing a number.
104 if (fn.livein_begin() != fn.livein_end()) {
105 unsigned FirstLiveIn = fn.livein_begin()->first;
107 // Find a reg class that contains this live in.
108 const TargetRegisterClass *RC = 0;
109 for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(),
110 E = mri_->regclass_end(); RCI != E; ++RCI)
111 if ((*RCI)->contains(FirstLiveIn)) {
116 MachineInstr *OldFirstMI = fn.begin()->begin();
117 mri_->copyRegToReg(*fn.begin(), fn.begin()->begin(),
118 FirstLiveIn, FirstLiveIn, RC);
119 assert(OldFirstMI != fn.begin()->begin() &&
120 "copyRetToReg didn't insert anything!");
123 // number MachineInstrs
124 unsigned miIndex = 0;
125 for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end();
126 mbb != mbbEnd; ++mbb)
127 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
129 bool inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second;
130 assert(inserted && "multiple MachineInstr -> index mappings");
131 i2miMap_.push_back(mi);
132 miIndex += InstrSlots::NUM;
135 // Note intervals due to live-in values.
136 if (fn.livein_begin() != fn.livein_end()) {
137 MachineBasicBlock *Entry = fn.begin();
138 for (MachineFunction::livein_iterator I = fn.livein_begin(),
139 E = fn.livein_end(); I != E; ++I) {
140 handlePhysicalRegisterDef(Entry, Entry->begin(),
141 getOrCreateInterval(I->first), true);
142 for (const unsigned* AS = mri_->getAliasSet(I->first); *AS; ++AS)
143 handlePhysicalRegisterDef(Entry, Entry->begin(),
144 getOrCreateInterval(*AS), true);
150 numIntervals += getNumIntervals();
152 DEBUG(std::cerr << "********** INTERVALS **********\n";
153 for (iterator I = begin(), E = end(); I != E; ++I) {
154 I->second.print(std::cerr, mri_);
158 // join intervals if requested
159 if (EnableJoining) joinIntervals();
161 numIntervalsAfter += getNumIntervals();
163 // perform a final pass over the instructions and compute spill
164 // weights, coalesce virtual registers and remove identity moves
165 const LoopInfo& loopInfo = getAnalysis<LoopInfo>();
167 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
168 mbbi != mbbe; ++mbbi) {
169 MachineBasicBlock* mbb = mbbi;
170 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
172 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
174 // if the move will be an identity move delete it
175 unsigned srcReg, dstReg, RegRep;
176 if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
177 (RegRep = rep(srcReg)) == rep(dstReg)) {
178 // remove from def list
179 LiveInterval &interval = getOrCreateInterval(RegRep);
180 RemoveMachineInstrFromMaps(mii);
181 mii = mbbi->erase(mii);
185 for (unsigned i = 0; i < mii->getNumOperands(); ++i) {
186 const MachineOperand& mop = mii->getOperand(i);
187 if (mop.isRegister() && mop.getReg() &&
188 MRegisterInfo::isVirtualRegister(mop.getReg())) {
189 // replace register with representative register
190 unsigned reg = rep(mop.getReg());
191 mii->getOperand(i).setReg(reg);
193 LiveInterval &RegInt = getInterval(reg);
195 (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth);
203 for (iterator I = begin(), E = end(); I != E; ++I) {
204 LiveInterval &li = I->second;
205 if (MRegisterInfo::isVirtualRegister(li.reg))
206 // If the live interval legnth is essentially zero, i.e. in every live
207 // range the use follows def immediately, it doesn't make sense to spill
208 // it and hope it will be easier to allocate for this li.
209 if (isZeroLengthInterval(&li))
210 li.weight = float(HUGE_VAL);
217 /// print - Implement the dump method.
218 void LiveIntervals::print(std::ostream &O, const Module* ) const {
219 O << "********** INTERVALS **********\n";
220 for (const_iterator I = begin(), E = end(); I != E; ++I) {
221 I->second.print(std::cerr, mri_);
225 O << "********** MACHINEINSTRS **********\n";
226 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
227 mbbi != mbbe; ++mbbi) {
228 O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
229 for (MachineBasicBlock::iterator mii = mbbi->begin(),
230 mie = mbbi->end(); mii != mie; ++mii) {
231 O << getInstructionIndex(mii) << '\t' << *mii;
236 std::vector<LiveInterval*> LiveIntervals::
237 addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
238 // since this is called after the analysis is done we don't know if
239 // LiveVariables is available
240 lv_ = getAnalysisToUpdate<LiveVariables>();
242 std::vector<LiveInterval*> added;
244 assert(li.weight != HUGE_VAL &&
245 "attempt to spill already spilled interval!");
247 DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: ";
248 li.print(std::cerr, mri_); std::cerr << '\n');
250 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
252 for (LiveInterval::Ranges::const_iterator
253 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
254 unsigned index = getBaseIndex(i->start);
255 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM;
256 for (; index != end; index += InstrSlots::NUM) {
257 // skip deleted instructions
258 while (index != end && !getInstructionFromIndex(index))
259 index += InstrSlots::NUM;
260 if (index == end) break;
262 MachineInstr *MI = getInstructionFromIndex(index);
264 // NewRegLiveIn - This instruction might have multiple uses of the spilled
265 // register. In this case, for the first use, keep track of the new vreg
266 // that we reload it into. If we see a second use, reuse this vreg
267 // instead of creating live ranges for two reloads.
268 unsigned NewRegLiveIn = 0;
271 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
272 MachineOperand& mop = MI->getOperand(i);
273 if (mop.isRegister() && mop.getReg() == li.reg) {
274 if (NewRegLiveIn && mop.isUse()) {
275 // We already emitted a reload of this value, reuse it for
276 // subsequent operands.
277 MI->getOperand(i).setReg(NewRegLiveIn);
278 DEBUG(std::cerr << "\t\t\t\treused reload into reg" << NewRegLiveIn
279 << " for operand #" << i << '\n');
280 } else if (MachineInstr* fmi = mri_->foldMemoryOperand(MI, i, slot)) {
281 // Attempt to fold the memory reference into the instruction. If we
282 // can do this, we don't need to insert spill code.
284 lv_->instructionChanged(MI, fmi);
285 MachineBasicBlock &MBB = *MI->getParent();
286 vrm.virtFolded(li.reg, MI, i, fmi);
288 i2miMap_[index/InstrSlots::NUM] = fmi;
289 mi2iMap_[fmi] = index;
290 MI = MBB.insert(MBB.erase(MI), fmi);
292 // Folding the load/store can completely change the instruction in
293 // unpredictable ways, rescan it from the beginning.
296 // This is tricky. We need to add information in the interval about
297 // the spill code so we have to use our extra load/store slots.
299 // If we have a use we are going to have a load so we start the
300 // interval from the load slot onwards. Otherwise we start from the
302 unsigned start = (mop.isUse() ?
303 getLoadIndex(index) :
305 // If we have a def we are going to have a store right after it so
306 // we end the interval after the use of the next
307 // instruction. Otherwise we end after the use of this instruction.
308 unsigned end = 1 + (mop.isDef() ?
309 getStoreIndex(index) :
312 // create a new register for this spill
313 NewRegLiveIn = mf_->getSSARegMap()->createVirtualRegister(rc);
314 MI->getOperand(i).setReg(NewRegLiveIn);
316 vrm.assignVirt2StackSlot(NewRegLiveIn, slot);
317 LiveInterval& nI = getOrCreateInterval(NewRegLiveIn);
320 // the spill weight is now infinity as it
321 // cannot be spilled again
322 nI.weight = float(HUGE_VAL);
323 LiveRange LR(start, end, nI.getNextValue(~0U));
324 DEBUG(std::cerr << " +" << LR);
326 added.push_back(&nI);
328 // update live variables if it is available
330 lv_->addVirtualRegisterKilled(NewRegLiveIn, MI);
332 // If this is a live in, reuse it for subsequent live-ins. If it's
333 // a def, we can't do this.
334 if (!mop.isUse()) NewRegLiveIn = 0;
336 DEBUG(std::cerr << "\t\t\t\tadded new interval: ";
337 nI.print(std::cerr, mri_); std::cerr << '\n');
347 void LiveIntervals::printRegName(unsigned reg) const {
348 if (MRegisterInfo::isPhysicalRegister(reg))
349 std::cerr << mri_->getName(reg);
351 std::cerr << "%reg" << reg;
354 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
355 MachineBasicBlock::iterator mi,
356 LiveInterval &interval) {
357 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
358 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
360 // Virtual registers may be defined multiple times (due to phi
361 // elimination and 2-addr elimination). Much of what we do only has to be
362 // done once for the vreg. We use an empty interval to detect the first
363 // time we see a vreg.
364 if (interval.empty()) {
365 // Get the Idx of the defining instructions.
366 unsigned defIndex = getDefIndex(getInstructionIndex(mi));
368 unsigned ValNum = interval.getNextValue(defIndex);
369 assert(ValNum == 0 && "First value in interval is not 0?");
370 ValNum = 0; // Clue in the optimizer.
372 // Loop over all of the blocks that the vreg is defined in. There are
373 // two cases we have to handle here. The most common case is a vreg
374 // whose lifetime is contained within a basic block. In this case there
375 // will be a single kill, in MBB, which comes after the definition.
376 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
377 // FIXME: what about dead vars?
379 if (vi.Kills[0] != mi)
380 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
382 killIdx = defIndex+1;
384 // If the kill happens after the definition, we have an intra-block
386 if (killIdx > defIndex) {
387 assert(vi.AliveBlocks.empty() &&
388 "Shouldn't be alive across any blocks!");
389 LiveRange LR(defIndex, killIdx, ValNum);
390 interval.addRange(LR);
391 DEBUG(std::cerr << " +" << LR << "\n");
396 // The other case we handle is when a virtual register lives to the end
397 // of the defining block, potentially live across some blocks, then is
398 // live into some number of blocks, but gets killed. Start by adding a
399 // range that goes from this definition to the end of the defining block.
400 LiveRange NewLR(defIndex,
401 getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
403 DEBUG(std::cerr << " +" << NewLR);
404 interval.addRange(NewLR);
406 // Iterate over all of the blocks that the variable is completely
407 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
409 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
410 if (vi.AliveBlocks[i]) {
411 MachineBasicBlock* mbb = mf_->getBlockNumbered(i);
413 LiveRange LR(getInstructionIndex(&mbb->front()),
414 getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
416 interval.addRange(LR);
417 DEBUG(std::cerr << " +" << LR);
422 // Finally, this virtual register is live from the start of any killing
423 // block to the 'use' slot of the killing instruction.
424 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
425 MachineInstr *Kill = vi.Kills[i];
426 LiveRange LR(getInstructionIndex(Kill->getParent()->begin()),
427 getUseIndex(getInstructionIndex(Kill))+1,
429 interval.addRange(LR);
430 DEBUG(std::cerr << " +" << LR);
434 // If this is the second time we see a virtual register definition, it
435 // must be due to phi elimination or two addr elimination. If this is
436 // the result of two address elimination, then the vreg is the first
437 // operand, and is a def-and-use.
438 if (mi->getOperand(0).isRegister() &&
439 mi->getOperand(0).getReg() == interval.reg &&
440 mi->getOperand(0).isDef() && mi->getOperand(0).isUse()) {
441 // If this is a two-address definition, then we have already processed
442 // the live range. The only problem is that we didn't realize there
443 // are actually two values in the live interval. Because of this we
444 // need to take the LiveRegion that defines this register and split it
446 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst));
447 unsigned RedefIndex = getDefIndex(getInstructionIndex(mi));
449 // Delete the initial value, which should be short and continuous,
450 // because the 2-addr copy must be in the same MBB as the redef.
451 interval.removeRange(DefIndex, RedefIndex);
453 // Two-address vregs should always only be redefined once. This means
454 // that at this point, there should be exactly one value number in it.
455 assert(interval.containsOneValue() && "Unexpected 2-addr liveint!");
457 // The new value number is defined by the instruction we claimed defined
459 unsigned ValNo = interval.getNextValue(DefIndex);
461 // Value#1 is now defined by the 2-addr instruction.
462 interval.setInstDefiningValNum(0, RedefIndex);
464 // Add the new live interval which replaces the range for the input copy.
465 LiveRange LR(DefIndex, RedefIndex, ValNo);
466 DEBUG(std::cerr << " replace range with " << LR);
467 interval.addRange(LR);
469 // If this redefinition is dead, we need to add a dummy unit live
470 // range covering the def slot.
471 if (lv_->RegisterDefIsDead(mi, interval.reg))
472 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
474 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_));
477 // Otherwise, this must be because of phi elimination. If this is the
478 // first redefinition of the vreg that we have seen, go back and change
479 // the live range in the PHI block to be a different value number.
480 if (interval.containsOneValue()) {
481 assert(vi.Kills.size() == 1 &&
482 "PHI elimination vreg should have one kill, the PHI itself!");
484 // Remove the old range that we now know has an incorrect number.
485 MachineInstr *Killer = vi.Kills[0];
486 unsigned Start = getInstructionIndex(Killer->getParent()->begin());
487 unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
488 DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: ";
489 interval.print(std::cerr, mri_); std::cerr << "\n");
490 interval.removeRange(Start, End);
491 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_));
493 // Replace the interval with one of a NEW value number. Note that this
494 // value number isn't actually defined by an instruction, weird huh? :)
495 LiveRange LR(Start, End, interval.getNextValue(~0U));
496 DEBUG(std::cerr << " replace range with " << LR);
497 interval.addRange(LR);
498 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_));
501 // In the case of PHI elimination, each variable definition is only
502 // live until the end of the block. We've already taken care of the
503 // rest of the live range.
504 unsigned defIndex = getDefIndex(getInstructionIndex(mi));
505 LiveRange LR(defIndex,
506 getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
507 interval.getNextValue(defIndex));
508 interval.addRange(LR);
509 DEBUG(std::cerr << " +" << LR);
513 DEBUG(std::cerr << '\n');
516 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
517 MachineBasicBlock::iterator mi,
518 LiveInterval& interval,
520 // A physical register cannot be live across basic block, so its
521 // lifetime must end somewhere in its defining basic block.
522 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
523 typedef LiveVariables::killed_iterator KillIter;
525 unsigned baseIndex = getInstructionIndex(mi);
526 unsigned start = getDefIndex(baseIndex);
527 unsigned end = start;
529 // If it is not used after definition, it is considered dead at
530 // the instruction defining it. Hence its interval is:
531 // [defSlot(def), defSlot(def)+1)
532 if (lv_->RegisterDefIsDead(mi, interval.reg)) {
533 DEBUG(std::cerr << " dead");
534 end = getDefIndex(start) + 1;
538 // If it is not dead on definition, it must be killed by a
539 // subsequent instruction. Hence its interval is:
540 // [defSlot(def), useSlot(kill)+1)
541 while (++mi != MBB->end()) {
542 baseIndex += InstrSlots::NUM;
543 if (lv_->KillsRegister(mi, interval.reg)) {
544 DEBUG(std::cerr << " killed");
545 end = getUseIndex(baseIndex) + 1;
550 // The only case we should have a dead physreg here without a killing or
551 // instruction where we know it's dead is if it is live-in to the function
553 assert(isLiveIn && "physreg was not killed in defining block!");
554 end = getDefIndex(start) + 1; // It's dead.
557 assert(start < end && "did not find end of interval?");
559 LiveRange LR(start, end, interval.getNextValue(isLiveIn ? ~0U : start));
560 interval.addRange(LR);
561 DEBUG(std::cerr << " +" << LR << '\n');
564 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
565 MachineBasicBlock::iterator MI,
567 if (MRegisterInfo::isVirtualRegister(reg))
568 handleVirtualRegisterDef(MBB, MI, getOrCreateInterval(reg));
569 else if (allocatableRegs_[reg]) {
570 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(reg));
571 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS)
572 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(*AS));
576 /// computeIntervals - computes the live intervals for virtual
577 /// registers. for some ordering of the machine instructions [1,N] a
578 /// live interval is an interval [i, j) where 1 <= i <= j < N for
579 /// which a variable is live
580 void LiveIntervals::computeIntervals() {
581 DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n");
582 DEBUG(std::cerr << "********** Function: "
583 << ((Value*)mf_->getFunction())->getName() << '\n');
584 bool IgnoreFirstInstr = mf_->livein_begin() != mf_->livein_end();
586 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
588 MachineBasicBlock* mbb = I;
589 DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n");
591 MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
592 if (IgnoreFirstInstr) { ++mi; IgnoreFirstInstr = false; }
593 for (; mi != miEnd; ++mi) {
594 const TargetInstrDescriptor& tid =
595 tm_->getInstrInfo()->get(mi->getOpcode());
596 DEBUG(std::cerr << getInstructionIndex(mi) << "\t" << *mi);
598 // handle implicit defs
599 if (tid.ImplicitDefs) {
600 for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
601 handleRegisterDef(mbb, mi, *id);
604 // handle explicit defs
605 for (int i = mi->getNumOperands() - 1; i >= 0; --i) {
606 MachineOperand& mop = mi->getOperand(i);
607 // handle register defs - build intervals
608 if (mop.isRegister() && mop.getReg() && mop.isDef())
609 handleRegisterDef(mbb, mi, mop.getReg());
615 /// AdjustCopiesBackFrom - We found a non-trivially-coallescable copy with IntA
616 /// being the source and IntB being the dest, thus this defines a value number
617 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
618 /// see if we can merge these two pieces of B into a single value number,
619 /// eliminating a copy. For example:
623 /// B1 = A3 <- this copy
625 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
626 /// value number to be replaced with B0 (which simplifies the B liveinterval).
628 /// This returns true if an interval was modified.
630 bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
631 MachineInstr *CopyMI,
633 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
634 // the example above.
635 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
636 unsigned BValNo = BLR->ValId;
638 // Get the location that B is defined at. Two options: either this value has
639 // an unknown definition point or it is defined at CopyIdx. If unknown, we
641 unsigned BValNoDefIdx = IntB.getInstForValNum(BValNo);
642 if (BValNoDefIdx == ~0U) return false;
643 assert(BValNoDefIdx == CopyIdx &&
644 "Copy doesn't define the value?");
646 // AValNo is the value number in A that defines the copy, A0 in the example.
647 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1);
648 unsigned AValNo = AValLR->ValId;
650 // If AValNo is defined as a copy from IntB, we can potentially process this.
652 // Get the instruction that defines this value number.
653 unsigned AValNoInstIdx = IntA.getInstForValNum(AValNo);
655 // If it's unknown, ignore it.
656 if (AValNoInstIdx == ~0U || AValNoInstIdx == ~1U) return false;
657 // Otherwise, get the instruction for it.
658 MachineInstr *AValNoInstMI = getInstructionFromIndex(AValNoInstIdx);
660 // If the value number is not defined by a copy instruction, ignore it.
661 unsigned SrcReg, DstReg;
662 if (!tii_->isMoveInstr(*AValNoInstMI, SrcReg, DstReg))
665 // If the source register comes from an interval other than IntB, we can't
667 assert(rep(DstReg) == IntA.reg && "Not defining a reg in IntA?");
668 if (rep(SrcReg) != IntB.reg) return false;
670 // Get the LiveRange in IntB that this value number starts with.
671 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNoInstIdx-1);
673 // Make sure that the end of the live range is inside the same block as
675 MachineInstr *ValLREndInst = getInstructionFromIndex(ValLR->end-1);
676 if (ValLREndInst->getParent() != CopyMI->getParent()) return false;
678 // Okay, we now know that ValLR ends in the same block that the CopyMI
679 // live-range starts. If there are no intervening live ranges between them in
680 // IntB, we can merge them.
681 if (ValLR+1 != BLR) return false;
683 DEBUG(std::cerr << "\nExtending: "; IntB.print(std::cerr, mri_));
685 // Okay, we can merge them. We need to insert a new liverange:
686 // [ValLR.end, BLR.begin) of either value number, then we merge the
687 // two value numbers.
688 IntB.addRange(LiveRange(ValLR->end, BLR->start, BValNo));
690 // Okay, merge "B1" into the same value number as "B0".
691 if (BValNo != ValLR->ValId)
692 IntB.MergeValueNumberInto(BValNo, ValLR->ValId);
693 DEBUG(std::cerr << " result = "; IntB.print(std::cerr, mri_);
696 // Finally, delete the copy instruction.
697 RemoveMachineInstrFromMaps(CopyMI);
698 CopyMI->eraseFromParent();
704 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
705 /// which are the src/dst of the copy instruction CopyMI. This returns true
706 /// if the copy was successfully coallesced away, or if it is never possible
707 /// to coallesce these this copy, due to register constraints. It returns
708 /// false if it is not currently possible to coallesce this interval, but
709 /// it may be possible if other things get coallesced.
710 bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
711 unsigned SrcReg, unsigned DstReg) {
714 DEBUG(std::cerr << getInstructionIndex(CopyMI) << '\t' << *CopyMI);
716 // Get representative registers.
717 SrcReg = rep(SrcReg);
718 DstReg = rep(DstReg);
720 // If they are already joined we continue.
721 if (SrcReg == DstReg) {
722 DEBUG(std::cerr << "\tCopy already coallesced.\n");
723 return true; // Not coallescable.
726 // If they are both physical registers, we cannot join them.
727 if (MRegisterInfo::isPhysicalRegister(SrcReg) &&
728 MRegisterInfo::isPhysicalRegister(DstReg)) {
729 DEBUG(std::cerr << "\tCan not coallesce physregs.\n");
730 return true; // Not coallescable.
733 // We only join virtual registers with allocatable physical registers.
734 if (MRegisterInfo::isPhysicalRegister(SrcReg) && !allocatableRegs_[SrcReg]){
735 DEBUG(std::cerr << "\tSrc reg is unallocatable physreg.\n");
736 return true; // Not coallescable.
738 if (MRegisterInfo::isPhysicalRegister(DstReg) && !allocatableRegs_[DstReg]){
739 DEBUG(std::cerr << "\tDst reg is unallocatable physreg.\n");
740 return true; // Not coallescable.
743 // If they are not of the same register class, we cannot join them.
744 if (differingRegisterClasses(SrcReg, DstReg)) {
745 DEBUG(std::cerr << "\tSrc/Dest are different register classes.\n");
746 return true; // Not coallescable.
749 LiveInterval &SrcInt = getInterval(SrcReg);
750 LiveInterval &DestInt = getInterval(DstReg);
751 assert(SrcInt.reg == SrcReg && DestInt.reg == DstReg &&
752 "Register mapping is horribly broken!");
754 DEBUG(std::cerr << "\t\tInspecting "; SrcInt.print(std::cerr, mri_);
755 std::cerr << " and "; DestInt.print(std::cerr, mri_);
758 // If two intervals contain a single value and are joined by a copy, it
759 // does not matter if the intervals overlap, they can always be joined.
761 bool Joinable = SrcInt.containsOneValue() && DestInt.containsOneValue();
763 unsigned MIDefIdx = getDefIndex(getInstructionIndex(CopyMI));
765 // If the intervals think that this is joinable, do so now.
766 if (!Joinable && DestInt.joinable(SrcInt, MIDefIdx))
769 // If DestInt is actually a copy from SrcInt (which we know) that is used
770 // to define another value of SrcInt, we can change the other range of
771 // SrcInt to be the value of the range that defines DestInt, simplying the
772 // interval an promoting coallescing.
773 if (!Joinable && AdjustCopiesBackFrom(SrcInt, DestInt, CopyMI, MIDefIdx))
776 // If this looks joinable, do the final, expensive last check, checking to see
777 // if aliases overlap. If they do, we can never join these.
778 if (Joinable && overlapsAliases(&SrcInt, &DestInt)) {
779 DEBUG(std::cerr << "Alias Overlap Interference!\n");
780 return true; // Can never join these.
784 DEBUG(std::cerr << "Interference!\n");
788 DestInt.join(SrcInt, MIDefIdx);
789 DEBUG(std::cerr << "\n\t\tJoined. Result = "; DestInt.print(std::cerr, mri_);
792 if (!MRegisterInfo::isPhysicalRegister(SrcReg)) {
793 r2iMap_.erase(SrcReg);
794 r2rMap_[SrcReg] = DstReg;
796 // Otherwise merge the data structures the other way so we don't lose
797 // the physreg information.
798 r2rMap_[DstReg] = SrcReg;
799 DestInt.reg = SrcReg;
800 SrcInt.swap(DestInt);
801 r2iMap_.erase(DstReg);
810 // DepthMBBCompare - Comparison predicate that sort first based on the loop
811 // depth of the basic block (the unsigned), and then on the MBB number.
812 struct DepthMBBCompare {
813 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
814 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
815 if (LHS.first > RHS.first) return true; // Deeper loops first
816 return LHS.first == RHS.first &&
817 LHS.second->getNumber() < RHS.second->getNumber();
823 void LiveIntervals::CopyCoallesceInMBB(MachineBasicBlock *MBB,
824 std::vector<CopyRec> &TryAgain) {
825 DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
827 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
829 MachineInstr *Inst = MII++;
831 // If this isn't a copy, we can't join intervals.
832 unsigned SrcReg, DstReg;
833 if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue;
835 if (!JoinCopy(Inst, SrcReg, DstReg))
836 TryAgain.push_back(getCopyRec(Inst, SrcReg, DstReg));
841 void LiveIntervals::joinIntervals() {
842 DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n");
844 std::vector<CopyRec> TryAgainList;
846 const LoopInfo &LI = getAnalysis<LoopInfo>();
847 if (LI.begin() == LI.end()) {
848 // If there are no loops in the function, join intervals in function order.
849 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
851 CopyCoallesceInMBB(I, TryAgainList);
853 // Otherwise, join intervals in inner loops before other intervals.
854 // Unfortunately we can't just iterate over loop hierarchy here because
855 // there may be more MBB's than BB's. Collect MBB's for sorting.
856 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
857 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
859 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
861 // Sort by loop depth.
862 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
864 // Finally, join intervals in loop nest order.
865 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
866 CopyCoallesceInMBB(MBBs[i].second, TryAgainList);
869 // Joining intervals can allow other intervals to be joined. Iteratively join
870 // until we make no progress.
871 bool ProgressMade = true;
872 while (ProgressMade) {
873 ProgressMade = false;
875 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
876 CopyRec &TheCopy = TryAgainList[i];
878 JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) {
879 TheCopy.MI = 0; // Mark this one as done.
885 DEBUG(std::cerr << "*** Register mapping ***\n");
886 DEBUG(for (int i = 0, e = r2rMap_.size(); i != e; ++i)
888 std::cerr << " reg " << i << " -> ";
889 printRegName(r2rMap_[i]);
894 /// Return true if the two specified registers belong to different register
895 /// classes. The registers may be either phys or virt regs.
896 bool LiveIntervals::differingRegisterClasses(unsigned RegA,
897 unsigned RegB) const {
899 // Get the register classes for the first reg.
900 if (MRegisterInfo::isPhysicalRegister(RegA)) {
901 assert(MRegisterInfo::isVirtualRegister(RegB) &&
902 "Shouldn't consider two physregs!");
903 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
906 // Compare against the regclass for the second reg.
907 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
908 if (MRegisterInfo::isVirtualRegister(RegB))
909 return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
911 return !RegClass->contains(RegB);
914 bool LiveIntervals::overlapsAliases(const LiveInterval *LHS,
915 const LiveInterval *RHS) const {
916 if (!MRegisterInfo::isPhysicalRegister(LHS->reg)) {
917 if (!MRegisterInfo::isPhysicalRegister(RHS->reg))
918 return false; // vreg-vreg merge has no aliases!
922 assert(MRegisterInfo::isPhysicalRegister(LHS->reg) &&
923 MRegisterInfo::isVirtualRegister(RHS->reg) &&
924 "first interval must describe a physical register");
926 for (const unsigned *AS = mri_->getAliasSet(LHS->reg); *AS; ++AS)
927 if (RHS->overlaps(getInterval(*AS)))
933 LiveInterval LiveIntervals::createInterval(unsigned reg) {
934 float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
935 (float)HUGE_VAL :0.0F;
936 return LiveInterval(reg, Weight);