1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "LiveRangeCalc.h"
20 #include "llvm/ADT/DenseSet.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/IR/Value.h"
31 #include "llvm/Support/BlockFrequency.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/Format.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
45 #define DEBUG_TYPE "regalloc"
47 char LiveIntervals::ID = 0;
48 char &llvm::LiveIntervalsID = LiveIntervals::ID;
49 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
50 "Live Interval Analysis", false, false)
51 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
52 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
53 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
54 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
55 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
56 "Live Interval Analysis", false, false)
59 static cl::opt<bool> EnablePrecomputePhysRegs(
60 "precompute-phys-liveness", cl::Hidden,
61 cl::desc("Eagerly compute live intervals for all physreg units."));
63 static bool EnablePrecomputePhysRegs = false;
66 static cl::opt<bool> EnableSubRegLiveness(
67 "enable-subreg-liveness", cl::Hidden, cl::init(true),
68 cl::desc("Enable subregister liveness tracking."));
71 cl::opt<bool> UseSegmentSetForPhysRegs(
72 "use-segment-set-for-physregs", cl::Hidden, cl::init(true),
74 "Use segment set for the computation of the live ranges of physregs."));
77 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
79 AU.addRequired<AAResultsWrapperPass>();
80 AU.addPreserved<AAResultsWrapperPass>();
81 // LiveVariables isn't really required by this analysis, it is only required
82 // here to make sure it is live during TwoAddressInstructionPass and
83 // PHIElimination. This is temporary.
84 AU.addRequired<LiveVariables>();
85 AU.addPreserved<LiveVariables>();
86 AU.addPreservedID(MachineLoopInfoID);
87 AU.addRequiredTransitiveID(MachineDominatorsID);
88 AU.addPreservedID(MachineDominatorsID);
89 AU.addPreserved<SlotIndexes>();
90 AU.addRequiredTransitive<SlotIndexes>();
91 MachineFunctionPass::getAnalysisUsage(AU);
94 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
95 DomTree(nullptr), LRCalc(nullptr) {
96 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
99 LiveIntervals::~LiveIntervals() {
103 void LiveIntervals::releaseMemory() {
104 // Free the live intervals themselves.
105 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
106 delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
107 VirtRegIntervals.clear();
108 RegMaskSlots.clear();
110 RegMaskBlocks.clear();
112 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
113 delete RegUnitRanges[i];
114 RegUnitRanges.clear();
116 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
117 VNInfoAllocator.Reset();
120 /// runOnMachineFunction - calculates LiveIntervals
122 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
124 MRI = &MF->getRegInfo();
125 TRI = MF->getSubtarget().getRegisterInfo();
126 TII = MF->getSubtarget().getInstrInfo();
127 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
128 Indexes = &getAnalysis<SlotIndexes>();
129 DomTree = &getAnalysis<MachineDominatorTree>();
131 if (EnableSubRegLiveness && MF->getSubtarget().enableSubRegLiveness())
132 MRI->enableSubRegLiveness(true);
135 LRCalc = new LiveRangeCalc();
137 // Allocate space for all virtual registers.
138 VirtRegIntervals.resize(MRI->getNumVirtRegs());
142 computeLiveInRegUnits();
144 if (EnablePrecomputePhysRegs) {
145 // For stress testing, precompute live ranges of all physical register
146 // units, including reserved registers.
147 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
154 /// print - Implement the dump method.
155 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
156 OS << "********** INTERVALS **********\n";
158 // Dump the regunits.
159 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
160 if (LiveRange *LR = RegUnitRanges[i])
161 OS << PrintRegUnit(i, TRI) << ' ' << *LR << '\n';
163 // Dump the virtregs.
164 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
165 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
166 if (hasInterval(Reg))
167 OS << getInterval(Reg) << '\n';
171 for (unsigned i = 0, e = RegMaskSlots.size(); i != e; ++i)
172 OS << ' ' << RegMaskSlots[i];
178 void LiveIntervals::printInstrs(raw_ostream &OS) const {
179 OS << "********** MACHINEINSTRS **********\n";
180 MF->print(OS, Indexes);
183 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
184 void LiveIntervals::dumpInstrs() const {
189 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
190 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
191 llvm::huge_valf : 0.0F;
192 return new LiveInterval(reg, Weight);
196 /// computeVirtRegInterval - Compute the live interval of a virtual register,
197 /// based on defs and uses.
198 void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
199 assert(LRCalc && "LRCalc not initialized.");
200 assert(LI.empty() && "Should only compute empty intervals.");
201 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
202 LRCalc->calculate(LI, MRI->shouldTrackSubRegLiveness(LI.reg));
203 computeDeadValues(LI, nullptr);
206 void LiveIntervals::computeVirtRegs() {
207 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
208 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
209 if (MRI->reg_nodbg_empty(Reg))
211 createAndComputeVirtRegInterval(Reg);
215 void LiveIntervals::computeRegMasks() {
216 RegMaskBlocks.resize(MF->getNumBlockIDs());
218 // Find all instructions with regmask operands.
219 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
221 MachineBasicBlock *MBB = MBBI;
222 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
223 RMB.first = RegMaskSlots.size();
224 for (MachineBasicBlock::iterator MI = MBB->begin(), ME = MBB->end();
226 for (const MachineOperand &MO : MI->operands()) {
229 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
230 RegMaskBits.push_back(MO.getRegMask());
232 // Compute the number of register mask instructions in this block.
233 RMB.second = RegMaskSlots.size() - RMB.first;
237 //===----------------------------------------------------------------------===//
238 // Register Unit Liveness
239 //===----------------------------------------------------------------------===//
241 // Fixed interference typically comes from ABI boundaries: Function arguments
242 // and return values are passed in fixed registers, and so are exception
243 // pointers entering landing pads. Certain instructions require values to be
244 // present in specific registers. That is also represented through fixed
248 /// computeRegUnitInterval - Compute the live range of a register unit, based
249 /// on the uses and defs of aliasing registers. The range should be empty,
250 /// or contain only dead phi-defs from ABI blocks.
251 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
252 assert(LRCalc && "LRCalc not initialized.");
253 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
255 // The physregs aliasing Unit are the roots and their super-registers.
256 // Create all values as dead defs before extending to uses. Note that roots
257 // may share super-registers. That's OK because createDeadDefs() is
258 // idempotent. It is very rare for a register unit to have multiple roots, so
259 // uniquing super-registers is probably not worthwhile.
260 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
261 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
262 Supers.isValid(); ++Supers) {
263 if (!MRI->reg_empty(*Supers))
264 LRCalc->createDeadDefs(LR, *Supers);
268 // Now extend LR to reach all uses.
269 // Ignore uses of reserved registers. We only track defs of those.
270 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
271 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
272 Supers.isValid(); ++Supers) {
273 unsigned Reg = *Supers;
274 if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg))
275 LRCalc->extendToUses(LR, Reg);
279 // Flush the segment set to the segment vector.
280 if (UseSegmentSetForPhysRegs)
281 LR.flushSegmentSet();
285 /// computeLiveInRegUnits - Precompute the live ranges of any register units
286 /// that are live-in to an ABI block somewhere. Register values can appear
287 /// without a corresponding def when entering the entry block or a landing pad.
289 void LiveIntervals::computeLiveInRegUnits() {
290 RegUnitRanges.resize(TRI->getNumRegUnits());
291 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
293 // Keep track of the live range sets allocated.
294 SmallVector<unsigned, 8> NewRanges;
296 // Check all basic blocks for live-ins.
297 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
299 const MachineBasicBlock *MBB = MFI;
301 // We only care about ABI blocks: Entry + landing pads.
302 if ((MFI != MF->begin() && !MBB->isEHPad()) || MBB->livein_empty())
305 // Create phi-defs at Begin for all live-in registers.
306 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
307 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
308 for (const auto &LI : MBB->liveins()) {
309 for (MCRegUnitIterator Units(LI.PhysReg, TRI); Units.isValid(); ++Units) {
310 unsigned Unit = *Units;
311 LiveRange *LR = RegUnitRanges[Unit];
313 // Use segment set to speed-up initial computation of the live range.
314 LR = RegUnitRanges[Unit] = new LiveRange(UseSegmentSetForPhysRegs);
315 NewRanges.push_back(Unit);
317 VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
319 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
322 DEBUG(dbgs() << '\n');
324 DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");
326 // Compute the 'normal' part of the ranges.
327 for (unsigned i = 0, e = NewRanges.size(); i != e; ++i) {
328 unsigned Unit = NewRanges[i];
329 computeRegUnitRange(*RegUnitRanges[Unit], Unit);
334 static void createSegmentsForValues(LiveRange &LR,
335 iterator_range<LiveInterval::vni_iterator> VNIs) {
336 for (auto VNI : VNIs) {
339 SlotIndex Def = VNI->def;
340 LR.addSegment(LiveRange::Segment(Def, Def.getDeadSlot(), VNI));
344 typedef SmallVector<std::pair<SlotIndex, VNInfo*>, 16> ShrinkToUsesWorkList;
346 static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes,
347 ShrinkToUsesWorkList &WorkList,
348 const LiveRange &OldRange) {
349 // Keep track of the PHIs that are in use.
350 SmallPtrSet<VNInfo*, 8> UsedPHIs;
351 // Blocks that have already been added to WorkList as live-out.
352 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
354 // Extend intervals to reach all uses in WorkList.
355 while (!WorkList.empty()) {
356 SlotIndex Idx = WorkList.back().first;
357 VNInfo *VNI = WorkList.back().second;
359 const MachineBasicBlock *MBB = Indexes.getMBBFromIndex(Idx.getPrevSlot());
360 SlotIndex BlockStart = Indexes.getMBBStartIdx(MBB);
362 // Extend the live range for VNI to be live at Idx.
363 if (VNInfo *ExtVNI = LR.extendInBlock(BlockStart, Idx)) {
364 assert(ExtVNI == VNI && "Unexpected existing value number");
366 // Is this a PHIDef we haven't seen before?
367 if (!VNI->isPHIDef() || VNI->def != BlockStart ||
368 !UsedPHIs.insert(VNI).second)
370 // The PHI is live, make sure the predecessors are live-out.
371 for (auto &Pred : MBB->predecessors()) {
372 if (!LiveOut.insert(Pred).second)
374 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
375 // A predecessor is not required to have a live-out value for a PHI.
376 if (VNInfo *PVNI = OldRange.getVNInfoBefore(Stop))
377 WorkList.push_back(std::make_pair(Stop, PVNI));
382 // VNI is live-in to MBB.
383 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
384 LR.addSegment(LiveRange::Segment(BlockStart, Idx, VNI));
386 // Make sure VNI is live-out from the predecessors.
387 for (auto &Pred : MBB->predecessors()) {
388 if (!LiveOut.insert(Pred).second)
390 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
391 assert(OldRange.getVNInfoBefore(Stop) == VNI &&
392 "Wrong value out of predecessor");
393 WorkList.push_back(std::make_pair(Stop, VNI));
398 bool LiveIntervals::shrinkToUses(LiveInterval *li,
399 SmallVectorImpl<MachineInstr*> *dead) {
400 DEBUG(dbgs() << "Shrink: " << *li << '\n');
401 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
402 && "Can only shrink virtual registers");
404 // Shrink subregister live ranges.
405 bool NeedsCleanup = false;
406 for (LiveInterval::SubRange &S : li->subranges()) {
407 shrinkToUses(S, li->reg);
412 li->removeEmptySubRanges();
414 // Find all the values used, including PHI kills.
415 ShrinkToUsesWorkList WorkList;
417 // Visit all instructions reading li->reg.
418 for (MachineRegisterInfo::reg_instr_iterator
419 I = MRI->reg_instr_begin(li->reg), E = MRI->reg_instr_end();
421 MachineInstr *UseMI = &*(I++);
422 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
424 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
425 LiveQueryResult LRQ = li->Query(Idx);
426 VNInfo *VNI = LRQ.valueIn();
428 // This shouldn't happen: readsVirtualRegister returns true, but there is
429 // no live value. It is likely caused by a target getting <undef> flags
431 DEBUG(dbgs() << Idx << '\t' << *UseMI
432 << "Warning: Instr claims to read non-existent value in "
436 // Special case: An early-clobber tied operand reads and writes the
437 // register one slot early.
438 if (VNInfo *DefVNI = LRQ.valueDefined())
441 WorkList.push_back(std::make_pair(Idx, VNI));
444 // Create new live ranges with only minimal live segments per def.
446 createSegmentsForValues(NewLR, make_range(li->vni_begin(), li->vni_end()));
447 extendSegmentsToUses(NewLR, *Indexes, WorkList, *li);
449 // Move the trimmed segments back.
450 li->segments.swap(NewLR.segments);
452 // Handle dead values.
453 bool CanSeparate = computeDeadValues(*li, dead);
454 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
458 bool LiveIntervals::computeDeadValues(LiveInterval &LI,
459 SmallVectorImpl<MachineInstr*> *dead) {
460 bool PHIRemoved = false;
461 for (auto VNI : LI.valnos) {
464 SlotIndex Def = VNI->def;
465 LiveRange::iterator I = LI.FindSegmentContaining(Def);
466 assert(I != LI.end() && "Missing segment for VNI");
468 // Is the register live before? Otherwise we may have to add a read-undef
469 // flag for subregister defs.
470 if (MRI->shouldTrackSubRegLiveness(LI.reg)) {
471 if ((I == LI.begin() || std::prev(I)->end < Def) && !VNI->isPHIDef()) {
472 MachineInstr *MI = getInstructionFromIndex(Def);
473 MI->addRegisterDefReadUndef(LI.reg);
477 if (I->end != Def.getDeadSlot())
479 if (VNI->isPHIDef()) {
480 // This is a dead PHI. Remove it.
483 DEBUG(dbgs() << "Dead PHI at " << Def << " may separate interval\n");
486 // This is a dead def. Make sure the instruction knows.
487 MachineInstr *MI = getInstructionFromIndex(Def);
488 assert(MI && "No instruction defining live value");
489 MI->addRegisterDead(LI.reg, TRI);
490 if (dead && MI->allDefsAreDead()) {
491 DEBUG(dbgs() << "All defs dead: " << Def << '\t' << *MI);
499 void LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg)
501 DEBUG(dbgs() << "Shrink: " << SR << '\n');
502 assert(TargetRegisterInfo::isVirtualRegister(Reg)
503 && "Can only shrink virtual registers");
504 // Find all the values used, including PHI kills.
505 ShrinkToUsesWorkList WorkList;
507 // Visit all instructions reading Reg.
509 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
510 MachineInstr *UseMI = MO.getParent();
511 if (UseMI->isDebugValue())
513 // Maybe the operand is for a subregister we don't care about.
514 unsigned SubReg = MO.getSubReg();
516 unsigned SubRegMask = TRI->getSubRegIndexLaneMask(SubReg);
517 if ((SubRegMask & SR.LaneMask) == 0)
520 // We only need to visit each instruction once.
521 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
526 LiveQueryResult LRQ = SR.Query(Idx);
527 VNInfo *VNI = LRQ.valueIn();
528 // For Subranges it is possible that only undef values are left in that
529 // part of the subregister, so there is no real liverange at the use
533 // Special case: An early-clobber tied operand reads and writes the
534 // register one slot early.
535 if (VNInfo *DefVNI = LRQ.valueDefined())
538 WorkList.push_back(std::make_pair(Idx, VNI));
541 // Create a new live ranges with only minimal live segments per def.
543 createSegmentsForValues(NewLR, make_range(SR.vni_begin(), SR.vni_end()));
544 extendSegmentsToUses(NewLR, *Indexes, WorkList, SR);
546 // Move the trimmed ranges back.
547 SR.segments.swap(NewLR.segments);
549 // Remove dead PHI value numbers
550 for (auto VNI : SR.valnos) {
553 const LiveRange::Segment *Segment = SR.getSegmentContaining(VNI->def);
554 assert(Segment != nullptr && "Missing segment for VNI");
555 if (Segment->end != VNI->def.getDeadSlot())
557 if (VNI->isPHIDef()) {
558 // This is a dead PHI. Remove it.
560 SR.removeSegment(*Segment);
561 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
565 DEBUG(dbgs() << "Shrunk: " << SR << '\n');
568 void LiveIntervals::extendToIndices(LiveRange &LR,
569 ArrayRef<SlotIndex> Indices) {
570 assert(LRCalc && "LRCalc not initialized.");
571 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
572 for (unsigned i = 0, e = Indices.size(); i != e; ++i)
573 LRCalc->extend(LR, Indices[i]);
576 void LiveIntervals::pruneValue(LiveRange &LR, SlotIndex Kill,
577 SmallVectorImpl<SlotIndex> *EndPoints) {
578 LiveQueryResult LRQ = LR.Query(Kill);
579 VNInfo *VNI = LRQ.valueOutOrDead();
583 MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill);
584 SlotIndex MBBEnd = Indexes->getMBBEndIdx(KillMBB);
586 // If VNI isn't live out from KillMBB, the value is trivially pruned.
587 if (LRQ.endPoint() < MBBEnd) {
588 LR.removeSegment(Kill, LRQ.endPoint());
589 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
593 // VNI is live out of KillMBB.
594 LR.removeSegment(Kill, MBBEnd);
595 if (EndPoints) EndPoints->push_back(MBBEnd);
597 // Find all blocks that are reachable from KillMBB without leaving VNI's live
598 // range. It is possible that KillMBB itself is reachable, so start a DFS
599 // from each successor.
600 typedef SmallPtrSet<MachineBasicBlock*, 9> VisitedTy;
602 for (MachineBasicBlock::succ_iterator
603 SuccI = KillMBB->succ_begin(), SuccE = KillMBB->succ_end();
604 SuccI != SuccE; ++SuccI) {
605 for (df_ext_iterator<MachineBasicBlock*, VisitedTy>
606 I = df_ext_begin(*SuccI, Visited), E = df_ext_end(*SuccI, Visited);
608 MachineBasicBlock *MBB = *I;
610 // Check if VNI is live in to MBB.
611 SlotIndex MBBStart, MBBEnd;
612 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);
613 LiveQueryResult LRQ = LR.Query(MBBStart);
614 if (LRQ.valueIn() != VNI) {
615 // This block isn't part of the VNI segment. Prune the search.
620 // Prune the search if VNI is killed in MBB.
621 if (LRQ.endPoint() < MBBEnd) {
622 LR.removeSegment(MBBStart, LRQ.endPoint());
623 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
628 // VNI is live through MBB.
629 LR.removeSegment(MBBStart, MBBEnd);
630 if (EndPoints) EndPoints->push_back(MBBEnd);
636 //===----------------------------------------------------------------------===//
637 // Register allocator hooks.
640 void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
641 // Keep track of regunit ranges.
642 SmallVector<std::pair<const LiveRange*, LiveRange::const_iterator>, 8> RU;
643 // Keep track of subregister ranges.
644 SmallVector<std::pair<const LiveInterval::SubRange*,
645 LiveRange::const_iterator>, 4> SRs;
647 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
648 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
649 if (MRI->reg_nodbg_empty(Reg))
651 const LiveInterval &LI = getInterval(Reg);
655 // Find the regunit intervals for the assigned register. They may overlap
656 // the virtual register live range, cancelling any kills.
658 for (MCRegUnitIterator Units(VRM->getPhys(Reg), TRI); Units.isValid();
660 const LiveRange &RURange = getRegUnit(*Units);
663 RU.push_back(std::make_pair(&RURange, RURange.find(LI.begin()->end)));
666 if (MRI->subRegLivenessEnabled()) {
668 for (const LiveInterval::SubRange &SR : LI.subranges()) {
669 SRs.push_back(std::make_pair(&SR, SR.find(LI.begin()->end)));
673 // Every instruction that kills Reg corresponds to a segment range end
675 for (LiveInterval::const_iterator RI = LI.begin(), RE = LI.end(); RI != RE;
677 // A block index indicates an MBB edge.
678 if (RI->end.isBlock())
680 MachineInstr *MI = getInstructionFromIndex(RI->end);
684 // Check if any of the regunits are live beyond the end of RI. That could
685 // happen when a physreg is defined as a copy of a virtreg:
687 // %EAX = COPY %vreg5
688 // FOO %vreg5 <--- MI, cancel kill because %EAX is live.
691 // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX.
692 for (auto &RUP : RU) {
693 const LiveRange &RURange = *RUP.first;
694 LiveRange::const_iterator &I = RUP.second;
695 if (I == RURange.end())
697 I = RURange.advanceTo(I, RI->end);
698 if (I == RURange.end() || I->start >= RI->end)
700 // I is overlapping RI.
704 if (MRI->subRegLivenessEnabled()) {
705 // When reading a partial undefined value we must not add a kill flag.
706 // The regalloc might have used the undef lane for something else.
708 // %vreg1 = ... ; R32: %vreg1
709 // %vreg2:high16 = ... ; R64: %vreg2
710 // = read %vreg2<kill> ; R64: %vreg2
711 // = read %vreg1 ; R32: %vreg1
712 // The <kill> flag is correct for %vreg2, but the register allocator may
713 // assign R0L to %vreg1, and R0 to %vreg2 because the low 32bits of R0
714 // are actually never written by %vreg2. After assignment the <kill>
715 // flag at the read instruction is invalid.
716 unsigned DefinedLanesMask;
718 // Compute a mask of lanes that are defined.
719 DefinedLanesMask = 0;
720 for (auto &SRP : SRs) {
721 const LiveInterval::SubRange &SR = *SRP.first;
722 LiveRange::const_iterator &I = SRP.second;
725 I = SR.advanceTo(I, RI->end);
726 if (I == SR.end() || I->start >= RI->end)
728 // I is overlapping RI
729 DefinedLanesMask |= SR.LaneMask;
732 DefinedLanesMask = ~0u;
734 bool IsFullWrite = false;
735 for (const MachineOperand &MO : MI->operands()) {
736 if (!MO.isReg() || MO.getReg() != Reg)
739 // Reading any undefined lanes?
740 unsigned UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
741 if ((UseMask & ~DefinedLanesMask) != 0)
743 } else if (MO.getSubReg() == 0) {
744 // Writing to the full register?
750 // If an instruction writes to a subregister, a new segment starts in
751 // the LiveInterval. But as this is only overriding part of the register
752 // adding kill-flags is not correct here after registers have been
755 // Next segment has to be adjacent in the subregister write case.
756 LiveRange::const_iterator N = std::next(RI);
757 if (N != LI.end() && N->start == RI->end)
762 MI->addRegisterKilled(Reg, nullptr);
765 MI->clearRegisterKills(Reg, nullptr);
771 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
772 // A local live range must be fully contained inside the block, meaning it is
773 // defined and killed at instructions, not at block boundaries. It is not
774 // live in or or out of any block.
776 // It is technically possible to have a PHI-defined live range identical to a
777 // single block, but we are going to return false in that case.
779 SlotIndex Start = LI.beginIndex();
783 SlotIndex Stop = LI.endIndex();
787 // getMBBFromIndex doesn't need to search the MBB table when both indexes
788 // belong to proper instructions.
789 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
790 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
791 return MBB1 == MBB2 ? MBB1 : nullptr;
795 LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
796 for (const VNInfo *PHI : LI.valnos) {
797 if (PHI->isUnused() || !PHI->isPHIDef())
799 const MachineBasicBlock *PHIMBB = getMBBFromIndex(PHI->def);
800 // Conservatively return true instead of scanning huge predecessor lists.
801 if (PHIMBB->pred_size() > 100)
803 for (MachineBasicBlock::const_pred_iterator
804 PI = PHIMBB->pred_begin(), PE = PHIMBB->pred_end(); PI != PE; ++PI)
805 if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(*PI)))
812 LiveIntervals::getSpillWeight(bool isDef, bool isUse,
813 const MachineBlockFrequencyInfo *MBFI,
814 const MachineInstr *MI) {
815 BlockFrequency Freq = MBFI->getBlockFreq(MI->getParent());
816 const float Scale = 1.0f / MBFI->getEntryFreq();
817 return (isDef + isUse) * (Freq.getFrequency() * Scale);
821 LiveIntervals::addSegmentToEndOfBlock(unsigned reg, MachineInstr* startInst) {
822 LiveInterval& Interval = createEmptyInterval(reg);
823 VNInfo* VN = Interval.getNextValue(
824 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
825 getVNInfoAllocator());
826 LiveRange::Segment S(
827 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
828 getMBBEndIdx(startInst->getParent()), VN);
829 Interval.addSegment(S);
835 //===----------------------------------------------------------------------===//
836 // Register mask functions
837 //===----------------------------------------------------------------------===//
839 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
840 BitVector &UsableRegs) {
843 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
845 // Use a smaller arrays for local live ranges.
846 ArrayRef<SlotIndex> Slots;
847 ArrayRef<const uint32_t*> Bits;
848 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
849 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
850 Bits = getRegMaskBitsInBlock(MBB->getNumber());
852 Slots = getRegMaskSlots();
853 Bits = getRegMaskBits();
856 // We are going to enumerate all the register mask slots contained in LI.
857 // Start with a binary search of RegMaskSlots to find a starting point.
858 ArrayRef<SlotIndex>::iterator SlotI =
859 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
860 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
862 // No slots in range, LI begins after the last call.
868 assert(*SlotI >= LiveI->start);
869 // Loop over all slots overlapping this segment.
870 while (*SlotI < LiveI->end) {
871 // *SlotI overlaps LI. Collect mask bits.
873 // This is the first overlap. Initialize UsableRegs to all ones.
875 UsableRegs.resize(TRI->getNumRegs(), true);
878 // Remove usable registers clobbered by this mask.
879 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
880 if (++SlotI == SlotE)
883 // *SlotI is beyond the current LI segment.
884 LiveI = LI.advanceTo(LiveI, *SlotI);
887 // Advance SlotI until it overlaps.
888 while (*SlotI < LiveI->start)
889 if (++SlotI == SlotE)
894 //===----------------------------------------------------------------------===//
895 // IntervalUpdate class.
896 //===----------------------------------------------------------------------===//
898 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
899 class LiveIntervals::HMEditor {
902 const MachineRegisterInfo& MRI;
903 const TargetRegisterInfo& TRI;
906 SmallPtrSet<LiveRange*, 8> Updated;
910 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
911 const TargetRegisterInfo& TRI,
912 SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)
913 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),
914 UpdateFlags(UpdateFlags) {}
916 // FIXME: UpdateFlags is a workaround that creates live intervals for all
917 // physregs, even those that aren't needed for regalloc, in order to update
918 // kill flags. This is wasteful. Eventually, LiveVariables will strip all kill
919 // flags, and postRA passes will use a live register utility instead.
920 LiveRange *getRegUnitLI(unsigned Unit) {
922 return &LIS.getRegUnit(Unit);
923 return LIS.getCachedRegUnit(Unit);
926 /// Update all live ranges touched by MI, assuming a move from OldIdx to
928 void updateAllRanges(MachineInstr *MI) {
929 DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " << *MI);
930 bool hasRegMask = false;
931 for (MachineOperand &MO : MI->operands()) {
936 // Aggressively clear all kill flags.
937 // They are reinserted by VirtRegRewriter.
941 unsigned Reg = MO.getReg();
944 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
945 LiveInterval &LI = LIS.getInterval(Reg);
946 if (LI.hasSubRanges()) {
947 unsigned SubReg = MO.getSubReg();
948 unsigned LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
949 for (LiveInterval::SubRange &S : LI.subranges()) {
950 if ((S.LaneMask & LaneMask) == 0)
952 updateRange(S, Reg, S.LaneMask);
955 updateRange(LI, Reg, 0);
959 // For physregs, only update the regunits that actually have a
960 // precomputed live range.
961 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
962 if (LiveRange *LR = getRegUnitLI(*Units))
963 updateRange(*LR, *Units, 0);
966 updateRegMaskSlots();
970 /// Update a single live range, assuming an instruction has been moved from
971 /// OldIdx to NewIdx.
972 void updateRange(LiveRange &LR, unsigned Reg, unsigned LaneMask) {
973 if (!Updated.insert(&LR).second)
977 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
978 dbgs() << PrintReg(Reg);
980 dbgs() << format(" L%04X", LaneMask);
982 dbgs() << PrintRegUnit(Reg, &TRI);
984 dbgs() << ":\t" << LR << '\n';
986 if (SlotIndex::isEarlierInstr(OldIdx, NewIdx))
989 handleMoveUp(LR, Reg, LaneMask);
990 DEBUG(dbgs() << " -->\t" << LR << '\n');
994 /// Update LR to reflect an instruction has been moved downwards from OldIdx
997 /// 1. Live def at OldIdx:
998 /// Move def to NewIdx, assert endpoint after NewIdx.
1000 /// 2. Live def at OldIdx, killed at NewIdx:
1001 /// Change to dead def at NewIdx.
1002 /// (Happens when bundling def+kill together).
1004 /// 3. Dead def at OldIdx:
1005 /// Move def to NewIdx, possibly across another live value.
1007 /// 4. Def at OldIdx AND at NewIdx:
1008 /// Remove segment [OldIdx;NewIdx) and value defined at OldIdx.
1009 /// (Happens when bundling multiple defs together).
1011 /// 5. Value read at OldIdx, killed before NewIdx:
1012 /// Extend kill to NewIdx.
1014 void handleMoveDown(LiveRange &LR) {
1015 // First look for a kill at OldIdx.
1016 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
1017 LiveRange::iterator E = LR.end();
1018 // Is LR even live at OldIdx?
1019 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
1022 // Handle a live-in value.
1023 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1024 bool isKill = SlotIndex::isSameInstr(OldIdx, I->end);
1025 // If the live-in value already extends to NewIdx, there is nothing to do.
1026 if (!SlotIndex::isEarlierInstr(I->end, NewIdx))
1028 // Aggressively remove all kill flags from the old kill point.
1029 // Kill flags shouldn't be used while live intervals exist, they will be
1030 // reinserted by VirtRegRewriter.
1031 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(I->end))
1032 for (MIBundleOperands MO(KillMI); MO.isValid(); ++MO)
1033 if (MO->isReg() && MO->isUse())
1034 MO->setIsKill(false);
1035 // Adjust I->end to reach NewIdx. This may temporarily make LR invalid by
1036 // overlapping ranges. Case 5 above.
1037 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1038 // If this was a kill, there may also be a def. Otherwise we're done.
1044 // Check for a def at OldIdx.
1045 if (I == E || !SlotIndex::isSameInstr(OldIdx, I->start))
1047 // We have a def at OldIdx.
1048 VNInfo *DefVNI = I->valno;
1049 assert(DefVNI->def == I->start && "Inconsistent def");
1050 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1051 // If the defined value extends beyond NewIdx, just move the def down.
1052 // This is case 1 above.
1053 if (SlotIndex::isEarlierInstr(NewIdx, I->end)) {
1054 I->start = DefVNI->def;
1057 // The remaining possibilities are now:
1058 // 2. Live def at OldIdx, killed at NewIdx: isSameInstr(I->end, NewIdx).
1059 // 3. Dead def at OldIdx: I->end = OldIdx.getDeadSlot().
1060 // In either case, it is possible that there is an existing def at NewIdx.
1061 assert((I->end == OldIdx.getDeadSlot() ||
1062 SlotIndex::isSameInstr(I->end, NewIdx)) &&
1063 "Cannot move def below kill");
1064 LiveRange::iterator NewI = LR.advanceTo(I, NewIdx.getRegSlot());
1065 if (NewI != E && SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1066 // There is an existing def at NewIdx, case 4 above. The def at OldIdx is
1067 // coalesced into that value.
1068 assert(NewI->valno != DefVNI && "Multiple defs of value?");
1069 LR.removeValNo(DefVNI);
1072 // There was no existing def at NewIdx. Turn *I into a dead def at NewIdx.
1073 // If the def at OldIdx was dead, we allow it to be moved across other LR
1074 // values. The new range should be placed immediately before NewI, move any
1075 // intermediate ranges up.
1076 assert(NewI != I && "Inconsistent iterators");
1077 std::copy(std::next(I), NewI, I);
1079 = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1082 /// Update LR to reflect an instruction has been moved upwards from OldIdx
1085 /// 1. Live def at OldIdx:
1086 /// Hoist def to NewIdx.
1088 /// 2. Dead def at OldIdx:
1089 /// Hoist def+end to NewIdx, possibly move across other values.
1091 /// 3. Dead def at OldIdx AND existing def at NewIdx:
1092 /// Remove value defined at OldIdx, coalescing it with existing value.
1094 /// 4. Live def at OldIdx AND existing def at NewIdx:
1095 /// Remove value defined at NewIdx, hoist OldIdx def to NewIdx.
1096 /// (Happens when bundling multiple defs together).
1098 /// 5. Value killed at OldIdx:
1099 /// Hoist kill to NewIdx, then scan for last kill between NewIdx and
1102 void handleMoveUp(LiveRange &LR, unsigned Reg, unsigned LaneMask) {
1103 // First look for a kill at OldIdx.
1104 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
1105 LiveRange::iterator E = LR.end();
1106 // Is LR even live at OldIdx?
1107 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
1110 // Handle a live-in value.
1111 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1112 // If the live-in value isn't killed here, there is nothing to do.
1113 if (!SlotIndex::isSameInstr(OldIdx, I->end))
1115 // Adjust I->end to end at NewIdx. If we are hoisting a kill above
1116 // another use, we need to search for that use. Case 5 above.
1117 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1119 // If OldIdx also defines a value, there couldn't have been another use.
1120 if (I == E || !SlotIndex::isSameInstr(I->start, OldIdx)) {
1121 // No def, search for the new kill.
1122 // This can never be an early clobber kill since there is no def.
1123 std::prev(I)->end = findLastUseBefore(Reg, LaneMask).getRegSlot();
1128 // Now deal with the def at OldIdx.
1129 assert(I != E && SlotIndex::isSameInstr(I->start, OldIdx) && "No def?");
1130 VNInfo *DefVNI = I->valno;
1131 assert(DefVNI->def == I->start && "Inconsistent def");
1132 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1134 // Check for an existing def at NewIdx.
1135 LiveRange::iterator NewI = LR.find(NewIdx.getRegSlot());
1136 if (SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1137 assert(NewI->valno != DefVNI && "Same value defined more than once?");
1138 // There is an existing def at NewIdx.
1139 if (I->end.isDead()) {
1140 // Case 3: Remove the dead def at OldIdx.
1141 LR.removeValNo(DefVNI);
1144 // Case 4: Replace def at NewIdx with live def at OldIdx.
1145 I->start = DefVNI->def;
1146 LR.removeValNo(NewI->valno);
1150 // There is no existing def at NewIdx. Hoist DefVNI.
1151 if (!I->end.isDead()) {
1152 // Leave the end point of a live def.
1153 I->start = DefVNI->def;
1157 // DefVNI is a dead def. It may have been moved across other values in LR,
1158 // so move I up to NewI. Slide [NewI;I) down one position.
1159 std::copy_backward(NewI, I, std::next(I));
1160 *NewI = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1163 void updateRegMaskSlots() {
1164 SmallVectorImpl<SlotIndex>::iterator RI =
1165 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1167 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&
1168 "No RegMask at OldIdx.");
1169 *RI = NewIdx.getRegSlot();
1170 assert((RI == LIS.RegMaskSlots.begin() ||
1171 SlotIndex::isEarlierInstr(*std::prev(RI), *RI)) &&
1172 "Cannot move regmask instruction above another call");
1173 assert((std::next(RI) == LIS.RegMaskSlots.end() ||
1174 SlotIndex::isEarlierInstr(*RI, *std::next(RI))) &&
1175 "Cannot move regmask instruction below another call");
1178 // Return the last use of reg between NewIdx and OldIdx.
1179 SlotIndex findLastUseBefore(unsigned Reg, unsigned LaneMask) {
1181 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1182 SlotIndex LastUse = NewIdx;
1183 for (MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
1184 unsigned SubReg = MO.getSubReg();
1185 if (SubReg != 0 && LaneMask != 0
1186 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask) == 0)
1189 const MachineInstr *MI = MO.getParent();
1190 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1191 if (InstSlot > LastUse && InstSlot < OldIdx)
1197 // This is a regunit interval, so scanning the use list could be very
1198 // expensive. Scan upwards from OldIdx instead.
1199 assert(NewIdx < OldIdx && "Expected upwards move");
1200 SlotIndexes *Indexes = LIS.getSlotIndexes();
1201 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(NewIdx);
1203 // OldIdx may not correspond to an instruction any longer, so set MII to
1204 // point to the next instruction after OldIdx, or MBB->end().
1205 MachineBasicBlock::iterator MII = MBB->end();
1206 if (MachineInstr *MI = Indexes->getInstructionFromIndex(
1207 Indexes->getNextNonNullIndex(OldIdx)))
1208 if (MI->getParent() == MBB)
1211 MachineBasicBlock::iterator Begin = MBB->begin();
1212 while (MII != Begin) {
1213 if ((--MII)->isDebugValue())
1215 SlotIndex Idx = Indexes->getInstructionIndex(MII);
1217 // Stop searching when NewIdx is reached.
1218 if (!SlotIndex::isEarlierInstr(NewIdx, Idx))
1221 // Check if MII uses Reg.
1222 for (MIBundleOperands MO(MII); MO.isValid(); ++MO)
1224 TargetRegisterInfo::isPhysicalRegister(MO->getReg()) &&
1225 TRI.hasRegUnit(MO->getReg(), Reg))
1228 // Didn't reach NewIdx. It must be the first instruction in the block.
1233 void LiveIntervals::handleMove(MachineInstr* MI, bool UpdateFlags) {
1234 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1235 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1236 Indexes->removeMachineInstrFromMaps(MI);
1237 SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
1238 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1239 OldIndex < getMBBEndIdx(MI->getParent()) &&
1240 "Cannot handle moves across basic block boundaries.");
1242 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1243 HME.updateAllRanges(MI);
1246 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1247 MachineInstr* BundleStart,
1249 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1250 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1251 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1252 HME.updateAllRanges(MI);
1255 void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
1256 const MachineBasicBlock::iterator End,
1257 const SlotIndex endIdx,
1258 LiveRange &LR, const unsigned Reg,
1259 const unsigned LaneMask) {
1260 LiveInterval::iterator LII = LR.find(endIdx);
1261 SlotIndex lastUseIdx;
1262 if (LII != LR.end() && LII->start < endIdx)
1263 lastUseIdx = LII->end;
1267 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1269 MachineInstr *MI = I;
1270 if (MI->isDebugValue())
1273 SlotIndex instrIdx = getInstructionIndex(MI);
1274 bool isStartValid = getInstructionFromIndex(LII->start);
1275 bool isEndValid = getInstructionFromIndex(LII->end);
1277 // FIXME: This doesn't currently handle early-clobber or multiple removed
1278 // defs inside of the region to repair.
1279 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
1280 OE = MI->operands_end(); OI != OE; ++OI) {
1281 const MachineOperand &MO = *OI;
1282 if (!MO.isReg() || MO.getReg() != Reg)
1285 unsigned SubReg = MO.getSubReg();
1286 unsigned Mask = TRI->getSubRegIndexLaneMask(SubReg);
1287 if ((Mask & LaneMask) == 0)
1291 if (!isStartValid) {
1292 if (LII->end.isDead()) {
1293 SlotIndex prevStart;
1294 if (LII != LR.begin())
1295 prevStart = std::prev(LII)->start;
1297 // FIXME: This could be more efficient if there was a
1298 // removeSegment method that returned an iterator.
1299 LR.removeSegment(*LII, true);
1300 if (prevStart.isValid())
1301 LII = LR.find(prevStart);
1305 LII->start = instrIdx.getRegSlot();
1306 LII->valno->def = instrIdx.getRegSlot();
1307 if (MO.getSubReg() && !MO.isUndef())
1308 lastUseIdx = instrIdx.getRegSlot();
1310 lastUseIdx = SlotIndex();
1315 if (!lastUseIdx.isValid()) {
1316 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1317 LiveRange::Segment S(instrIdx.getRegSlot(),
1318 instrIdx.getDeadSlot(), VNI);
1319 LII = LR.addSegment(S);
1320 } else if (LII->start != instrIdx.getRegSlot()) {
1321 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1322 LiveRange::Segment S(instrIdx.getRegSlot(), lastUseIdx, VNI);
1323 LII = LR.addSegment(S);
1326 if (MO.getSubReg() && !MO.isUndef())
1327 lastUseIdx = instrIdx.getRegSlot();
1329 lastUseIdx = SlotIndex();
1330 } else if (MO.isUse()) {
1331 // FIXME: This should probably be handled outside of this branch,
1332 // either as part of the def case (for defs inside of the region) or
1333 // after the loop over the region.
1334 if (!isEndValid && !LII->end.isBlock())
1335 LII->end = instrIdx.getRegSlot();
1336 if (!lastUseIdx.isValid())
1337 lastUseIdx = instrIdx.getRegSlot();
1344 LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
1345 MachineBasicBlock::iterator Begin,
1346 MachineBasicBlock::iterator End,
1347 ArrayRef<unsigned> OrigRegs) {
1348 // Find anchor points, which are at the beginning/end of blocks or at
1349 // instructions that already have indexes.
1350 while (Begin != MBB->begin() && !Indexes->hasIndex(Begin))
1352 while (End != MBB->end() && !Indexes->hasIndex(End))
1356 if (End == MBB->end())
1357 endIdx = getMBBEndIdx(MBB).getPrevSlot();
1359 endIdx = getInstructionIndex(End);
1361 Indexes->repairIndexesInRange(MBB, Begin, End);
1363 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1365 MachineInstr *MI = I;
1366 if (MI->isDebugValue())
1368 for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
1369 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
1371 TargetRegisterInfo::isVirtualRegister(MOI->getReg()) &&
1372 !hasInterval(MOI->getReg())) {
1373 createAndComputeVirtRegInterval(MOI->getReg());
1378 for (unsigned i = 0, e = OrigRegs.size(); i != e; ++i) {
1379 unsigned Reg = OrigRegs[i];
1380 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1383 LiveInterval &LI = getInterval(Reg);
1384 // FIXME: Should we support undefs that gain defs?
1385 if (!LI.hasAtLeastOneValue())
1388 for (LiveInterval::SubRange &S : LI.subranges()) {
1389 repairOldRegInRange(Begin, End, endIdx, S, Reg, S.LaneMask);
1391 repairOldRegInRange(Begin, End, endIdx, LI, Reg);
1395 void LiveIntervals::removePhysRegDefAt(unsigned Reg, SlotIndex Pos) {
1396 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
1397 if (LiveRange *LR = getCachedRegUnit(*Units))
1398 if (VNInfo *VNI = LR->getVNInfoAt(Pos))
1399 LR->removeValNo(VNI);
1403 void LiveIntervals::removeVRegDefAt(LiveInterval &LI, SlotIndex Pos) {
1404 VNInfo *VNI = LI.getVNInfoAt(Pos);
1407 LI.removeValNo(VNI);
1409 // Also remove the value in subranges.
1410 for (LiveInterval::SubRange &S : LI.subranges()) {
1411 if (VNInfo *SVNI = S.getVNInfoAt(Pos))
1412 S.removeValNo(SVNI);
1414 LI.removeEmptySubRanges();
1417 void LiveIntervals::splitSeparateComponents(LiveInterval &LI,
1418 SmallVectorImpl<LiveInterval*> &SplitLIs) {
1419 ConnectedVNInfoEqClasses ConEQ(*this);
1420 unsigned NumComp = ConEQ.Classify(&LI);
1423 DEBUG(dbgs() << " Split " << NumComp << " components: " << LI << '\n');
1424 unsigned Reg = LI.reg;
1425 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
1426 for (unsigned I = 1; I < NumComp; ++I) {
1427 unsigned NewVReg = MRI->createVirtualRegister(RegClass);
1428 LiveInterval &NewLI = createEmptyInterval(NewVReg);
1429 SplitLIs.push_back(&NewLI);
1431 ConEQ.Distribute(LI, SplitLIs.data(), *MRI);