1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LLVMTargetMachine class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Pass.h"
17 #include "llvm/Assembly/PrintModulePass.h"
18 #include "llvm/Analysis/LoopPass.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/Collector.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Transforms/Scalar.h"
23 #include "llvm/Support/CommandLine.h"
26 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
27 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
28 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
29 cl::desc("Print LLVM IR input to isel pass"));
30 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
31 cl::desc("Dump emitter generated instructions as assembly"));
32 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
33 cl::desc("Dump garbage collector data"));
35 // Hidden options to help debugging
37 EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
38 cl::desc("Perform sinking on machine code"));
40 PerformLICM("machine-licm",
41 cl::init(false), cl::Hidden,
42 cl::desc("Perform loop-invariant code motion on machine code"));
45 LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
47 CodeGenFileType FileType,
49 // Standard LLVM-Level Passes.
51 // Run loop strength reduction before anything else.
53 PM.add(createLoopStrengthReducePass(getTargetLowering()));
55 PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
58 PM.add(createGCLoweringPass());
60 if (!ExceptionHandling)
61 PM.add(createLowerInvokePass(getTargetLowering()));
63 // Make sure that no unreachable blocks are instruction selected.
64 PM.add(createUnreachableBlockEliminationPass());
67 PM.add(createCodeGenPreparePass(getTargetLowering()));
70 PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel *** \n",
73 // Ask the target for an isel.
74 if (addInstSelector(PM, Fast))
75 return FileModel::Error;
77 // Print the instruction selected machine code...
79 PM.add(createMachineFunctionPrinterPass(cerr));
82 PM.add(createMachineLICMPass());
85 PM.add(createMachineSinkingPass());
87 // Perform register allocation to convert to a concrete x86 representation
88 PM.add(createRegisterAllocator());
91 PM.add(createMachineFunctionPrinterPass(cerr));
93 PM.add(createLowerSubregsPass());
95 if (PrintMachineCode) // Print the subreg lowered code
96 PM.add(createMachineFunctionPrinterPass(cerr));
98 // Run post-ra passes.
99 if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
100 PM.add(createMachineFunctionPrinterPass(cerr));
102 // Insert prolog/epilog code. Eliminate abstract frame index references...
103 PM.add(createPrologEpilogCodeInserter());
105 // Second pass scheduler.
107 PM.add(createPostRAScheduler());
109 // Branch folding must be run after regalloc and prolog/epilog insertion.
111 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
113 PM.add(createGCMachineCodeAnalysisPass());
114 if (PrintMachineCode)
115 PM.add(createMachineFunctionPrinterPass(cerr));
118 PM.add(createCollectorMetadataPrinter(*cerr));
120 // Fold redundant debug labels.
121 PM.add(createDebugLabelFoldingPass());
123 if (PrintMachineCode) // Print the register-allocated code
124 PM.add(createMachineFunctionPrinterPass(cerr));
126 if (addPreEmitPass(PM, Fast) && PrintMachineCode)
127 PM.add(createMachineFunctionPrinterPass(cerr));
132 case TargetMachine::AssemblyFile:
133 if (addAssemblyEmitter(PM, Fast, Out))
134 return FileModel::Error;
135 return FileModel::AsmFile;
136 case TargetMachine::ObjectFile:
137 if (getMachOWriterInfo())
138 return FileModel::MachOFile;
139 else if (getELFWriterInfo())
140 return FileModel::ElfFile;
143 return FileModel::Error;
146 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
147 /// be split up (e.g., to add an object writer pass), this method can be used to
148 /// finish up adding passes to emit the file, if necessary.
149 bool LLVMTargetMachine::addPassesToEmitFileFinish(FunctionPassManager &PM,
150 MachineCodeEmitter *MCE,
153 addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
155 PM.add(createCollectorMetadataDeleter());
157 // Delete machine code for this function
158 PM.add(createMachineCodeDeleter());
160 return false; // success!
163 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
164 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
165 /// actually outputting the machine code and resolving things like the address
166 /// of functions. This method should returns true if machine code emission is
169 bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
170 MachineCodeEmitter &MCE,
172 // Standard LLVM-Level Passes.
174 // Run loop strength reduction before anything else.
176 PM.add(createLoopStrengthReducePass(getTargetLowering()));
178 PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
181 PM.add(createGCLoweringPass());
183 // FIXME: Implement the invoke/unwind instructions!
184 PM.add(createLowerInvokePass(getTargetLowering()));
186 // Make sure that no unreachable blocks are instruction selected.
187 PM.add(createUnreachableBlockEliminationPass());
190 PM.add(createCodeGenPreparePass(getTargetLowering()));
193 PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel *** \n",
196 // Ask the target for an isel.
197 if (addInstSelector(PM, Fast))
200 // Print the instruction selected machine code...
201 if (PrintMachineCode)
202 PM.add(createMachineFunctionPrinterPass(cerr));
205 PM.add(createMachineLICMPass());
208 PM.add(createMachineSinkingPass());
210 // Perform register allocation to convert to a concrete x86 representation
211 PM.add(createRegisterAllocator());
213 if (PrintMachineCode)
214 PM.add(createMachineFunctionPrinterPass(cerr));
216 PM.add(createLowerSubregsPass());
218 if (PrintMachineCode) // Print the subreg lowered code
219 PM.add(createMachineFunctionPrinterPass(cerr));
221 // Run post-ra passes.
222 if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
223 PM.add(createMachineFunctionPrinterPass(cerr));
225 // Insert prolog/epilog code. Eliminate abstract frame index references...
226 PM.add(createPrologEpilogCodeInserter());
228 if (PrintMachineCode) // Print the register-allocated code
229 PM.add(createMachineFunctionPrinterPass(cerr));
231 // Second pass scheduler.
233 PM.add(createPostRAScheduler());
235 // Branch folding must be run after regalloc and prolog/epilog insertion.
237 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
239 PM.add(createGCMachineCodeAnalysisPass());
240 if (PrintMachineCode)
241 PM.add(createMachineFunctionPrinterPass(cerr));
244 PM.add(createCollectorMetadataPrinter(*cerr));
246 if (addPreEmitPass(PM, Fast) && PrintMachineCode)
247 PM.add(createMachineFunctionPrinterPass(cerr));
249 addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
251 PM.add(createCollectorMetadataDeleter());
253 // Delete machine code for this function
254 PM.add(createMachineCodeDeleter());
256 return false; // success!