1 //===- SchedGraph.cpp - Scheduling Graph Implementation -------------------===//
3 // Scheduling graph based on SSA graph plus extra dependence edges capturing
4 // dependences due to machine resources (machine registers, CC registers, and
7 //===----------------------------------------------------------------------===//
9 #include "SchedGraph.h"
10 #include "llvm/CodeGen/InstrSelection.h"
11 #include "llvm/CodeGen/MachineCodeForInstruction.h"
12 #include "llvm/CodeGen/MachineFunction.h"
13 #include "llvm/Target/TargetRegInfo.h"
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/Target/MachineInstrInfo.h"
16 #include "llvm/Function.h"
17 #include "llvm/iOther.h"
18 #include "Support/StringExtras.h"
19 #include "Support/STLExtras.h"
25 //*********************** Internal Data Structures *************************/
27 // The following two types need to be classes, not typedefs, so we can use
28 // opaque declarations in SchedGraph.h
30 struct RefVec: public vector<pair<SchedGraphNode*, int> > {
31 typedef vector< pair<SchedGraphNode*, int> >:: iterator iterator;
32 typedef vector< pair<SchedGraphNode*, int> >::const_iterator const_iterator;
35 struct RegToRefVecMap: public hash_map<int, RefVec> {
36 typedef hash_map<int, RefVec>:: iterator iterator;
37 typedef hash_map<int, RefVec>::const_iterator const_iterator;
40 struct ValueToDefVecMap: public hash_map<const Instruction*, RefVec> {
41 typedef hash_map<const Instruction*, RefVec>:: iterator iterator;
42 typedef hash_map<const Instruction*, RefVec>::const_iterator const_iterator;
46 // class SchedGraphEdge
50 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
51 SchedGraphNode* _sink,
52 SchedGraphEdgeDepType _depType,
53 unsigned int _depOrderType,
58 depOrderType(_depOrderType),
59 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
62 assert(src != sink && "Self-loop in scheduling graph!");
63 src->addOutEdge(this);
64 sink->addInEdge(this);
69 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
70 SchedGraphNode* _sink,
72 unsigned int _depOrderType,
77 depOrderType(_depOrderType),
78 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
81 assert(src != sink && "Self-loop in scheduling graph!");
82 src->addOutEdge(this);
83 sink->addInEdge(this);
88 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
89 SchedGraphNode* _sink,
91 unsigned int _depOrderType,
95 depType(MachineRegister),
96 depOrderType(_depOrderType),
97 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
98 machineRegNum(_regNum)
100 assert(src != sink && "Self-loop in scheduling graph!");
101 src->addOutEdge(this);
102 sink->addInEdge(this);
107 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
108 SchedGraphNode* _sink,
109 ResourceId _resourceId,
113 depType(MachineResource),
114 depOrderType(NonDataDep),
115 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
116 resourceId(_resourceId)
118 assert(src != sink && "Self-loop in scheduling graph!");
119 src->addOutEdge(this);
120 sink->addInEdge(this);
124 SchedGraphEdge::~SchedGraphEdge()
128 void SchedGraphEdge::dump(int indent) const {
129 cerr << std::string(indent*2, ' ') << *this;
134 // class SchedGraphNode
138 SchedGraphNode::SchedGraphNode(unsigned NID,
139 MachineBasicBlock *mbb,
141 const TargetMachine& Target)
142 : nodeId(NID), MBB(mbb), minstr(mbb ? (*mbb)[indexInBB] : 0),
143 origIndexInBB(indexInBB), latency(0) {
146 MachineOpCode mopCode = minstr->getOpCode();
147 latency = Target.getInstrInfo().hasResultInterlock(mopCode)
148 ? Target.getInstrInfo().minLatency(mopCode)
149 : Target.getInstrInfo().maxLatency(mopCode);
155 SchedGraphNode::~SchedGraphNode()
157 // for each node, delete its out-edges
158 std::for_each(beginOutEdges(), endOutEdges(),
159 deleter<SchedGraphEdge>);
162 void SchedGraphNode::dump(int indent) const {
163 cerr << std::string(indent*2, ' ') << *this;
168 SchedGraphNode::addInEdge(SchedGraphEdge* edge)
170 inEdges.push_back(edge);
175 SchedGraphNode::addOutEdge(SchedGraphEdge* edge)
177 outEdges.push_back(edge);
181 SchedGraphNode::removeInEdge(const SchedGraphEdge* edge)
183 assert(edge->getSink() == this);
185 for (iterator I = beginInEdges(); I != endInEdges(); ++I)
194 SchedGraphNode::removeOutEdge(const SchedGraphEdge* edge)
196 assert(edge->getSrc() == this);
198 for (iterator I = beginOutEdges(); I != endOutEdges(); ++I)
213 SchedGraph::SchedGraph(MachineBasicBlock &mbb, const TargetMachine& target)
220 SchedGraph::~SchedGraph()
222 for (const_iterator I = begin(); I != end(); ++I)
230 SchedGraph::dump() const
232 cerr << " Sched Graph for Basic Block: ";
233 cerr << MBB.getBasicBlock()->getName()
234 << " (" << MBB.getBasicBlock() << ")";
236 cerr << "\n\n Actual Root nodes : ";
237 for (unsigned i=0, N=graphRoot->outEdges.size(); i < N; i++)
238 cerr << graphRoot->outEdges[i]->getSink()->getNodeId()
239 << ((i == N-1)? "" : ", ");
241 cerr << "\n Graph Nodes:\n";
242 for (const_iterator I=begin(); I != end(); ++I)
243 cerr << "\n" << *I->second;
250 SchedGraph::eraseIncomingEdges(SchedGraphNode* node, bool addDummyEdges)
252 // Delete and disconnect all in-edges for the node
253 for (SchedGraphNode::iterator I = node->beginInEdges();
254 I != node->endInEdges(); ++I)
256 SchedGraphNode* srcNode = (*I)->getSrc();
257 srcNode->removeOutEdge(*I);
261 srcNode != getRoot() &&
262 srcNode->beginOutEdges() == srcNode->endOutEdges())
263 { // srcNode has no more out edges, so add an edge to dummy EXIT node
264 assert(node != getLeaf() && "Adding edge that was just removed?");
265 (void) new SchedGraphEdge(srcNode, getLeaf(),
266 SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
270 node->inEdges.clear();
274 SchedGraph::eraseOutgoingEdges(SchedGraphNode* node, bool addDummyEdges)
276 // Delete and disconnect all out-edges for the node
277 for (SchedGraphNode::iterator I = node->beginOutEdges();
278 I != node->endOutEdges(); ++I)
280 SchedGraphNode* sinkNode = (*I)->getSink();
281 sinkNode->removeInEdge(*I);
285 sinkNode != getLeaf() &&
286 sinkNode->beginInEdges() == sinkNode->endInEdges())
287 { //sinkNode has no more in edges, so add an edge from dummy ENTRY node
288 assert(node != getRoot() && "Adding edge that was just removed?");
289 (void) new SchedGraphEdge(getRoot(), sinkNode,
290 SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
294 node->outEdges.clear();
298 SchedGraph::eraseIncidentEdges(SchedGraphNode* node, bool addDummyEdges)
300 this->eraseIncomingEdges(node, addDummyEdges);
301 this->eraseOutgoingEdges(node, addDummyEdges);
306 SchedGraph::addDummyEdges()
308 assert(graphRoot->outEdges.size() == 0);
310 for (const_iterator I=begin(); I != end(); ++I)
312 SchedGraphNode* node = (*I).second;
313 assert(node != graphRoot && node != graphLeaf);
314 if (node->beginInEdges() == node->endInEdges())
315 (void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep,
316 SchedGraphEdge::NonDataDep, 0);
317 if (node->beginOutEdges() == node->endOutEdges())
318 (void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep,
319 SchedGraphEdge::NonDataDep, 0);
325 SchedGraph::addCDEdges(const TerminatorInst* term,
326 const TargetMachine& target)
328 const MachineInstrInfo& mii = target.getInstrInfo();
329 MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
331 // Find the first branch instr in the sequence of machine instrs for term
334 while (! mii.isBranch(termMvec[first]->getOpCode()) &&
335 ! mii.isReturn(termMvec[first]->getOpCode()))
337 assert(first < termMvec.size() &&
338 "No branch instructions for terminator? Ok, but weird!");
339 if (first == termMvec.size())
342 SchedGraphNode* firstBrNode = getGraphNodeForInstr(termMvec[first]);
344 // Add CD edges from each instruction in the sequence to the
345 // *last preceding* branch instr. in the sequence
346 // Use a latency of 0 because we only need to prevent out-of-order issue.
348 for (unsigned i = termMvec.size(); i > first+1; --i)
350 SchedGraphNode* toNode = getGraphNodeForInstr(termMvec[i-1]);
351 assert(toNode && "No node for instr generated for branch/ret?");
353 for (unsigned j = i-1; j != 0; --j)
354 if (mii.isBranch(termMvec[j-1]->getOpCode()) ||
355 mii.isReturn(termMvec[j-1]->getOpCode()))
357 SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]);
358 assert(brNode && "No node for instr generated for branch/ret?");
359 (void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
360 SchedGraphEdge::NonDataDep, 0);
361 break; // only one incoming edge is enough
365 // Add CD edges from each instruction preceding the first branch
366 // to the first branch. Use a latency of 0 as above.
368 for (unsigned i = first; i != 0; --i)
370 SchedGraphNode* fromNode = getGraphNodeForInstr(termMvec[i-1]);
371 assert(fromNode && "No node for instr generated for branch?");
372 (void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
373 SchedGraphEdge::NonDataDep, 0);
376 // Now add CD edges to the first branch instruction in the sequence from
377 // all preceding instructions in the basic block. Use 0 latency again.
379 for (unsigned i=0, N=MBB.size(); i < N; i++)
381 if (MBB[i] == termMvec[first]) // reached the first branch
384 SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
385 if (fromNode == NULL)
386 continue; // dummy instruction, e.g., PHI
388 (void) new SchedGraphEdge(fromNode, firstBrNode,
389 SchedGraphEdge::CtrlDep,
390 SchedGraphEdge::NonDataDep, 0);
392 // If we find any other machine instructions (other than due to
393 // the terminator) that also have delay slots, add an outgoing edge
394 // from the instruction to the instructions in the delay slots.
396 unsigned d = mii.getNumDelaySlots(MBB[i]->getOpCode());
397 assert(i+d < N && "Insufficient delay slots for instruction?");
399 for (unsigned j=1; j <= d; j++)
401 SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
402 assert(toNode && "No node for machine instr in delay slot?");
403 (void) new SchedGraphEdge(fromNode, toNode,
404 SchedGraphEdge::CtrlDep,
405 SchedGraphEdge::NonDataDep, 0);
410 static const int SG_LOAD_REF = 0;
411 static const int SG_STORE_REF = 1;
412 static const int SG_CALL_REF = 2;
414 static const unsigned int SG_DepOrderArray[][3] = {
415 { SchedGraphEdge::NonDataDep,
416 SchedGraphEdge::AntiDep,
417 SchedGraphEdge::AntiDep },
418 { SchedGraphEdge::TrueDep,
419 SchedGraphEdge::OutputDep,
420 SchedGraphEdge::TrueDep | SchedGraphEdge::OutputDep },
421 { SchedGraphEdge::TrueDep,
422 SchedGraphEdge::AntiDep | SchedGraphEdge::OutputDep,
423 SchedGraphEdge::TrueDep | SchedGraphEdge::AntiDep
424 | SchedGraphEdge::OutputDep }
428 // Add a dependence edge between every pair of machine load/store/call
429 // instructions, where at least one is a store or a call.
430 // Use latency 1 just to ensure that memory operations are ordered;
431 // latency does not otherwise matter (true dependences enforce that).
434 SchedGraph::addMemEdges(const vector<SchedGraphNode*>& memNodeVec,
435 const TargetMachine& target)
437 const MachineInstrInfo& mii = target.getInstrInfo();
439 // Instructions in memNodeVec are in execution order within the basic block,
440 // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
442 for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
444 MachineOpCode fromOpCode = memNodeVec[im]->getOpCode();
445 int fromType = mii.isCall(fromOpCode)? SG_CALL_REF
446 : mii.isLoad(fromOpCode)? SG_LOAD_REF
448 for (unsigned jm=im+1; jm < NM; jm++)
450 MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
451 int toType = mii.isCall(toOpCode)? SG_CALL_REF
452 : mii.isLoad(toOpCode)? SG_LOAD_REF
455 if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF)
456 (void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm],
457 SchedGraphEdge::MemoryDep,
458 SG_DepOrderArray[fromType][toType], 1);
463 // Add edges from/to CC reg instrs to/from call instrs.
464 // Essentially this prevents anything that sets or uses a CC reg from being
465 // reordered w.r.t. a call.
466 // Use a latency of 0 because we only need to prevent out-of-order issue,
467 // like with control dependences.
470 SchedGraph::addCallCCEdges(const vector<SchedGraphNode*>& memNodeVec,
471 MachineBasicBlock& bbMvec,
472 const TargetMachine& target)
474 const MachineInstrInfo& mii = target.getInstrInfo();
475 vector<SchedGraphNode*> callNodeVec;
477 // Find the call instruction nodes and put them in a vector.
478 for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
479 if (mii.isCall(memNodeVec[im]->getOpCode()))
480 callNodeVec.push_back(memNodeVec[im]);
482 // Now walk the entire basic block, looking for CC instructions *and*
483 // call instructions, and keep track of the order of the instructions.
484 // Use the call node vec to quickly find earlier and later call nodes
485 // relative to the current CC instruction.
487 int lastCallNodeIdx = -1;
488 for (unsigned i=0, N=bbMvec.size(); i < N; i++)
489 if (mii.isCall(bbMvec[i]->getOpCode()))
492 for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
493 if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
495 assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
497 else if (mii.isCCInstr(bbMvec[i]->getOpCode()))
498 { // Add incoming/outgoing edges from/to preceding/later calls
499 SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
501 for ( ; j <= lastCallNodeIdx; j++)
502 (void) new SchedGraphEdge(callNodeVec[j], ccNode,
503 MachineCCRegsRID, 0);
504 for ( ; j < (int) callNodeVec.size(); j++)
505 (void) new SchedGraphEdge(ccNode, callNodeVec[j],
506 MachineCCRegsRID, 0);
512 SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
513 const TargetMachine& target)
515 // This assumes that such hardwired registers are never allocated
516 // to any LLVM value (since register allocation happens later), i.e.,
517 // any uses or defs of this register have been made explicit!
518 // Also assumes that two registers with different numbers are
521 for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
522 I != regToRefVecMap.end(); ++I)
524 int regNum = (*I).first;
525 RefVec& regRefVec = (*I).second;
527 // regRefVec is ordered by control flow order in the basic block
528 for (unsigned i=0; i < regRefVec.size(); ++i)
530 SchedGraphNode* node = regRefVec[i].first;
531 unsigned int opNum = regRefVec[i].second;
532 bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
534 node->getMachineInstr()->operandIsDefinedAndUsed(opNum);
536 for (unsigned p=0; p < i; ++p)
538 SchedGraphNode* prevNode = regRefVec[p].first;
539 if (prevNode != node)
541 unsigned int prevOpNum = regRefVec[p].second;
543 prevNode->getMachineInstr()->operandIsDefined(prevOpNum);
544 bool prevIsDefAndUse =
545 prevNode->getMachineInstr()->operandIsDefinedAndUsed(prevOpNum);
549 new SchedGraphEdge(prevNode, node, regNum,
550 SchedGraphEdge::OutputDep);
551 if (!prevIsDef || prevIsDefAndUse)
552 new SchedGraphEdge(prevNode, node, regNum,
553 SchedGraphEdge::AntiDep);
557 if (!isDef || isDefAndUse)
558 new SchedGraphEdge(prevNode, node, regNum,
559 SchedGraphEdge::TrueDep);
567 // Adds dependences to/from refNode from/to all other defs
568 // in the basic block. refNode may be a use, a def, or both.
569 // We do not consider other uses because we are not building use-use deps.
572 SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
573 const RefVec& defVec,
574 const Value* defValue,
576 bool refNodeIsDefAndUse,
577 const TargetMachine& target)
579 bool refNodeIsUse = !refNodeIsDef || refNodeIsDefAndUse;
581 // Add true or output dep edges from all def nodes before refNode in BB.
582 // Add anti or output dep edges to all def nodes after refNode.
583 for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I)
585 if ((*I).first == refNode)
586 continue; // Dont add any self-loops
588 if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB())
589 { // (*).first is before refNode
591 (void) new SchedGraphEdge((*I).first, refNode, defValue,
592 SchedGraphEdge::OutputDep);
594 (void) new SchedGraphEdge((*I).first, refNode, defValue,
595 SchedGraphEdge::TrueDep);
598 { // (*).first is after refNode
600 (void) new SchedGraphEdge(refNode, (*I).first, defValue,
601 SchedGraphEdge::OutputDep);
603 (void) new SchedGraphEdge(refNode, (*I).first, defValue,
604 SchedGraphEdge::AntiDep);
611 SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
612 const ValueToDefVecMap& valueToDefVecMap,
613 const TargetMachine& target)
615 SchedGraphNode* node = getGraphNodeForInstr(&MI);
619 // Add edges for all operands of the machine instruction.
621 for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i)
623 switch (MI.getOperandType(i))
625 case MachineOperand::MO_VirtualRegister:
626 case MachineOperand::MO_CCRegister:
627 if (const Instruction* srcI =
628 dyn_cast_or_null<Instruction>(MI.getOperand(i).getVRegValue()))
630 ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
631 if (I != valueToDefVecMap.end())
632 addEdgesForValue(node, I->second, srcI,
633 MI.operandIsDefined(i),
634 MI.operandIsDefinedAndUsed(i), target);
638 case MachineOperand::MO_MachineRegister:
641 case MachineOperand::MO_SignExtendedImmed:
642 case MachineOperand::MO_UnextendedImmed:
643 case MachineOperand::MO_PCRelativeDisp:
644 break; // nothing to do for immediate fields
647 assert(0 && "Unknown machine operand type in SchedGraph builder");
652 // Add edges for values implicitly used by the machine instruction.
653 // Examples include function arguments to a Call instructions or the return
654 // value of a Ret instruction.
656 for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i)
657 if (! MI.implicitRefIsDefined(i) ||
658 MI.implicitRefIsDefinedAndUsed(i))
659 if (const Instruction *srcI =
660 dyn_cast_or_null<Instruction>(MI.getImplicitRef(i)))
662 ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
663 if (I != valueToDefVecMap.end())
664 addEdgesForValue(node, I->second, srcI,
665 MI.implicitRefIsDefined(i),
666 MI.implicitRefIsDefinedAndUsed(i), target);
672 SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
673 SchedGraphNode* node,
674 vector<SchedGraphNode*>& memNodeVec,
675 RegToRefVecMap& regToRefVecMap,
676 ValueToDefVecMap& valueToDefVecMap)
678 const MachineInstrInfo& mii = target.getInstrInfo();
681 MachineOpCode opCode = node->getOpCode();
682 if (mii.isLoad(opCode) || mii.isStore(opCode) || mii.isCall(opCode))
683 memNodeVec.push_back(node);
685 // Collect the register references and value defs. for explicit operands
687 const MachineInstr& minstr = *node->getMachineInstr();
688 for (int i=0, numOps = (int) minstr.getNumOperands(); i < numOps; i++)
690 const MachineOperand& mop = minstr.getOperand(i);
692 // if this references a register other than the hardwired
693 // "zero" register, record the reference.
694 if (mop.getType() == MachineOperand::MO_MachineRegister)
696 int regNum = mop.getMachineRegNum();
697 if (regNum != target.getRegInfo().getZeroRegNum())
698 regToRefVecMap[mop.getMachineRegNum()].push_back(
699 std::make_pair(node, i));
700 continue; // nothing more to do
703 // ignore all other non-def operands
704 if (! minstr.operandIsDefined(i))
707 // We must be defining a value.
708 assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
709 mop.getType() == MachineOperand::MO_CCRegister)
710 && "Do not expect any other kind of operand to be defined!");
712 const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
713 valueToDefVecMap[defInstr].push_back(std::make_pair(node, i));
717 // Collect value defs. for implicit operands. The interface to extract
718 // them assumes they must be virtual registers!
720 for (unsigned i=0, N = minstr.getNumImplicitRefs(); i != N; ++i)
721 if (minstr.implicitRefIsDefined(i))
722 if (const Instruction* defInstr =
723 dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
724 valueToDefVecMap[defInstr].push_back(std::make_pair(node, -i));
729 SchedGraph::buildNodesForBB(const TargetMachine& target,
730 MachineBasicBlock& MBB,
731 vector<SchedGraphNode*>& memNodeVec,
732 RegToRefVecMap& regToRefVecMap,
733 ValueToDefVecMap& valueToDefVecMap)
735 const MachineInstrInfo& mii = target.getInstrInfo();
737 // Build graph nodes for each VM instruction and gather def/use info.
738 // Do both those together in a single pass over all machine instructions.
739 for (unsigned i=0; i < MBB.size(); i++)
740 if (!mii.isDummyPhiInstr(MBB[i]->getOpCode())) {
741 SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
742 noteGraphNodeForInstr(MBB[i], node);
744 // Remember all register references and value defs
745 findDefUseInfoAtInstr(target, node, memNodeVec, regToRefVecMap,
752 SchedGraph::buildGraph(const TargetMachine& target)
754 // Use this data structure to note all machine operands that compute
755 // ordinary LLVM values. These must be computed defs (i.e., instructions).
756 // Note that there may be multiple machine instructions that define
758 ValueToDefVecMap valueToDefVecMap;
760 // Use this data structure to note all memory instructions.
761 // We use this to add memory dependence edges without a second full walk.
763 // vector<const Instruction*> memVec;
764 vector<SchedGraphNode*> memNodeVec;
766 // Use this data structure to note any uses or definitions of
767 // machine registers so we can add edges for those later without
768 // extra passes over the nodes.
769 // The vector holds an ordered list of references to the machine reg,
770 // ordered according to control-flow order. This only works for a
771 // single basic block, hence the assertion. Each reference is identified
772 // by the pair: <node, operand-number>.
774 RegToRefVecMap regToRefVecMap;
776 // Make a dummy root node. We'll add edges to the real roots later.
777 graphRoot = new SchedGraphNode(0, NULL, -1, target);
778 graphLeaf = new SchedGraphNode(1, NULL, -1, target);
780 //----------------------------------------------------------------
781 // First add nodes for all the machine instructions in the basic block
782 // because this greatly simplifies identifying which edges to add.
783 // Do this one VM instruction at a time since the SchedGraphNode needs that.
784 // Also, remember the load/store instructions to add memory deps later.
785 //----------------------------------------------------------------
787 buildNodesForBB(target, MBB, memNodeVec, regToRefVecMap, valueToDefVecMap);
789 //----------------------------------------------------------------
790 // Now add edges for the following (all are incoming edges except (4)):
791 // (1) operands of the machine instruction, including hidden operands
792 // (2) machine register dependences
793 // (3) memory load/store dependences
794 // (3) other resource dependences for the machine instruction, if any
795 // (4) output dependences when multiple machine instructions define the
796 // same value; all must have been generated from a single VM instrn
797 // (5) control dependences to branch instructions generated for the
798 // terminator instruction of the BB. Because of delay slots and
799 // 2-way conditional branches, multiple CD edges are needed
800 // (see addCDEdges for details).
801 // Also, note any uses or defs of machine registers.
803 //----------------------------------------------------------------
805 // First, add edges to the terminator instruction of the basic block.
806 this->addCDEdges(MBB.getBasicBlock()->getTerminator(), target);
808 // Then add memory dep edges: store->load, load->store, and store->store.
809 // Call instructions are treated as both load and store.
810 this->addMemEdges(memNodeVec, target);
812 // Then add edges between call instructions and CC set/use instructions
813 this->addCallCCEdges(memNodeVec, MBB, target);
815 // Then add incoming def-use (SSA) edges for each machine instruction.
816 for (unsigned i=0, N=MBB.size(); i < N; i++)
817 addEdgesForInstruction(*MBB[i], valueToDefVecMap, target);
819 #ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
820 // Then add non-SSA edges for all VM instructions in the block.
821 // We assume that all machine instructions that define a value are
822 // generated from the VM instruction corresponding to that value.
823 // TODO: This could probably be done much more efficiently.
824 for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
825 this->addNonSSAEdgesForValue(*II, target);
826 #endif //NEED_SEPARATE_NONSSA_EDGES_CODE
828 // Then add edges for dependences on machine registers
829 this->addMachineRegEdges(regToRefVecMap, target);
831 // Finally, add edges from the dummy root and to dummy leaf
832 this->addDummyEdges();
837 // class SchedGraphSet
841 SchedGraphSet::SchedGraphSet(const Function* _function,
842 const TargetMachine& target) :
845 buildGraphsForMethod(method, target);
850 SchedGraphSet::~SchedGraphSet()
852 // delete all the graphs
853 for(iterator I = begin(), E = end(); I != E; ++I)
854 delete *I; // destructor is a friend
859 SchedGraphSet::dump() const
861 cerr << "======== Sched graphs for function `" << method->getName()
864 for (const_iterator I=begin(); I != end(); ++I)
867 cerr << "\n====== End graphs for function `" << method->getName()
873 SchedGraphSet::buildGraphsForMethod(const Function *F,
874 const TargetMachine& target)
876 MachineFunction &MF = MachineFunction::get(F);
877 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
878 addGraph(new SchedGraph(*I, target));
882 std::ostream &operator<<(std::ostream &os, const SchedGraphEdge& edge)
884 os << "edge [" << edge.src->getNodeId() << "] -> ["
885 << edge.sink->getNodeId() << "] : ";
887 switch(edge.depType) {
888 case SchedGraphEdge::CtrlDep: os<< "Control Dep"; break;
889 case SchedGraphEdge::ValueDep: os<< "Reg Value " << edge.val; break;
890 case SchedGraphEdge::MemoryDep: os<< "Memory Dep"; break;
891 case SchedGraphEdge::MachineRegister: os<< "Reg " <<edge.machineRegNum;break;
892 case SchedGraphEdge::MachineResource: os<<"Resource "<<edge.resourceId;break;
893 default: assert(0); break;
896 os << " : delay = " << edge.minDelay << "\n";
901 std::ostream &operator<<(std::ostream &os, const SchedGraphNode& node)
903 os << std::string(8, ' ')
904 << "Node " << node.nodeId << " : "
905 << "latency = " << node.latency << "\n" << std::string(12, ' ');
907 if (node.getMachineInstr() == NULL)
908 os << "(Dummy node)\n";
911 os << *node.getMachineInstr() << "\n" << std::string(12, ' ');
912 os << node.inEdges.size() << " Incoming Edges:\n";
913 for (unsigned i=0, N=node.inEdges.size(); i < N; i++)
914 os << std::string(16, ' ') << *node.inEdges[i];
916 os << std::string(12, ' ') << node.outEdges.size()
917 << " Outgoing Edges:\n";
918 for (unsigned i=0, N=node.outEdges.size(); i < N; i++)
919 os << std::string(16, ' ') << *node.outEdges[i];