1 //===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The inline spiller modifies the machine function directly instead of
11 // inserting spills and restores in VirtRegMap.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
17 #include "LiveRangeEdit.h"
18 #include "VirtRegMap.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/LiveStackAnalysis.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineLoopInfo.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/raw_ostream.h"
35 class InlineSpiller : public Spiller {
36 MachineFunctionPass &Pass;
41 MachineDominatorTree &MDT;
42 MachineLoopInfo &Loops;
44 MachineFrameInfo &MFI;
45 MachineRegisterInfo &MRI;
46 const TargetInstrInfo &TII;
47 const TargetRegisterInfo &TRI;
49 // Variables that are valid during spill(), but used by multiple methods.
51 LiveInterval *StackInt;
55 // All registers to spill to StackSlot, including the main register.
56 SmallVector<unsigned, 8> RegsToSpill;
58 // All COPY instructions to/from snippets.
59 // They are ignored since both operands refer to the same stack slot.
60 SmallPtrSet<MachineInstr*, 8> SnippetCopies;
62 // Values that failed to remat at some point.
63 SmallPtrSet<VNInfo*, 8> UsedValues;
65 // Information about a value that was defined by a copy from a sibling
68 // True when all reaching defs were reloads: No spill is necessary.
69 bool AllDefsAreReloads;
71 // The preferred register to spill.
74 // The value of SpillReg that should be spilled.
77 // A defining instruction that is not a sibling copy or a reload, or NULL.
78 // This can be used as a template for rematerialization.
81 SibValueInfo(unsigned Reg, VNInfo *VNI)
82 : AllDefsAreReloads(false), SpillReg(Reg), SpillVNI(VNI), DefMI(0) {}
85 // Values in RegsToSpill defined by sibling copies.
86 typedef DenseMap<VNInfo*, SibValueInfo> SibValueMap;
87 SibValueMap SibValues;
89 // Dead defs generated during spilling.
90 SmallVector<MachineInstr*, 8> DeadDefs;
95 InlineSpiller(MachineFunctionPass &pass,
100 LIS(pass.getAnalysis<LiveIntervals>()),
101 LSS(pass.getAnalysis<LiveStacks>()),
102 AA(&pass.getAnalysis<AliasAnalysis>()),
103 MDT(pass.getAnalysis<MachineDominatorTree>()),
104 Loops(pass.getAnalysis<MachineLoopInfo>()),
106 MFI(*mf.getFrameInfo()),
107 MRI(mf.getRegInfo()),
108 TII(*mf.getTarget().getInstrInfo()),
109 TRI(*mf.getTarget().getRegisterInfo()) {}
111 void spill(LiveRangeEdit &);
114 bool isSnippet(const LiveInterval &SnipLI);
115 void collectRegsToSpill();
117 bool isRegToSpill(unsigned Reg) {
118 return std::find(RegsToSpill.begin(),
119 RegsToSpill.end(), Reg) != RegsToSpill.end();
122 bool isSibling(unsigned Reg);
123 MachineInstr *traceSiblingValue(unsigned, VNInfo*, VNInfo*);
124 void analyzeSiblingValues();
126 bool hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI);
127 void eliminateRedundantSpills(LiveInterval &LI, VNInfo *VNI);
129 void markValueUsed(LiveInterval*, VNInfo*);
130 bool reMaterializeFor(LiveInterval&, MachineBasicBlock::iterator MI);
131 void reMaterializeAll();
133 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
134 bool foldMemoryOperand(MachineBasicBlock::iterator MI,
135 const SmallVectorImpl<unsigned> &Ops,
136 MachineInstr *LoadMI = 0);
137 void insertReload(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
138 void insertSpill(LiveInterval &NewLI, const LiveInterval &OldLI,
139 MachineBasicBlock::iterator MI);
141 void spillAroundUses(unsigned Reg);
146 Spiller *createInlineSpiller(MachineFunctionPass &pass,
149 return new InlineSpiller(pass, mf, vrm);
153 //===----------------------------------------------------------------------===//
155 //===----------------------------------------------------------------------===//
157 // When spilling a virtual register, we also spill any snippets it is connected
158 // to. The snippets are small live ranges that only have a single real use,
159 // leftovers from live range splitting. Spilling them enables memory operand
160 // folding or tightens the live range around the single use.
162 // This minimizes register pressure and maximizes the store-to-load distance for
163 // spill slots which can be important in tight loops.
165 /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
166 /// otherwise return 0.
167 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) {
170 if (MI->getOperand(0).getSubReg() != 0)
172 if (MI->getOperand(1).getSubReg() != 0)
174 if (MI->getOperand(0).getReg() == Reg)
175 return MI->getOperand(1).getReg();
176 if (MI->getOperand(1).getReg() == Reg)
177 return MI->getOperand(0).getReg();
181 /// isSnippet - Identify if a live interval is a snippet that should be spilled.
182 /// It is assumed that SnipLI is a virtual register with the same original as
184 bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
185 unsigned Reg = Edit->getReg();
187 // A snippet is a tiny live range with only a single instruction using it
188 // besides copies to/from Reg or spills/fills. We accept:
190 // %snip = COPY %Reg / FILL fi#
192 // %Reg = COPY %snip / SPILL %snip, fi#
194 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
197 MachineInstr *UseMI = 0;
199 // Check that all uses satisfy our criteria.
200 for (MachineRegisterInfo::reg_nodbg_iterator
201 RI = MRI.reg_nodbg_begin(SnipLI.reg);
202 MachineInstr *MI = RI.skipInstruction();) {
204 // Allow copies to/from Reg.
205 if (isFullCopyOf(MI, Reg))
208 // Allow stack slot loads.
210 if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot)
213 // Allow stack slot stores.
214 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
217 // Allow a single additional instruction.
218 if (UseMI && MI != UseMI)
225 /// collectRegsToSpill - Collect live range snippets that only have a single
227 void InlineSpiller::collectRegsToSpill() {
228 unsigned Reg = Edit->getReg();
230 // Main register always spills.
231 RegsToSpill.assign(1, Reg);
232 SnippetCopies.clear();
234 // Snippets all have the same original, so there can't be any for an original
239 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg);
240 MachineInstr *MI = RI.skipInstruction();) {
241 unsigned SnipReg = isFullCopyOf(MI, Reg);
242 if (!isSibling(SnipReg))
244 LiveInterval &SnipLI = LIS.getInterval(SnipReg);
245 if (!isSnippet(SnipLI))
247 SnippetCopies.insert(MI);
248 if (!isRegToSpill(SnipReg))
249 RegsToSpill.push_back(SnipReg);
251 DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n');
256 //===----------------------------------------------------------------------===//
258 //===----------------------------------------------------------------------===//
260 // After live range splitting, some values to be spilled may be defined by
261 // copies from sibling registers. We trace the sibling copies back to the
262 // original value if it still exists. We need it for rematerialization.
264 // Even when the value can't be rematerialized, we still want to determine if
265 // the value has already been spilled, or we may want to hoist the spill from a
268 bool InlineSpiller::isSibling(unsigned Reg) {
269 return TargetRegisterInfo::isVirtualRegister(Reg) &&
270 VRM.getOriginal(Reg) == Original;
273 /// traceSiblingValue - Trace a value that is about to be spilled back to the
274 /// real defining instructions by looking through sibling copies. Always stay
275 /// within the range of OrigVNI so the registers are known to carry the same
278 /// Determine if the value is defined by all reloads, so spilling isn't
279 /// necessary - the value is already in the stack slot.
281 /// Return a defining instruction that may be a candidate for rematerialization.
283 MachineInstr *InlineSpiller::traceSiblingValue(unsigned UseReg, VNInfo *UseVNI,
285 DEBUG(dbgs() << "Tracing value " << PrintReg(UseReg) << ':'
286 << UseVNI->id << '@' << UseVNI->def << '\n');
287 SmallPtrSet<VNInfo*, 8> Visited;
288 SmallVector<std::pair<unsigned, VNInfo*>, 8> WorkList;
289 WorkList.push_back(std::make_pair(UseReg, UseVNI));
291 // Best spill candidate seen so far. This must dominate UseVNI.
292 SibValueInfo SVI(UseReg, UseVNI);
293 MachineBasicBlock *UseMBB = LIS.getMBBFromIndex(UseVNI->def);
294 unsigned SpillDepth = Loops.getLoopDepth(UseMBB);
295 bool SeenOrigPHI = false; // Original PHI met.
300 tie(Reg, VNI) = WorkList.pop_back_val();
301 if (!Visited.insert(VNI))
304 // Is this value a better spill candidate?
305 if (!isRegToSpill(Reg)) {
306 MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
307 if (MBB != UseMBB && MDT.dominates(MBB, UseMBB)) {
308 // This is a valid spill location dominating UseVNI.
309 // Prefer to spill at a smaller loop depth.
310 unsigned Depth = Loops.getLoopDepth(MBB);
311 if (Depth < SpillDepth) {
312 DEBUG(dbgs() << " spill depth " << Depth << ": " << PrintReg(Reg)
313 << ':' << VNI->id << '@' << VNI->def << '\n');
321 // Trace through PHI-defs created by live range splitting.
322 if (VNI->isPHIDef()) {
323 if (VNI->def == OrigVNI->def) {
324 DEBUG(dbgs() << " orig phi value " << PrintReg(Reg) << ':'
325 << VNI->id << '@' << VNI->def << '\n');
329 // Get values live-out of predecessors.
330 LiveInterval &LI = LIS.getInterval(Reg);
331 MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
332 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
333 PE = MBB->pred_end(); PI != PE; ++PI) {
334 VNInfo *PVNI = LI.getVNInfoAt(LIS.getMBBEndIdx(*PI).getPrevSlot());
336 WorkList.push_back(std::make_pair(Reg, PVNI));
341 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
342 assert(MI && "Missing def");
344 // Trace through sibling copies.
345 if (unsigned SrcReg = isFullCopyOf(MI, Reg)) {
346 if (isSibling(SrcReg)) {
347 LiveInterval &SrcLI = LIS.getInterval(SrcReg);
348 VNInfo *SrcVNI = SrcLI.getVNInfoAt(VNI->def.getUseIndex());
349 assert(SrcVNI && "Copy from non-existing value");
350 DEBUG(dbgs() << " copy of " << PrintReg(SrcReg) << ':'
351 << SrcVNI->id << '@' << SrcVNI->def << '\n');
352 WorkList.push_back(std::make_pair(SrcReg, SrcVNI));
357 // Track reachable reloads.
359 if (Reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) {
360 DEBUG(dbgs() << " reload " << PrintReg(Reg) << ':'
361 << VNI->id << "@" << VNI->def << '\n');
362 SVI.AllDefsAreReloads = true;
366 // We have an 'original' def. Don't record trivial cases.
368 DEBUG(dbgs() << "Not a sibling copy.\n");
372 // Potential remat candidate.
373 DEBUG(dbgs() << " def " << PrintReg(Reg) << ':'
374 << VNI->id << '@' << VNI->def << '\t' << *MI);
376 } while (!WorkList.empty());
378 if (SeenOrigPHI || SVI.DefMI)
379 SVI.AllDefsAreReloads = false;
382 if (SVI.AllDefsAreReloads)
383 dbgs() << "All defs are reloads.\n";
385 dbgs() << "Prefer to spill " << PrintReg(SVI.SpillReg) << ':'
386 << SVI.SpillVNI->id << '@' << SVI.SpillVNI->def << '\n';
388 SibValues.insert(std::make_pair(UseVNI, SVI));
392 /// analyzeSiblingValues - Trace values defined by sibling copies back to
393 /// something that isn't a sibling copy.
395 /// Keep track of values that may be rematerializable.
396 void InlineSpiller::analyzeSiblingValues() {
399 // No siblings at all?
400 if (Edit->getReg() == Original)
403 LiveInterval &OrigLI = LIS.getInterval(Original);
404 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
405 unsigned Reg = RegsToSpill[i];
406 LiveInterval &LI = LIS.getInterval(Reg);
407 for (LiveInterval::const_vni_iterator VI = LI.vni_begin(),
408 VE = LI.vni_end(); VI != VE; ++VI) {
412 MachineInstr *DefMI = 0;
413 // Check possible sibling copies.
414 if (VNI->isPHIDef() || VNI->getCopy()) {
415 VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
416 if (OrigVNI->def != VNI->def)
417 DefMI = traceSiblingValue(Reg, VNI, OrigVNI);
419 if (!DefMI && !VNI->isPHIDef())
420 DefMI = LIS.getInstructionFromIndex(VNI->def);
422 Edit->checkRematerializable(VNI, DefMI, TII, AA);
427 /// hoistSpill - Given a sibling copy that defines a value to be spilled, insert
428 /// a spill at a better location.
429 bool InlineSpiller::hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI) {
430 SlotIndex Idx = LIS.getInstructionIndex(CopyMI);
431 VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getDefIndex());
432 assert(VNI && VNI->def == Idx.getDefIndex() && "Not defined by copy");
433 SibValueMap::const_iterator I = SibValues.find(VNI);
434 if (I == SibValues.end())
437 const SibValueInfo &SVI = I->second;
439 // Let the normal folding code deal with the boring case.
440 if (!SVI.AllDefsAreReloads && SVI.SpillVNI == VNI)
443 // Conservatively extend the stack slot range to the range of the original
444 // value. We may be able to do better with stack slot coloring by being more
446 assert(StackInt && "No stack slot assigned yet.");
447 LiveInterval &OrigLI = LIS.getInterval(Original);
448 VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
449 StackInt->MergeValueInAsValue(OrigLI, OrigVNI, StackInt->getValNumInfo(0));
450 DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": "
451 << *StackInt << '\n');
453 // Already spilled everywhere.
454 if (SVI.AllDefsAreReloads)
457 // We are going to spill SVI.SpillVNI immediately after its def, so clear out
458 // any later spills of the same value.
459 eliminateRedundantSpills(LIS.getInterval(SVI.SpillReg), SVI.SpillVNI);
461 MachineBasicBlock *MBB = LIS.getMBBFromIndex(SVI.SpillVNI->def);
462 MachineBasicBlock::iterator MII;
463 if (SVI.SpillVNI->isPHIDef())
464 MII = MBB->SkipPHIsAndLabels(MBB->begin());
466 MII = LIS.getInstructionFromIndex(SVI.SpillVNI->def);
469 // Insert spill without kill flag immediately after def.
470 TII.storeRegToStackSlot(*MBB, MII, SVI.SpillReg, false, StackSlot,
471 MRI.getRegClass(SVI.SpillReg), &TRI);
472 --MII; // Point to store instruction.
473 LIS.InsertMachineInstrInMaps(MII);
474 VRM.addSpillSlotUse(StackSlot, MII);
475 DEBUG(dbgs() << "\thoisted: " << SVI.SpillVNI->def << '\t' << *MII);
479 /// eliminateRedundantSpills - SLI:VNI is known to be on the stack. Remove any
480 /// redundant spills of this value in SLI.reg and sibling copies.
481 void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
482 assert(VNI && "Missing value");
483 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
484 WorkList.push_back(std::make_pair(&SLI, VNI));
485 assert(StackInt && "No stack slot assigned yet.");
489 tie(LI, VNI) = WorkList.pop_back_val();
490 unsigned Reg = LI->reg;
491 DEBUG(dbgs() << "Checking redundant spills for " << PrintReg(Reg) << ':'
492 << VNI->id << '@' << VNI->def << '\n');
494 // Regs to spill are taken care of.
495 if (isRegToSpill(Reg))
498 // Add all of VNI's live range to StackInt.
499 StackInt->MergeValueInAsValue(*LI, VNI, StackInt->getValNumInfo(0));
500 DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n');
502 // Find all spills and copies of VNI.
503 for (MachineRegisterInfo::use_nodbg_iterator UI = MRI.use_nodbg_begin(Reg);
504 MachineInstr *MI = UI.skipInstruction();) {
505 if (!MI->isCopy() && !MI->getDesc().mayStore())
507 SlotIndex Idx = LIS.getInstructionIndex(MI);
508 if (LI->getVNInfoAt(Idx) != VNI)
511 // Follow sibling copies down the dominator tree.
512 if (unsigned DstReg = isFullCopyOf(MI, Reg)) {
513 if (isSibling(DstReg)) {
514 LiveInterval &DstLI = LIS.getInterval(DstReg);
515 VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getDefIndex());
516 assert(DstVNI && "Missing defined value");
517 assert(DstVNI->def == Idx.getDefIndex() && "Wrong copy def slot");
518 WorkList.push_back(std::make_pair(&DstLI, DstVNI));
525 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
526 DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << *MI);
527 // eliminateDeadDefs won't normally remove stores, so switch opcode.
528 MI->setDesc(TII.get(TargetOpcode::KILL));
529 DeadDefs.push_back(MI);
532 } while (!WorkList.empty());
536 //===----------------------------------------------------------------------===//
538 //===----------------------------------------------------------------------===//
540 /// markValueUsed - Remember that VNI failed to rematerialize, so its defining
541 /// instruction cannot be eliminated. See through snippet copies
542 void InlineSpiller::markValueUsed(LiveInterval *LI, VNInfo *VNI) {
543 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
544 WorkList.push_back(std::make_pair(LI, VNI));
546 tie(LI, VNI) = WorkList.pop_back_val();
547 if (!UsedValues.insert(VNI))
550 if (VNI->isPHIDef()) {
551 MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
552 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
553 PE = MBB->pred_end(); PI != PE; ++PI) {
554 VNInfo *PVNI = LI->getVNInfoAt(LIS.getMBBEndIdx(*PI).getPrevSlot());
556 WorkList.push_back(std::make_pair(LI, PVNI));
561 // Follow snippet copies.
562 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
563 if (!SnippetCopies.count(MI))
565 LiveInterval &SnipLI = LIS.getInterval(MI->getOperand(1).getReg());
566 assert(isRegToSpill(SnipLI.reg) && "Unexpected register in copy");
567 VNInfo *SnipVNI = SnipLI.getVNInfoAt(VNI->def.getUseIndex());
568 assert(SnipVNI && "Snippet undefined before copy");
569 WorkList.push_back(std::make_pair(&SnipLI, SnipVNI));
570 } while (!WorkList.empty());
573 /// reMaterializeFor - Attempt to rematerialize before MI instead of reloading.
574 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg,
575 MachineBasicBlock::iterator MI) {
576 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getUseIndex();
577 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx);
580 DEBUG(dbgs() << "\tadding <undef> flags: ");
581 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
582 MachineOperand &MO = MI->getOperand(i);
583 if (MO.isReg() && MO.isUse() && MO.getReg() == Edit->getReg())
586 DEBUG(dbgs() << UseIdx << '\t' << *MI);
590 if (SnippetCopies.count(MI))
593 // Use an OrigVNI from traceSiblingValue when ParentVNI is a sibling copy.
594 LiveRangeEdit::Remat RM(ParentVNI);
595 SibValueMap::const_iterator SibI = SibValues.find(ParentVNI);
596 if (SibI != SibValues.end())
597 RM.OrigMI = SibI->second.DefMI;
598 if (!Edit->canRematerializeAt(RM, UseIdx, false, LIS)) {
599 markValueUsed(&VirtReg, ParentVNI);
600 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
604 // If the instruction also writes Edit->getReg(), it had better not require
605 // the same register for uses and defs.
607 SmallVector<unsigned, 8> Ops;
608 tie(Reads, Writes) = MI->readsWritesVirtualRegister(Edit->getReg(), &Ops);
610 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
611 MachineOperand &MO = MI->getOperand(Ops[i]);
612 if (MO.isUse() ? MI->isRegTiedToDefOperand(Ops[i]) : MO.getSubReg()) {
613 markValueUsed(&VirtReg, ParentVNI);
614 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
620 // Before rematerializing into a register for a single instruction, try to
621 // fold a load into the instruction. That avoids allocating a new register.
622 if (RM.OrigMI->getDesc().canFoldAsLoad() &&
623 foldMemoryOperand(MI, Ops, RM.OrigMI)) {
624 Edit->markRematerialized(RM.ParentVNI);
628 // Alocate a new register for the remat.
629 LiveInterval &NewLI = Edit->create(LIS, VRM);
630 NewLI.markNotSpillable();
632 // Rematting for a copy: Set allocation hint to be the destination register.
634 MRI.setRegAllocationHint(NewLI.reg, 0, MI->getOperand(0).getReg());
636 // Finally we can rematerialize OrigMI before MI.
637 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM,
639 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'
640 << *LIS.getInstructionFromIndex(DefIdx));
643 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
644 MachineOperand &MO = MI->getOperand(Ops[i]);
645 if (MO.isReg() && MO.isUse() && MO.getReg() == Edit->getReg()) {
646 MO.setReg(NewLI.reg);
650 DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI);
652 VNInfo *DefVNI = NewLI.getNextValue(DefIdx, 0, LIS.getVNInfoAllocator());
653 NewLI.addRange(LiveRange(DefIdx, UseIdx.getDefIndex(), DefVNI));
654 DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
658 /// reMaterializeAll - Try to rematerialize as many uses as possible,
659 /// and trim the live ranges after.
660 void InlineSpiller::reMaterializeAll() {
661 // analyzeSiblingValues has already tested all relevant defining instructions.
662 if (!Edit->anyRematerializable(LIS, TII, AA))
667 // Try to remat before all uses of snippets.
668 bool anyRemat = false;
669 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
670 unsigned Reg = RegsToSpill[i];
671 LiveInterval &LI = LIS.getInterval(Reg);
672 for (MachineRegisterInfo::use_nodbg_iterator
673 RI = MRI.use_nodbg_begin(Reg);
674 MachineInstr *MI = RI.skipInstruction();)
675 anyRemat |= reMaterializeFor(LI, MI);
680 // Remove any values that were completely rematted.
681 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
682 unsigned Reg = RegsToSpill[i];
683 LiveInterval &LI = LIS.getInterval(Reg);
684 for (LiveInterval::vni_iterator I = LI.vni_begin(), E = LI.vni_end();
687 if (VNI->isUnused() || VNI->isPHIDef() || VNI->hasPHIKill() ||
688 UsedValues.count(VNI))
690 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
691 MI->addRegisterDead(Reg, &TRI);
692 if (!MI->allDefsAreDead())
694 DEBUG(dbgs() << "All defs dead: " << *MI);
695 DeadDefs.push_back(MI);
696 // Remove all Reg references so we don't insert spill code around MI.
697 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
698 MOE = MI->operands_end(); MOI != MOE ; ++MOI)
699 if (MOI->isReg() && MOI->getReg() == Reg)
701 VNI->setIsUnused(true);
706 /// If MI is a load or store of StackSlot, it can be removed.
707 bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
710 if (!(InstrReg = TII.isLoadFromStackSlot(MI, FI)) &&
711 !(InstrReg = TII.isStoreToStackSlot(MI, FI)))
714 // We have a stack access. Is it the right register and slot?
715 if (InstrReg != Reg || FI != StackSlot)
718 DEBUG(dbgs() << "Coalescing stack access: " << *MI);
719 LIS.RemoveMachineInstrFromMaps(MI);
720 MI->eraseFromParent();
724 /// foldMemoryOperand - Try folding stack slot references in Ops into MI.
725 /// @param MI Instruction using or defining the current register.
726 /// @param Ops Operand indices from readsWritesVirtualRegister().
727 /// @param LoadMI Load instruction to use instead of stack slot when non-null.
728 /// @return True on success, and MI will be erased.
729 bool InlineSpiller::foldMemoryOperand(MachineBasicBlock::iterator MI,
730 const SmallVectorImpl<unsigned> &Ops,
731 MachineInstr *LoadMI) {
732 // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
734 SmallVector<unsigned, 8> FoldOps;
735 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
736 unsigned Idx = Ops[i];
737 MachineOperand &MO = MI->getOperand(Idx);
740 // FIXME: Teach targets to deal with subregs.
743 // We cannot fold a load instruction into a def.
744 if (LoadMI && MO.isDef())
746 // Tied use operands should not be passed to foldMemoryOperand.
747 if (!MI->isRegTiedToDefOperand(Idx))
748 FoldOps.push_back(Idx);
751 MachineInstr *FoldMI =
752 LoadMI ? TII.foldMemoryOperand(MI, FoldOps, LoadMI)
753 : TII.foldMemoryOperand(MI, FoldOps, StackSlot);
756 LIS.ReplaceMachineInstrInMaps(MI, FoldMI);
758 VRM.addSpillSlotUse(StackSlot, FoldMI);
759 MI->eraseFromParent();
760 DEBUG(dbgs() << "\tfolded: " << *FoldMI);
764 /// insertReload - Insert a reload of NewLI.reg before MI.
765 void InlineSpiller::insertReload(LiveInterval &NewLI,
766 MachineBasicBlock::iterator MI) {
767 MachineBasicBlock &MBB = *MI->getParent();
768 SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
769 TII.loadRegFromStackSlot(MBB, MI, NewLI.reg, StackSlot,
770 MRI.getRegClass(NewLI.reg), &TRI);
771 --MI; // Point to load instruction.
772 SlotIndex LoadIdx = LIS.InsertMachineInstrInMaps(MI).getDefIndex();
773 VRM.addSpillSlotUse(StackSlot, MI);
774 DEBUG(dbgs() << "\treload: " << LoadIdx << '\t' << *MI);
775 VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0,
776 LIS.getVNInfoAllocator());
777 NewLI.addRange(LiveRange(LoadIdx, Idx, LoadVNI));
780 /// insertSpill - Insert a spill of NewLI.reg after MI.
781 void InlineSpiller::insertSpill(LiveInterval &NewLI, const LiveInterval &OldLI,
782 MachineBasicBlock::iterator MI) {
783 MachineBasicBlock &MBB = *MI->getParent();
785 // Get the defined value. It could be an early clobber so keep the def index.
786 SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
787 VNInfo *VNI = OldLI.getVNInfoAt(Idx);
788 assert(VNI && VNI->def.getDefIndex() == Idx && "Inconsistent VNInfo");
791 TII.storeRegToStackSlot(MBB, ++MI, NewLI.reg, true, StackSlot,
792 MRI.getRegClass(NewLI.reg), &TRI);
793 --MI; // Point to store instruction.
794 SlotIndex StoreIdx = LIS.InsertMachineInstrInMaps(MI).getDefIndex();
795 VRM.addSpillSlotUse(StackSlot, MI);
796 DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MI);
797 VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, LIS.getVNInfoAllocator());
798 NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
801 /// spillAroundUses - insert spill code around each use of Reg.
802 void InlineSpiller::spillAroundUses(unsigned Reg) {
803 LiveInterval &OldLI = LIS.getInterval(Reg);
805 // Iterate over instructions using Reg.
806 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg);
807 MachineInstr *MI = RI.skipInstruction();) {
809 // Debug values are not allowed to affect codegen.
810 if (MI->isDebugValue()) {
811 // Modify DBG_VALUE now that the value is in a spill slot.
812 uint64_t Offset = MI->getOperand(1).getImm();
813 const MDNode *MDPtr = MI->getOperand(2).getMetadata();
814 DebugLoc DL = MI->getDebugLoc();
815 if (MachineInstr *NewDV = TII.emitFrameIndexDebugValue(MF, StackSlot,
816 Offset, MDPtr, DL)) {
817 DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
818 MachineBasicBlock *MBB = MI->getParent();
819 MBB->insert(MBB->erase(MI), NewDV);
821 DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI);
822 MI->eraseFromParent();
827 // Ignore copies to/from snippets. We'll delete them.
828 if (SnippetCopies.count(MI))
831 // Stack slot accesses may coalesce away.
832 if (coalesceStackAccess(MI, Reg))
835 // Analyze instruction.
837 SmallVector<unsigned, 8> Ops;
838 tie(Reads, Writes) = MI->readsWritesVirtualRegister(Reg, &Ops);
840 // Check for a sibling copy.
841 unsigned SibReg = isFullCopyOf(MI, Reg);
842 if (SibReg && isSibling(SibReg)) {
844 // Hoist the spill of a sib-reg copy.
845 if (hoistSpill(OldLI, MI)) {
846 // This COPY is now dead, the value is already in the stack slot.
847 MI->getOperand(0).setIsDead();
848 DeadDefs.push_back(MI);
852 // This is a reload for a sib-reg copy. Drop spills downstream.
853 SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
854 LiveInterval &SibLI = LIS.getInterval(SibReg);
855 eliminateRedundantSpills(SibLI, SibLI.getVNInfoAt(Idx));
856 // The COPY will fold to a reload below.
860 // Attempt to fold memory ops.
861 if (foldMemoryOperand(MI, Ops))
864 // Allocate interval around instruction.
865 // FIXME: Infer regclass from instruction alone.
866 LiveInterval &NewLI = Edit->createFrom(Reg, LIS, VRM);
867 NewLI.markNotSpillable();
870 insertReload(NewLI, MI);
872 // Rewrite instruction operands.
873 bool hasLiveDef = false;
874 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
875 MachineOperand &MO = MI->getOperand(Ops[i]);
876 MO.setReg(NewLI.reg);
878 if (!MI->isRegTiedToDefOperand(Ops[i]))
886 // FIXME: Use a second vreg if instruction has no tied ops.
887 if (Writes && hasLiveDef)
888 insertSpill(NewLI, OldLI, MI);
890 DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
894 void InlineSpiller::spill(LiveRangeEdit &edit) {
896 assert(!TargetRegisterInfo::isStackSlot(edit.getReg())
897 && "Trying to spill a stack slot.");
898 // Share a stack slot among all descendants of Original.
899 Original = VRM.getOriginal(edit.getReg());
900 StackSlot = VRM.getStackSlot(Original);
903 DEBUG(dbgs() << "Inline spilling "
904 << MRI.getRegClass(edit.getReg())->getName()
905 << ':' << edit.getParent() << "\nFrom original "
906 << LIS.getInterval(Original) << '\n');
907 assert(edit.getParent().isSpillable() &&
908 "Attempting to spill already spilled value.");
909 assert(DeadDefs.empty() && "Previous spill didn't remove dead defs");
911 collectRegsToSpill();
912 analyzeSiblingValues();
915 // Remat may handle everything.
916 if (Edit->getParent().empty())
919 // Update LiveStacks now that we are committed to spilling.
920 if (StackSlot == VirtRegMap::NO_STACK_SLOT) {
921 StackSlot = VRM.assignVirt2StackSlot(Original);
922 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original));
923 StackInt->getNextValue(SlotIndex(), 0, LSS.getVNInfoAllocator());
925 StackInt = &LSS.getInterval(StackSlot);
927 if (Original != edit.getReg())
928 VRM.assignVirt2StackSlot(edit.getReg(), StackSlot);
930 assert(StackInt->getNumValNums() == 1 && "Bad stack interval values");
931 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
932 StackInt->MergeRangesInAsValue(LIS.getInterval(RegsToSpill[i]),
933 StackInt->getValNumInfo(0));
934 DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n');
936 // Spill around uses of all RegsToSpill.
937 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
938 spillAroundUses(RegsToSpill[i]);
940 // Hoisted spills may cause dead code.
941 if (!DeadDefs.empty()) {
942 DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n");
943 Edit->eliminateDeadDefs(DeadDefs, LIS, VRM, TII);
946 // Finally delete the SnippetCopies.
947 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(edit.getReg());
948 MachineInstr *MI = RI.skipInstruction();) {
949 assert(SnippetCopies.count(MI) && "Remaining use wasn't a snippet copy");
950 // FIXME: Do this with a LiveRangeEdit callback.
951 VRM.RemoveMachineInstrFromMaps(MI);
952 LIS.RemoveMachineInstrFromMaps(MI);
953 MI->eraseFromParent();
956 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
957 edit.eraseVirtReg(RegsToSpill[i], LIS);