1 //===-- llvm/CodeGen/DwarfExpression.h - Dwarf Compile Unit ---*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains support for writing dwarf compile unit.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_CODEGEN_ASMPRINTER_DWARFEXPRESSION_H
15 #define LLVM_LIB_CODEGEN_ASMPRINTER_DWARFEXPRESSION_H
17 #include "llvm/Support/DataTypes.h"
23 /// Base class containing the logic for constructing DWARF expressions
24 /// independently of whether they are emitted into a DIE or into a .debug_loc
26 class DwarfExpression {
30 DwarfExpression(TargetMachine &TM) : TM(TM) {}
31 virtual ~DwarfExpression() {}
33 virtual void EmitOp(uint8_t Op, const char* Comment = nullptr) = 0;
34 virtual void EmitSigned(int Value) = 0;
35 virtual void EmitUnsigned(unsigned Value) = 0;
37 virtual unsigned getFrameRegister() = 0;
39 /// Emit a dwarf register operation.
40 void AddReg(int DwarfReg, const char* Comment = nullptr);
41 /// Emit an (double-)indirect dwarf register operation.
42 void AddRegIndirect(int DwarfReg, int Offset, bool Deref = false);
44 /// Emit a dwarf register operation for describing
45 /// - a small value occupying only part of a register or
46 /// - a register representing only part of a value.
47 void AddOpPiece(unsigned SizeInBits, unsigned OffsetInBits = 0);
48 /// Emit a shift-right dwarf expression.
49 void AddShr(unsigned ShiftBy);
51 /// Emit an indirect dwarf register operation for the given machine register.
52 /// Returns false if no DWARF register exists for MachineReg.
53 bool AddMachineRegIndirect(unsigned MachineReg, int Offset);
55 /// \brief Emit a partial DWARF register operation.
56 /// \param MLoc the register
57 /// \param PieceSize size and
58 /// \param PieceOffset offset of the piece in bits, if this is one
59 /// piece of an aggregate value.
61 /// If size and offset is zero an operation for the entire
62 /// register is emitted: Some targets do not provide a DWARF
63 /// register number for every register. If this is the case, this
64 /// function will attempt to emit a DWARF register by emitting a
65 /// piece of a super-register or by piecing together multiple
66 /// subregisters that alias the register.
67 void AddMachineRegPiece(unsigned MachineReg,
68 unsigned PieceSizeInBits = 0,
69 unsigned PieceOffsetInBits = 0);